From 38605636366c442b5da96a5b1c9ead71356ccbf0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 15 Jun 2018 20:38:44 +0200 Subject: [PATCH 001/109] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 0710f9dedd..054e68145a 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Arduino core support for STM32 based boards -### Latest release [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.2.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.2.0...master) +### Latest release [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...master) **Warning**: release versioning has been changed from date versioning to semantic one. See [Release Versioning change](https://github.com/stm32duino/wiki/wiki/Release-Versioning-change) From 4e1c22561ae15c976a42699c97e08c53dbb3f4b7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 5 Jul 2018 11:31:11 +0200 Subject: [PATCH 002/109] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 054e68145a..2c67ea06bd 100644 --- a/README.md +++ b/README.md @@ -63,7 +63,7 @@ For advanced user, you can use the repository: see the [Using git repository](ht * STM32L4 * [Nucleo L432KC](http://www.st.com/en/evaluation-tools/nucleo-l432kc.html) * [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) - * [NUCLEO-L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) + * [NUCLEO-L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) * [NUCLEO-L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) From 5b811b459872a9474470987654d3d6fe57c5c7eb Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 18 Jul 2018 11:15:14 +0200 Subject: [PATCH 003/109] [Boards.txt] Set -Os as default flags optimize Signed-off-by: Frederic.Pillon --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index f44e737cec..ce94d61608 100644 --- a/platform.txt +++ b/platform.txt @@ -81,7 +81,7 @@ build.info.flags=-D{build.series} -DARDUINO={runtime.ide.version} -DARDUINO_{bui # Defaults config build.xSerial=-DHAL_UART_MODULE_ENABLED build.enable_usb= -build.flags.optimize= +build.flags.optimize=-Os build.flags.ldspecs= # Pre and post build hooks From 3c66de722951baacb106901cb5503eb41940e720 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 08:37:33 +0200 Subject: [PATCH 004/109] HAL_UARTEx_(Enable|Disable)ClockStopMode not always defined Fix #280 Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/uart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/uart.c b/cores/arduino/stm32/uart.c index 42bd4bf786..222526a654 100644 --- a/cores/arduino/stm32/uart.c +++ b/cores/arduino/stm32/uart.c @@ -314,10 +314,14 @@ void uart_init(serial_t *obj) */ if(obj->uart == LPUART1) { if (obj->baudrate <= 9600) { +#if defined(USART_CR3_UCESM) HAL_UARTEx_EnableClockStopMode(huart); +#endif HAL_UARTEx_EnableStopMode(huart); } else { +#if defined(USART_CR3_UCESM) HAL_UARTEx_DisableClockStopMode(huart); +#endif HAL_UARTEx_DisableStopMode(huart); } /* Trying default LPUART clock source */ From 28d0abae8a90a440cbc184ccc1d48f2d6b20a224 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 11:44:19 +0200 Subject: [PATCH 005/109] [F1xxx] LSI typical value is 40kHz Fix #270 Signed-off-by: Frederic.Pillon --- variants/BLUEPILL_F103C8/stm32f1xx_hal_conf.h | 2 +- variants/DISCO_F100RB/stm32f1xx_hal_conf.h | 2 +- variants/MAPLEMINI_F103CB/stm32f1xx_hal_conf.h | 2 +- variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/variants/BLUEPILL_F103C8/stm32f1xx_hal_conf.h b/variants/BLUEPILL_F103C8/stm32f1xx_hal_conf.h index 50e9693dfa..eb758ccc19 100644 --- a/variants/BLUEPILL_F103C8/stm32f1xx_hal_conf.h +++ b/variants/BLUEPILL_F103C8/stm32f1xx_hal_conf.h @@ -114,7 +114,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ diff --git a/variants/DISCO_F100RB/stm32f1xx_hal_conf.h b/variants/DISCO_F100RB/stm32f1xx_hal_conf.h index 5ab4ad2780..1aecd8d9f5 100644 --- a/variants/DISCO_F100RB/stm32f1xx_hal_conf.h +++ b/variants/DISCO_F100RB/stm32f1xx_hal_conf.h @@ -114,7 +114,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ diff --git a/variants/MAPLEMINI_F103CB/stm32f1xx_hal_conf.h b/variants/MAPLEMINI_F103CB/stm32f1xx_hal_conf.h index 50e9693dfa..eb758ccc19 100644 --- a/variants/MAPLEMINI_F103CB/stm32f1xx_hal_conf.h +++ b/variants/MAPLEMINI_F103CB/stm32f1xx_hal_conf.h @@ -114,7 +114,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ diff --git a/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h b/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h index 50e9693dfa..eb758ccc19 100644 --- a/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h +++ b/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h @@ -114,7 +114,7 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ From 5eea46a64140c7dbdacf8cda61822fcfbc07b813 Mon Sep 17 00:00:00 2001 From: Angela Randolph Date: Thu, 21 Jun 2018 11:54:25 +0200 Subject: [PATCH 006/109] Add script to build the core Python script used to build sketch(es) thanks to Arduino Builder Python requirement >= 3.2 (due to concurrent.futures usage) usage: arduino-builder.py [-h] [-l [{board,sketch}] | -a] [-b pattern] [-c] [--arch architecture] [--config ] [-v] [--bin | --travis] [-i | -f | -s pattern | -e ] Signed-off-by: Angela Randolph --- CI/build/.flake8 | 2 + CI/build/README.md | 64 +++ CI/build/arduino-builder.py | 800 ++++++++++++++++++++++++++ CI/build/conf/cores_config.json | 115 ++++ CI/build/conf/exclude_list.txt | 16 + CI/build/conf/path_config_travis.json | 7 + CI/build/conf/sketch_list.txt | 53 ++ 7 files changed, 1057 insertions(+) create mode 100644 CI/build/.flake8 create mode 100644 CI/build/README.md create mode 100644 CI/build/arduino-builder.py create mode 100644 CI/build/conf/cores_config.json create mode 100644 CI/build/conf/exclude_list.txt create mode 100644 CI/build/conf/path_config_travis.json create mode 100644 CI/build/conf/sketch_list.txt diff --git a/CI/build/.flake8 b/CI/build/.flake8 new file mode 100644 index 0000000000..2bcd70e390 --- /dev/null +++ b/CI/build/.flake8 @@ -0,0 +1,2 @@ +[flake8] +max-line-length = 88 diff --git a/CI/build/README.md b/CI/build/README.md new file mode 100644 index 0000000000..8691ca373a --- /dev/null +++ b/CI/build/README.md @@ -0,0 +1,64 @@ +# arduino-builder.py + +This script manages _[arduino-builder](https://github.com/arduino/arduino-builder)_ command line tool for compiling Arduino sketch(es). + +## Requirements +- [Arduino IDE](https://www.arduino.cc/en/Main/Software) (_[arduino-builder](https://github.com/arduino/arduino-builder)_ is included) +- Python version greater than or equal to 3.2 (due to `concurrent.futures` usage) + +## Usage + +``` +usage: arduino-builder.py [-h] [-l [{board,sketch}] | -a] [-b pattern] [-c] + [--arch architecture] + [--config ] [-v] + [--bin | --travis] + [-i | -f | -s pattern | -e ] + +Manage arduino-builder command line tool for compiling Arduino sketch(es). + +optional arguments: + -h, --help show this help message and exit + -l [{board,sketch}], --list [{board,sketch}] + list available board(s) or sketch(es) + -a, --all build all sketches found for all available boards + -b pattern, --board pattern + pattern to find one or more board(s) to build + -c, --clean clean output directory + /arduinoBuilderOutput + --arch architecture core architecture to build. Default build architecture + is stm32 + --config + JSON file containing the build configuration for one + or more maintainer/architecture. Board options for + build, applicability of sketches for boards or + required options. If sketch is not listed then + applicable to all board. Default core configuration is + for 'stm32' architecture in: /arduino- + builder/conf/cores_config.json + -v, --verbose enable arduino-builder verbose mode + --bin save binaries + --travis Custom configuration for Travis CI build + +Sketch(es) options: + By default build /arduino/examples/01.Basics/Blink/Blink.ino + + -i , --ino + single ino file to build + -f , --file + file containing list of sketches to build + -s pattern, --sketches pattern + pattern to find one or more sketch to build + -e , --exclude + file containing pattern of sketches to ignore. Default + path : /arduino-builder/conf/exclude_list.txt +``` + +## Cores configuration files + +ToDo + +## Usage examples + +ToDo + diff --git a/CI/build/arduino-builder.py b/CI/build/arduino-builder.py new file mode 100644 index 0000000000..da3767a841 --- /dev/null +++ b/CI/build/arduino-builder.py @@ -0,0 +1,800 @@ +# -*- coding: utf-8 -*- + +# File name : arduino-builder.py +# Author : Angela RANDOLPH +# Other contributors : Frederic PILLON +# Created : 26/04/2018 +# Python Version : >= 3.2 (due to concurrent.futures usage) + +# Description : Used to build sketch(es) thanks to Arduino Builder +# See https://github.com/arduino/arduino-builder +import os +import re +import sys +import json +import time +import shutil +import subprocess +import tempfile +import argparse +import concurrent.futures +import collections +from datetime import timedelta + +# Create a Json file for a better path management +path_config_filename = "path_config.json" +home = os.path.expanduser("~") +tempdir = tempfile.gettempdir() +build_id = time.strftime("_%Y-%m-%d_%H-%M-%S") +script_path = os.path.dirname(os.path.abspath(__file__)) + +try: + path_config_file = open(path_config_filename, "r") +except IOError: + print( + "Please set your configuration in '{}' file".format( + os.path.join(script_path, path_config_filename) + ) + ) + path_config_file = open(path_config_filename, "w") + if sys.platform.startswith("win32"): + print("Default config set for Windows environment.") + arduino_path = "C:\\Program Files (x86)\\Arduino" # arduino default path + arduino_packages = home + "\\AppData\\Local\\Arduino15\\packages" # Windows 7 + arduino_user_sketchbook = home + "\\My Documents\\Arduino" + # Windows 7 temporary directory using by arduino builder + build_output_dir = tempdir + "\\temp_arduinoBuilderOutput" + root_output_dir = home + "\\arduinoBuilderOutput" # output directory + elif sys.platform.startswith("linux"): + print("Default config set for Linux environment.") + arduino_path = home + "/Documents/arduino-1.8.5" + arduino_packages = home + "/.arduino15/packages" + arduino_user_sketchbook = home + "/Documents/Arduino" + build_output_dir = tempdir + "/temp_arduinoBuilderOutput" + root_output_dir = home + "/Documents/arduinoBuilderOutput" + elif sys.platform.startswith("darwin"): + print("Default config set for Mac OSX environment.") + arduino_path = home + "/Applications/Arduino/" + arduino_packages = home + "/Library/Arduino15/packages" + arduino_user_sketchbook = home + "/Documents/Arduino" + build_output_dir = tempdir + "/temp_arduinoBuilderOutput" + root_output_dir = home + "/Documents/arduinoBuilderOutput" + else: + print("Platform unknown.") + arduino_path = "" + arduino_packages = "" + arduino_user_sketchbook = "" + build_output_dir = "" + root_output_dir = "" + path_config_file.write( + json.dumps( + { + "ARDUINO_PATH": arduino_path, + "ARDUINO_PACKAGES": arduino_packages, + "ARDUINO_USER_SKETCHBOOK": arduino_user_sketchbook, + "BUILD_OUPUT_DIR": build_output_dir, + "ROOT_OUPUT_DIR": root_output_dir, + }, + indent=2, + ) + ) + path_config_file.close() + exit(1) + +path_config = json.load(path_config_file) +path_config_file.close() + +# Common path +arduino_path = path_config["ARDUINO_PATH"] +arduino_packages = path_config["ARDUINO_PACKAGES"] +arduino_user_sketchbook = path_config["ARDUINO_USER_SKETCHBOOK"] +build_output_dir = path_config["BUILD_OUPUT_DIR"] + build_id +root_output_dir = path_config["ROOT_OUPUT_DIR"] + +assert os.path.exists( + arduino_path +), "Path does not exist: {} . Please set this path in the json config file".format( + arduino_path +) +assert os.path.exists( + arduino_packages +), "Path does not exist: {} . Please set this path in the json config file".format( + arduino_packages +) + +assert os.path.exists( + arduino_user_sketchbook +), "Path does not exist: {} . Please set this path in the json config file".format( + arduino_user_sketchbook +) + +arduino_builder = os.path.join(arduino_path, "arduino-builder") +arduino_hardware_path = os.path.join(arduino_path, "hardware") +arduino_lib_path = os.path.join(arduino_path, "libraries") +arduino_sketchbook_path = os.path.join(arduino_path, "examples") +arduino_user_lib_path = os.path.join(arduino_user_sketchbook, "libraries") +tools_path = os.path.join(arduino_path, "tools-builder") +output_dir = os.path.join(root_output_dir, "build" + build_id) +log_file = os.path.join(output_dir, "build_result.log") + +# Ouput directory path +bin_dir = "binaries" + +# Default +sketch_default = os.path.join( + arduino_sketchbook_path, "01.Basics", "Blink", "Blink.ino" +) +exclude_file_default = os.path.join("conf", "exclude_list.txt") +cores_config_file_default = os.path.join("conf", "cores_config.json") + +maintainer_default = "STM32" +arch_default = "stm32" + +core_config = None +maintainer = maintainer_default +arch = arch_default +core_path = "" + +# List +sketch_list = [] +exclude_list = [] + +# Dict +board_type = collections.OrderedDict() # (key: board name, value: board type) +board_fqbn = {} # key: board name, value: fqbn +board_options = {} # key: board name, value: options +sketch_options = {} # key: sketch pattern, value: options +na_sketch_pattern = {} # key: board name, value: sketch pattern list + +# Counter +nb_build_passed = 0 +nb_build_failed = 0 +nb_build_skipped = 0 + +# Timing +startTime = time.time() + + +# Create a folder if not exists +def createFolder(folder): + try: + if not os.path.exists(folder): + os.makedirs(folder) + except OSError: + print("Error: Creating directory. " + folder) + + +# Delete targeted folder recursively +def deleteFolder(folder): + if os.path.isdir(folder): + shutil.rmtree(folder, ignore_errors=True) + + +def cat(file): + with open(file, "r") as f: + print(f.read()) + print("") + + +# Create the log output file and folders +def create_output_log_tree(): + # Log output file + with open(log_file, "w") as file: + file.write("************************************** \n") + file.write("*********** OUTPUT / RESULT ********** \n") + file.write("************************************** \n") + file.write(time.strftime("%A %d %B %Y %H:%M:%S ")) + file.write("\nPath : {} \n".format(os.path.abspath(output_dir))) + # Folders + for board in board_type: + createFolder(os.path.join(output_dir, board)) + if args.bin: + createFolder(os.path.join(output_dir, board, bin_dir)) + createFolder(os.path.join(build_output_dir, board)) + + +def load_core_config(): + global core_config + global maintainer + global arch + cores_config_filename = "" + if args.config: + assert os.path.exists( + args.config + ), "User core configuration JSON file does not exist" + cores_config_filename = args.config + else: + cores_config_filename = cores_config_file_default + print("Cores configuration JSON file that will be used: " + cores_config_filename) + try: + cores_config_file = open(cores_config_filename, "r") + cores_config = json.load(cores_config_file) + cores_config_file.close() + + if args.arch: + arch = args.arch + for core in cores_config["cores"]: + if arch == core["architecture"]: + core_config = core + maintainer = core["maintainer"] + print( + "Build configuration for '" + + maintainer + + "' maintainer and '" + + arch + + "' architecture" + ) + break + else: + print( + "Core architecture '" + arch + "' not found in " + cores_config_filename + ) + arch = arch_default + core_config = None + except IOError: + print( + "Can't open {} file. Build configuration will not be used.".format( + cores_config_filename + ) + ) + finally: + if core_config is None: + print( + "Using default configuration for '" + + maintainer_default + + "' maintainer and '" + + arch_default + + "' architecture" + ) + + +# Board list have to be initialized before call this function +def parse_core_config(): + assert board_type, "Board list not initialized" + # Extract boards names to create a set + board_name_set = set([board for board in board_type]) + for sketch in core_config["sketches"]: + if sketch["applicable"] is True: + # Remove boards in the list + na_board_set = board_name_set - set(sketch["boards"]) + else: + # Add boards in the list + na_board_set = set(sketch["boards"]) - ( + set(sketch["boards"]) - board_name_set + ) + if "options" in sketch: + sketch_options[sketch["pattern"]] = sketch["options"] + if len(na_board_set): + for board_name in na_board_set: + if board_name in na_sketch_pattern: + na_sketch_pattern[board_name].append(sketch["pattern"]) + else: + na_sketch_pattern[board_name] = [sketch["pattern"]] + + for board in core_config["boards"]: + if "fqbn" in board: + board_fqbn[board["name"]] = board["fqbn"] + if "options" in board: + board_options[board["name"]] = board["options"] + + # for key, value in na_sketch_pattern.items(): + # print("{}: {}\n".format(key, value)) + # for key, value in board_fqbn.items(): + # print("{}: {}\n".format(key, value)) + + +def manage_exclude_list(file): + with open(file, "r") as f: + for line in f.readlines(): + if line.rstrip(): + exclude_list.append(line.rstrip()) + if exclude_list: + for pattern in exclude_list: + exclude_pattern = re.compile(".*" + pattern + ".*", re.IGNORECASE) + for s in reversed(sketch_list): + if exclude_pattern.search(s): + sketch_list.remove(s) + + +# Manage sketches list +def manage_inos(): + # Find all inos or all patterned inos + if args.all or args.sketches or args.list == "sketch": + find_inos() + if args.exclude: + assert os.path.exists(args.exclude), "Excluded list file does not exist" + manage_exclude_list(args.exclude) + elif os.path.exists(exclude_file_default): + manage_exclude_list(exclude_file_default) + # Only one sketch + elif args.ino: + if os.path.exists(args.ino): + sketch_list.append(args.ino) + else: + assert os.path.exists( + os.path.join(arduino_path, args.ino) + ), "Sketch path does not exist" + sketch_list.append(os.path.join(arduino_path, args.ino)) + # Sketches listed in a file + elif args.file: + assert os.path.exists(args.file), "Sketches list file does not exist" + with open(args.file, "r") as f: + for line in f.readlines(): + if line.rstrip(): + ino = line.rstrip() + if os.path.exists(ino): + sketch_list.append(ino) + elif os.path.exists(os.path.join(arduino_path, ino)): + sketch_list.append(os.path.join(arduino_path, ino)) + else: + print("Ignore {} as does not exist.".format(ino)) + # Default sketch to build + else: + sketch_list.append(sketch_default) + assert len(sketch_list), "No sketch to build!" + + +# Find all .ino files +def find_inos(): + # Path list order must be kept as we avoid duplicated sketch name + # Last one found will be kept + # Preferred order is: user, core then offical + pathList = [ + arduino_sketchbook_path, + arduino_lib_path, + core_path, + arduino_user_sketchbook, + ] + # key: path, value: name + ordered_path = collections.OrderedDict() + # key: name, value: path + ordered_name = collections.OrderedDict() + if args.sketches: + arg_sketch_pattern = re.compile(args.sketches, re.IGNORECASE) + for path in pathList: + for root, dirs, files in os.walk(path, followlinks=True): + for file in files: + if file.endswith((".ino", ".pde")): + if args.sketches: + if arg_sketch_pattern.search(os.path.join(root, file)) is None: + continue + if root in ordered_path: + # If several sketch are in the same path + # Check which one to kept + # Commonly, example structure is: + # dirname/dirname.ino + if ( + os.path.basename(root) + == os.path.splitext(ordered_path[root])[0] + ): + continue + ordered_path[root] = file + # Remove duplicated sketch name + for path, name in ordered_path.items(): + ordered_name[name] = path + for name, path in ordered_name.items(): + sketch_list.append(os.path.join(path, name)) + sketch_list.sort() + + +# Return a list of all board using the board.txt file for the specified architecture +def find_board(): + global core_path + global board_type + board_found = {} + # board can be available at 2 differents menu levels: + # - First: + # genericSTM32F103C.build.variant=generic_stm32f103c + # - Second: + # Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.variant=NUCLEO_L496ZG + # genericSTM32F103C.menu.device_variant.STM32F103C8= + # genericSTM32F103R.menu.device_variant.STM32F103R8.build.variant + board_pattern = re.compile( + "([^#\.]+)(?:\.menu\.(?:pnum|device_variant)\.)?([^\.]+)?(?:\.build\.variant)?=" + ) + core_pattern = re.compile( + "\\" + + os.path.sep + + maintainer + + "\\" + + os.path.sep + + "[^\\" + + os.path.sep + + "]*\\" + + os.path.sep + + "?" + + arch + ) + if args.board: + arg_board_pattern = re.compile(args.board, re.IGNORECASE) + for path in [arduino_packages, arduino_hardware_path]: + for root, dirs, files in os.walk(path, followlinks=True): + if "boards.txt" in files and core_pattern.search(root): + core_path = root + with open(os.path.join(root, "boards.txt"), "r") as f: + for line in f.readlines(): + res = board_pattern.match(line) + if res: + if args.board: + if res.lastindex == 1: + if arg_board_pattern.search(res.group(1)) is None: + continue + else: + if arg_board_pattern.search(res.group(2)) is None: + continue + + if res.lastindex == 1: + board_found[res.group(1)] = "" + else: + if res.group(1) in board_found: + del board_found[res.group(1)] + board_found[res.group(2)] = res.group(1) + if board_found: + board_type = collections.OrderedDict(sorted(board_found.items())) + return + assert board_type, "No board found!" + + +# Check the status +def check_status(status, build_conf, boardKo): + global nb_build_passed + global nb_build_failed + sketch_name = os.path.basename(build_conf[4][-1]) + if status == 0: + print(" --> " + build_conf[0] + " SUCESS") + if args.bin: + bin_copy(build_conf[0], sketch_name) + nb_build_passed += 1 + elif status == 1: + print(" --> " + build_conf[0] + " FAILED") + boardKo.append(build_conf[0]) + if args.travis: + cat(os.path.join(build_conf[3], sketch_name + ".log")) + nb_build_failed += 1 + else: + print("Error ! Check the run_command exit status ! Return code = " + status) + + +# Log sketch build result +def log_sketch_build_result(sketch, boardKo, boardSkipped): + with open(log_file, "a") as f: + f.write( + """ +Sketch: {0}/{1} +{2} +Build PASSED: {3}/{4} +Build FAILED: {5}/{4} +Build SKIPPED: {6}/{4} +""".format( + sketch_list.index(sketch) + 1, + len(sketch_list), + sketch, + len(board_type) - len(boardKo) - len(boardSkipped), + len(board_type), + len(boardKo), + len(boardSkipped), + ) + ) + if len(boardKo): + f.write("Failed boards :\n" + "\n".join(boardKo)) + f.write("\n") + if len(boardSkipped): + f.write("Skipped boards :\n" + "\n".join(boardSkipped)) + f.write("\n") + +# Log final result +def log_final_result(): + # Also equal to len(board_type) * len(sketch_list) + nb_build_total = nb_build_passed + nb_build_failed + nb_build_skipped + passed = "TOTAL PASSED = {}/{} ({}%) ".format( + nb_build_passed, + nb_build_total, + round(nb_build_passed * 100.0 / nb_build_total, 2), + ) + failed = "TOTAL FAILED = {}/{} ({}%) ".format( + nb_build_failed, + nb_build_total, + round(nb_build_failed * 100.0 / nb_build_total, 2), + ) + skipped = "TOTAL SKIPPED = {}/{} ({}%) ".format( + nb_build_skipped, + nb_build_total, + round(nb_build_skipped * 100.0 / nb_build_total, 2), + ) + duration = str(timedelta(seconds=time.time() - startTime)) + with open(log_file, "a") as f: + f.write("\n****************** PROCESSING COMPLETED ******************\n") + f.write(time.strftime("%A %d %B %Y %H:%M:%S\n")) + f.write("{}\n".format(passed)) + f.write("{}\n".format(failed)) + f.write("{}\n".format(skipped)) + f.write("Logs are available here: {}\n".format(output_dir)) + f.write("Build duration: " + duration) + print("\n****************** PROCESSING COMPLETED ******************") + print(passed) + print(failed) + print(skipped) + print("Logs are available here: " + output_dir) + print("Build duration: " + duration) + + +# Create a "bin" directory for each board and copy all binary files +# from the builder output directory into it +def bin_copy(board_name, sketch_name): + try: + shutil.copy( + os.path.join(build_output_dir, board_name, sketch_name + ".bin"), + os.path.abspath(os.path.join(output_dir, board_name, bin_dir)), + ) + except OSError as e: + print( + "Impossible to copy the binary from the arduino builder output: " + + e.strerror + ) + raise + + +# Set up specific options to customise arduino builder command +def get_fqbn(b_name, b_type): + if b_name in board_fqbn and board_fqbn[b_name]: + return board_fqbn[b_name] + else: + if b_type: + if arch == "stm32": + opt = b_type + ":pnum=" + b_name + else: + opt = b_type + ":device_variant=" + b_name + if b_name in board_options and board_options[b_name]: + opt += "," + board_options[b_name] + else: + opt = b_name + if b_name in board_options and board_options[b_name]: + opt += ":" + board_options[b_name] + return maintainer + ":" + arch + ":" + opt + + +# Generate arduino builder basic command +def genBasicCommand(b_name, b_type): + cmd = [] + cmd.append(arduino_builder) + cmd.append("-hardware") + cmd.append(arduino_hardware_path) + cmd.append("-hardware") + cmd.append(arduino_packages) + cmd.append("-tools") + cmd.append(tools_path) + cmd.append("-tools") + cmd.append(arduino_packages) + cmd.append("-libraries") + cmd.append(arduino_lib_path) + cmd.append("-libraries") + cmd.append(arduino_user_lib_path) + cmd.append("-ide-version=10805") + cmd.append("-warnings=all") + if args.verbose: + cmd.append("-verbose") + cmd.append("-build-path") + cmd.append(os.path.join(build_output_dir, b_name)) + cmd.append("-fqbn") + cmd.append(get_fqbn(b_name, b_type)) + cmd.append("dummy_sketch") + return cmd + + +def create_build_conf_list(): + build_conf_list = [] + idx = 1 + for b_name in board_type: + build_conf_list.append( + ( + b_name, + idx, + len(board_type), + os.path.join(output_dir, b_name), + genBasicCommand(b_name, board_type[b_name]), + ) + ) + idx += 1 + return build_conf_list + + +def build_config(gen_build_conf_list, sketch, boardSkipped): + global nb_build_skipped + build_conf_list = list(gen_build_conf_list) + for idx in reversed(range(len(build_conf_list))): + build_conf_list[idx][4][-1] = sketch + if na_sketch_pattern: + if build_conf_list[idx][0] in na_sketch_pattern: + for pattern in na_sketch_pattern[build_conf_list[idx][0]]: + if re.search(pattern, sketch, re.IGNORECASE): + print( + "Build {} ({}/{})... SKIPPED".format( + build_conf_list[idx][0], + build_conf_list[idx][1], + build_conf_list[idx][2], + ) + ) + boardSkipped.append(build_conf_list[idx][0]) + del build_conf_list[idx] + nb_build_skipped += 1 + break + else: + # get specific sketch options to append to the fqbn + for pattern in sketch_options: + if pattern in sketch_options: + if re.search(pattern, sketch, re.IGNORECASE): + if build_conf_list[idx][4][-2].count(":") == 3: + build_conf_list[idx][4][-2] += ( + "," + sketch_options[pattern] + ) + else: + build_conf_list[idx][4][-2] += ( + ":" + sketch_options[pattern] + ) + return build_conf_list + + +# Automatic run +def build_all(): + create_output_log_tree() + gen_build_conf_list = create_build_conf_list() + + for sketch_nb, sketch in enumerate(sketch_list, start=1): + boardKo = [] + boardSkipped = [] + print("\nBuilding : {} ({}/{}) ".format(sketch, sketch_nb, len(sketch_list))) + build_conf_list = build_config(gen_build_conf_list, sketch, boardSkipped) + + with concurrent.futures.ProcessPoolExecutor() as executor: + for build_conf, res in zip( + build_conf_list, executor.map(build, build_conf_list) + ): + check_status(res, build_conf, boardKo) + log_sketch_build_result(sketch, boardKo, boardSkipped) + log_final_result() + + +# Run arduino builder command +def build(build_conf): + print("Build {} ({}/{})... ".format(build_conf[0], build_conf[1], build_conf[2])) + cmd = build_conf[4] + with open( + os.path.join(build_conf[3], os.path.basename(cmd[-1]) + ".log"), "w" + ) as stdout: + res = subprocess.Popen(cmd, stdout=stdout, stderr=subprocess.STDOUT) + res.wait() + return res.returncode + + +# Parser +parser = argparse.ArgumentParser( + description="Manage arduino-builder command line tool for compiling\ + Arduino sketch(es)." +) + +g0 = parser.add_mutually_exclusive_group() +g0.add_argument( + "-l", + "--list", + help="list available board(s) or sketch(es)", + nargs="?", + const="board", + # default="board", + choices=("board", "sketch"), +) +g0.add_argument( + "-a", + "--all", + help="build all sketches found for all available boards", + action="store_true", +) +parser.add_argument( + "-b", + "--board", + metavar="pattern", + help="pattern to find one or more board(s) to build", +) +parser.add_argument( + "-c", + "--clean", + help="clean output directory " + root_output_dir, + action="store_true", +) +parser.add_argument( + "--arch", + metavar="architecture", + help="core architecture to build. Default build architecture is '" + + arch_default + + "'", +) +parser.add_argument( + "--config", + metavar="", + help="JSON file containing the build configuration for one or more\ + maintainer/architecture. Board options for build, applicability of\ + sketches for boards or required options. If sketch is not listed\ + then applicable to all board. Default core configuration is for '" + + arch_default + + " 'architecture in: " + + os.path.join(script_path, cores_config_file_default), +) + +parser.add_argument( + "-v", "--verbose", help="enable arduino-builder verbose mode", action="store_true" +) + +g1 = parser.add_mutually_exclusive_group() +g1.add_argument("--bin", help="save binaries", action="store_true") +g1.add_argument( + "--travis", help="Custom configuration for Travis CI build", action="store_true" +) + +# Sketch options +sketchg0 = parser.add_argument_group( + title="Sketch(es) options", description="By default build " + sketch_default +) + +sketchg1 = sketchg0.add_mutually_exclusive_group() +sketchg1.add_argument( + "-i", "--ino", metavar="", help="single ino file to build" +) +sketchg1.add_argument( + "-f", + "--file", + metavar="", + help="file containing list of sketches to build", +) +sketchg1.add_argument( + "-s", + "--sketches", + metavar="pattern", + help="pattern to find one or more sketch to build", +) +sketchg1.add_argument( + "-e", + "--exclude", + metavar="", + help="file containing pattern of sketches to ignore.\ + Default path : " + + os.path.join(script_path, exclude_file_default), +) + +args = parser.parse_args() + + +def main(): + if args.clean: + deleteFolder(root_output_dir) + + load_core_config() + + find_board() + if args.list == "board": + print("%i board(s) available" % len(board_type)) + for board in board_type: + print(board) + quit() + + manage_inos() + if args.list == "sketch": + for sketch in sketch_list: + print(sketch) + print("%i sketches found" % len(sketch_list)) + quit() + + if core_config: + parse_core_config() + + createFolder(build_output_dir) + createFolder(output_dir) + + build_all() + + deleteFolder(build_output_dir) + + if nb_build_failed: + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json new file mode 100644 index 0000000000..c64d36d004 --- /dev/null +++ b/CI/build/conf/cores_config.json @@ -0,0 +1,115 @@ +{ + "cores": [ + { + "maintainer": "STM32", + "architecture": "stm32", + "boards": [ + { + "name": "NUCLEO_L031K6", + "options": "opt=oslto" + }, + { + "name": "BLUEPILL_F103C8", + "options": "flash=C8" + } + ], + "sketches": [ + { + "pattern": "DISCO_IOT_|M24SR64-Y|MX25R6435F", + "applicable": true, + "boards": [ "DISCO_L475VG_IOT" ] + }, + { + "pattern": "SPBTLE_BeaconDemo.ino|SPBTLE_SensorDemo.ino|BTLE_sensors_TimeOfFlight_demo.ino", + "applicable": true, + "boards": [ "DISCO_L475VG_IOT" ] + }, + { + "pattern": "STM32Ethernet|Ethernet_MQTT_Adafruit.io.ino|Hello_stm32", + "applicable": true, + "boards": [ "NUCLEO_F429ZI", "DISCO_F746NG" ] + }, + { + "pattern": "ISM43362-M3G-L44|WiFi_MQTT_Adafruit.io.ino|mqtt_B-L475E-IOT01A.ino", + "applicable": true, + "boards": [ "DISCO_L475VG_IOT" ] + }, + { + "pattern": "ExternalWakeup.ino|BleSensors_SensiBLE|NucleoCar", + "applicable": false, + "boards": [ + "NUCLEO_L031K6", + "NUCLEO_L432KC", + "NUCLEO_F303K8", + "BLUEPILL_F103C8", + "MAPLEMINI_F103CB", + "RAK811_TRACKER" + ] + }, + { + "pattern": "04.Communication/(Multi)?Serial(Passthrough)?", + "applicable": true, + "boards": [ "" ] + }, + { + "pattern": "STM32SD", + "applicable": true, + "boards": [ "DISCO_F746NG" ] + }, + { + "pattern": "09.USB", + "applicable": true, + "boards": [ "NUCLEO_F429ZI", "DISCO_L475VG_IOT", "DISCO_F407VG" ], + "options": "usb=HID" + }, + { + "pattern": "X_NUCLEO_IDB05A1_HelloWorld.ino", + "applicable": false, + "boards": [ + "NUCLEO_L031K6", + "NUCLEO_L432KC", + "NUCLEO_F303K8", + "BLUEPILL_F103C8", + "MAPLEMINI_F103CB", + "RAK811_TRACKER" + ] + }, + { + "pattern": "X_NUCLEO_IKA01A1_HelloWorld.ino|X_NUCLEO_IHM02A1_HelloWorld.ino", + "applicable": false, + "boards": [ "RAK811_TRACKER" ] + } + ] + }, + { + "maintainer": "Arduino_STM32", + "architecture": "STM32F1", + "boards": [ + { + "name": "mapleMini", + "options": "bootloader_version=original,cpu_speed=speed_72mhz" + } + ], + "sketches": [ + { + "pattern": "sketchbook", + "applicable": true, + "boards": [ "" ] + } + ] + }, + { + "maintainer": "Arduino_STM32", + "architecture": "STM32F4", + "boards": [ + ], + "sketches": [ + { + "pattern": "", + "applicable": false, + "boards": [ "netduino2plus" ] + } + ] + } + ] +} diff --git a/CI/build/conf/exclude_list.txt b/CI/build/conf/exclude_list.txt new file mode 100644 index 0000000000..305937633e --- /dev/null +++ b/CI/build/conf/exclude_list.txt @@ -0,0 +1,16 @@ +Adafruit_Circuit +ArduinoYun +Bridge +Esplora +GSM +firmata_test +mqtt_esp8266 +mqtt_stream +OldStandardFirmata +Robot_Control +Robot_Motor +SpacebrewYun +StandardFirmataBLE +StandardFirmataChipKIT +StandardFirmataWiFi +Temboo diff --git a/CI/build/conf/path_config_travis.json b/CI/build/conf/path_config_travis.json new file mode 100644 index 0000000000..597663e91d --- /dev/null +++ b/CI/build/conf/path_config_travis.json @@ -0,0 +1,7 @@ +{ + "ARDUINO_PATH": "/home/travis/IDE/arduino", + "ARDUINO_PACKAGES": "/home/travis/.arduino15/packages", + "ARDUINO_USER_SKETCHBOOK": "/home/travis/Arduino", + "BUILD_OUPUT_DIR": "/tmp/BuildOutput", + "ROOT_OUPUT_DIR": "/home/travis/arduinoBuilderOutput" +} \ No newline at end of file diff --git a/CI/build/conf/sketch_list.txt b/CI/build/conf/sketch_list.txt new file mode 100644 index 0000000000..cbf92333ce --- /dev/null +++ b/CI/build/conf/sketch_list.txt @@ -0,0 +1,53 @@ +examples/01.Basics/BareMinimum/BareMinimum.ino +examples/01.Basics/AnalogReadSerial/AnalogReadSerial.ino +examples/01.Basics/DigitalReadSerial/DigitalReadSerial.ino +examples/01.Basics/Blink/Blink.ino +examples/03.Analog/AnalogInOutSerial/AnalogInOutSerial.ino +examples/03.Analog/Fading/Fading.ino +examples/03.Analog/Calibration/Calibration.ino +examples/03.Analog/AnalogInput/AnalogInput.ino +examples/09.USB/KeyboardAndMouseControl/KeyboardAndMouseControl.ino +examples/08.Strings/StringSubstring/StringSubstring.ino +examples/08.Strings/StringStartsWithEndsWith/StringStartsWithEndsWith.ino +examples/08.Strings/StringCharacters/StringCharacters.ino +examples/08.Strings/StringToInt/StringToInt.ino +examples/08.Strings/StringReplace/StringReplace.ino +examples/08.Strings/StringCaseChanges/StringCaseChanges.ino +examples/08.Strings/StringLengthTrim/StringLengthTrim.ino +examples/08.Strings/CharacterAnalysis/CharacterAnalysis.ino +examples/07.Display/RowColumnScanning/RowColumnScanning.ino +examples/07.Display/barGraph/barGraph.ino +examples/04.Communication/ReadASCIIString/ReadASCIIString.ino +examples/04.Communication/Midi/Midi.ino +examples/04.Communication/SerialEvent/SerialEvent.ino +examples/04.Communication/MultiSerial/MultiSerial.ino +examples/04.Communication/SerialCallResponse/SerialCallResponse.ino +examples/04.Communication/SerialPassthrough/SerialPassthrough.ino +examples/05.Control/Arrays/Arrays.ino +examples/05.Control/switchCase/switchCase.ino +examples/05.Control/switchCase2/switchCase2.ino +examples/05.Control/ForLoopIteration/ForLoopIteration.ino +examples/05.Control/IfStatementConditional/IfStatementConditional.ino +examples/05.Control/WhileStatementConditional/WhileStatementConditional.ino +examples/02.Digital/StateChangeDetection/StateChangeDetection.ino +examples/02.Digital/Button/Button.ino +examples/02.Digital/toneMelody/toneMelody.ino +examples/02.Digital/DigitalInputPullup/DigitalInputPullup.ino +libraries/Ethernet/examples/WebClient/WebClient.ino +libraries/Ethernet/examples/WebServer/WebServer.ino +libraries/Ethernet/examples/UdpNtpClient/UdpNtpClient.ino +libraries/LiquidCrystal/examples/HelloWorld/HelloWorld.ino +libraries/LiquidCrystal/examples/Display/Display.ino +libraries/TFT/examples/Arduino/TFTBitmapLogo/TFTBitmapLogo.ino +libraries/WiFi/examples/ConnectWithWEP/ConnectWithWEP.ino +libraries/WiFi/examples/WiFiWebServer/WiFiWebServer.ino +libraries/WiFi/examples/ConnectWithWPA/ConnectWithWPA.ino +libraries/WiFi/examples/WiFiUdpSendReceiveString/WiFiUdpSendReceiveString.ino +libraries/WiFi/examples/WiFiWebClient/WiFiWebClient.ino +libraries/Servo/examples/Knob/Knob.ino +libraries/Firmata/examples/StandardFirmata/StandardFirmata.ino +libraries/SD/examples/Datalogger/Datalogger.ino +libraries/SD/examples/CardInfo/CardInfo.ino +libraries/SD/examples/DumpFile/DumpFile.ino +libraries/SD/examples/listfiles/listfiles.ino +libraries/Stepper/examples/stepper_speedControl/stepper_speedControl.ino From dbd75d73ac42032935bc8001008d81f4ece14ae5 Mon Sep 17 00:00:00 2001 From: Angela Randolph Date: Thu, 21 Jun 2018 13:37:02 +0200 Subject: [PATCH 007/109] Create .travis.yml Signed-off-by: Angela Randolph --- .travis.yml | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .travis.yml diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000000..b6785dcd85 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,38 @@ +language: python +python: + - "3.6" +os: + - linux +matrix: + include: + - env: + - NAME= arduinoCI + - IDE_VERSION=1.8.5 + # Use in CI/build/conf/path_config_travis.json + - ARDUINO_IDE_PATH=$HOME/IDE/arduino + install: + # Install Arduino IDE + - mkdir -p $ARDUINO_IDE_PATH + - wget http://downloads.arduino.cc/arduino-$IDE_VERSION-linux64.tar.xz + - tar xf arduino-$IDE_VERSION-linux64.tar.xz --strip-components=1 -C $ARDUINO_IDE_PATH + - rm arduino-$IDE_VERSION-linux64.tar.xz + # Install STM32 core supported by ST + - cd $ARDUINO_IDE_PATH + # Add json packages url to the Arduino IDE + - ./arduino --save-prefs --pref "boardsmanager.additional.urls=https://github.com/stm32duino/BoardManagerFiles/raw/master/STM32/package_stm_index.json" + # Install the latest core version + - ./arduino --install-boards STM32:stm32 + - rm -fr $HOME/.arduino15/packages/STM32/hardware/stm32/* + # Replace default core with the one being built + - sudo ln -s $TRAVIS_BUILD_DIR $HOME/.arduino15/packages/STM32/hardware/stm32/* + before_script: + - cd $TRAVIS_BUILD_DIR/CI/build/ + - cp ./conf/path_config_travis.json ./path_config.json + script: + - python arduino-builder.py --travis + after_failure: + - echo " The build is failed. If script return a non-zero return status , we suggest you to take the above logs into consideration. Otherwise, consult the TRAVIS CI documentation to learn more about build failure" +notifications: + email: + on_success: always + on_failure: always From a68d97d642206c3eb0fec288f33f78e18e73772a Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 17:12:59 +0200 Subject: [PATCH 008/109] Update STM32F3xx HAL Drivers to v1.5.2 Included in STM32CubeF3 FW V1.10.0 Signed-off-by: Frederic.Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 694 ++-- .../Inc/Legacy/stm32f3xx_hal_can_legacy.h | 819 +++++ .../STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h | 11 + .../Inc/stm32f3xx_hal_can.h | 787 +++-- .../Inc/stm32f3xx_hal_comp.h | 26 +- .../Inc/stm32f3xx_hal_comp_ex.h | 365 +-- .../Inc/stm32f3xx_hal_conf_template.h | 5 + .../Inc/stm32f3xx_hal_hrtim.h | 264 +- .../Inc/stm32f3xx_hal_rcc.h | 2 +- .../Inc/stm32f3xx_hal_sdadc.h | 100 +- .../Inc/stm32f3xx_ll_comp.h | 80 +- .../Inc/stm32f3xx_ll_tim.h | 9 +- .../Inc/stm32f3xx_ll_utils.h | 1 - .../STM32F3xx_HAL_Driver/Release_Notes.html | 32 +- .../Src/Legacy/stm32f3xx_hal_can.c | 1700 ++++++++++ .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c | 8 +- .../Src/stm32f3xx_hal_can.c | 2789 +++++++++-------- .../Src/stm32f3xx_hal_comp.c | 216 +- .../Src/stm32f3xx_hal_dma.c | 16 +- .../Src/stm32f3xx_hal_flash.c | 4 +- .../Src/stm32f3xx_hal_hrtim.c | 463 +-- .../Src/stm32f3xx_hal_rcc.c | 136 +- .../Src/stm32f3xx_hal_rtc.c | 6 +- .../Src/stm32f3xx_hal_sdadc.c | 144 +- .../Src/stm32f3xx_hal_tim.c | 24 + .../Src/stm32f3xx_hal_tim_ex.c | 142 +- .../Src/stm32f3xx_ll_comp.c | 40 +- .../Src/stm32f3xx_ll_rcc.c | 15 + .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 29 files changed, 5977 insertions(+), 2923 deletions(-) create mode 100644 system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32f3xx_hal_can_legacy.h create mode 100644 system/Drivers/STM32F3xx_HAL_Driver/Src/Legacy/stm32f3xx_hal_can.c diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d261da88f6..d08046169f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -35,8 +35,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { @@ -58,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -90,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -109,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -136,7 +136,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -152,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -224,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -253,28 +255,116 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32H7 */ + /** * @} */ @@ -282,7 +372,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -354,15 +444,39 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -375,7 +489,7 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ @@ -385,7 +499,7 @@ #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 @@ -398,7 +512,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -426,22 +540,31 @@ #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -467,7 +590,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -540,7 +663,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -570,7 +693,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -594,11 +717,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -607,14 +730,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -623,7 +746,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -635,18 +758,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -659,31 +782,27 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -691,15 +810,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -720,7 +839,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -738,7 +857,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -754,13 +873,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -818,6 +937,14 @@ #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif /** * @} */ @@ -861,7 +988,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -901,7 +1028,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -926,7 +1053,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -944,9 +1071,12 @@ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ @@ -958,7 +1088,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -973,39 +1103,39 @@ /** * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1018,11 +1148,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1032,12 +1162,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1045,7 +1175,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1126,6 +1256,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1139,17 +1271,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1160,7 +1292,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1172,31 +1304,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1211,8 +1343,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1221,7 +1353,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1229,6 +1361,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1240,7 +1373,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1310,7 +1443,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1337,7 +1469,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1410,7 +1542,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1597,7 +1729,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1616,11 +1748,11 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) @@ -1643,11 +1775,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1658,7 +1790,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1667,7 +1799,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1696,8 +1828,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1762,7 +1894,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1770,37 +1902,37 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1817,7 +1949,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2045,6 +2177,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2236,13 +2383,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2295,111 +2442,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2407,29 +2554,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2445,8 +2591,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2468,8 +2612,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2633,7 +2775,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2641,6 +2783,30 @@ #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG @@ -2694,7 +2860,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2810,17 +2981,19 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32WL) +#else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2856,7 +3029,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2881,26 +3054,26 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2909,8 +3082,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2940,6 +3113,17 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif /** * @} */ @@ -2958,7 +3142,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2990,7 +3174,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -3002,8 +3186,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3108,7 +3292,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3117,7 +3301,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3128,7 +3312,10 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#if defined(STM32F7) +#else #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +#endif /** * @} */ @@ -3154,11 +3341,22 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ @@ -3167,7 +3365,7 @@ } #endif -#endif /* ___STM32_HAL_LEGACY */ +#endif /* STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32f3xx_hal_can_legacy.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32f3xx_hal_can_legacy.h new file mode 100644 index 0000000000..ca30cfa04f --- /dev/null +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32f3xx_hal_can_legacy.h @@ -0,0 +1,819 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_CAN_H +#define __STM32F3xx_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ + defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ + defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F302x8) || \ + defined(STM32F373xC) || defined(STM32F378xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t BankNumber; /*!< Select the start slave bank filter + F3 devices don't support CAN2 interface (Slave). Therefore this parameter + is meaningless but it has been kept for compatibility accross STM32 families */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code + This parameter can be a value of @ref CAN_Error_Code */ + +}CAN_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ + +/** + * @} + */ + + +/** @defgroup CAN_interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ + +/** + * @} + */ + +/** @defgroup CAN_Mailboxes CAN Mailboxes +* @{ +*/ +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__ CAN handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) + + /** + * @brief Release the specified receive FIFO. + * @param __HANDLE__ CAN handle. + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__ specifies the CAN Handle. + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disables the DBG Freeze for CAN. + * @param __HANDLE__ specifies the CAN Handle. + * @param __NEWSTATE__ new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) +#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) + +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F302x8 || */ + /* STM32F373xC || STM32F378xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_CAN_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h index 9762483f59..8f57ea8f77 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h @@ -900,6 +900,17 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); * @} */ +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @{ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h index ca30cfa04f..cc84073db8 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h @@ -34,19 +34,13 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F3xx_CAN_H -#define __STM32F3xx_CAN_H +#ifndef STM32F3xx_HAL_CAN_H +#define STM32F3xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ - defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ - defined(STM32F302x8) || \ - defined(STM32F373xC) || defined(STM32F378xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" @@ -54,6 +48,7 @@ * @{ */ +#if defined (CAN) /** @addtogroup CAN * @{ */ @@ -61,96 +56,90 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ - */ -/** - * @brief HAL State structures definition - */ + */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ - -}HAL_CAN_StateTypeDef; - -/** + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE. */ -}CAN_InitTypeDef; - -/** + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** * @brief CAN filter configuration structure definition */ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + This parameter mus be a number between Min_Data = 0 and Max_Data = 13. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -159,25 +148,26 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t BankNumber; /*!< Select the start slave bank filter - F3 devices don't support CAN2 interface (Slave). Therefore this parameter - is meaningless but it has been kept for compatibility accross STM32 families */ - -}CAN_FilterConfTypeDef; + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + STM32F3xx devices don't support slave CAN instance (dual CAN). Therefore + this parameter is meaningless but it has been kept for compatibility accross + STM32 families. */ + +} CAN_FilterTypeDef; -/** - * @brief CAN Tx message structure definition +/** + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ @@ -187,65 +177,59 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - -}CanTxMsgTypeDef; + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -/** - * @brief CAN Rx message structure definition +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ - -}CanRxMsgTypeDef; + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ -/** - * @brief CAN handle Structure definition - */ -typedef struct +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +} CAN_HandleTypeDef; - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - __IO uint32_t ErrorCode; /*!< CAN Error code - This parameter can be a value of @ref CAN_Error_Code */ - -}CAN_HandleTypeDef; /** * @} */ @@ -259,19 +243,32 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ -#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ -#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ -#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + /** * @} */ @@ -280,7 +277,7 @@ typedef struct * @{ */ #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -349,8 +346,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -358,8 +355,17 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ /** * @} */ @@ -367,8 +373,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -376,8 +382,8 @@ typedef struct /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ -#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -385,101 +391,100 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ -/** @defgroup CAN_flags CAN Flags +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ +/** @defgroup CAN_flags CAN Flags + * @{ + */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ -#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ -#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ -#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ -#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ - +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ - -/** @defgroup CAN_interrupts CAN Interrupts + +/** @defgroup CAN_Interrupts CAN Interrupts * @{ - */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ - -/** - * @} - */ - -/** @defgroup CAN_Mailboxes CAN Mailboxes -* @{ -*/ -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ @@ -502,7 +507,8 @@ typedef struct /** * @brief Enable the specified CAN interrupts. * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) @@ -510,198 +516,175 @@ typedef struct /** * @brief Disable the specified CAN interrupts. * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__ CAN handle. - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) +/** + * @} + */ -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the CAN Handle. - * @param __INTERRUPT__ specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__ CAN handle. - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ - /** - * @brief Release the specified receive FIFO. - * @param __HANDLE__ CAN handle. - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** - * @brief Cancel a transmit request. - * @param __HANDLE__ specifies the CAN Handle. - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); /** - * @brief Enable or disables the DBG Freeze for CAN. - * @param __HANDLE__ specifies the CAN Handle. - * @param __NEWSTATE__ new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management * @{ */ - -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions * @{ */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + /** * @} - */ - + */ + /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -719,13 +702,12 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ #define CAN_FLAG_MASK (0x000000FFU) /** * @} @@ -740,55 +722,50 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) - +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) - -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) - +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) - #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) - +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) - -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) -#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U)) - +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) - #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} @@ -799,21 +776,17 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ + +#endif /* CAN */ /** * @} */ -#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ - /* STM32F302xC || STM32F303xC || STM32F358xx || */ - /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ - /* STM32F302x8 || */ - /* STM32F373xC || STM32F378xx */ - #ifdef __cplusplus } #endif -#endif /* __STM32F3xx_CAN_H */ +#endif /* STM32F3xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h index 0f3ab649b3..2ed0a89153 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h @@ -30,7 +30,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -38,7 +38,7 @@ #define __STM32F3xx_HAL_COMP_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,12 +52,12 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup COMP_Exported_Types COMP Exported Types * @{ */ -/** - * @brief COMP Init structure definition +/** + * @brief COMP Init structure definition */ typedef struct { @@ -90,13 +90,13 @@ typedef struct uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available). This parameter can be a value of @ref COMPEx_WindowMode */ - + uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode). This parameter can be a value of @ref COMP_TriggerMode */ -}COMP_InitTypeDef; +} COMP_InitTypeDef; -/** +/** * @brief HAL State structures definition */ typedef enum @@ -106,9 +106,9 @@ typedef enum HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ -}HAL_COMP_StateTypeDef; +} HAL_COMP_StateTypeDef; -/** +/** * @brief COMP Handle Structure definition */ typedef struct @@ -117,7 +117,7 @@ typedef struct COMP_InitTypeDef Init; /*!< COMP required parameters */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ -}COMP_HandleTypeDef; +} COMP_HandleTypeDef; /** * @} @@ -139,7 +139,7 @@ typedef struct /** @defgroup COMP_OutputLevel COMP Output Level * @{ - */ + */ /* When output polarity is not inverted, comparator output is low when the non-inverting input is at a lower voltage than the inverting input*/ #define COMP_OUTPUTLEVEL_LOW (0x00000000U) @@ -202,7 +202,7 @@ typedef struct */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h index 8a2a937e7c..f4fe440449 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h @@ -30,7 +30,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -38,7 +38,7 @@ #define __STM32F3xx_HAL_COMP_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,9 +50,9 @@ /** @defgroup COMPEx COMPEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup COMPEx_Exported_Constants COMP Extended Exported Constants * @{ @@ -89,7 +89,9 @@ #define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6) +#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2), + connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB2 for COMP4, PB15 for COMP6) connected to comparator inverting input */ /* Aliases for compatibility */ #define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1 @@ -112,7 +114,7 @@ #define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2), connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_IO2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< IO2 (PB2 for COMP4, PB15 for COMP6) +#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB2 for COMP4, PB15 for COMP6) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC2_CH1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_CH1_OUT connected to comparator inverting input */ @@ -156,7 +158,7 @@ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ /** * @} - */ + */ #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices) * @{ @@ -166,7 +168,7 @@ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */ /** * @} - */ + */ #elif defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices) * @{ @@ -187,7 +189,7 @@ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ /** * @} - */ + */ #else /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices) * @{ @@ -226,7 +228,7 @@ #define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ /** * @} - */ + */ #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** @defgroup COMPEx_Output COMP Extended Output (STM32F303x8/STM32F334x8/STM32F328xx Product devices) * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb @@ -257,7 +259,7 @@ #define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ /** * @} - */ + */ #elif defined(STM32F302xC) || defined(STM32F302xE) /** @defgroup COMPEx_Output COMP Extended Output (STM32F302xC/STM32F302xE Product devices) * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb @@ -291,7 +293,7 @@ #define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */ /** * @} - */ + */ #elif defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup COMPEx_Output COMP Extended Output (STM32F303xC/STM32F358xx Product devices) * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb @@ -346,7 +348,7 @@ #define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ /** * @} - */ + */ #elif defined(STM32F303xE) || defined(STM32F398xx) /** @defgroup COMPEx_Output COMP Extended Output (STM32F303xE/STM32F398xx Product devices) * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb @@ -406,7 +408,7 @@ #define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ /** * @} - */ + */ #elif defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup COMPEx_Output COMP Extended Output (STM32F373xC/STM32F378xx Product devices) * Elements value convention: 00000XXX000000YYb @@ -432,7 +434,7 @@ #define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U) /*!< COMP2 output connected to TIM3 OCREF Clear */ /** * @} - */ + */ #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) @@ -554,7 +556,7 @@ #endif /* STM32F302xE || */ /* STM32F302xC */ - + #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F303xE/STM32F398xx/STM32F303xC/STM32F358xx Product devices) @@ -650,12 +652,12 @@ } \ CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \ } while(0U) - + /** * @brief Lock a comparator instance * @param __HANDLE__ COMP handle * @retval None. - */ + */ #define __HAL_COMP_LOCK(__HANDLE__) \ do { \ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \ @@ -674,9 +676,9 @@ * @arg @ref COMP_FLAG_LOCK lock flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \ - (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \ - (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__)))) +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \ + (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__)))) #else @@ -698,7 +700,7 @@ * @brief Lock a comparator instance * @param __HANDLE__ COMP handle * @retval None. - */ + */ #define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK) /** @brief Check whether the specified COMP flag is set or not. @@ -708,7 +710,7 @@ * @arg @ref COMP_FLAG_LOCK lock flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) #endif /* STM32F373xC || STM32F378xx */ @@ -719,49 +721,49 @@ /** * @brief Enable the COMP1 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP1 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) /** @@ -793,7 +795,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) - + /** * @brief Clear the COMP1 EXTI flag. * @retval None @@ -807,49 +809,49 @@ /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP2 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) /** @@ -881,7 +883,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) - + /** * @brief Clear the COMP2 EXTI flag. * @retval None @@ -894,49 +896,49 @@ /** * @brief Enable the COMP3 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3) /** * @brief Disable the COMP3 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3) /** * @brief Enable the COMP3 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3) /** * @brief Disable the COMP3 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3) /** * @brief Enable the COMP3 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP3 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3) /** @@ -968,7 +970,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP3_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP3) - + /** * @brief Clear the COMP3 EXTI flag. * @retval None @@ -986,49 +988,49 @@ /** * @brief Enable the COMP4 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4) /** * @brief Disable the COMP4 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4) /** * @brief Enable the COMP4 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4) /** * @brief Disable the COMP4 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4) /** * @brief Enable the COMP4 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP4 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP4 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4) /** @@ -1060,7 +1062,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP4_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP4) - + /** * @brief Clear the COMP4 EXTI flag. * @retval None @@ -1078,49 +1080,49 @@ /** * @brief Enable the COMP5 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5) /** * @brief Disable the COMP5 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5) /** * @brief Enable the COMP5 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5) /** * @brief Disable the COMP5 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5) /** * @brief Enable the COMP5 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP5 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP5 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP5_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5) /** @@ -1152,7 +1154,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP5_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP5) - + /** * @brief Clear the COMP5 EXTI flag. * @retval None @@ -1170,49 +1172,49 @@ /** * @brief Enable the COMP6 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6) /** * @brief Disable the COMP6 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6) /** * @brief Enable the COMP6 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6) /** * @brief Disable the COMP6 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6) /** * @brief Enable the COMP6 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP6 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP6 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP6_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6) /** @@ -1244,7 +1246,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP6_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP6) - + /** * @brief Clear the COMP6 EXTI flag. * @retval None @@ -1261,49 +1263,49 @@ /** * @brief Enable the COMP7 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7) /** * @brief Disable the COMP7 EXTI line rising edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7) /** * @brief Enable the COMP7 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7) /** * @brief Disable the COMP7 EXTI line falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7) /** * @brief Enable the COMP7 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the COMP7 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Enable the COMP7 EXTI line in interrupt mode. * @retval None - */ + */ #define __HAL_COMP_COMP7_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7) /** @@ -1335,7 +1337,7 @@ * @retval RESET or SET */ #define __HAL_COMP_COMP7_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP7) - + /** * @brief Clear the COMP7 EXTI flag. * @retval None @@ -1348,7 +1350,7 @@ /** * @} */ - + /* Private types -------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup COMPEx_Private_Constants COMP Extended Private Constants @@ -1356,7 +1358,7 @@ */ /** @defgroup COMPEx_ExtiLineEvent COMP Extended EXTI lines * @{ - */ + */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) @@ -1411,22 +1413,22 @@ /** @defgroup COMPEx_Misc COMP Extended miscellaneous defines * @{ - */ + */ /* CSR masks redefinition for internal use */ #define COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL /*!< COMP_CSR_COMPxINSEL Mask */ -#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL /*!< COMP_CSR_COMPxOUTSEL Mask */ +#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL /*!< COMP_CSR_COMPxOUTSEL Mask */ #define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */ #if defined(STM32F373xC) || defined(STM32F378xx) -/* CSR register reset value */ +/* CSR register reset value */ #define COMP_CSR_RESET_VALUE (0x00000000U) #define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU) #define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU) -/* CSR COMP1/COMP2 shift */ +/* CSR COMP1/COMP2 shift */ #define COMP_CSR_COMP1_SHIFT 0U #define COMP_CSR_COMP2_SHIFT 16U #else -/* CSR register reset value */ +/* CSR register reset value */ #define COMP_CSR_RESET_VALUE (0x00000000U) #endif /* STM32F373xC || STM32F378xx */ @@ -1482,7 +1484,7 @@ /** @defgroup COMPEx_Private_Macros COMP Extended Private Macros * @{ */ -/** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle +/** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ @@ -1511,7 +1513,7 @@ COMP_EXTI_LINE_COMP6) #endif /* STM32F302xE || */ /* STM32F302xC */ - + #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /** @@ -1528,7 +1530,7 @@ COMP_EXTI_LINE_COMP7) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ - + #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Get the specified EXTI line for a comparator instance @@ -1545,7 +1547,7 @@ /** @defgroup COMPEx_Private_Macros_Misc COMP Extended miscellaneous private macros * @{ - */ + */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @@ -1553,8 +1555,7 @@ * @param __HANDLE__ COMP handle * @note The common output selection is checked versus the COMP instance to set the right output configuration * @retval None. - */ - + */ #define COMP_INIT(__HANDLE__) \ do { \ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \ @@ -1586,7 +1587,7 @@ * @brief DeInit a comparator instance * @param __HANDLE__ COMP handle * @retval None. - */ + */ #define COMP_DEINIT(__HANDLE__) \ do { \ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \ @@ -1604,47 +1605,47 @@ /** * @brief Enable the Exti Line rising edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__)) /** * @brief Disable the Exti Line rising edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)) /** * @brief Enable the Exti Line falling edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__)) /** * @brief Disable the Exti Line falling edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)) /** * @brief Enable the COMP Exti Line interrupt generation. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__)) - + /** * @brief Disable the COMP Exti Line interrupt generation. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__)) @@ -1652,15 +1653,15 @@ /** * @brief Enable the COMP Exti Line event generation. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__)) - + /** * @brief Disable the COMP Exti Line event generation. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__)) @@ -1668,15 +1669,15 @@ /** * @brief Check whether the specified EXTI line flag is set or not. * @param __FLAG__ specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval The state of __FLAG__ (SET or RESET). */ #define COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__)) - + /** * @brief Clear the COMP Exti flags. * @param __FLAG__ specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__)) @@ -1688,10 +1689,10 @@ * @brief Init a comparator instance * @param __HANDLE__ COMP handle * @retval None. - */ + */ #define COMP_INIT(__HANDLE__) \ do { \ - __IO uint32_t csrreg = 0U; \ + __IO uint32_t csrreg = 0U; \ \ csrreg = READ_REG((__HANDLE__)->Instance->CSR); \ MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \ @@ -1709,53 +1710,53 @@ * @brief DeInit a comparator instance * @param __HANDLE__ COMP handle * @retval None. - */ + */ #define COMP_DEINIT(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->CSR, COMP_CSR_RESET_VALUE) /** * @brief Enable the Exti Line rising edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_RISING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->RTSR2, (__EXTILINE__)) : SET_BIT(EXTI->RTSR, (__EXTILINE__))) /** * @brief Disable the Exti Line rising edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_RISING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->RTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))) /** * @brief Enable the Exti Line falling edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->FTSR2, (__EXTILINE__)) : SET_BIT(EXTI->FTSR, (__EXTILINE__))) /** * @brief Disable the Exti Line falling edge trigger. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->FTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))) /** * @brief Enable the COMP Exti Line interrupt generation. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_ENABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->IMR2, (__EXTILINE__)) : SET_BIT(EXTI->IMR, (__EXTILINE__))) - + /** * @brief Disable the COMP Exti Line interrupt generation. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_DISABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->IMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->IMR, (__EXTILINE__))) @@ -1763,15 +1764,15 @@ /** * @brief Enable the COMP Exti Line event generation. * @param __EXTILINE__ specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. - */ + */ #define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->EMR2, (__EXTILINE__)) : SET_BIT(EXTI->EMR, (__EXTILINE__))) - + /** * @brief Disable the COMP Exti Line event generation. * @param __EXTILINE__ specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->EMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->EMR, (__EXTILINE__))) @@ -1779,15 +1780,15 @@ /** * @brief Check whether the specified EXTI line flag is set or not. * @param __FLAG__ specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval The state of __FLAG__ (SET or RESET). */ #define COMP_EXTI_GET_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? READ_BIT(EXTI->PR2, (__FLAG__)) : READ_BIT(EXTI->PR, (__FLAG__))) - + /** * @brief Clear the COMP Exti flags. * @param __FLAG__ specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMPEx_ExtiLineEvent + * This parameter can be a value of @ref COMPEx_ExtiLineEvent * @retval None. */ #define COMP_EXTI_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? WRITE_REG(EXTI->PR2, (__FLAG__)) : WRITE_REG(EXTI->PR, (__FLAG__))) @@ -1801,7 +1802,7 @@ * - On devices STM32F302x, STM32F32xx, STM32F33x, there is * only 1 comparator inverting input connected to a GPIO. * Legacy definition of literal COMP_INVERTINGINPUT_IO1 - * was initially the only selection, but depending on + * was initially the only selection, but depending on * comparator instance it corresponds to COMP_INVERTINGINPUT_IO2 * (for instances COMP4, COMP6). * Since, COMP_INVERTINGINPUT_IO2 has been created and this macro @@ -1809,7 +1810,7 @@ * of comparator instance. * - On other STM32F3 devices, this macro performs no action. * @param __COMP_INSTANCE__ COMP instance - * @param __INVERTINGINPUT__ COMP inverting input + * @param __INVERTINGINPUT__ COMP inverting input * @retval None. */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) @@ -1843,7 +1844,7 @@ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) - + #define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ @@ -2383,7 +2384,7 @@ || \ (((INPUT) == COMP_NONINVERTINGINPUT_IO1))) -#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */ +#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */ #define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */ @@ -2780,11 +2781,11 @@ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h index 75277b5f75..95b297a87e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h @@ -51,6 +51,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_CEC_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED @@ -202,6 +203,10 @@ #include "stm32f3xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f3xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f3xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h index 71e0563b6f..dfbdc7406f 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h @@ -41,8 +41,7 @@ extern "C" { #endif -#if defined(STM32F334x8) - +#if defined(HRTIM1) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" @@ -82,7 +81,7 @@ typedef struct This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger - to be synchronized) or a master (generating a synchronization signal) or both. + to be synchronized) or a master (generating a synchronization signal) or both. This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when the HRTIM instance is configured as a slave). @@ -241,7 +240,7 @@ typedef struct { uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. Specifies the size of the DMA transfer */ uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. - Specifies whether or not hald mode is enabled + Specifies whether or not half mode is enabled This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). @@ -308,30 +307,30 @@ typedef struct { * @brief Capture unit configuration definition */ typedef struct { - uint32_t Trigger; /*!< Specifies source(s) triggering the capture. - This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ + uint32_t Trigger; /*!< Specifies source(s) triggering the capture. + This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ } HRTIM_CaptureCfgTypeDef; /** * @brief Output configuration definition */ typedef struct { - uint32_t Polarity; /*!< Specifies the output polarity. - This parameter can be any value of @ref HRTIM_Output_Polarity */ - uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. - This parameter can be a combination of @ref HRTIM_Output_Set_Source */ - uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. - This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ - uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. - This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ - uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. - This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ - uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. - This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ - uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled - This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ - uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. - This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ + uint32_t Polarity; /*!< Specifies the output polarity. + This parameter can be any value of @ref HRTIM_Output_Polarity */ + uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. + This parameter can be a combination of @ref HRTIM_Output_Set_Source */ + uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. + This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ + uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. + This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ + uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. + This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ + uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. + This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ + uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled + This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ + uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. + This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ } HRTIM_OutputCfgTypeDef; /** @@ -407,7 +406,7 @@ typedef struct { uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. This parameter can be a value of @ref HRTIM_Fault_Filter */ uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. - This parameter can be a value of @ref HRTIM_Fault_Lock */ + This parameter can be a value of @ref HRTIM_Fault_Lock */ } HRTIM_FaultCfgTypeDef; /** @@ -443,7 +442,7 @@ typedef struct { /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants * @{ @@ -535,22 +534,21 @@ typedef struct { /** * @} */ - /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels * @{ * @brief Constants defining external event channel identifiers */ -#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ -#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ -#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ -#define HRTIM_EVENT_3 (0x00000004U) /*!< External event channel 3 identifier */ -#define HRTIM_EVENT_4 (0x00000008U) /*!< External event channel 4 identifier */ -#define HRTIM_EVENT_5 (0x00000010U) /*!< External event channel 5 identifier */ -#define HRTIM_EVENT_6 (0x00000020U) /*!< External event channel 6 identifier */ -#define HRTIM_EVENT_7 (0x00000040U) /*!< External event channel 7 identifier */ -#define HRTIM_EVENT_8 (0x00000080U) /*!< External event channel 8 identifier */ -#define HRTIM_EVENT_9 (0x00000100U) /*!< External event channel 9 identifier */ -#define HRTIM_EVENT_10 (0x00000200U) /*!< External event channel 10 identifier */ +#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ +#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ +#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ +#define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ +#define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ +#define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ +#define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ +#define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ +#define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ +#define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ +#define HRTIM_EVENT_10 (0x00000010U) /*!< External event channel 10 identifier */ /** * @} */ @@ -605,7 +603,7 @@ typedef struct { /** * @} */ - + /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event * @{ * @brief Constants defining the timer behavior following the synchronization event @@ -706,7 +704,7 @@ typedef struct { * @{ * @brief Constants defining whether a faut channel is enabled for a timer */ -#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ +#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ @@ -754,15 +752,15 @@ typedef struct { #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ -#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ +#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ /** * @} */ @@ -829,12 +827,12 @@ typedef struct { * counter reset or roll-over to 0 after reaching the period value * in continuous mode */ -#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ +#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ /** * @} */ - + /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode * @{ * @brief Constants defining whether the compare register is behaving in @@ -881,7 +879,7 @@ typedef struct { * @brief Constants defining the events that can be selected to configure the * set crossbar of a timer output */ -#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ +#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ @@ -922,7 +920,7 @@ typedef struct { * @brief Constants defining the events that can be selected to configure the * set crossbar of a timer output */ -#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ +#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ @@ -963,7 +961,7 @@ typedef struct { * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered */ -#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ +#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ /** * @} @@ -973,7 +971,7 @@ typedef struct { * @{ * @brief Constants defining the output level when output is in IDLE state */ -#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ +#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ /** * @} @@ -983,7 +981,7 @@ typedef struct { * @{ * @brief Constants defining the output level when output is in FAULT state */ -#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ +#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ @@ -996,7 +994,7 @@ typedef struct { * @brief Constants defining whether or not chopper mode is enabled for a timer output */ -#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ +#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ /** * @} @@ -1007,18 +1005,19 @@ typedef struct { * @brief Constants defining the idle mode entry is delayed by forcing a deadtime insertion before switching the outputs to their idle state */ -#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ +#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */ /** * @} */ + /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger * @{ * @brief Constants defining the events that can be selected to trigger the * capture of the timing unit counter */ -#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ +#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ @@ -1053,6 +1052,9 @@ typedef struct { /** * @} */ +/** + * @} + */ /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter * @{ @@ -1090,7 +1092,7 @@ typedef struct { /** * @} */ - + /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio * @{ * @brief Constants defining division ratio between the timer clock frequency @@ -1146,7 +1148,7 @@ typedef struct { * @brief Constants defining whether the deadtime is positive or negative * (overlapping signal) on falling edge */ -#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */ +#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */ #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */ /** * @} @@ -1157,7 +1159,7 @@ typedef struct { * @brief Constants defining whether or not the deadtime (falling sign and * value) is write protected */ -#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */ +#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */ #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */ /** * @} @@ -1168,7 +1170,7 @@ typedef struct { * @brief Constants defining whether or not the deadtime falling sign is write * protected */ -#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */ +#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */ #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */ /** * @} @@ -1203,7 +1205,7 @@ typedef struct { * @brief Constants defining the duty cycle of the generated high frequency carrier * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) */ -#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ +#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ @@ -1220,7 +1222,7 @@ typedef struct { * @brief Constants defining the pulse width of the first pulse of the generated * high frequency carrier */ -#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ +#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ @@ -1257,7 +1259,7 @@ typedef struct { * @{ * @brief Constants defining defining the synchronization input source */ -#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ +#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ /** @@ -1269,7 +1271,7 @@ typedef struct { * @brief Constants defining the source and event to be sent on the * synchronization outputs */ -#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */ +#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */ #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/ #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */ #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */ @@ -1281,7 +1283,7 @@ typedef struct { * @{ * @brief Constants defining the routing and conditioning of the synchronization output event */ -#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ +#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ /** @@ -1328,9 +1330,8 @@ typedef struct { * @brief Constants defining whether or not an external event is programmed in fast mode */ - -#define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ -#define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ +#define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ +#define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ /** * @} */ @@ -1376,20 +1377,20 @@ typedef struct { /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources * @{ - * @brief Constants defining whether a faults is be triggered by any external + * @brief Constants defining whether a fault is triggered by any external * or internal fault source */ -#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ +#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ /** * @} */ - + /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity * @{ * @brief Constants defining the polarity of a fault event */ -#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ +#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ /** * @} @@ -1419,13 +1420,13 @@ typedef struct { /** * @} */ - + /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock * @{ * @brief Constants defining whether or not the fault programming bits are write protected */ -#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ +#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ /** * @} @@ -1450,7 +1451,7 @@ typedef struct { * @brief Constants defining if the burst mode is entered once or if it is * continuously operating */ -#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ +#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ /** * @} @@ -1516,7 +1517,7 @@ typedef struct { * @brief Constants defining the events that can be used tor trig the burst * mode operation */ -#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ +#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ @@ -1557,7 +1558,7 @@ typedef struct { * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register). */ -#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ +#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ @@ -1573,7 +1574,7 @@ typedef struct { * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 */ -#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ +#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ @@ -1640,7 +1641,6 @@ typedef struct { #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ - /** * @} */ @@ -1663,7 +1663,7 @@ typedef struct { * @brief Constants defining the registers that can be written during a burst * DMA operation */ -#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ +#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ @@ -1693,7 +1693,7 @@ typedef struct { * @{ * @brief Constants used to enable or disable the burst mode controller */ -#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ +#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ /** * @} @@ -1705,10 +1705,6 @@ typedef struct { */ #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ - -#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) /** * @} */ @@ -1773,7 +1769,7 @@ typedef struct { * @{ * @brief Constants defining the operating state of the burst mode controller */ -#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ +#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ /** * @} @@ -1784,7 +1780,7 @@ typedef struct { * @brief Constants defining on which output the signal is currently applied * in push-pull mode */ -#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ +#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ /** * @} @@ -1796,7 +1792,7 @@ typedef struct { * push-pull mode balanced fault mode or delayed idle mode, when the * protection was triggered */ -#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ +#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ /** * @} @@ -1805,7 +1801,7 @@ typedef struct { /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable * @{ */ -#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ +#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ @@ -1821,7 +1817,7 @@ typedef struct { /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable * @{ */ -#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ +#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ @@ -1836,7 +1832,7 @@ typedef struct { /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable * @{ */ -#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ +#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ @@ -1876,10 +1872,10 @@ typedef struct { #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ -#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ -#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ -#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ -#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ +#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ +#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ +#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ +#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ /** * @} */ @@ -1908,7 +1904,7 @@ typedef struct { /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable * @{ */ -#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ +#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ @@ -1923,7 +1919,7 @@ typedef struct { /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable * @{ */ -#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ +#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ @@ -1950,7 +1946,6 @@ typedef struct { /** @addtogroup HRTIM_Private_Macros HRTIM Private Macros * @{ */ - #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ @@ -1977,7 +1972,7 @@ typedef struct { #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) - + #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ @@ -2002,7 +1997,8 @@ typedef struct { ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_1) || \ + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ ((EVENT) == HRTIM_EVENT_2) || \ ((EVENT) == HRTIM_EVENT_3) || \ ((EVENT) == HRTIM_EVENT_4) || \ @@ -2052,7 +2048,7 @@ typedef struct { (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) -#define IS_HHRTIM_DACSYNC(DACSYNC)\ +#define IS_HRTIM_DACSYNC(DACSYNC)\ (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ @@ -2078,10 +2074,9 @@ typedef struct { ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) -#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \ - (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) - +#define IS_HRTIM_TIMERBURSTMODE(MODE) \ + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) @@ -2089,10 +2084,8 @@ typedef struct { #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) - #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) - #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) @@ -2120,7 +2113,22 @@ typedef struct { #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) -#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U) +#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U) + +#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + +#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + +#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ @@ -2241,6 +2249,7 @@ typedef struct { (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ @@ -2362,7 +2371,7 @@ typedef struct { ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) - + #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) @@ -2376,11 +2385,11 @@ typedef struct { ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) - + #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) - + #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) @@ -2528,20 +2537,25 @@ typedef struct { ((FILTER) == HRTIM_EVENTFILTER_13) || \ ((FILTER) == HRTIM_EVENTFILTER_14) || \ ((FILTER) == HRTIM_EVENTFILTER_15)))) - + #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) +#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ @@ -2648,7 +2662,7 @@ typedef struct { ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ @@ -2669,22 +2683,23 @@ typedef struct { (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) - + #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) - + + #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U) #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U) - + #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) -#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U) +#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) @@ -2768,7 +2783,8 @@ typedef struct { }\ }\ } while(0U) - + + /** @brief Enables or disables the specified HRTIM common interrupts. * @param __HANDLE__ specifies the HRTIM Handle. * @param __INTERRUPT__ specifies the interrupt source to enable or disable. @@ -3168,7 +3184,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); - + HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate); @@ -3445,14 +3461,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); - HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); - HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3501,7 +3515,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, /* HRTIM peripheral state functions */ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3596,7 +3610,7 @@ void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); * @} */ -#endif /* defined(STM32F334x8) */ +#endif /* HRTIM1 */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h index decab31f25..ef77a3d726 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h @@ -1703,7 +1703,7 @@ typedef struct */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h index bdcfd9f87d..d19b4a3d59 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h @@ -140,7 +140,7 @@ typedef struct /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode * @{ */ -#define SDADC_LOWPOWER_NONE (0x00000000U) +#define SDADC_LOWPOWER_NONE (0x00000000UL) #define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI #define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI /** @@ -150,7 +150,7 @@ typedef struct /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode * @{ */ -#define SDADC_FAST_CONV_DISABLE (0x00000000U) +#define SDADC_FAST_CONV_DISABLE (0x00000000UL) #define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST /** * @} @@ -159,7 +159,7 @@ typedef struct /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode * @{ */ -#define SDADC_SLOW_CLOCK_DISABLE (0x00000000U) +#define SDADC_SLOW_CLOCK_DISABLE (0x00000000UL) #define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK /** * @} @@ -168,7 +168,7 @@ typedef struct /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage * @{ */ -#define SDADC_VREF_EXT (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */ +#define SDADC_VREF_EXT (0x00000000UL) /*!< The reference voltage is forced externally using VREF pin */ #define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */ #define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */ #define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */ @@ -180,7 +180,7 @@ typedef struct * @{ */ -#define SDADC_CONF_INDEX_0 (0x00000000U) /*!< Configuration 0 Register selected */ +#define SDADC_CONF_INDEX_0 (0x00000000UL) /*!< Configuration 0 Register selected */ #define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */ #define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */ /** @@ -190,7 +190,7 @@ typedef struct /** @defgroup SDADC_InputMode SDADC Input Mode * @{ */ -#define SDADC_INPUT_MODE_DIFF (0x00000000U) /*!< Conversions are executed in differential mode */ +#define SDADC_INPUT_MODE_DIFF (0x00000000UL) /*!< Conversions are executed in differential mode */ #define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */ #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */ /** @@ -200,7 +200,7 @@ typedef struct /** @defgroup SDADC_Gain SDADC Gain * @{ */ -#define SDADC_GAIN_1 (0x00000000U) /*!< Gain equal to 1U */ +#define SDADC_GAIN_1 (0x00000000UL) /*!< Gain equal to 1U */ #define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */ #define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */ #define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */ @@ -214,7 +214,7 @@ typedef struct /** @defgroup SDADC_CommonMode SDADC Common Mode * @{ */ -#define SDADC_COMMON_MODE_VSSA (0x00000000U) /*!< Select SDADC VSSA as common mode */ +#define SDADC_COMMON_MODE_VSSA (0x00000000UL) /*!< Select SDADC VSSA as common mode */ #define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */ #define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */ /** @@ -234,16 +234,16 @@ typedef struct e.g. for channel 5 definition: - the channel mask is 0x00000020 (bit 5 is set) - the channel number 5 is 0x00050000 - --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */ -#define SDADC_CHANNEL_0 (0x00000001U) -#define SDADC_CHANNEL_1 (0x00010002U) -#define SDADC_CHANNEL_2 (0x00020004U) -#define SDADC_CHANNEL_3 (0x00030008U) -#define SDADC_CHANNEL_4 (0x00040010U) -#define SDADC_CHANNEL_5 (0x00050020U) -#define SDADC_CHANNEL_6 (0x00060040U) -#define SDADC_CHANNEL_7 (0x00070080U) -#define SDADC_CHANNEL_8 (0x00080100U) + --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ +#define SDADC_CHANNEL_0 (0x00000001UL) +#define SDADC_CHANNEL_1 (0x00010002UL) +#define SDADC_CHANNEL_2 (0x00020004UL) +#define SDADC_CHANNEL_3 (0x00030008UL) +#define SDADC_CHANNEL_4 (0x00040010UL) +#define SDADC_CHANNEL_5 (0x00050020UL) +#define SDADC_CHANNEL_6 (0x00060040UL) +#define SDADC_CHANNEL_7 (0x00070080UL) +#define SDADC_CHANNEL_8 (0x00080100UL) /** * @} */ @@ -251,7 +251,7 @@ typedef struct /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence * @{ */ -#define SDADC_CALIBRATION_SEQ_1 (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */ +#define SDADC_CALIBRATION_SEQ_1 (0x00000000UL) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */ #define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */ #define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */ /** @@ -261,8 +261,8 @@ typedef struct /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode * @{ */ -#define SDADC_CONTINUOUS_CONV_OFF (0x00000000U) /*!< Conversion are not continuous */ -#define SDADC_CONTINUOUS_CONV_ON (0x00000001U) /*!< Conversion are continuous */ +#define SDADC_CONTINUOUS_CONV_OFF (0x00000000UL) /*!< Conversion are not continuous */ +#define SDADC_CONTINUOUS_CONV_ON (0x00000001UL) /*!< Conversion are continuous */ /** * @} */ @@ -270,9 +270,9 @@ typedef struct /** @defgroup SDADC_Trigger SDADC Trigger * @{ */ -#define SDADC_SOFTWARE_TRIGGER (0x00000000U) /*!< Software trigger */ -#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */ -#define SDADC_EXTERNAL_TRIGGER (0x00000002U) /*!< External trigger */ +#define SDADC_SOFTWARE_TRIGGER (0x00000000UL) /*!< Software trigger */ +#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001UL) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */ +#define SDADC_EXTERNAL_TRIGGER (0x00000002UL) /*!< External trigger */ /** * @} */ @@ -280,26 +280,26 @@ typedef struct /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger * @{ */ -#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_EXTI11 (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ -#define SDADC_EXT_TRIG_EXTI15 (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ +#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500UL) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500UL) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500UL) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_EXTI11 (0x00000700UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ +#define SDADC_EXT_TRIG_EXTI15 (0x00000600UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ /** * @} */ @@ -317,7 +317,7 @@ typedef struct /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay * @{ */ -#define SDADC_INJECTED_DELAY_NONE (0x00000000U) /*!< No delay on injected conversion */ +#define SDADC_INJECTED_DELAY_NONE (0x00000000UL) /*!< No delay on injected conversion */ #define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */ /** * @} @@ -326,7 +326,7 @@ typedef struct /** @defgroup SDADC_MultimodeType SDADC Multimode Type * @{ */ -#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */ +#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000UL) /*!< Get conversion values for SDADC1 and SDADC2 */ #define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */ /** * @} @@ -335,10 +335,10 @@ typedef struct /** @defgroup SDADC_ErrorCode SDADC Error Code * @{ */ -#define SDADC_ERROR_NONE (0x00000000U) /*!< No error */ -#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001U) /*!< Overrun occurs during regular conversion */ -#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002U) /*!< Overrun occurs during injected conversion */ -#define SDADC_ERROR_DMA (0x00000003U) /*!< DMA error occurs */ +#define SDADC_ERROR_NONE (0x00000000UL) /*!< No error */ +#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001UL) /*!< Overrun occurs during regular conversion */ +#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002UL) /*!< Overrun occurs during injected conversion */ +#define SDADC_ERROR_DMA (0x00000003UL) /*!< DMA error occurs */ /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h index a185f54a4b..f8ef0231bd 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_comp.h @@ -93,37 +93,37 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputSelection; /*!< Set comparator output selection. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -784,7 +784,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1) * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1) * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) - * + * * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC * @retval None */ @@ -808,7 +808,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1) * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1) * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) - * + * * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC */ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) @@ -862,7 +862,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) - * + * * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. @@ -906,7 +906,7 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) - * + * * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. @@ -941,7 +941,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) - * + * * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. @@ -1035,7 +1035,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_HYSTERESIS_LOW (1) * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1) * @arg @ref LL_COMP_HYSTERESIS_HIGH (1) - * + * * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC * @retval None */ @@ -1059,7 +1059,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_LOW (1) * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1) * @arg @ref LL_COMP_HYSTERESIS_HIGH (1) - * + * * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC */ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) @@ -1130,7 +1130,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4) * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4) * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4) - * + * * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n @@ -1141,7 +1141,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) */ __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection) { - MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxOUTSEL , OutputSelection); + MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxOUTSEL, OutputSelection); } /** @@ -1194,7 +1194,7 @@ __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t Ou * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4) * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4) * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4) - * + * * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n @@ -1258,7 +1258,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3) * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3) - * + * * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx. @@ -1293,7 +1293,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3) * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3) - * + * * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx. @@ -1513,32 +1513,32 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputSelection; /*!< Set comparator output selection. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ } LL_COMP_InitTypeDef; @@ -1815,7 +1815,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod { MODIFY_REG(COMP->CSR, COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx), - PowerMode << __COMP_BITOFFSET_INSTANCE(COMPx) ); + PowerMode << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -1869,7 +1869,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @param InputPlus This parameter can be one of the following values: * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) - * + * * (1) Parameter available only on COMP instance: COMP1. * @retval None */ @@ -1880,7 +1880,7 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin /* kept unmodified. */ MODIFY_REG(COMP->CSR, (COMP_CSR_COMP1INSEL | (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx))) << __COMP_BITOFFSET_INSTANCE(COMPx), - (InputMinus | InputPlus) << __COMP_BITOFFSET_INSTANCE(COMPx) ); + (InputMinus | InputPlus) << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -1894,7 +1894,7 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin * @param InputPlus This parameter can be one of the following values: * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) - * + * * (1) Parameter available only on COMP instance: COMP1. * @retval None */ @@ -1905,7 +1905,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu /* kept unmodified. */ MODIFY_REG(COMP->CSR, (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx)) << __COMP_BITOFFSET_INSTANCE(COMPx), - InputPlus << __COMP_BITOFFSET_INSTANCE(COMPx) ); + InputPlus << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -1919,7 +1919,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) - * + * * (1) Parameter available only on COMP instance: COMP1. */ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) @@ -1957,7 +1957,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi { MODIFY_REG(COMP->CSR, COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx), - InputMinus << __COMP_BITOFFSET_INSTANCE(COMPx) ); + InputMinus << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -2004,7 +2004,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In { MODIFY_REG(COMP->CSR, COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx), - InputHysteresis << __COMP_BITOFFSET_INSTANCE(COMPx) ); + InputHysteresis << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -2051,7 +2051,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1) * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1) - * + * * (1) Parameter availability depending on timer availability * on the selected device. * @retval None @@ -2060,7 +2060,7 @@ __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t Ou { MODIFY_REG(COMP->CSR, COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx), - OutputSelection << __COMP_BITOFFSET_INSTANCE(COMPx) ); + OutputSelection << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -2079,7 +2079,7 @@ __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t Ou * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1) * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1) - * + * * (1) Parameter availability depending on timer availability * on the selected device. */ @@ -2105,7 +2105,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out { MODIFY_REG(COMP->CSR, COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx), - OutputPolarity << __COMP_BITOFFSET_INSTANCE(COMPx) ); + OutputPolarity << __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -2170,7 +2170,8 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) { - return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)); + return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN << + __COMP_BITOFFSET_INSTANCE(COMPx)); } /** @@ -2199,7 +2200,8 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) { - return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)); + return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK << + __COMP_BITOFFSET_INSTANCE(COMPx)); } /** diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h index 0652ca9867..8bd8250950 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h @@ -1488,9 +1488,12 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) /** * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. + * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode * @param TIMx Timer instance diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h index 5f46fcd6ec..99fb02f232 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h +++ b/system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h @@ -250,7 +250,6 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html index 7f23eded23..befb300bad 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F3xx_HAL_Driver/Release_Notes.html @@ -676,9 +676,35 @@

Update History

-

V1.5.1 -/ 11-May-2018

Main changes

  • Patch release to fix known defects and -enhancements implementation

HAL Drivers changes

  • HAL update
    • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
      • Add the following API's :  
        • HAL_GetTickPrio(): Returns a tick priority.
        • HAL_SetTickFreq(): Sets new tick frequency.
        • HAL_GetTickFreq(): Returns tick frequency.
      • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
    • Update UNUSED() macro implementation to avoid GCC warning
      • The warning is detected when the UNUSED() macro is called from C++ file
    • Update __weak and __packed defined values for ARM compiler
    • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
  • HAL I2C update
    • Update Interface APIs headers to remove confusing message about device address
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
    • Update I2C_TransferConfig() to fix wrong bit management
  • HAL SMBUS update
    • Update conditions on HAL SMBUS slave transfer APIs to avoid block on read or write operations
  • HAL FLASH update
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL PCD update
    • Update +

      V1.5.2 +/ 12-June-2018

      Main changes

      • Maintenance release to fix known defects and +enhancements implementation

      Generic drivers changes

      • Some global variables on stm32xxx_hal.c updated to be declared as extern
            HAL drivers changes
      • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
        • Rework of HAL CAN driver (compatibility break) 
          • A +new HAL CAN driver has been redesigned with new APIs, to bypass +limitations on CAN Tx/Rx FIFO management present with previous HAL CAN +driver version.
          • The +new HAL CAN driver is the recommended version. It is located as usual +in Drivers/STM32F3xx_HAL_Driver/Src and +Drivers/STM32F3xx_HAL_Driver/Inc folders. It can be enabled through +switch HAL_CAN_MODULE_ENABLED in stm32f3xx_hal_conf.h
          • The +legacy HAL CAN driver is also present in the release in +Drivers/STM32F3xx_HAL_Driver/Src/Legacy and +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy folders for software +compatibility reasons. Its usage is not recommended as +deprecated. It can however be enabled through switch +HAL_CAN_LEGACY_MODULE_ENABLED in stm32f3xx_hal_conf.h
      • HAL update
        • Add definiton of HAL_CAN_LEGACY_MODULE_ENABLED swith in stm32f3xx_hal_conf_template.h
      • HAL CAN update
        • Fields of CAN_InitTypeDef structure are reworked:
          • SJW +to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to +TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to +AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to +TransmitFifoPriority
        • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's
        • HAL_CAN_Transmit() +is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then +HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
        • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.
        • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() 
          to get Rx message.
        • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage()
          in the receivecallback to get Rx message
        • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
        • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
        • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
        • More complete "How to use the new driver" is detailed in the driver header section itself.
      • HAL COMP update
        • Fix wrong configuration of Comparator 4 inverting input for stm32f301x8 device
      • HAL DMA update
        • Add clean of callbacks in HAL_DMA_DeInit() API
      • HAL HRTIM update
        • Add more flexibility on GetTimerIdxFromDMAHandle() static function
      • HAL RCC update
        • Update HAL_RCC_ClockConfig() API to:
          • check on null pointer
          • optimize code size by updating the handling method of the SWS bits
          • update +to use  __HAL_FLASH_GET_LATENCY() flash macro instead of using +direct register access to LATENCY bits in FLASH ACR register.
        • Update HAL_RCC_DeInit() API to
          • Be able to return HAL
          • Add checks for HSI and PLL ready before modifying RCC CFGR registers
          • Clear all interrupt falgs
          • Initialize systick interrupt period
      • HAL RTC update
        • Fix warning with static analysis: remove unused variables
      • HAL TIM update
        • Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4
        • Add +a note in functions header to perform timer reset when switching +from Aligned counter mode to Edge counter mode (or reverse)

      LL Drivers changes

      • LL TIM
        • Add +a note in macros header to perform timer reset when switching from +Aligned counter mode to Edge counter mode (or reverse)
      • LL UTILS
        • Remove the set of SysTick_CTRL_TICKINT bit in SysTick->CTRL from LL_InitTick()
      • LL RCC
        • Update LL_RCC_DeInit() API to
          • Be able to return LL status
          • Add checks for HSI and PLL ready before modifying RCC CFGR registers
          • Clear all interrupt falgs

      V1.5.1 +/ 11-May-2018

      Main changes

      • General updates to fix known defects and enhancements implementation

      HAL Drivers changes

      • HAL update
        • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
          • Add the following API's :  
            • HAL_GetTickPrio(): Returns a tick priority.
            • HAL_SetTickFreq(): Sets new tick frequency.
            • HAL_GetTickFreq(): Returns tick frequency.
          • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
        • Update UNUSED() macro implementation to avoid GCC warning
          • The warning is detected when the UNUSED() macro is called from C++ file
        • Update __weak and __packed defined values for ARM compiler
        • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
      • HAL I2C update
        • Update Interface APIs headers to remove confusing message about device address
        • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
        • Update I2C_TransferConfig() to fix wrong bit management
      • HAL SMBUS update
        • Update conditions on HAL SMBUS slave transfer APIs to avoid block on read or write operations
      • HAL FLASH update
        • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
      • HAL PCD update
        • Update redefinition of registers with adjusted address by adding volatile keyword to avoid unexpected change of Memory-mapped peripheral registers

      LL Drivers changes

      • LL ADC
        • Update redefinition of registers with adjusted address by adding volatile diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/Legacy/stm32f3xx_hal_can.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/Legacy/stm32f3xx_hal_can.c new file mode 100644 index 0000000000..99f2bf704c --- /dev/null +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/Legacy/stm32f3xx_hal_can.c @@ -0,0 +1,1700 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE(); + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins to AF9 using the + following function HAL_GPIO_Init(); + + (#) Initialise and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() function. + + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2016 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ + defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ + defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F302x8) || \ + defined(STM32F373xC) || defined(STM32F378xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ + uint32_t tickstart = 0U; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SJW | + hcan->Init.BS1 | + hcan->Init.BS2 | + (hcan->Init.Prescaler - 1U) )); + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) + { + status = CAN_INITSTATUS_SUCCESS; + } + } + + if(status == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + + filternbrbitpos = (1U) << sFilterConfig->FilterNumber; + + /* Initialisation mode for the filter */ + SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT); + + /* Filter Deactivation */ + CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(hcan->Instance->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + SET_BIT(hcan->Instance->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(hcan->Instance->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(hcan->Instance->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT)); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Select one empty transmit mailbox */ + if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Cancel transmission */ + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber FIFO number. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_TIMEOUT; + } + } + } + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; + } + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; + /* Get the DLC */ + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; + /* Get the FMI */ + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the data field */ + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber FIFO number. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_BUSY; + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + MODIFY_REG(hcan->Instance->MCR, + CAN_MCR_INRQ , + CAN_MCR_SLEEP ); + + /* Sleep mode status */ + if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + return HAL_TIMEOUT; + } + } + + if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + /* Check Transmit request completion status */ + if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + { + /* Check Transmit success */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) || + (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + } + } + + /* Check End of reception flag for FIFO0 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + /* Check End of reception flag for FIFO1 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Check Error Warning Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-Off Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* No need for clear of Bus-Off Flag as read-only */ + } + + /* Check Last error code Flag */ + if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + switch(hcan->Instance->ESR & CAN_ESR_LEC) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI Flag */ + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + +@endverbatim + * @{ + */ + +/** + * @brief return the CAN state + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CAN_Private_Functions CAN Private Functions + * @brief CAN Frame message Rx/Tx functions + * + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + * @retval None + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; + } + pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; + /* Get the DLC */ + pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; + /* Get the FMI */ + pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the data field */ + pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; + pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; + pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; + pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; + pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; + pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; + pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; + pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1)) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F302x8 || */ + /* STM32F373xC || STM32F378xx */ + +#endif /* HAL_CAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c index 4c252d7d14..84cbf7936c 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c @@ -68,11 +68,11 @@ * @{ */ /** - * @brief STM32F3xx HAL Driver version number V1.5.1 + * @brief STM32F3xx HAL Driver version number V1.5.2 */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32F3xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ @@ -85,8 +85,8 @@ */ /* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables * @{ */ __IO uint32_t uwTick; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c index 99f2bf704c..2f7f05a0c0 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c @@ -3,73 +3,130 @@ * @file stm32f3xx_hal_can.c * @author MCD Application Team * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim - ============================================================================== + ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE(); - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init(); - - (#) Initialise and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. - - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + @endverbatim - ****************************************************************************** * @attention * @@ -97,7 +154,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -107,19 +164,19 @@ * @{ */ +#if defined(CAN) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - -#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ - defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ - defined(STM32F302x8) || \ - defined(STM32F373xC) || defined(STM32F378xx) - + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants @@ -132,347 +189,218 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) + + if (hcan->State == HAL_CAN_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - + /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + tickstart = HAL_GetTick(); - /* Check acknowledge */ - if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + return HAL_ERROR; } + } - /* Set the bit timing register */ - WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - hcan->Init.SJW | - hcan->Init.BS1 | - hcan->Init.BS2 | - (hcan->Init.Prescaler - 1U) )); + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Request leave initialisation */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Check acknowledged */ - if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) - { - status = CAN_INITSTATUS_SUCCESS; + return HAL_ERROR; } } - - if(status == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0U; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - - filternbrbitpos = (1U) << sFilterConfig->FilterNumber; - /* Initialisation mode for the filter */ - SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT); - - /* Filter Deactivation */ - CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos); - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) { - /* 16-bit scale for the filter */ - CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos); - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + else { - /* 32-bit scale for the filter */ - SET_BIT(hcan->Instance->FS1R, filternbrbitpos); - - /* 32-bit identifier or First 32-bit identifier */ - hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } - /* 32-bit mask or Second 32-bit identifier */ - hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /*Id/Mask mode for the filter*/ - CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - SET_BIT(hcan->Instance->FM1R, filternbrbitpos); + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) { - /* FIFO 0 assignation for the filter */ - CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos); + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } else { - /* FIFO 1 assignation for the filter */ - SET_BIT(hcan->Instance->FFA1R, filternbrbitpos); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - SET_BIT(hcan->Instance->FA1R, filternbrbitpos); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - /* Leave the initialisation mode for the filter */ - CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT)); - + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } @@ -480,953 +408,1444 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) /** * @brief Initializes the CAN MSP. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the CAN MSP. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief IO operation functions +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + @endverbatim * @{ */ /** - * @brief Initiates and transmits a CAN frame message. + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout Timeout duration. - * @retval HAL status + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { - /* Process locked */ - __HAL_LOCK(hcan); + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + + /* CAN is single instance with 14 dedicated filters banks */ - /* Change CAN state */ - switch(hcan->State) + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } - /* Select one empty transmit mailbox */ - if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { - transmitmailbox = CAN_TXMAILBOX_0; + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } - else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { - transmitmailbox = CAN_TXMAILBOX_1; + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); } - else + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { - transmitmailbox = CAN_TXMAILBOX_2; + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); } - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ - hcan->pTxMsg->RTR); + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); } else { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); - - /* Request transmission */ - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - - /* Cancel transmission */ - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); } - /* Change CAN state */ - switch(hcan->State) + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; + SET_BIT(can_ip->FA1R, filternbrbitpos); } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + uint32_t tickstart; - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + if (hcan->State == HAL_CAN_STATE_READY) { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); - - /* Change CAN state */ - switch(hcan->State) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } } - /* Set CAN error code to none */ + /* Reset the CAN ErrorCode */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - /* Return function status */ return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receives a correct CAN frame. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber FIFO number. - * @param Timeout Timeout duration. + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + uint32_t tickstart; - return HAL_BUSY; - } - - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + if (hcan->State == HAL_CAN_STATE_LISTENING) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - return HAL_BUSY; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - return HAL_TIMEOUT; + return HAL_ERROR; } } - } - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Get the Id */ - pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; } else { - pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; } - pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; - /* Get the DLC */ - pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; - /* Get the FMI */ - pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; - pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; - pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; - pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; - pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; - pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; - pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; - pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; } +} - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; + status = 1U; } } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Receives a correct CAN frame. + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber FIFO number. + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } - /* Process locked */ - __HAL_LOCK(hcan); + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } - return HAL_BUSY; + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); } - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; - return HAL_BUSY; + /* Call Error callback function */ + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); } +} - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } +/** + * @} + */ - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } - - /* Return function status */ - return HAL_OK; -} +@endverbatim + * @{ + */ /** - * @brief Enters the Sleep (low power) mode. + * @brief Transmission Mailbox 0 complete callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - MODIFY_REG(hcan->Instance->MCR, - CAN_MCR_INRQ , - CAN_MCR_SLEEP ); - - /* Sleep mode status */ - if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || - HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Return function status */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || - HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ } /** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. + * @brief Transmission Mailbox 1 complete callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Sleep mode status */ - while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} - return HAL_TIMEOUT; - } - } +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK)) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} - /* Return function status */ - return HAL_ERROR; - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ } /** - * @brief Handles CAN interrupt request - * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { - uint32_t errorcode = HAL_CAN_ERROR_NONE; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Check Overrun flag for FIFO0 */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) - { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Check Overrun flag for FIFO1 */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) - { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) - { - /* Check Transmit request completion status */ - if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) - { - /* Check Transmit success */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) || - (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) || - (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))) - { - /* Call transmit function */ - CAN_Transmit_IT(hcan); - } - else /* Transmit failure */ - { - /* Set CAN error code to TXFAIL error */ - errorcode |= HAL_CAN_ERROR_TXFAIL; - } + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} - /* Clear transmission status flags (RQCPx and TXOKx) */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ - CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); - } - } - - /* Check End of reception flag for FIFO0 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U)) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); - } - - /* Check End of reception flag for FIFO1 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U)) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); - } - - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; - - /* Check Error Warning Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-Off Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - /* No need for clear of Bus-Off Flag as read-only */ - } - - /* Check Last error code Flag */ - if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - switch(hcan->Instance->ESR & CAN_ESR_LEC) - { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Clear Last error code Flag */ - CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - } + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} - /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) - { - /* Clear ERRI Flag */ - SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME ); +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); - /* Call Error callback function */ - HAL_CAN_ErrorCallback(hcan); - } + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ } /** - * @brief Transmission complete callback in non blocking mode + * @brief Sleep callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + the HAL_CAN_SleepCallback could be implemented in the user file */ } /** - * @brief Transmission complete callback in non blocking mode + * @brief WakeUp from Rx message callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } @@ -1450,249 +1869,115 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief return the CAN state + * @brief Return the CAN state. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + /* Return CAN state */ - return hcan->State; + return state; } /** - * @brief Return the CAN error code + * @brief Return the CAN error code. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ - -/** - * @} - */ - -/** @addtogroup CAN_Private_Functions CAN Private Functions - * @brief CAN Frame message Rx/Tx functions - * - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. + * @brief Reset the CAN error code. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber Specify the FIFO number + * the configuration information for the specified CAN. * @retval HAL status - * @retval None */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; - /* Get the Id */ - pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { - pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos; + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos; - } - pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos; - /* Get the DLC */ - pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos; - /* Get the FMI */ - pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos; - pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos; - pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos; - pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos; - pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos; - pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos; - pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos; - pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos; - - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } - - if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1)) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } + status = HAL_ERROR; } - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; + /* Return the status */ + return status; } /** * @} */ -#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ - /* STM32F302xC || STM32F303xC || STM32F358xx || */ - /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ - /* STM32F302x8 || */ - /* STM32F373xC || STM32F378xx */ + +/** + * @} + */ #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN */ + /** * @} */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c index 4727519150..be39d0e08e 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c @@ -3,14 +3,14 @@ * @file stm32f3xx_hal_comp.c * @author MCD Application Team * @brief COMP HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions * + Start/Stop operation functions in polling mode. * + Start/Stop operation functions in interrupt mode. * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ================================================================================ ##### COMP Peripheral features ##### @@ -19,21 +19,21 @@ [..] The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7: (#) The non inverting input and inverting input can be set to GPIO pins. - For STM32F3xx devices please refer to the COMP peripheral section in corresponding + For STM32F3xx devices please refer to the COMP peripheral section in corresponding Reference Manual. - + (#) The COMP output is available using HAL_COMP_GetOutputLevel() and can be set on GPIO pins. - For STM32F3xx devices please refer to the COMP peripheral section in corresponding + For STM32F3xx devices please refer to the COMP peripheral section in corresponding Reference Manual. - + (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...). - For STM32F3xx devices please refer to the COMP peripheral section in corresponding + For STM32F3xx devices please refer to the COMP peripheral section in corresponding Reference Manual. - + (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input. - + (#) The seven comparators have interrupt capability with wake-up from Sleep and Stop modes (through the EXTI controller): (++) COMP1 is internally connected to EXTI Line 21 @@ -44,29 +44,29 @@ (++) COMP6 is internally connected to EXTI Line 32 (++) COMP7 is internally connected to EXTI Line 33. - From the corresponding IRQ handler, the right interrupt source can be retrieved with the + From the corresponding IRQ handler, the right interrupt source can be retrieved with the adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). - + ##### How to use this driver ##### ================================================================================ [..] This driver provides functions to configure and program the Comparators of all STM32F3xx devices. To use the comparator, perform the following steps: - + (#) Fill in the HAL_COMP_MspInit() to (++) Configure the comparator input in analog mode using HAL_GPIO_Init() - (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator + (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator output to the GPIO pin - (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and + (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions. - + (#) Configure the comparator using HAL_COMP_Init() function: (++) Select the inverting input (input minus) (++) Select the non-inverting input (input plus) - (++) Select the output polarity + (++) Select the output polarity (++) Select the output redirection (++) Select the hysteresis level (++) Select the power mode @@ -76,22 +76,22 @@ to enable the comparator(s). (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init( - function with new input parameter values; HAL_COMP_MspInit() function shall be adapted + function with new input parameter values; HAL_COMP_MspInit() function shall be adapted to support multi configurations. (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions. - + (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions to manage comparator outputs (events and output level). - (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() + (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() function. (#) De-initialize the comparator using HAL_COMP_DeInit() function. (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function. Only a MCU reset can reset that protection. - + @endverbatim ****************************************************************************** * @attention @@ -120,14 +120,14 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Additional Tables: Table 1. COMP Inputs for the STM32F303xB/STM32F303xC/STM32F303xE devices - +------------------------------------------------------------------------------------------+ + +------------------------------------------------------------------------------------------+ | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |-----------------|----------------|---------------|---------------------------------------| | | 1U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | @@ -141,10 +141,10 @@ |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------| | Non Inverting | IO1 | PA1 | PA7 | PB14U | PB0 | PD12U | PD11U | PA0 | | Input | IO2 | --- | PA3 | PD14U | PE7 | PB13U | PB11U | PC1 | - +------------------------------------------------------------------------------------------+ + +------------------------------------------------------------------------------------------+ Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices - +-------------------------------------------------------+ + +-------------------------------------------------------+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |-------|-------|-------|-------|-------|-------|-------| | PA0 | PA2 | PB1 | PC8 | PC7 | PA10U | PC2 | @@ -155,7 +155,7 @@ +-------------------------------------------------------+ Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices - +----------------------------------------------------------------------------------------------------------------------+ + +----------------------------------------------------------------------------------------------------------------------+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |----------------|----------------|----------------|----------------|----------------|----------------|----------------| | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | @@ -170,7 +170,7 @@ | + | + | + | + | + | + | + | | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | | | | | | | | | - | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR | + | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR | | | | | | | | | | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR | | | | | | | | | @@ -178,7 +178,7 @@ | | | | | | | | | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 | | | | | | | | | - | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR| + | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR| | | | | | | | | | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN | +----------------------------------------------------------------------------------------------------------------------+ @@ -199,7 +199,7 @@ | + | + | + | + | + | + | + | | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | | | | | | | | | - | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR | + | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR | | | | | | | | | | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR | | | | | | | | | @@ -207,7 +207,7 @@ | | | | | | | | | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 | | | | | | | | | - | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR| + | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR| | | | | | | | | | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN | | | | | | | | | @@ -223,7 +223,7 @@ | | | | | | | | +----------------------------------------------------------------------------------------------------------------------+ (1U): This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead - of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to + of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to add a digital filter (3 bits) on the COMP output. Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices @@ -274,10 +274,10 @@ * @{ */ -/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and de-initialization functions. +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -298,9 +298,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -316,11 +316,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_MODE(hcomp->Init.Mode)); - assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); - assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) + if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); @@ -330,8 +330,8 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Init the low level hardware : SYSCFG to access comparators */ HAL_COMP_MspInit(hcomp); - - if(hcomp->State == HAL_COMP_STATE_RESET) + + if (hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; @@ -340,7 +340,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Manage inverting input comparator inverting input connected to a GPIO */ /* for STM32F302x, STM32F32xx, STM32F33x. */ hcomp->Init.InvertingInput = COMP_INVERTINGINPUT_SELECTION(hcomp->Instance, hcomp->Init.InvertingInput); - + /* Set COMP parameters */ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */ /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */ @@ -354,7 +354,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Initialize the COMP state*/ hcomp->State = HAL_COMP_STATE_READY; } - + return status; } @@ -370,7 +370,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -386,11 +386,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_COMP_MspDeInit(hcomp); hcomp->State = HAL_COMP_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hcomp); } - + return status; } @@ -428,13 +428,13 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions - * @brief Start-Stop operation functions. +/** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions + * @brief Start-Stop operation functions. * -@verbatim +@verbatim =============================================================================== ##### Start Stop operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start a comparator without interrupt generation. (+) Stop a comparator without interrupt generation. @@ -455,9 +455,9 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; uint32_t extiline = 0U; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -466,16 +466,16 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_READY) + if (hcomp->State == HAL_COMP_STATE_READY) { /* Get the EXTI Line output configuration */ extiline = COMP_GET_EXTI_LINE(hcomp->Instance); /* Configure the event generation */ - if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING|COMP_TRIGGERMODE_EVENT_FALLING)) != RESET) + if ((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING | COMP_TRIGGERMODE_EVENT_FALLING)) != RESET) { /* Configure the event trigger rising edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET) + if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET) { COMP_EXTI_RISING_ENABLE(extiline); } @@ -485,7 +485,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) } /* Configure the trigger falling edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET) + if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET) { COMP_EXTI_FALLING_ENABLE(extiline); } @@ -521,11 +521,11 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_BUSY) + if (hcomp->State == HAL_COMP_STATE_BUSY) { /* Disable the EXTI Line event mode if any */ COMP_EXTI_DISABLE_EVENT(COMP_GET_EXTI_LINE(hcomp->Instance)); @@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) status = HAL_ERROR; } } - + return status; } @@ -559,12 +559,12 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) * @retval HAL status. */ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) -{ +{ HAL_StatusTypeDef status = HAL_OK; uint32_t extiline = 0U; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -573,16 +573,16 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if(hcomp->State == HAL_COMP_STATE_READY) + if (hcomp->State == HAL_COMP_STATE_READY) { /* Configure the EXTI event generation */ - if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING|COMP_TRIGGERMODE_IT_FALLING)) != RESET) + if ((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING | COMP_TRIGGERMODE_IT_FALLING)) != RESET) { /* Get the EXTI Line output configuration */ extiline = COMP_GET_EXTI_LINE(hcomp->Instance); /* Configure the trigger rising edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) + if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) { COMP_EXTI_RISING_ENABLE(extiline); } @@ -591,7 +591,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) COMP_EXTI_RISING_DISABLE(extiline); } /* Configure the trigger falling edge */ - if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) + if ((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) { COMP_EXTI_FALLING_ENABLE(extiline); } @@ -633,12 +633,12 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Disable the EXTI Line interrupt mode */ COMP_EXTI_DISABLE_IT(COMP_GET_EXTI_LINE(hcomp->Instance)); - + status = HAL_COMP_Stop(hcomp); - + return status; } @@ -650,13 +650,13 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance); - + /* Check COMP EXTI flag */ - if(COMP_EXTI_GET_FLAG(extiline) != RESET) + if (COMP_EXTI_GET_FLAG(extiline) != RESET) { /* Clear COMP EXTI pending bit */ COMP_EXTI_CLEAR_FLAG(extiline); - + /* COMP trigger user callback */ HAL_COMP_TriggerCallback(hcomp); } @@ -681,22 +681,22 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions * @brief Management functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the comparators. + This subsection provides a set of functions allowing to control the comparators. @endverbatim * @{ */ /** - * @brief Lock the selected comparator configuration. + * @brief Lock the selected comparator configuration. * @note A system reset is required to unlock the comparator configuration. * @param hcomp COMP handle * @retval HAL status @@ -706,7 +706,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) + if ((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } @@ -716,32 +716,32 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set lock flag on state */ - switch(hcomp->State) + switch (hcomp->State) { - case HAL_COMP_STATE_BUSY: - hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; - break; - case HAL_COMP_STATE_READY: - hcomp->State = HAL_COMP_STATE_READY_LOCKED; - break; - default: - /* unexpected state */ - status = HAL_ERROR; - break; + case HAL_COMP_STATE_BUSY: + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: + /* unexpected state */ + status = HAL_ERROR; + break; } } - - if(status == HAL_OK) + + if (status == HAL_OK) { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } - - return status; + + return status; } /** - * @brief Return the output level (high or low) of the selected comparator. + * @brief Return the output level (high or low) of the selected comparator. * The output level depends on the selected polarity. * If the polarity is not inverted: * - Comparator output is low when the non-inverting input is at a lower @@ -754,38 +754,38 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * - Comparator output is low when the non-inverting input is at a higher * voltage than the inverting input * @param hcomp COMP handle - * @retval Returns the selected comparator output level: + * @retval Returns the selected comparator output level: * @arg @ref COMP_OUTPUTLEVEL_LOW * @arg @ref COMP_OUTPUTLEVEL_HIGH - * + * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { - uint32_t level=0U; - + uint32_t level = 0U; + /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT); - if(level != 0U) + if (level != 0U) { - return(COMP_OUTPUTLEVEL_HIGH); + return (COMP_OUTPUTLEVEL_HIGH); } - return(COMP_OUTPUTLEVEL_LOW); + return (COMP_OUTPUTLEVEL_LOW); } /** * @} */ -/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -801,7 +801,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == NULL) + if (hcomp == NULL) { return HAL_COMP_STATE_RESET; } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c index 69e42aa981..9a1a46d472 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c @@ -194,12 +194,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ DMA_CalcBaseAndBitshift(hdma); - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -250,10 +244,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - /* Initialize the error code */ + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Initialize the DMA state */ + /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c index b29dcdc6d0..c55de9fdea 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c @@ -171,7 +171,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programmation (only exception to this + * @note FLASH should be previously erased before new programming (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programation procedure */ + /* In case of error, stop programming procedure */ if (status != HAL_OK) { break; diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c index 6292c3097a..f596783ee8 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c @@ -105,7 +105,7 @@ (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL calibration is executed periodically and compensate for potential voltage and temperature drifts. DLL calibration period is specified by the - CalibrationRate argument. + CalibrationRate argument. (#)HRTIM timers cannot be used until the high resolution unit is ready. This can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns @@ -158,22 +158,22 @@ =================================================== [..] (#) Start or Stop simple timers - (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(), + (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(), HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(), HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA(). - (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(), + (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(), HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(), HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(), HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(), - (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(), + (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(), HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(), HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(), HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(), - (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(), + (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(), HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(), HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(), HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA(). - (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(), + (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(), HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(), HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It(). @@ -181,8 +181,8 @@ ==================================================== [..] (#) Completes waveform timer configuration - (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer - operating in wave form mode mainly consists in: + (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer + operating in wave form mode mainly consists in: (+++)Enabling the HRTIM timer interrupts and DMA requests. (+++)Enabling the half mode for the HRTIM timer. (+++)Defining how the HRTIM timer reacts to external synchronization input. @@ -190,89 +190,89 @@ (+++)Enabling the fault channels for the HRTIM timer. (+++)Enabling the dead-time insertion for the HRTIM timer. (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs - on which the delayed protection are applied). + on which the delayed protection are applied). (+++)Specifying the HRTIM timer update and reset triggers. (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling). - (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external + (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external event blanking and windowing circuitry of a HRTIM timer: (+++)Blanking: to mask external events during a defined time period a defined time period - (+++)Windowing, to enable external events only during a defined time period - (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion + (+++)Windowing, to enable external events only during a defined time period + (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion unit for a HRTIM timer. Allows to generate a couple of complementary signals from a single reference waveform, with programmable delays between active state. - (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of + (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of the high-frequency carrier signal added on top of the timing unit output. Chopper mode can be enabled or disabled for each timer output separately (see HAL_HRTIM_WaveformOutputConfig()). - (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst + (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst controller. Allows having multiple HRTIM registers updated with a single DMA request. The burst DMA operation is started by calling HAL_HRTIM_BurstDMATransfer(). - (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit + (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit of a HRTIM timer. This operation consists in setting the compare value and possibly specifying the auto delayed mode for compare units 2 and 4 (allows to have compare events generated relatively to capture events). Note that when auto delayed mode is needed, the capture unit associated to the compare unit must be configured separately. - (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit + (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit of a HRTIM timer. This operation consists in specifying the source(s) triggering the capture (timer register update event, external event, timer output set/reset event, other HRTIM timer related events). - (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer + (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer output mainly consists in: (+++)Setting the output polarity (active high or active low), (+++)Defining the set/reset crossbar for the output, (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states., - + (#) Set waveform timer output(s) level - (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its + (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its active or inactive level. For example, when deadtime insertion is enabled it is necessary to force the output level by software to have the outputs in a complementary state as soon as the RUN mode is entered. - + (#) Enable or Disable waveform timer output(s) - (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop(). - + (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop(). + (#) Start or Stop waveform HRTIM timer(s). - (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(), - (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(), - (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(), + (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(), + (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(), + (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(), (#) Burst mode controller enabling: - (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the + (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the burst mode controller. (#) Some HRTIM operations can be triggered by software: - (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function + (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function trigs the burst operation. - (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the + (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the capture of the HRTIM timer counter. - (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the + (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the update of the pre-loadable registers of the HRTIM timer - (++)HAL_HRTIM_SoftwareReset():calling this function resets the + (++)HAL_HRTIM_SoftwareReset():calling this function resets the HRTIM timer counter. (#) Some functions can be used any time to retrieve HRTIM timer related information - (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the + (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the capture register of the designated capture unit. - (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level + (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level (ACTIVE/INACTIVE) of the designated timer output. - (++)HAL_HRTIM_WaveformGetOutputState():returns actual state + (++)HAL_HRTIM_WaveformGetOutputState():returns actual state (IDLE/RUN/FAULT) of the designated timer output. - (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level + (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level (ACTIVE/INACTIVE) of the designated output when the delayed protection was triggered. - (++)HAL_HRTIM_GetBurstStatus(): returns the actual status + (++)HAL_HRTIM_GetBurstStatus(): returns the actual status (ACTIVE/INACTIVE) of the burst mode controller. - (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode + (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()), the push-pull status indicates on which output the signal is currently active (e.g signal applied on output 1 and output 2 forced inactive or vice versa). - (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode + (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()), the idle push-pull status indicates during which period the delayed protection request occurred (e.g. protection occurred @@ -280,7 +280,7 @@ vice versa). (#) Some functions can be used any time to retrieve actual HRTIM status - (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state. + (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state. @endverbatim @@ -323,7 +323,7 @@ #ifdef HAL_HRTIM_MODULE_ENABLED -#if defined(STM32F334x8) +#if defined(HRTIM1) /** @defgroup HRTIM HRTIM * @brief HRTIM HAL module driver @@ -421,7 +421,8 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma); +static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, + DMA_HandleTypeDef * hdma); static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); @@ -461,7 +462,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); (+) Initialize the HRTIM MSP (+) De-initialize the HRTIM MSP (+) Start the high-resolution unit (start DLL calibration) - (+) Check that the high resolution unit is ready (DLL calibration done) + (+) Check that the high resolution unit is ready (DLL calibration done) (+) Configure the time base unit of a HRTIM timer @endverbatim @@ -498,7 +499,7 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL; hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL; hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL; - + /* HRTIM output synchronization configuration (if required) */ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET) { @@ -554,7 +555,7 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) /* Initialize the lock status of the HRTIM HAL API */ __HAL_UNLOCK(hhrtim); - /* Tnitialize timer related parameters */ + /* Initialize timer related parameters */ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; timer_idx <= HRTIM_TIMERINDEX_MASTER ; timer_idx++) @@ -613,7 +614,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief MSP de-initialization for a for a HRTIM instance + * @brief MSP de-initialization of a HRTIM instance * @param hhrtim pointer to HAL HRTIM handle * @retval None */ @@ -786,7 +787,7 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, * @note The time-base unit initialization parameters specify: * The timer counter operating mode (continuous, one shot), * The timer clock prescaler, - * The timer period , + * The timer period, * The timer repetition counter. * @retval HAL status */ @@ -842,7 +843,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, (+) Start simple time base and enable DMA transfer (+) Stop simple time base and disable DMA transfer -@- When a HRTIM timer operates in simple time base mode, the timer - counter counts from 0 to the period value. + counter counts from 0 to the period value. @endverbatim * @{ @@ -1038,11 +1039,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if(hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if(hhrtim->State == HAL_HRTIM_STATE_READY) { if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { @@ -1059,6 +1060,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1068,6 +1070,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } + /* Set the DMA transfer completed callback */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) { @@ -1102,7 +1105,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK; + return HAL_OK; } /** @@ -1653,17 +1656,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel); /* Get the timer DMA handler */ - hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + __HAL_UNLOCK(hhrtim); return HAL_ERROR; } - + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; @@ -1732,14 +1736,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + hhrtim->State = HAL_HRTIM_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Disable the DMA */ @@ -1780,7 +1785,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, (+) Stop simple PWM output and disable interrupt (+) Start simple PWM output and enable DMA transfer (+) Stop simple PWM output and disable DMA transfer - -@- When a HRTIM timer operates in simple PWM output mode + -@- When a HRTIM timer operates in simple PWM output mode the output level is set to a programmable value when a match is found between the compare register and the counter and reset when the timer period is reached. Duty cycle is determined by the @@ -1845,7 +1850,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } /* Process Locked */ - __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY; + __HAL_LOCK(hhrtim); + + hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Configure timer compare unit */ switch (PWMChannel) @@ -1888,7 +1895,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; - + if (CompareUnit == HRTIM_COMPAREUNIT_1) { OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; @@ -2234,14 +2241,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - - return HAL_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); + + return HAL_ERROR; } /* Set the DMA error callback */ @@ -2333,14 +2341,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - - return HAL_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); + + return HAL_ERROR; } /* Disable the DMA */ @@ -2775,13 +2784,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { hhrtim->State = HAL_HRTIM_STATE_ERROR; - + /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - + return HAL_ERROR; } @@ -2813,7 +2823,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2); } break; - default: + default: break; } @@ -2862,13 +2872,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { hhrtim->State = HAL_HRTIM_STATE_ERROR; - + /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - + return HAL_ERROR; } @@ -3048,7 +3059,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; - + if (CompareUnit == HRTIM_COMPAREUNIT_1) { OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; @@ -3351,7 +3362,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, ##### HRTIM configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the HRTIM - resources shared by all the HRTIM timers operating in waveform mode: + resources shared by all the HRTIM timers operating in waveform mode: (+) Configure the burst mode controller (+) Configure an external event conditionning (+) Configure the external events sampling clock @@ -3437,6 +3448,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @param Event external event to configure * This parameter can be one of the following values: + * @arg HRTIM_EVENT_NONE: no external Event * @arg HRTIM_EVENT_1: External event 1 * @arg HRTIM_EVENT_2: External event 2 * @arg HRTIM_EVENT_3: External event 3 @@ -3550,7 +3562,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; - + /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source)); @@ -3571,7 +3583,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure fault channel */ hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1; hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2; - + switch (Fault) { case HRTIM_FAULT_1: @@ -3587,7 +3599,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U); - hrtim_fltinr1 |= (pFaultCfg->Source << 8U); + hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT2SRC_Pos; hrtim_fltinr1 |= (pFaultCfg->Filter << 8U); hrtim_fltinr1 |= (pFaultCfg->Lock << 8U); } @@ -3596,16 +3608,16 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U); - hrtim_fltinr1 |= (pFaultCfg->Source << 16U); + hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT3SRC_Pos; hrtim_fltinr1 |= (pFaultCfg->Filter << 16U); hrtim_fltinr1 |= (pFaultCfg->Lock << 16U); - } + } break; case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U); - hrtim_fltinr1 |= (pFaultCfg->Source << 24U); + hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR1_FLT4SRC_Pos; hrtim_fltinr1 |= (pFaultCfg->Filter << 24U); hrtim_fltinr1 |= (pFaultCfg->Lock << 24U); } @@ -3614,7 +3626,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= pFaultCfg->Polarity; - hrtim_fltinr2 |= pFaultCfg->Source; + hrtim_fltinr1 |= pFaultCfg->Source << HRTIM_FLTINR2_FLT5SRC_Pos; hrtim_fltinr2 |= pFaultCfg->Filter; hrtim_fltinr2 |= pFaultCfg->Lock; } @@ -3681,7 +3693,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, return HAL_OK; } - + /** * @brief Enables or disables the HRTIMx Fault mode. * @param hhrtim pointer to HAL HRTIM handle @@ -3738,7 +3750,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E; hrtim_fltinr2 |= Enable; } - + /* Update the HRTIMx registers */ hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1; hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2; @@ -3780,7 +3792,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the ADC trigger update source */ hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1; - + switch (ADCTrigger) { case HRTIM_ADCTRIGGER_1: @@ -3834,6 +3846,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, return HAL_OK; } + /** * @} */ @@ -3845,7 +3858,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, ##### HRTIM timer configuration and control functions ##### =============================================================================== [..] This section provides functions used to configure and control a - HRTIM timer operating in waveform mode: + HRTIM timer operating in waveform mode: (+) Configure HRTIM timer general behavior (+) Configure HRTIM timer event filtering (+) Configure HRTIM timer deadtime insertion @@ -3904,7 +3917,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable)); assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync)); assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync)); - assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro)); + assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro)); assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable)); assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); @@ -3945,7 +3958,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger)); assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger)); assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate)); - + /* Configure timing unit */ HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg); } @@ -3980,7 +3993,6 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @param Event external event for which timer event filtering must be configured * This parameter can be one of the following values: - * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration * @arg HRTIM_EVENT_1: External event 1 * @arg HRTIM_EVENT_2: External event 2 * @arg HRTIM_EVENT_3: External event 3 @@ -4414,7 +4426,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; } break; - default: + default: break; } } @@ -4490,7 +4502,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, } } break; - default: + default: break; } } @@ -5081,17 +5093,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); - if (hdma == NULL) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - - return HAL_ERROR; - } - /* Set the DMA error callback */ + if (hdma == NULL) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); + + return HAL_ERROR; + } + + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -5168,6 +5181,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); + if (hdma == NULL) { /* Disable the DMA request(s) */ @@ -5473,6 +5487,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx); + if (hdma == NULL) { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -5482,7 +5497,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, return HAL_ERROR; } - + /* Set the DMA transfer completed callback */ hdma->XferCpltCallback = HRTIM_BurstDMACplt; @@ -5607,7 +5622,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim) { - /* Return ADC state */ + /* Return HRTIM state */ return hhrtim->State; } @@ -5657,6 +5672,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, return captured_value; } + /** * @brief Returns actual level (active or inactive) of the designated output * @param hhrtim pointer to HAL HRTIM handle @@ -5868,8 +5884,8 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 - * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1 - * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2 + * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 + * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, @@ -6098,7 +6114,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Fault1Callback could be implenetd in the user file + the HAL_HRTIM_Fault1Callback could be implemented in the user file */ } @@ -6113,7 +6129,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Fault2Callback could be implenetd in the user file + the HAL_HRTIM_Fault2Callback could be implemented in the user file */ } @@ -6128,7 +6144,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Fault3Callback could be implenetd in the user file + the HAL_HRTIM_Fault3Callback could be implemented in the user file */ } @@ -6143,7 +6159,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Fault4Callback could be implenetd in the user file + the HAL_HRTIM_Fault4Callback could be implemented in the user file */ } @@ -6158,7 +6174,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Fault5Callback could be implenetd in the user file + the HAL_HRTIM_Fault5Callback could be implemented in the user file */ } @@ -6173,7 +6189,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file + the HAL_HRTIM_SystemFaultCallback could be implemented in the user file */ } @@ -6188,7 +6204,7 @@ __weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file + the HAL_HRTIM_DLLCalbrationCallback could be implemented in the user file */ } @@ -6203,7 +6219,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_BurstModeCallback could be implenetd in the user file + the HAL_HRTIM_BurstModeCallback could be implemented in the user file */ } @@ -6218,7 +6234,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file + the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file */ } @@ -6243,7 +6259,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file + the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file */ } @@ -6268,7 +6284,7 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file + the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file */ } @@ -6294,7 +6310,7 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file + the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file */ } @@ -6320,7 +6336,7 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file + the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file */ } @@ -6346,7 +6362,7 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file + the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file */ } @@ -6372,7 +6388,7 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file + the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file */ } @@ -6396,7 +6412,7 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file */ } @@ -6420,7 +6436,7 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file */ } @@ -6445,7 +6461,7 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file + the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file */ } @@ -6470,7 +6486,7 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file + the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file */ } @@ -6494,7 +6510,7 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file */ } @@ -6518,7 +6534,7 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file */ } @@ -6542,7 +6558,7 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file */ } @@ -6556,7 +6572,7 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_C for timer C * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E - * @retval None + * @retval None */ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) @@ -6566,7 +6582,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file + the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file */ } @@ -6591,7 +6607,7 @@ __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, UNUSED(TimerIdx); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file + the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file */ } @@ -6606,7 +6622,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) UNUSED(hhrtim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HRTIM_ErrorCallback could be implenetd in the user file + the HAL_HRTIM_ErrorCallback could be implemented in the user file */ } @@ -6651,7 +6667,7 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, } /** - * @brief Configures timing unit (timer A to timer E) time base + * @brief Configures timing unit (Timer A to Timer E) time base * @param hhrtim pointer to HAL HRTIM handle * @param TimerIdx Timer index * @param pTimeBaseCfg pointer to the time base configuration structure @@ -6734,7 +6750,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, } /** - * @brief Configures timing unit (timer A to timer E) in waveform mode + * @brief Configures timing unit (Timer A to Timer E) in waveform mode * @param hhrtim pointer to HAL HRTIM handle * @param TimerIdx Timer index * @param pTimerCfg pointer to the timer configuration data structure @@ -6749,7 +6765,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t hrtim_timoutr; uint32_t hrtim_timrstr; uint32_t hrtim_bmcr; - + /* UPDGAT bitfield must be reset before programming a new value */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT); @@ -6783,7 +6799,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Timing unit registers update handling */ hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT); hrtim_timcr |= pTimerCfg->UpdateGating; - + /* Enable/Disable registers update on repetition */ hrtim_timcr &= ~(HRTIM_TIMCR_TREPU); if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED) @@ -6803,7 +6819,6 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER); hrtim_timcr |= pTimerCfg->UpdateTrigger; - /* Enable/Disable the fault channel at timer level */ hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN); hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN); @@ -6871,7 +6886,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, default: break; } - + /* Update the HRTIM registers */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr; hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr; @@ -7156,6 +7171,13 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { + case HRTIM_EVENT_NONE: + { + hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1 = 0U; + hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2 = 0U; + hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3 = 0U; + } + break; case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); @@ -7595,35 +7617,36 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma) +static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, + DMA_HandleTypeDef * hdma) { uint32_t timed_idx = 0xFFFFFFFFU; - if (hdma->Instance == DMA1_Channel2) + if (hdma == hhrtim->hdmaMaster) { timed_idx = HRTIM_TIMERINDEX_MASTER; } - else if (hdma->Instance == DMA1_Channel3) + else if (hdma == hhrtim->hdmaTimerA) { timed_idx = HRTIM_TIMERINDEX_TIMER_A; } - else if (hdma->Instance == DMA1_Channel4) + else if (hdma == hhrtim->hdmaTimerB) { timed_idx = HRTIM_TIMERINDEX_TIMER_B; } - else if (hdma->Instance == DMA1_Channel5) + else if (hdma == hhrtim->hdmaTimerC) { timed_idx = HRTIM_TIMERINDEX_TIMER_C; } - else if (hdma->Instance == DMA1_Channel6) + else if (hdma == hhrtim->hdmaTimerD) { timed_idx = HRTIM_TIMERINDEX_TIMER_D; } - else if (hdma->Instance == DMA1_Channel7) + else if (hdma == hhrtim->hdmaTimerE) { timed_idx = HRTIM_TIMERINDEX_TIMER_E; } - + return timed_idx; } @@ -7988,50 +8011,50 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } } - /* Timer ouput 1 set event */ + /* Timer output 1 set event */ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET) { if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); - /* Invoke ouput 1 set event callback */ + /* Invoke output 1 set event callback */ HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx); } } - /* Timer ouput 1 reset event */ + /* Timer output 1 reset event */ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET) { if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); - /* Invoke ouput 1 reset event callback */ + /* Invoke output 1 reset event callback */ HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx); } } - /* Timer ouput 2 set event */ + /* Timer output 2 set event */ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET) { if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); - /* Invoke ouput 2 set event callback */ + /* Invoke output 2 set event callback */ HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx); } } - /* Timer ouput 2 reset event */ + /* Timer output 2 reset event */ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET) { if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); - /* Invoke ouput 2 reset event callback */ + /* Invoke output 2 reset event callback */ HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx); } } @@ -8108,69 +8131,69 @@ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - + HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; - timer_idx = GetTimerIdxFromDMAHandle(hdma); + timer_idx = GetTimerIdxFromDMAHandle(hrtim, hdma); + + if ( !IS_HRTIM_TIMERINDEX(timer_idx) ) return; + - if (IS_HRTIM_TIMING_UNIT( timer_idx)) + if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET) { - if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET) - { - HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET) - { - HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET) - { - HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET) - { - HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET) - { - HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET) - { - HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET) - { - HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET) - { - HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET) - { - HAL_HRTIM_Output1SetCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET) - { - HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET) - { - HAL_HRTIM_Output2SetCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET) - { - HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET) - { - HAL_HRTIM_CounterResetCallback(hrtim, timer_idx); - } - else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET) - { - HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx); - } + HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET) + { + HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET) + { + HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET) + { + HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET) + { + HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET) + { + HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET) + { + HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET) + { + HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET) + { + HAL_HRTIM_Output1SetCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET) + { + HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET) + { + HAL_HRTIM_Output2SetCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET) + { + HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET) + { + HAL_HRTIM_CounterResetCallback(hrtim, timer_idx); + } + else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET) + { + HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx); } } @@ -8195,7 +8218,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; - HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma)); + HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); } /** @@ -8205,7 +8228,8 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) /** * @} */ -#endif /* STM32F334x8 */ + +#endif /* HRTIM1 */ #endif /* HAL_HRTIM_MODULE_ENABLED */ @@ -8214,6 +8238,3 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c index 0fa36cc975..ff1ef7ae76 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c @@ -227,36 +227,92 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, * @note This function does not modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks - * @retval None + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { - /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + uint32_t tickstart = 0; + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Insure HSIRDY bit is set before writing default HSITRIM value */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM default value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO); + /* Insure HSI selected as system clock source */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till system clock source is ready */ + while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable for HSI as system clock source */ + SystemCoreClock = HSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + /* Reset HSEON, CSSON, PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); - + /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + /* Insure PLLRDY is reset */ + /* Get start tick */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - + /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); - + /* Reset CFGR3 register */ CLEAR_REG(RCC->CFGR3); - + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + /* Disable all interrupts */ CLEAR_REG(RCC->CIR); - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; + /* Reset all CSR flags */ + __HAL_RCC_CLEAR_RESET_FLAGS(); + + return HAL_OK; } /** @@ -275,10 +331,15 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ @@ -626,9 +687,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0U; - + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); @@ -637,14 +703,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -689,51 +755,29 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui return HAL_ERROR; } } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick */ tickstart = HAL_GetTick(); - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } + } /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c index 642074cff2..14edff617d 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c @@ -688,10 +688,8 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ (((uint32_t)sDate->Month) << 8U) | \ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c index 5845cba10a..3eaf1b2566 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c @@ -205,11 +205,11 @@ /** @defgroup SDADC_Private_Define SDADC Private Define * @{ */ -#define SDADC_TIMEOUT 200 -#define SDADC_CONFREG_OFFSET 0x00000020 -#define SDADC_JDATAR_CH_OFFSET 24 -#define SDADC_MSB_MASK 0xFFFF0000U -#define SDADC_LSB_MASK 0x0000FFFFU +#define SDADC_TIMEOUT 200UL +#define SDADC_CONFREG_OFFSET 0x00000020UL +#define SDADC_JDATAR_CH_OFFSET 24UL +#define SDADC_MSB_MASK 0xFFFF0000UL +#define SDADC_LSB_MASK 0x0000FFFFUL /** * @} */ @@ -322,7 +322,7 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc) hsdadc->Instance->CR2 |= SDADC_CR2_ADON; /* Wait end of stabilization */ - while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0U) + while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0UL) { } @@ -353,14 +353,14 @@ HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc) hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON); /* Reset all registers */ - hsdadc->Instance->CR1 = 0x00000000U; - hsdadc->Instance->CR2 = 0x00000000U; - hsdadc->Instance->JCHGR = 0x00000001U; - hsdadc->Instance->CONF0R = 0x00000000U; - hsdadc->Instance->CONF1R = 0x00000000U; - hsdadc->Instance->CONF2R = 0x00000000U; - hsdadc->Instance->CONFCHR1 = 0x00000000U; - hsdadc->Instance->CONFCHR2 = 0x00000000U; + hsdadc->Instance->CR1 = 0x00000000UL; + hsdadc->Instance->CR2 = 0x00000000UL; + hsdadc->Instance->JCHGR = 0x00000001UL; + hsdadc->Instance->CONF0R = 0x00000000UL; + hsdadc->Instance->CONF1R = 0x00000000UL; + hsdadc->Instance->CONF2R = 0x00000000UL; + hsdadc->Instance->CONFCHR1 = 0x00000000UL; + hsdadc->Instance->CONFCHR2 = 0x00000000UL; /* Call MSP deinit function */ HAL_SDADC_MspDeInit(hsdadc); @@ -443,12 +443,12 @@ HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, SDADC_ConfParamTypeDef* ConfParamStruct) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0U; + uint32_t tmp; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); assert_param(IS_SDADC_CONF_INDEX(ConfIndex)); - assert_param(ConfParamStruct != NULL); + assert_param(ConfParamStruct != ((void*) 0)); assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode)); assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain)); assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode)); @@ -473,7 +473,7 @@ HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, /* Program configuration register with parameters */ tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \ SDADC_CONFREG_OFFSET + \ - (uint32_t)(ConfIndex << 2U)); + (uint32_t)(ConfIndex << 2UL)); *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \ ConfParamStruct->Gain | \ ConfParamStruct->CommonMode | \ @@ -503,7 +503,7 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, uint32_t ConfIndex) { HAL_StatusTypeDef status = HAL_OK; - uint32_t channelnum = 0U; + uint32_t channelnum; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -530,11 +530,11 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, if(Channel != SDADC_CHANNEL_8) { /* Get channel number */ - channelnum = (uint32_t)(Channel>>16U); + channelnum = (uint32_t)(Channel>>16UL); /* Set the channel configuration */ - hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2U)); - hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2U)); + hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << ((channelnum << 2UL) & 0x1FUL)); + hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << ((channelnum << 2UL) & 0x1FUL)); } else { @@ -1014,7 +1014,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint3 /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1096,7 +1096,7 @@ HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, */ HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1148,7 +1148,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint3 /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1185,7 +1185,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint3 */ HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1215,7 +1215,7 @@ HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc) */ HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc) */ HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1282,12 +1282,12 @@ HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc) HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); - assert_param(pData != NULL); - assert_param(Length != 0U); + assert_param(pData != ((void*) 0)); + assert_param(Length != 0UL); /* Check that DMA is not enabled for injected conversion */ if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN) @@ -1353,7 +1353,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pDa */ HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1410,7 +1410,7 @@ uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc) */ HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1463,7 +1463,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0UL)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1482,7 +1482,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad } /* Update remaining injected conversions */ hsdadc->InjConvRemaining--; - if(hsdadc->InjConvRemaining == 0U) + if(hsdadc->InjConvRemaining == 0UL) { /* end of injected sequence, reset the value */ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr; @@ -1510,7 +1510,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad */ HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1540,7 +1540,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc) */ HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1571,7 +1571,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc) */ HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1607,12 +1607,12 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc) HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); - assert_param(pData != NULL); - assert_param(Length != 0U); + assert_param(pData != ((void*) 0)); + assert_param(Length != 0UL); /* Check that DMA is not enabled for regular conversion */ if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN) @@ -1678,7 +1678,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint3 */ HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1720,11 +1720,11 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc) */ uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel) { - uint32_t value = 0U; + uint32_t value; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != ((void*) 0)); /* Read SDADC_JDATAR register and extract channel and conversion value */ value = hsdadc->Instance->JDATAR; @@ -1747,12 +1747,12 @@ uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Chann HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); - assert_param(pData != NULL); - assert_param(Length != 0U); + assert_param(pData != ((void*) 0)); + assert_param(Length != 0UL); /* Check instance is SDADC1 */ if(hsdadc->Instance != SDADC1) @@ -1831,7 +1831,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint */ HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1877,7 +1877,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc) */ uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc) { - uint32_t value = 0U; + uint32_t value; /* Check parameters and check instance is SDADC1 */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1903,12 +1903,12 @@ uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc) HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); - assert_param(pData != NULL); - assert_param(Length != 0U); + assert_param(pData != ((void*) 0)); + assert_param(Length != 0UL); /* Check instance is SDADC1 */ if(hsdadc->Instance != SDADC1) @@ -1987,7 +1987,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsda */ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -2033,7 +2033,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdad */ uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc) { - uint32_t value = 0U; + uint32_t value; /* Check parameters and check instance is SDADC1 */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -2054,9 +2054,11 @@ uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc) */ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) { + uint32_t tmp_isr = hsdadc->Instance->ISR; + /* Check if end of regular conversion */ - if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \ - ((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE)) + if(((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) && + ((tmp_isr & SDADC_ISR_REOCF) == SDADC_ISR_REOCF)) { /* Call regular conversion complete callback */ HAL_SDADC_ConvCpltCallback(hsdadc); @@ -2074,15 +2076,15 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) } } /* Check if end of injected conversion */ - else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \ - ((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE)) + else if(((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE) && + ((tmp_isr & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF)) { /* Call injected conversion complete callback */ HAL_SDADC_InjectedConvCpltCallback(hsdadc); /* Update remaining injected conversions */ hsdadc->InjConvRemaining--; - if(hsdadc->InjConvRemaining ==0U) + if(hsdadc->InjConvRemaining ==0UL) { /* end of injected sequence, reset the value */ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr; @@ -2102,8 +2104,8 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) } } /* Check if end of calibration */ - else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \ - ((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE)) + else if(((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE) && + ((tmp_isr & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF)) { /* Clear EOCALIE bit in SDADC_CR1 register */ hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE); @@ -2118,8 +2120,8 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) hsdadc->State = HAL_SDADC_STATE_READY; } /* Check if overrun occurs during regular conversion */ - else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \ - ((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE)) + else if(((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE) && + ((tmp_isr & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)) { /* Set CLRROVRF bit in SDADC_CLRISR register */ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF; @@ -2131,8 +2133,8 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) HAL_SDADC_ErrorCallback(hsdadc); } /* Check if overrun occurs during injected conversion */ - else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \ - ((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE)) + else if(((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE) && + ((tmp_isr & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)) { /* Set CLRJOVRF bit in SDADC_CLRISR register */ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF; @@ -2372,7 +2374,7 @@ uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc) */ static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Set INIT bit on SDADC_CR1 register */ hsdadc->Instance->CR1 |= SDADC_CR1_INIT; @@ -2409,18 +2411,18 @@ static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc) */ static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels) { - uint32_t nbChannels = 0U; + uint32_t nbChannels = 0UL; uint32_t tmp,i; /* Get the number of channels from bitfield */ tmp = (uint32_t) (Channels & SDADC_LSB_MASK); - for(i = 0U ; i < 9U ; i++) + for(i = 0UL ; i < 9UL ; i++) { - if((tmp & 0x00000001U) != 0U) + if((tmp & 0x00000001UL) != 0UL) { nbChannels++; } - tmp = (uint32_t) (tmp >> 1U); + tmp = (uint32_t) (tmp >> 1UL); } return nbChannels; } @@ -2490,7 +2492,7 @@ static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc) } /* Wait for the end of regular conversion */ tickstart = HAL_GetTick(); - while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0U) + while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0UL) { if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT) { @@ -2614,7 +2616,7 @@ static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc) } /* Wait for the end of injected conversion */ tickstart = HAL_GetTick(); - while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0U) + while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0UL) { if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT) { diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c index 964139f6a2..761adcb9a4 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c @@ -194,6 +194,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ @@ -472,6 +476,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ @@ -979,6 +987,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM handle * @retval HAL status */ @@ -1489,6 +1501,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ @@ -1961,6 +1977,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @param htim TIM OnePulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2237,6 +2257,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c index cbdfce1745..929f947173 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen return HAL_ERROR; } - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); @@ -323,7 +323,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1U, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -365,7 +365,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -389,7 +389,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -415,7 +415,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -462,7 +462,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ @@ -512,7 +512,6 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -542,7 +541,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -572,7 +570,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -602,14 +599,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - + default: break; } @@ -639,7 +629,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -672,13 +661,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } break; - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - default: break; } @@ -712,7 +694,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -772,7 +753,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan break; case TIM_CHANNEL_3: -{ + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; @@ -786,23 +767,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - + default: break; } @@ -829,7 +794,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -860,13 +824,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } break; - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - default: break; } @@ -929,7 +886,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -958,7 +914,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -988,7 +943,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1018,14 +972,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - + default: break; } @@ -1055,7 +1002,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1087,14 +1033,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - + default: break; } @@ -1128,7 +1067,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -1202,23 +1140,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - + default: break; } @@ -1245,7 +1167,6 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1275,14 +1196,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - + default: break; } @@ -1336,7 +1250,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { +{ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1408,7 +1322,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /* Return function status */ return HAL_OK; - } +} /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the @@ -2016,13 +1930,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - + /* Check input state */ __HAL_LOCK(htim); - + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); @@ -2033,22 +1947,22 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); - + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - + /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } - + /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - + __HAL_UNLOCK(htim); return HAL_OK; @@ -2089,7 +2003,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); @@ -2099,14 +2013,14 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - + /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c index 4e04504fb2..80ee35564a 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c @@ -617,13 +617,13 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); - + /* Note: Hardware constraint (refer to description of this function): */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0U) { LL_COMP_WriteReg(COMPx, CSR, 0x00000000U); } @@ -634,7 +634,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) /* The only way to unlock the comparator is a device hardware reset. */ status = ERROR; } - + return status; } @@ -653,7 +653,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); @@ -663,10 +663,10 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMPx, COMP_InitStruct->OutputSelection)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource)); - + /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0U) { /* Configuration of comparator instance : */ /* - PowerMode */ @@ -714,7 +714,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* Initialization error: COMP instance is locked. */ status = ERROR; } - + return status; } @@ -870,18 +870,18 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); - + /* Note: Hardware constraint (refer to description of this function): */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0U) { /* Note: Connection switch is applicable only to COMP instance COMP1, */ /* therefore is COMP2 is selected the equivalent bit is */ /* kept unmodified. */ - if(COMPx == COMP1) + if (COMPx == COMP1) { CLEAR_BIT(COMP->CSR, ( COMP_CSR_COMP1MODE @@ -906,7 +906,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) ) << __COMP_BITOFFSET_INSTANCE(COMPx) ); } - + } else { @@ -915,7 +915,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) /* The only way to unlock the comparator is a device hardware reset. */ status = ERROR; } - + return status; } @@ -934,7 +934,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); @@ -943,10 +943,10 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); - + /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0U) { /* Configuration of comparator instance : */ /* - PowerMode */ @@ -958,7 +958,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* Note: Connection switch is applicable only to COMP instance COMP1, */ /* therefore is COMP2 is selected the equivalent bit is */ /* kept unmodified. */ - if(COMPx == COMP1) + if (COMPx == COMP1) { MODIFY_REG(COMP->CSR, ( COMP_CSR_COMP1MODE @@ -997,14 +997,14 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru ) << __COMP_BITOFFSET_INSTANCE(COMPx) ); } - + } else { /* Initialization error: COMP instance is locked. */ status = ERROR; } - + return status; } diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c index 5872914535..f54406c20b 100644 --- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c +++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c @@ -244,6 +244,10 @@ ErrorStatus LL_RCC_DeInit(void) /* Set HSION bit */ LL_RCC_HSI_Enable(); + /* Wait for HSI READY bit */ + while(LL_RCC_HSI_IsReady() != 1U) + {} + /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); @@ -252,11 +256,19 @@ ErrorStatus LL_RCC_DeInit(void) CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL)); LL_RCC_WriteReg(CFGR, vl_mask); + /* Wait till system clock source is ready */ + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + {} + /* Reset HSEON, CSSON, PLLON bits */ vl_mask = 0xFFFFFFFFU; CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); LL_RCC_WriteReg(CR, vl_mask); + /* Wait for PLL READY bit to be reset */ + while(LL_RCC_PLL_IsReady() != 0U) + {} + /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); @@ -276,6 +288,9 @@ ErrorStatus LL_RCC_DeInit(void) /* Disable all interrupts */ LL_RCC_WriteReg(CIR, 0x00000000U); + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + return SUCCESS; } diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index abfad245e6..109c8de7b5 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -3,7 +3,7 @@ * STM32F0: 1.7.0 * STM32F1: 1.1.2 * STM32F2: 1.2.2 - * STM32F3: 1.5.1 + * STM32F3: 1.5.2 * STM32F4: 1.7.4 * STM32F7: 1.2.5 * STM32L0: 1.8.2 From 20a10274424fcebc7b11c8d9c564cdaf2e94afde Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 17:18:09 +0200 Subject: [PATCH 009/109] Updated stm32f3xx_hal_conf.h in variant Follow STM32F3xx HAL Drivers to v1.5.2 Signed-off-by: Frederic.Pillon --- variants/NUCLEO_F302R8/stm32f3xx_hal_conf.h | 5 +++++ variants/NUCLEO_F303K8/stm32f3xx_hal_conf.h | 5 +++++ variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h | 7 ++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/variants/NUCLEO_F302R8/stm32f3xx_hal_conf.h b/variants/NUCLEO_F302R8/stm32f3xx_hal_conf.h index 9f0fdee21c..0a67fc4890 100644 --- a/variants/NUCLEO_F302R8/stm32f3xx_hal_conf.h +++ b/variants/NUCLEO_F302R8/stm32f3xx_hal_conf.h @@ -53,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +// #define HAL_CAN_LEGACY_MODULE_ENABLED // #define HAL_CEC_MODULE_ENABLED // #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED @@ -204,6 +205,10 @@ #include "stm32f3xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f3xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f3xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ diff --git a/variants/NUCLEO_F303K8/stm32f3xx_hal_conf.h b/variants/NUCLEO_F303K8/stm32f3xx_hal_conf.h index 9eee3425dc..8f478e6573 100644 --- a/variants/NUCLEO_F303K8/stm32f3xx_hal_conf.h +++ b/variants/NUCLEO_F303K8/stm32f3xx_hal_conf.h @@ -53,6 +53,7 @@ #define HAL_ADC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ @@ -230,6 +231,10 @@ #include "stm32f3xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f3xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f3xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ diff --git a/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h b/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h index bdc387d9ff..f1009cb7e7 100644 --- a/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h +++ b/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h @@ -52,7 +52,8 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -//#define HAL_CAN_MODULE_ENABLED +// #define HAL_CAN_MODULE_ENABLED +// #define HAL_CAN_LEGACY_MODULE_ENABLED // #define HAL_CEC_MODULE_ENABLED // #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED @@ -204,6 +205,10 @@ #include "stm32f3xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f3xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f3xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ From 620cdb55c8232be4f01a7ee9e9d99a365a1137eb Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 17:40:00 +0200 Subject: [PATCH 010/109] Update STM32F3xx CMSIS to v2.3.3 Included in STM32CubeF3 FW V1.10.0 Signed-off-by: Frederic.Pillon --- .../Device/ST/STM32F3xx/Include/stm32f301x8.h | 15 ++++-------- .../Device/ST/STM32F3xx/Include/stm32f302x8.h | 15 ++++-------- .../Device/ST/STM32F3xx/Include/stm32f302xc.h | 14 ++--------- .../Device/ST/STM32F3xx/Include/stm32f302xe.h | 18 ++++---------- .../Device/ST/STM32F3xx/Include/stm32f303x8.h | 21 +++++----------- .../Device/ST/STM32F3xx/Include/stm32f303xc.h | 24 +++++-------------- .../Device/ST/STM32F3xx/Include/stm32f303xe.h | 22 ++++------------- .../Device/ST/STM32F3xx/Include/stm32f318xx.h | 19 +++++---------- .../Device/ST/STM32F3xx/Include/stm32f328xx.h | 17 ++++--------- .../Device/ST/STM32F3xx/Include/stm32f334x8.h | 21 +++++----------- .../Device/ST/STM32F3xx/Include/stm32f358xx.h | 24 +++++-------------- .../Device/ST/STM32F3xx/Include/stm32f373xc.h | 9 ++++--- .../Device/ST/STM32F3xx/Include/stm32f378xx.h | 13 ++++++---- .../Device/ST/STM32F3xx/Include/stm32f398xx.h | 18 ++------------ .../Device/ST/STM32F3xx/Include/stm32f3xx.h | 4 ++-- .../Device/ST/STM32F3xx/Release_Notes.html | 4 +++- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 17 files changed, 74 insertions(+), 186 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h index a20c44ef2e..0d5b174cf7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -8354,9 +8354,6 @@ typedef struct ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - ((INSTANCE) == TIM1) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) @@ -8385,11 +8382,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -8577,8 +8570,8 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn #define COMP1_2_IRQn COMP2_IRQn -#define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_3_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -8592,8 +8585,8 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler #define COMP1_2_IRQHandler COMP2_IRQHandler -#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h index b5753c5b1d..a95daf50dd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -12104,9 +12104,6 @@ typedef struct ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - ((INSTANCE) == TIM1) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) @@ -12135,11 +12132,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -12329,9 +12322,9 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -12348,9 +12341,9 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h index 807124fcc7..1f92ecf3ac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -12364,10 +12364,6 @@ typedef struct ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4)) -/****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - ((INSTANCE) == TIM1) - /****************** TIM Instances : supporting Hall interface *****************/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) @@ -12398,13 +12394,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h index 754bab04e8..45aa279ba1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -14100,10 +14100,6 @@ typedef struct ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4)) -/****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - ((INSTANCE) == TIM1) - /****************** TIM Instances : supporting Hall interface *****************/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) @@ -14134,13 +14130,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -14381,9 +14371,9 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define COMP1_2_3_IRQn COMP1_2_IRQn #define COMP2_IRQn COMP1_2_IRQn #define COMP_IRQn COMP1_2_IRQn +#define COMP1_2_3_IRQn COMP1_2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -14400,9 +14390,9 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler #define COMP2_IRQHandler COMP1_2_IRQHandler #define COMP_IRQHandler COMP1_2_IRQHandler +#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h index 2a4b8cc7eb..14d256badb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -11868,9 +11868,6 @@ typedef struct ((INSTANCE) == TIM3)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1)) @@ -11903,13 +11900,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -12113,9 +12104,9 @@ typedef struct #define ADC1_IRQn ADC1_2_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP1_2_IRQn COMP2_IRQn -#define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_3_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -12129,9 +12120,9 @@ typedef struct #define ADC1_IRQHandler ADC1_2_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler -#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_3_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h index ec70ffd225..4e7a442a35 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -13021,10 +13021,6 @@ typedef struct ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8)) @@ -13066,15 +13062,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -13339,9 +13327,9 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn #define SDADC1_IRQn ADC4_IRQn -#define COMP1_2_IRQn COMP1_2_3_IRQn -#define COMP2_IRQn COMP1_2_3_IRQn #define COMP_IRQn COMP1_2_3_IRQn +#define COMP2_IRQn COMP1_2_3_IRQn +#define COMP1_2_IRQn COMP1_2_3_IRQn #define COMP4_6_IRQn COMP4_5_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -13361,9 +13349,9 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler #define SDADC1_IRQHandler ADC4_IRQHandler -#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler -#define COMP2_IRQHandler COMP1_2_3_IRQHandler #define COMP_IRQHandler COMP1_2_3_IRQHandler +#define COMP2_IRQHandler COMP1_2_3_IRQHandler +#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h index 6e1348b119..95d22ecde3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -14837,11 +14837,6 @@ typedef struct ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM20)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ @@ -14888,16 +14883,7 @@ typedef struct ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15) || \ - ((INSTANCE) == TIM20)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -15188,8 +15174,8 @@ typedef struct #define ADC1_IRQn ADC1_2_IRQn #define SDADC1_IRQn ADC4_IRQn #define COMP1_2_IRQn COMP1_2_3_IRQn -#define COMP2_IRQn COMP1_2_3_IRQn #define COMP_IRQn COMP1_2_3_IRQn +#define COMP2_IRQn COMP1_2_3_IRQn #define COMP4_6_IRQn COMP4_5_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -15213,8 +15199,8 @@ typedef struct #define ADC1_IRQHandler ADC1_2_IRQHandler #define SDADC1_IRQHandler ADC4_IRQHandler #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler -#define COMP2_IRQHandler COMP1_2_3_IRQHandler #define COMP_IRQHandler COMP1_2_3_IRQHandler +#define COMP2_IRQHandler COMP1_2_3_IRQHandler #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h index d732bb6d2b..18af0998cf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -8339,9 +8339,6 @@ typedef struct ((INSTANCE) == TIM2)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - ((INSTANCE) == TIM1) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ ((INSTANCE) == TIM1) @@ -8370,11 +8367,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -8561,9 +8554,9 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn -#define COMP1_2_IRQn COMP2_IRQn -#define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_3_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -8576,9 +8569,9 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler -#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_3_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h index a743cc3774..2704126d0e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -11838,9 +11838,6 @@ typedef struct ((INSTANCE) == TIM3)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1)) @@ -11873,13 +11870,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -12083,9 +12074,9 @@ typedef struct #define ADC1_IRQn ADC1_2_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -12099,9 +12090,9 @@ typedef struct #define ADC1_IRQHandler ADC1_2_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h index 4101bac424..6d07fd5233 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -14826,9 +14826,6 @@ typedef struct ((INSTANCE) == TIM3)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1)) @@ -14861,13 +14858,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -15071,9 +15062,9 @@ typedef struct #define ADC1_IRQn ADC1_2_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP1_2_IRQn COMP2_IRQn -#define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_3_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define I2C3_ER_IRQn HRTIM1_FLT_IRQn #define I2C3_EV_IRQn HRTIM1_TIME_IRQn @@ -15089,9 +15080,9 @@ typedef struct #define ADC1_IRQHandler ADC1_2_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler -#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_3_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler #define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h index b2518d8006..1a3fbcaad5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -12807,10 +12807,6 @@ typedef struct ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8)) @@ -12852,15 +12848,7 @@ typedef struct ((INSTANCE) == TIM15)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ @@ -13124,9 +13112,9 @@ typedef struct #define SDADC1_IRQn ADC4_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP1_2_IRQn COMP1_2_3_IRQn -#define COMP2_IRQn COMP1_2_3_IRQn #define COMP_IRQn COMP1_2_3_IRQn +#define COMP2_IRQn COMP1_2_3_IRQn +#define COMP1_2_IRQn COMP1_2_3_IRQn #define COMP4_6_IRQn COMP4_5_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -13144,9 +13132,9 @@ typedef struct #define SDADC1_IRQHandler ADC4_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler -#define COMP2_IRQHandler COMP1_2_3_IRQHandler #define COMP_IRQHandler COMP1_2_3_IRQHandler +#define COMP2_IRQHandler COMP1_2_3_IRQHandler +#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h index 47025d87d6..66af9b7d0a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h @@ -11669,7 +11669,7 @@ typedef struct ((INSTANCE) == TIM19)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE) (0) +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (0) /****************** TIM Instances : supporting input XOR function *************/ #define IS_TIM_XOR_INSTANCE(INSTANCE)\ @@ -11701,6 +11701,9 @@ typedef struct ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM19)) +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) + /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ @@ -11940,9 +11943,9 @@ typedef struct #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn #define USBWakeUp_IRQn CEC_IRQn -#define COMP1_2_IRQn COMP_IRQn #define COMP1_2_3_IRQn COMP_IRQn #define COMP2_IRQn COMP_IRQn +#define COMP1_2_IRQn COMP_IRQn #define ADC4_IRQn SDADC1_IRQn #define TIM8_BRK_IRQn TIM12_IRQn #define TIM8_UP_IRQn TIM13_IRQn @@ -11962,9 +11965,9 @@ typedef struct #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler #define USBWakeUp_IRQHandler CEC_IRQHandler -#define COMP1_2_IRQHandler COMP_IRQHandler #define COMP1_2_3_IRQHandler COMP_IRQHandler #define COMP2_IRQHandler COMP_IRQHandler +#define COMP1_2_IRQHandler COMP_IRQHandler #define ADC4_IRQHandler SDADC1_IRQHandler #define TIM8_BRK_IRQHandler TIM12_IRQHandler #define TIM8_UP_IRQHandler TIM13_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h index fdede2a040..13e9a6b789 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h @@ -11462,7 +11462,7 @@ typedef struct ((INSTANCE) == TIM19)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE) (0) +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (0) /****************** TIM Instances : supporting input XOR function *************/ #define IS_TIM_XOR_INSTANCE(INSTANCE)\ @@ -11494,6 +11494,9 @@ typedef struct ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM19)) +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) + /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ @@ -11730,9 +11733,9 @@ typedef struct #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn #define USBWakeUp_IRQn CEC_IRQn -#define COMP1_2_IRQn COMP_IRQn -#define COMP1_2_3_IRQn COMP_IRQn #define COMP2_IRQn COMP_IRQn +#define COMP1_2_3_IRQn COMP_IRQn +#define COMP1_2_IRQn COMP_IRQn #define ADC4_IRQn SDADC1_IRQn #define TIM8_BRK_IRQn TIM12_IRQn #define TIM8_UP_IRQn TIM13_IRQn @@ -11751,9 +11754,9 @@ typedef struct #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler #define USBWakeUp_IRQHandler CEC_IRQHandler -#define COMP1_2_IRQHandler COMP_IRQHandler -#define COMP1_2_3_IRQHandler COMP_IRQHandler #define COMP2_IRQHandler COMP_IRQHandler +#define COMP1_2_3_IRQHandler COMP_IRQHandler +#define COMP1_2_IRQHandler COMP_IRQHandler #define ADC4_IRQHandler SDADC1_IRQHandler #define TIM8_BRK_IRQHandler TIM12_IRQHandler #define TIM8_UP_IRQHandler TIM13_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h index 5972d1fa44..4b4eee01b6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheralÂ’s registers hardware * ****************************************************************************** * @attention @@ -14610,11 +14610,6 @@ typedef struct ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting Hall interface *****************/ -#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM20)) - #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ @@ -14661,16 +14656,7 @@ typedef struct ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ - (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM3) || \ - ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM6) || \ - ((INSTANCE) == TIM7) || \ - ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15) || \ - ((INSTANCE) == TIM20)) +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h index 012868e7c3..4d0fbfb4ca 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h @@ -192,8 +192,8 @@ typedef enum typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.html index ebe2c8fe27..bab35bbabf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F3xx/Release_Notes.html @@ -87,7 +87,9 @@

          Update History

          -

          V2.3.2 / 23-June-2017

          Main +

          V2.3.3 / 11-June-2018

          Main +Changes

          +
          • General update
            • Align ErrorStatus typedef to common error handling ( stm32f3xx.h )
          • TIM updates
            • Add IS_TIM_SYNCHRO_INSTANCE macro for STM32F37xxx devices
            • Add IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE macro definition

          V2.3.2 / 23-June-2017

          Main Changes

          • Remove support of Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain.
          • FLASH updates
            • Clean-up OB_WRP2_nWRP2 && OB_WRP2_nWRP3 (Option Byte) definitions according to family diversity.
          • RTC updates
            • Renamed RTC_CR_BCK to RTC_CR_BKP in RTC_CR register in order to be aligned with STM32F3xx Reference Manual.
          • SYSCFG updates
            • Removed SYSCFG_CFGR3_DAC1_TRG3, SYSCFG_CFGR3_DAC1_TRG5, SYSCFG_CFGR3_TRIGGER definitions for STM32F328xx devices.
          • SPI updates
            • Removed SPI_SR_CHSIDE, SPI_SR_UDR definitions for STM32F303x8, STM32F328xx, STM32F334x8 devices.
          • EXTI updates
            • Add EXTI_EMR2_EM definition.
          • COMP updates
            • Clean-up COMPx_CSR definitions according to family diversity.

          V2.3.1 / 16-December-2016

          Main Changes

          diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index cb9f4972f7..6580c5586c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -3,7 +3,7 @@ * STM32F0: 2.3.3 * STM32F1: 4.2.0 * STM32F2: 2.2.1 - * STM32F3: 2.3.2 + * STM32F3: 2.3.3 * STM32F4: 2.6.2 * STM32F7: 1.2.2 * STM32L0: 1.7.2 From d4f0f1ef99b576e7a363da7a3f25e7fc8482c801 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 17:50:18 +0200 Subject: [PATCH 011/109] Update STM32F7xx HAL Drivers to v1.2.6 Included in STM32CubeF7 FW V1.12.0 Signed-off-by: Frederic.Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 27 +- .../Inc/stm32f7xx_hal_dma_ex.h | 8 +- .../Inc/stm32f7xx_hal_flash.h | 116 +- .../Inc/stm32f7xx_hal_flash_ex.h | 141 ++- .../Inc/stm32f7xx_hal_gpio_ex.h | 33 +- .../Inc/stm32f7xx_hal_hash.h | 4 +- .../Inc/stm32f7xx_hal_hash_ex.h | 4 +- .../Inc/stm32f7xx_hal_hcd.h | 39 +- .../Inc/stm32f7xx_hal_ltdc.h | 4 +- .../Inc/stm32f7xx_hal_pcd.h | 210 ++-- .../Inc/stm32f7xx_hal_pcd_ex.h | 31 +- .../Inc/stm32f7xx_hal_rcc_ex.h | 820 +++++++------- .../Inc/stm32f7xx_ll_usb.h | 326 +++--- .../STM32F7xx_HAL_Driver/Release_Notes.html | 4 +- .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 4 +- .../Src/stm32f7xx_hal_hash.c | 4 +- .../Src/stm32f7xx_hal_hash_ex.c | 4 +- .../Src/stm32f7xx_hal_hcd.c | 588 ++++++----- .../Src/stm32f7xx_hal_ltdc.c | 4 +- .../Src/stm32f7xx_hal_pcd.c | 608 ++++++----- .../Src/stm32f7xx_hal_pcd_ex.c | 186 +--- .../Src/stm32f7xx_hal_rcc_ex.c | 651 ++++++------ .../Src/stm32f7xx_ll_usb.c | 998 ++++++++++-------- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 24 files changed, 2534 insertions(+), 2282 deletions(-) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 24e0234348..4361ef4ef2 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -381,7 +381,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -431,12 +431,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -564,7 +564,7 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -2120,20 +2120,6 @@ #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2804,7 +2790,6 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -2932,10 +2917,8 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) -#else + #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h index 8eee9ae716..0830c7aab4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -93,7 +93,7 @@ typedef enum #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ @@ -103,7 +103,7 @@ typedef enum #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ /** * @} @@ -143,7 +143,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ ((CHANNEL) == DMA_CHANNEL_1) || \ ((CHANNEL) == DMA_CHANNEL_2) || \ @@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre ((CHANNEL) == DMA_CHANNEL_6) || \ ((CHANNEL) == DMA_CHANNEL_7)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h index 2923e66813..e98aea81e7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_FLASH_H @@ -50,40 +50,40 @@ /** @addtogroup FLASH * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ - + /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { - FLASH_PROC_NONE = 0U, + FLASH_PROC_NONE = 0U, FLASH_PROC_SECTERASE, FLASH_PROC_MASSERASE, FLASH_PROC_PROGRAM } FLASH_ProcedureTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - + __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ - + __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ __IO uint32_t Address; /* Internal variable to save address selected for program */ - + HAL_LockTypeDef Lock; /* FLASH locking object */ __IO uint32_t ErrorCode; /* FLASH error code */ @@ -97,12 +97,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ - */ + */ /** @defgroup FLASH_Error_Code FLASH Error Code - * @brief FLASH Error Code + * @brief FLASH Error Code * @{ - */ + */ #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ #define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ @@ -113,10 +113,10 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Type_Program FLASH Type Program * @{ - */ + */ #define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ #define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ #define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ @@ -128,7 +128,7 @@ typedef struct /** @defgroup FLASH_Flag_definition FLASH Flag definition * @brief Flag definition * @{ - */ + */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ @@ -169,11 +169,11 @@ typedef struct #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) /** * @} - */ + */ /** @defgroup FLASH_Keys FLASH Keys * @{ - */ + */ #define FLASH_KEY1 ((uint32_t)0x45670123U) #define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) @@ -185,6 +185,15 @@ typedef struct /** @defgroup FLASH_Sectors FLASH Sectors * @{ */ +#if (FLASH_SECTOR_TOTAL == 2) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#elif (FLASH_SECTOR_TOTAL == 4) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#else #define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ #define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ #define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ @@ -193,21 +202,22 @@ typedef struct #define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ #define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ #define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#endif /* FLASH_SECTOR_TOTAL */ /** * @} - */ + */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @{ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -216,74 +226,74 @@ typedef struct /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * The value of this parameter depend on device used within the same series - */ + */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** * @brief Enable the FLASH prefetch buffer. * @retval none - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) /** * @brief Disable the FLASH prefetch buffer. * @retval none - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) /** * @brief Enable the FLASH Adaptive Real-Time memory accelerator. * @note The ART accelerator is available only for flash access on ITCM interface. * @retval none - */ + */ #define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) /** * @brief Disable the FLASH Adaptive Real-Time memory accelerator. * @retval none - */ + */ #define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) /** * @brief Resets the FLASH Adaptive Real-Time memory accelerator. * @note This function must be used only when the Adaptive Real-Time memory accelerator - * is disabled. + * is disabled. * @retval None */ #define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt + * @arg FLASH_IT_ERR: Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt + * @arg FLASH_IT_ERR: Error Interrupt * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) /** - * @brief Get the specified FLASH flag status. + * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag * @arg FLASH_FLAG_BSY : FLASH Busy flag * @retval The new state of __FLAG__ (SET or RESET). */ @@ -293,12 +303,12 @@ typedef struct * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) @@ -321,7 +331,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** @@ -369,9 +379,9 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); * @{ */ -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) /** @@ -389,7 +399,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) /** * @} */ @@ -409,7 +419,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} - */ + */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h index 21ebcf0e74..dff3b4a32f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -52,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASH Exported Types * @{ */ @@ -65,11 +65,11 @@ typedef struct uint32_t TypeErase; /*!< Mass erase or sector Erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ -#if defined (FLASH_OPTCR_nDBANK) +#if defined (FLASH_OPTCR_nDBANK) uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. This parameter must be a value of @ref FLASHEx_Banks */ -#endif /* FLASH_OPTCR_nDBANK */ - +#endif /* FLASH_OPTCR_nDBANK */ + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled This parameter must be a value of @ref FLASHEx_Sectors */ @@ -101,10 +101,10 @@ typedef struct uint32_t BORLevel; /*!< Set the BOR Level. This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ - + uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. This parameter can be a value of @ref FLASHEx_Boot_Address */ @@ -116,7 +116,7 @@ typedef struct This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ #endif /* FLASH_OPTCR2_PCROP */ } FLASH_OBProgramInitTypeDef; @@ -132,16 +132,16 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ - */ + */ #define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ /** * @} */ - + /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range * @{ - */ + */ #define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ #define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ #define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ @@ -149,19 +149,19 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ - */ + */ #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ /** * @} */ - + /** @defgroup FLASHEx_Option_Type FLASH Option Type * @{ - */ + */ #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ @@ -175,49 +175,49 @@ typedef struct /** * @} */ - + /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection * @{ */ #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) #define OB_RDP_LEVEL_1 ((uint8_t)0x55U) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0 */ /** * @} - */ - + */ + /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog * @{ - */ + */ #define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ #define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ /** * @} - */ - + */ + /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ - */ + */ #define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ /** * @} - */ + */ /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP * @{ - */ + */ #define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ /** * @} - */ + */ /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY * @{ - */ + */ #define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ /** @@ -256,13 +256,13 @@ typedef struct #if defined (FLASH_OPTCR_nDBOOT) /** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT * @{ - */ + */ #define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ -#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash (Dual bank Boot mode), or RAM if Boot address option in RAM */ /** * @} - */ + */ #endif /* FLASH_OPTCR_nDBOOT */ #if defined (FLASH_OPTCR_nDBANK) @@ -293,7 +293,7 @@ typedef struct /** * @} */ - + /** @defgroup FLASH_Latency FLASH Latency * @{ */ @@ -364,14 +364,14 @@ typedef struct #endif /* FLASH_SECTOR_TOTAL == 24 */ /** * @} - */ + */ #if (FLASH_SECTOR_TOTAL == 24) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. * @{ @@ -388,7 +388,7 @@ typedef struct #define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ #define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ #define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ -#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ #define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ /* Dual Bank Sectors */ @@ -403,7 +403,7 @@ typedef struct #define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ #define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ #define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ -#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ #define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ #define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ #define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ @@ -421,7 +421,7 @@ typedef struct * @} */ #endif /* FLASH_SECTOR_TOTAL == 24 */ - + #if (FLASH_SECTOR_TOTAL == 8) /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ @@ -440,7 +440,34 @@ typedef struct */ #endif /* FLASH_SECTOR_TOTAL == 8 */ +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 2 */ + #if defined (FLASH_OPTCR2_PCROP) +#if (FLASH_SECTOR_TOTAL == 8) /** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors * @{ */ @@ -456,6 +483,21 @@ typedef struct /** * @} */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ /** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit * @{ @@ -469,8 +511,8 @@ typedef struct /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @{ @@ -485,7 +527,7 @@ typedef struct /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ @@ -520,15 +562,15 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); */ #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_4)) + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) + ((VALUE) == OB_WRPSTATE_ENABLE)) #if defined (FLASH_OPTCR2_PCROP) #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ @@ -607,6 +649,19 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) #endif /* FLASH_SECTOR_TOTAL == 24 */ +#if (FLASH_SECTOR_TOTAL == 4) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 2 */ + #if defined (FLASH_OPTCR_nDBANK) #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ ((VALUE) == OB_NDBANK_DUAL_BANK)) @@ -642,11 +697,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h index 4cd62e5e97..7f17aa41ae 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -64,7 +64,7 @@ */ /*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** * @brief AF 0 selection */ @@ -173,12 +173,12 @@ #define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @brief AF 10 selection */ @@ -220,14 +220,14 @@ #if defined (STM32F769xx) || defined (STM32F779xx) #define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) #define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @brief AF 15 selection */ @@ -236,7 +236,7 @@ /*----------------------------------------------------------------------------*/ /*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) /** * @brief AF 0 selection */ @@ -348,7 +348,7 @@ * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /*----------------------------------------------------------------------------*/ /** @@ -410,7 +410,8 @@ * @{ */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -421,9 +422,9 @@ ((__GPIOx__) == (GPIOH))? 7U :\ ((__GPIOx__) == (GPIOI))? 8U :\ ((__GPIOx__) == (GPIOJ))? 9U : 10U) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -432,7 +433,7 @@ ((__GPIOx__) == (GPIOF))? 5U :\ ((__GPIOx__) == (GPIOG))? 6U :\ ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /** * @} */ @@ -452,7 +453,7 @@ /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ @@ -611,7 +612,7 @@ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ ((AF) == GPIO_AF10_OTG_FS)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ @@ -638,7 +639,7 @@ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ ((AF) == GPIO_AF10_OTG_FS)) -#endif /* STM32F756xx || STM32F746xx */ +#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h index b79a5a5167..921dc21896 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -433,7 +433,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h index cad9c4611c..aab63ed0ff 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -183,7 +183,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h index efde17408d..bd08e87c70 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h @@ -48,8 +48,7 @@ * @{ */ -/** @defgroup HCD HCD - * @brief HCD HAL module driver +/** @addtogroup HCD * @{ */ @@ -63,18 +62,18 @@ */ typedef enum { - HAL_HCD_STATE_RESET = 0x00U, - HAL_HCD_STATE_READY = 0x01U, - HAL_HCD_STATE_ERROR = 0x02U, - HAL_HCD_STATE_BUSY = 0x03U, - HAL_HCD_STATE_TIMEOUT = 0x04U + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; -typedef USB_OTG_HCTypeDef HCD_HCTypeDef ; -typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ; -typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; /** * @} */ @@ -86,7 +85,7 @@ typedef struct { HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ void *pData; /*!< Pointer Stack Handler */ @@ -132,8 +131,8 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) @@ -166,9 +165,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); /** * @} */ @@ -233,14 +232,6 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ -/** @defgroup HCD_Instance_definition HCD Instance definition - * @{ - */ -#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ - ((INSTANCE) == USB_OTG_HS)) -/** - * @} - */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h index 8e048ecc3f..fe577b95b3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h @@ -41,7 +41,7 @@ extern "C" { #endif -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -646,7 +646,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h index faf27ecb63..6b4de792a9 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_PCD_H @@ -43,72 +43,75 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_ll_usb.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ - + /** * @brief PCD State structure definition - */ -typedef enum + */ +typedef enum { - HAL_PCD_STATE_RESET = 0x00U, - HAL_PCD_STATE_READY = 0x01U, - HAL_PCD_STATE_ERROR = 0x02U, - HAL_PCD_STATE_BUSY = 0x03U, - HAL_PCD_STATE_TIMEOUT = 0x04U + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 } PCD_StateTypeDef; /* Device LPM suspend state */ -typedef enum +typedef enum { - LPM_L0 = 0x00U, /* on */ - LPM_L1 = 0x01U, /* LPM L1 sleep */ - LPM_L2 = 0x02U, /* suspend */ - LPM_L3 = 0x03U, /* off */ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ }PCD_LPM_StateTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef ; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* USB_OTG_FS || USB_OTG_HS */ + -/** - * @brief PCD Handle Structure definition - */ +/** + * @brief PCD Handle Structure definition + */ typedef struct { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; /** * @} */ - -/* Include PCD HAL Extension module */ + +/* Include PCD HAL Extended module */ #include "stm32f7xx_hal_pcd_ex.h" /* Exported constants --------------------------------------------------------*/ @@ -119,13 +122,15 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ +#if defined (USB_OTG_HS) #define PCD_SPEED_HIGH 0U #define PCD_SPEED_HIGH_IN_FULL 1U +#endif #define PCD_SPEED_FULL 2U /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ @@ -145,87 +150,58 @@ typedef struct #ifndef USBD_FS_TRDT_VALUE #define USBD_FS_TRDT_VALUE 5U #endif /* USBD_HS_TRDT_VALUE */ - /** * @} */ /** * @} - */ - + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) + ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) - -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U) -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU) -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U) -#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - }while(0) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) - +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - }while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - }while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - }while(0) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* USB_OTG_FS || USB_OTG_HS */ -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) /** * @} */ @@ -240,7 +216,7 @@ typedef struct * @{ */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /** @@ -299,42 +275,70 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} - */ + */ /** * @} - */ + */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -/** @defgroup PCD_Instance_definition PCD Instance definition +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants * @{ */ -#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ - ((INSTANCE) == USB_OTG_HS)) +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#ifndef LL_EXTI_LINE_18 +#define LL_EXTI_LINE_18 0x00040000U +#endif + +#ifndef LL_EXTI_LINE_20 +#define LL_EXTI_LINE_20 0x00100000U +#endif + +#define USB_OTG_FS_WAKEUP_EXTI_LINE LL_EXTI_LINE_18 /*!< External interrupt line 17 Connected to the USB EXTI Line */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE LL_EXTI_LINE_20 /*!< External interrupt line 20 Connected to the USB HS EXTI Line */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + + +/** + * @} + */ + /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } #endif - #endif /* __STM32F7xx_HAL_PCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h index 64a146dbbc..1a3745eaf6 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @brief Header file of PCD HAL module. + * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention * @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_PCD_EX_H @@ -43,7 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" - + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -52,21 +52,21 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ -typedef enum +typedef enum { - PCD_LPM_L0_ACTIVE = 0x00U, /* on */ - PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; -typedef enum +typedef enum { - PCD_BCD_ERROR = 0xFF, + PCD_BCD_ERROR = 0xFF, PCD_BCD_CONTACT_DETECTION = 0xFE, PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, PCD_BCD_DISCOVERY_COMPLETED = 0x00, - + }PCD_BCD_MsgTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -78,27 +78,28 @@ typedef enum /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* USB_OTG_FS || USB_OTG_HS */ + HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h index 8f79fc4eb0..6181ff41e0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h - * @author MCD Application Team + * @author MCD Application Team * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_HAL_RCC_EX_H @@ -50,15 +50,15 @@ /** @addtogroup RCCEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ - -/** - * @brief RCC PLL configuration structure definition + +/** + * @brief RCC PLL configuration structure definition */ typedef struct { @@ -66,10 +66,10 @@ typedef struct This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ @@ -82,12 +82,12 @@ typedef struct #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -}RCC_PLLInitTypeDef; +}RCC_PLLInitTypeDef; -/** - * @brief PLLI2S Clock structure definition +/** + * @brief PLLI2S Clock structure definition */ typedef struct { @@ -96,58 +96,58 @@ typedef struct This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLI2S is selected as Clock Source SAI */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ }RCC_PLLI2SInitTypeDef; -/** - * @brief PLLSAI Clock structure definition +/** + * @brief PLLSAI Clock structure definition */ typedef struct { uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter will be used only when PLLSAI is disabled */ }RCC_PLLSAIInitTypeDef; -/** - * @brief RCC extended clocks structure definition +/** + * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. @@ -161,82 +161,82 @@ typedef struct uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. + uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. + + uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ - uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ - + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source + + uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source + + uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t Uart4ClockSelection; /*!< UART4 clock source + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - - uint32_t Uart5ClockSelection; /*!< UART5 clock source + + uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - - uint32_t Usart6ClockSelection; /*!< USART6 clock source + + uint32_t Usart6ClockSelection; /*!< USART6 clock source This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ - - uint32_t Uart7ClockSelection; /*!< UART7 clock source + + uint32_t Uart7ClockSelection; /*!< UART7 clock source This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ - - uint32_t Uart8ClockSelection; /*!< UART8 clock source + + uint32_t Uart8ClockSelection; /*!< UART8 clock source This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - uint32_t I2c2ClockSelection; /*!< I2C2 clock source + uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - uint32_t I2c3ClockSelection; /*!< I2C3 clock source + uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - - uint32_t I2c4ClockSelection; /*!< I2C4 clock source + + uint32_t I2c4ClockSelection; /*!< I2C4 clock source This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t CecClockSelection; /*!< CEC clock source + + uint32_t CecClockSelection; /*!< CEC clock source This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - + uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source + + uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - + #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ - - uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ }RCC_PeriphCLKInitTypeDef; /** * @} @@ -251,9 +251,9 @@ typedef struct * @{ */ #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) @@ -277,20 +277,20 @@ typedef struct #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) -#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /** * @} */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider * @{ */ @@ -301,8 +301,8 @@ typedef struct /** * @} */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider * @{ */ @@ -333,9 +333,8 @@ typedef struct /** * @} - */ - - + */ + /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source * @{ */ @@ -347,7 +346,7 @@ typedef struct #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source * @{ @@ -360,7 +359,7 @@ typedef struct #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ @@ -540,7 +539,7 @@ typedef struct */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source * @{ */ @@ -549,9 +548,9 @@ typedef struct /** * @} */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source * @{ */ @@ -576,16 +575,16 @@ typedef struct * @{ */ #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) -#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) /** * @} - */ + */ #endif /* STM32F769xx || STM32F779xx */ /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ @@ -593,14 +592,14 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable * @brief Enables or disables the AHB/APB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ - + /** @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ @@ -610,7 +609,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ @@ -618,7 +617,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ @@ -716,7 +715,8 @@ typedef struct } while(0) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ @@ -732,7 +732,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ @@ -740,7 +740,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) @@ -757,14 +757,16 @@ typedef struct #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** * @brief Enable ETHERNET clock. */ @@ -799,7 +801,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_ETH_CLK_ENABLE() do { \ __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ @@ -817,15 +819,16 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ @@ -834,9 +837,9 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ @@ -844,8 +847,8 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -862,12 +865,12 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ UNUSED(tmpreg); \ __HAL_RCC_SYSCFG_CLK_ENABLE();\ - } while(0) + } while(0) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -883,12 +886,12 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ @@ -896,14 +899,14 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ UNUSED(tmpreg); \ } while(0) - -#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) -#endif /* STM32F732xx || STM32F733xx */ - + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + /** @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. */ #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -926,8 +929,8 @@ typedef struct /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1011,7 +1014,7 @@ typedef struct #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ @@ -1020,7 +1023,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ @@ -1031,7 +1034,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ @@ -1103,7 +1106,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0) - + #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ @@ -1135,9 +1138,10 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ UNUSED(tmpreg); \ } while(0) - + #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ @@ -1169,7 +1173,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) @@ -1183,13 +1187,13 @@ typedef struct #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) @@ -1204,16 +1208,17 @@ typedef struct #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. */ #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ @@ -1249,7 +1254,7 @@ typedef struct } while(0) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ @@ -1257,7 +1262,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1363,7 +1368,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1371,26 +1376,26 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0) #define __HAL_RCC_MDIO_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1400,7 +1405,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ @@ -1408,16 +1413,16 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ UNUSED(tmpreg); \ } while(0) -#endif /* STM32F723xx || STM32F733xx */ - +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1431,25 +1436,24 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) -#endif /* STM32F723xx || STM32F733xx */ - +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + /** * @} */ - /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB/APB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1457,15 +1461,15 @@ typedef struct * using it. * @{ */ - + /** @brief Get the enable or disable status of the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. + * using it. */ #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) @@ -1478,11 +1482,12 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) @@ -1499,14 +1504,16 @@ typedef struct #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** * @brief Enable ETHERNET clock. */ @@ -1528,36 +1535,37 @@ typedef struct #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. + * using it. */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F732xx) || defined (STM32F733xx) +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) @@ -1568,7 +1576,7 @@ typedef struct * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. - */ + */ #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) @@ -1634,7 +1642,8 @@ typedef struct #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) @@ -1644,15 +1653,15 @@ typedef struct #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1676,23 +1685,23 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) @@ -1711,35 +1720,35 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ /** * @} - */ + */ /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset * @brief Forces or releases AHB/APB peripheral reset. * @{ */ - + /** @brief Force or release AHB1 peripheral reset. - */ + */ #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) @@ -1765,7 +1774,8 @@ typedef struct #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) @@ -1775,11 +1785,11 @@ typedef struct #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) @@ -1792,36 +1802,37 @@ typedef struct #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release AHB3 peripheral reset - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) - + /** @brief Force or release APB1 peripheral reset. - */ + */ #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) @@ -1877,17 +1888,18 @@ typedef struct #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - + #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Force or release APB2 peripheral reset. */ @@ -1906,12 +1918,12 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1928,12 +1940,12 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx */ +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) @@ -1941,10 +1953,10 @@ typedef struct #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) @@ -1954,7 +1966,7 @@ typedef struct #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /** * @} - */ + */ /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. @@ -1963,10 +1975,10 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ - */ - + */ + /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - */ + */ #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) @@ -2006,7 +2018,8 @@ typedef struct #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) @@ -2022,7 +2035,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2031,10 +2044,11 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) @@ -2047,18 +2061,18 @@ typedef struct #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - + #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2077,7 +2091,7 @@ typedef struct * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) @@ -2134,14 +2148,15 @@ typedef struct #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) @@ -2150,15 +2165,15 @@ typedef struct #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) @@ -2175,9 +2190,9 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -2195,9 +2210,9 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) @@ -2209,16 +2224,17 @@ typedef struct #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ @@ -2231,12 +2247,12 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ - + /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) @@ -2277,7 +2293,8 @@ typedef struct #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) @@ -2293,7 +2310,7 @@ typedef struct #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2302,34 +2319,35 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) - + #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx */ +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2348,7 +2366,7 @@ typedef struct * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) @@ -2361,10 +2379,10 @@ typedef struct #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -2394,10 +2412,10 @@ typedef struct #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) + defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx */ + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ @@ -2416,24 +2434,25 @@ typedef struct #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) - + #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) @@ -2450,16 +2469,16 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) @@ -2481,26 +2500,27 @@ typedef struct #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #if defined (STM32F769xx) || defined (STM32F779xx) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) #endif /* STM32F769xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} */ @@ -2513,7 +2533,7 @@ typedef struct * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input @@ -2549,7 +2569,7 @@ typedef struct * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input @@ -2575,45 +2595,45 @@ typedef struct ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*---------------------------------------------------------------------------------------------*/ -/** @brief Macro to configure the Timers clocks prescalers +/** @brief Macro to configure the Timers clocks prescalers * @param __PRESC__ specifies the Timers clocks prescalers selection * This parameter can be one of the following values: - * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding * to division by 8 or more. - */ + */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ RCC->DCKCFGR1 |= (__PRESC__); \ }while(0) -/** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in + * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - */ + */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ @@ -2621,18 +2641,18 @@ typedef struct /** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. + * on the I2S clock frequency. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ @@ -2641,20 +2661,20 @@ typedef struct #else /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in + * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ @@ -2662,33 +2682,33 @@ typedef struct /** @brief Macro to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. - * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. + * on the I2S clock frequency. */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. + * @note This function must be called before enabling the PLLI2S. * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) @@ -2696,69 +2716,69 @@ typedef struct * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between Min_Data = 1 and Max_Data = 32. - * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. + * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. - * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** @brief Macro to configure SAI1 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__ specifies the SAI1 clock source. * This parameter can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) - /** @brief Macro to configure SAI2 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and + * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__ specifies the SAI2 clock source. * This parameter can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) @@ -2766,15 +2786,15 @@ typedef struct /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices */ #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) @@ -2803,7 +2823,7 @@ typedef struct /** @brief Macro to Get I2S clock source selection. * @retval The clock source can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source */ #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) @@ -3125,7 +3145,7 @@ typedef struct #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. * This parameter can be one of the following values: @@ -3141,8 +3161,8 @@ typedef struct * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock */ #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the DFSDM1 clock * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. @@ -3174,25 +3194,25 @@ typedef struct * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F769xx) || defined (STM32F779xx) /** @brief Macro to configure the DSI clock. * @param __DSI_CLKSOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. */ #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) /** @brief Macro to Get the DSI clock. * @retval The clock source can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) -#endif /* STM32F769xx || STM32F779xx */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ /** * @} */ @@ -3210,7 +3230,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros * @{ @@ -3218,7 +3238,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ @@ -3294,7 +3314,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined (STM32F765xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ @@ -3321,8 +3341,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ @@ -3343,16 +3363,16 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F746xx || STM32F756xx */ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ ((VALUE) == RCC_PLLI2SP_DIV4) ||\ ((VALUE) == RCC_PLLI2SP_DIV6) ||\ ((VALUE) == RCC_PLLI2SP_DIV8)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -3362,7 +3382,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); ((VALUE) == RCC_PLLSAIP_DIV6) ||\ ((VALUE) == RCC_PLLSAIP_DIV8)) #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) @@ -3456,18 +3476,18 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); ((VALUE) == RCC_TIMPRES_ACTIVATED)) #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ - defined (STM32F746xx) || defined (STM32F756xx) + defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */ - +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ + #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - + #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ @@ -3486,19 +3506,19 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /** * @} - */ + */ /** * @} @@ -3506,11 +3526,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h index 87a0cdc81d..5018ba96ef 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @brief Header file of USB Core HAL module. + * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention * @@ -31,7 +31,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F7xx_LL_USB_H @@ -44,192 +44,190 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" -/** @addtogroup STM32F7xx_HAL +/** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @addtogroup USB_Core +/** @addtogroup USB_LL * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ -/** - * @brief USB Mode definition - */ -typedef enum +/** + * @brief USB Mode definition + */ +typedef enum { - USB_OTG_DEVICE_MODE = 0U, - USB_OTG_HOST_MODE = 1U, - USB_OTG_DRD_MODE = 2U - + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 }USB_OTG_ModeTypeDef; -/** - * @brief URB States definition - */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief URB States definition + */ typedef enum { - URB_IDLE = 0U, + URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_NYET, URB_ERROR, URB_STALL - }USB_OTG_URBStateTypeDef; -/** - * @brief Host channel States definition - */ +/** + * @brief Host channel States definition + */ typedef enum { - HC_IDLE = 0U, + HC_IDLE = 0, HC_XFRC, HC_HALTED, HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR - }USB_OTG_HCStateTypeDef; -/** - * @brief PCD Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - + This parameter can be any value of @ref USB_Core_PHY_ */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ }USB_OTG_CfgTypeDef; typedef struct { uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - + This parameter can be any value of @ref USB_EP_Type_ */ + uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - + uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ }USB_OTG_EPTypeDef; typedef struct { uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t speed; /*!< USB Host speed. This parameter can be any value of @ref USB_Core_Speed_ */ - + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. This parameter can be any value of @ref USB_EP_Type_ */ - + uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - + uint8_t data_pid; /*!< Initial data PID. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - + uint32_t xfer_len; /*!< Current transfer length. */ - + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - + uint8_t toggle_in; /*!< IN transfer current toggle flag. This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - + uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ }USB_OTG_HCTypeDef; - +#endif /* defined USB_OTG_FS || USB_OTG_HS */ + + /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ @@ -240,56 +238,55 @@ typedef struct * @} */ -/** @defgroup USB_Core_Speed_ USB Core Speed +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ - */ + */ #define USB_OTG_SPEED_HIGH 0U #define USB_OTG_SPEED_HIGH_IN_FULL 1U -#define USB_OTG_SPEED_LOW 2U +#define USB_OTG_SPEED_LOW 2U #define USB_OTG_SPEED_FULL 3U /** * @} */ - -/** @defgroup USB_Core_PHY_ USB Core PHY + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY * @{ - */ + */ #define USB_OTG_ULPI_PHY 1U #define USB_OTG_EMBEDDED_PHY 2U #define USB_OTG_HS_EMBEDDED_PHY 3U -#if !defined (USB_HS_PHYC_TUNE_VALUE) +#if !defined (USB_HS_PHYC_TUNE_VALUE) #define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ #endif /* USB_HS_PHYC_TUNE_VALUE */ - /** * @} */ - -/** @defgroup USB_Core_MPS_ USB Core MPS + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval * @{ - */ + */ #define DCFG_FRAME_INTERVAL_80 0U #define DCFG_FRAME_INTERVAL_85 1U #define DCFG_FRAME_INTERVAL_90 2U @@ -298,7 +295,7 @@ typedef struct * @} */ -/** @defgroup USB_EP0_MPS_ USB EP0 MPS +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ #define DEP0CTL_MPS_64 0U @@ -309,7 +306,7 @@ typedef struct * @} */ -/** @defgroup USB_EP_Speed_ USB EP Speed +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ #define EP_SPEED_LOW 0U @@ -319,7 +316,7 @@ typedef struct * @} */ -/** @defgroup USB_EP_Type_ USB EP Type +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ */ #define EP_TYPE_CTRL 0U @@ -331,7 +328,7 @@ typedef struct * @} */ -/** @defgroup USB_STS_Defines_ USB STS Defines +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ #define STS_GOUT_NAK 1U @@ -343,31 +340,31 @@ typedef struct * @} */ -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines * @{ - */ + */ #define HCFG_30_60_MHZ 0U #define HCFG_48_MHZ 1U #define HCFG_6_MHZ 2U /** * @} */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ - */ + */ #define HPRT0_PRTSPD_HIGH_SPEED 0U #define HPRT0_PRTSPD_FULL_SPEED 1U #define HPRT0_PRTSPD_LOW_SPEED 2U /** * @} - */ - + */ + #define HCCHAR_CTRL 0U #define HCCHAR_ISOC 1U #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U - + #define HC_PID_DATA0 0U #define HC_PID_DATA2 1U #define HC_PID_DATA1 2U @@ -377,31 +374,44 @@ typedef struct #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) -#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) - - + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** * @} */ + /* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - + #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* USB_OTG_FS || USB_OTG_HS */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); @@ -409,7 +419,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode); HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); @@ -441,27 +451,37 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +#endif /* USB_OTG_FS || USB_OTG_HS */ + +/** + * @} + */ +/** + * @} + */ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html index b4da2b3e5b..126ceb013e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html @@ -1,4 +1,4 @@ - + @@ -680,7 +680,7 @@

          -

          Update History

          V1.2.5 / 02-February-2018

          +

          Update History

          V1.2.6 / 29-June-2018

          Main Changes

          • Update to support STM32F730xx and STM32F750xx value lines
          • HAL DMA update
            • DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of STM32F730xx (same features as STM32F733xx line)
          • HAL FLASH update
            • Add support of STM32F730xx with 4 FLash sectors of 16KB each.
            • Add support of STM32F750xx with 2 FLash sectors of 32KB each.
          • HAL GPIO update
            • Add support of STM32F730xx value line : same features as STM32F733xx line
            • Add support of STM32F750xx value line : same features as STM32F756xx line
          • HAL RCC update
            • Add support of STM32F730xx value line : same features as STM32F733xx line
            • Add support of STM32F750xx value line : same features as STM32F756xx line
          • HAL HASH update
            • Add support of STM32F750xx value line : same features as STM32F756xx line
          • HAL LTDC update
            • Add support of STM32F750xx value line : same features as STM32F756xx line

          V1.2.5 / 02-February-2018

          Main Changes

          • General updates to fix known defects and enhancements implementation
          • HAL update
            • Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose
            • Update UNUSED() macro implementation to avoid GCC warning
              • The warning is detected when the UNUSED() macro is called from C++ file
          • HAL SAI update
            • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue
          • HAL PWR update
            • Update HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index c4610063bf..3bbc96de16 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -66,11 +66,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.2.5 + * @brief STM32F7xx HAL Driver version number V1.2.6 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c index d007ec39a8..395e0168b5 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c @@ -100,7 +100,7 @@ * @{ */ -#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup HASH HASH * @brief HASH HAL module driver. @@ -1867,7 +1867,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c index a0a7b2b7be..6f52f344e0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c @@ -96,7 +96,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) +#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined (STM32F750xx) /** @defgroup HASHEx HASHEx * @brief HASH Extension HAL module driver. @@ -1625,7 +1625,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @} */ -#endif /* STM32F756xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c index 6829bb0cc6..8625ab9995 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c @@ -87,7 +87,7 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private function ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ /** @defgroup HCD_Private_Functions HCD Private Functions * @{ */ @@ -133,26 +133,32 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - hhcd->State = HAL_HCD_STATE_BUSY; + if(hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_HCD_MspInit(hhcd); + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); + } + + hhcd->State = HAL_HCD_STATE_BUSY; /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); + __HAL_HCD_DISABLE(hhcd); - /*Init the Core (common init.) */ - USB_CoreInit(hhcd->Instance, hhcd->Init); + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); - /* Force Host Mode*/ - USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE); + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); - /* Init Host */ - USB_HostInit(hhcd->Instance, hhcd->Init); + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); - hhcd->State= HAL_HCD_STATE_READY; + hhcd->State= HAL_HCD_STATE_READY; - return HAL_OK; + return HAL_OK; } /** @@ -162,7 +168,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 1 to 15 * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 * @param speed Current device speed. * This parameter can be one of these values: @@ -187,16 +193,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; __HAL_LOCK(hhcd); - hhcd->hc[ch_num].do_ping = 0; + hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + hhcd->hc[ch_num].speed = speed; status = USB_HC_Init(hhcd->Instance, @@ -223,7 +238,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_UNLOCK(hhcd); return status; @@ -247,7 +262,7 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) /* DeInit the low level hardware */ HAL_HCD_MspDeInit(hhcd); - __HAL_HCD_DISABLE(hhcd); + __HAL_HCD_DISABLE(hhcd); hhcd->State = HAL_HCD_STATE_RESET; @@ -264,7 +279,7 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_MspInit could be implemented in the user file */ } @@ -279,7 +294,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_MspDeInit could be implemented in the user file */ } @@ -327,18 +342,20 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping) + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t* pbuff, + uint16_t length, + uint8_t do_ping) { + UNUSED(do_ping); + hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; - if(token == 0) + if(token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -351,15 +368,15 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch(ep_type) { case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ + if((token == 1U) && (direction == 0U)) /*send data */ { - if ( length == 0 ) + if (length == 0U) { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; + hhcd->hc[ch_num].toggle_out = 1U; } /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if (hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -371,10 +388,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_BULK: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -385,7 +402,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -397,21 +414,21 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_INTR: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -425,16 +442,19 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, case EP_TYPE_ISOC: hhcd->hc[ch_num].data_pid = HC_PID_DATA0; break; + + default: + break; } hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; - return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); } /** @@ -445,12 +465,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t i = 0 , interrupt = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; - /* ensure that we are in device mode */ + /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { - /* avoid spurious interrupt */ + /* Avoid spurious interrupt */ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; @@ -458,25 +479,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); } @@ -490,7 +511,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Port Interrupts */ HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } @@ -511,25 +532,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0; i < hhcd->Init.Host_channels ; i++) + for (i = 0U; i < hhcd->Init.Host_channels; i++) { - if (interrupt & (1 << i)) + if ((interrupt & (1UL << (i & 0xFU))) != 0U) { - if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { - HCD_HC_IN_IRQHandler (hhcd, i); + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); } else { - HCD_HC_OUT_IRQHandler (hhcd, i); + HCD_HC_OUT_IRQHandler (hhcd, (uint8_t)i); } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } - /* Handle Rx Queue Level Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) + /* Handle Rx Queue Level Interrupts */ + if((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); @@ -550,7 +571,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_SOF_Callback could be implemented in the user file */ } @@ -565,7 +586,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Connect_Callback could be implemented in the user file */ } @@ -580,35 +601,37 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } /** * @brief Port Enabled Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } /** * @brief Port Disabled Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ } @@ -632,8 +655,10 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file */ } @@ -666,7 +691,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); + (void)USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); return HAL_OK; } @@ -680,7 +705,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); - USB_StopHost(hhcd->Instance); + (void)USB_StopHost(hhcd->Instance); __HAL_UNLOCK(hhcd); return HAL_OK; } @@ -816,150 +841,166 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + + uint32_t tmpreg; - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - hhcd->hc[chnum].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); } - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) + else { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + /* ... */ } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - - if (hhcd->Init.dma_enable) + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + else if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } - hhcd->hc[chnum].toggle_in ^= 1; + else + { + /* ... */ + } + hhcd->hc[ch_num].toggle_in ^= 1U; } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); + __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if(hhcd->hc[chnum].state == HC_XFRC) + if(hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; + hhcd->hc[ch_num].urb_state = URB_DONE; } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + else if((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + hhcd->hc[ch_num].ErrCnt++; + if(hhcd->hc[ch_num].ErrCnt > 3U) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { - if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - hhcd->hc[chnum].ErrCnt = 0; - if (!hhcd->Init.dma_enable) + hhcd->hc[ch_num].ErrCnt = 0U; + if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ } } @@ -970,147 +1011,147 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if( hhcd->hc[chnum].do_ping == 1) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if( hhcd->hc[ch_num].do_ping == 1U) { - hhcd->hc[chnum].do_ping = 0; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { - hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].do_ping = 1; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt= 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; - + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].state = HC_NAK; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; - if ( hhcd->hc[chnum].do_ping == 0) + if (hhcd->hc[ch_num].do_ping == 0U) { - if (hhcd->hc[chnum].speed == HCD_SPEED_HIGH) + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) { - hhcd->hc[chnum].do_ping = 1; + hhcd->hc[ch_num].do_ping = 1U; } } - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); + __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if(hhcd->hc[chnum].state == HC_XFRC) + if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; - if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) + hhcd->hc[ch_num].urb_state = URB_DONE; + if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) { - hhcd->hc[chnum].toggle_out ^= 1; + hhcd->hc[ch_num].toggle_out ^= 1U; } } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - - else if (hhcd->hc[chnum].state == HC_NYET) + else if (hhcd->hc[ch_num].state == HC_NYET) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else + { + /* ... */ } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + /* ... */ } } @@ -1119,47 +1160,48 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) * @param hhcd HCD handle * @retval none */ -static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; - uint32_t pktsts; - uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; - - temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; switch (pktsts) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - - USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; - hhcd->hc[channelnum].xfer_count += pktcnt; + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) + if((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(channelnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; } } break; case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: break; + case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_CH_HALTED: default: @@ -1172,9 +1214,10 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval None */ -static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0, hprt0_dup; /* Handle Host Port Interrupts */ @@ -1182,7 +1225,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) hprt0_dup = USBx_HPRT0; hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); /* Check whether Port Connect detected */ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) @@ -1193,7 +1236,6 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) HAL_HCD_Connect_Callback(hhcd); } hprt0_dup |= USB_OTG_HPRT_PCDET; - } /* Check whether Port Enable Changed */ @@ -1207,28 +1249,28 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); } else { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } else { if(hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = (uint32_t)60000; + USBx_HOST->HFIR = 60000U; } } HAL_HCD_PortEnabled_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd); - } else { HAL_HCD_PortDisabled_Callback(hhcd); + /* Cleanup HPRT */ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); @@ -1237,7 +1279,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) } } - /* Check For an overcurrent */ + /* Check for an overcurrent */ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { hprt0_dup |= USB_OTG_HPRT_POCCHNG; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c index e6236d3c62..90854a82ba 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c @@ -113,7 +113,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /** @defgroup LTDC LTDC * @brief LTDC HAL module driver @@ -1904,7 +1904,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** * @} */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c index 2a9884fbbc..007e2e325a 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c @@ -77,7 +77,7 @@ * @{ */ -/** @defgroup PCD PCD +/** @defgroup PCD * @brief PCD HAL module driver * @{ */ @@ -87,6 +87,14 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * USB_OTG_CORE VERSION ID + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +#define USB_OTG_CORE_ID_320A 0x4F54320AU +#endif /* USB_OTG_FS || USB_OTG_HS */ /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ @@ -101,7 +109,9 @@ /** @defgroup PCD_Private_Functions PCD Private Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* USB_OTG_FS || USB_OTG_HS */ /** * @} */ @@ -126,13 +136,13 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and create the associated handle. + * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t i = 0; + uint8_t i; /* Check the PCD handle allocation */ if(hpcd == NULL) @@ -143,68 +153,66 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - hpcd->State = HAL_PCD_STATE_BUSY; + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + + hpcd->State = HAL_PCD_STATE_BUSY; /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); - - /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE); - - /* Init endpoints structures */ - for (i = 0; i < 15 ; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; - hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->IN_ep[i].type = EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; - } - - for (i = 0; i < 15 ; i++) - { - hpcd->OUT_ep[i].is_in = 0; - hpcd->OUT_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; - - hpcd->Instance->DIEPTXF[i] = 0; - } - - /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) - { - HAL_PCDEx_ActivateLPM(hpcd); - } -#if defined (USB_OTG_GCCFG_BCDEN) - /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) - { - HAL_PCDEx_ActivateBCD(hpcd); - } -#endif /* USB_OTG_GCCFG_BCDEN */ - - USB_DevDisconnect (hpcd->Instance); - return HAL_OK; + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + (void)USB_CoreInit(hpcd->Instance, hpcd->Init); + + /* Force Device Mode*/ + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + + /* Init endpoints structures */ + for (i = 0U; i < 15U; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < 15U; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + (void)USB_DevInit(hpcd->Instance, hpcd->Init); + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + (void)USB_DevDisconnect (hpcd->Instance); + + return HAL_OK; } /** @@ -223,7 +231,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - HAL_PCD_Stop(hpcd); + (void)HAL_PCD_Stop(hpcd); /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); @@ -243,7 +251,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_MspInit could be implemented in the user file */ } @@ -258,7 +266,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_MspDeInit could be implemented in the user file */ } @@ -267,7 +275,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @} */ -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions +/** @defgroup PCD_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim @@ -283,21 +291,21 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ /** - * @brief Start The USB OTG Device. + * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); + (void)USB_DevConnect (hpcd->Instance); __HAL_PCD_ENABLE(hpcd); __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Stop The USB OTG Device. + * @brief Stop the USB device. * @param hpcd PCD handle * @retval HAL status */ @@ -305,24 +313,27 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); + (void)USB_StopDevice(hpcd->Instance); + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** - * @brief Handle PCD interrupt request. + * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0; - uint32_t fifoemptymsk = 0, temp = 0; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 200000000; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t TempReg = USBx_BASE + 0x40U; + uint32_t gSNPSiD = *(uint32_t *) TempReg; + uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + uint32_t hclk; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -335,61 +346,90 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { - epnum = 0; + epnum = 0U; /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - while ( ep_intr ) + while (ep_intr != 0U) { - if (ep_intr & 0x1) + if ((ep_intr & 0x1U) != 0U) { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); - if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - /* setup/out transaction management for Core ID >= 310A */ - if (hpcd->Init.dma_enable == 1) + if (gSNPSiD > USB_OTG_CORE_ID_300A) { - if (USBx_OUTEP(0)->DOEPINT & (1 << 15)) + /* setup/out transaction management for Core ID >= 310A */ + if (hpcd->Init.dma_enable == 1U) { - CLEAR_OUT_EP_INTR(epnum, (1 << 15)); + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } } } - if(hpcd->Init.dma_enable == 1) + if(hpcd->Init.dma_enable == 1U) { hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; } - HAL_PCD_DataOutStageCallback(hpcd, epnum); - if(hpcd->Init.dma_enable == 1) + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, epnum); + } + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + + if(hpcd->Init.dma_enable == 1U) { - if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0)) + if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) { /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } } - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { - /* setup/out transaction management for Core ID >= 310A */ - if (hpcd->Init.dma_enable == 1) + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } + } + + if (gSNPSiD > USB_OTG_CORE_ID_300A) { - if (USBx_OUTEP(0)->DOEPINT & (1 << 15)) + /* setup/out transaction management for Core ID >= 310A */ + if (hpcd->Init.dma_enable == 1U) { - CLEAR_OUT_EP_INTR(epnum, (1 << 15)); + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 15)); + } } } @@ -402,14 +442,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + +#ifdef USB_OTG_DOEPINT_OTEPSPR /* Clear Status Phase Received interrupt */ if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } +#endif /* USB_OTG_DOEPINT_OTEPSPR */ } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -418,61 +461,61 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - epnum = 0; + epnum = 0U; - while ( ep_intr ) + while (ep_intr != 0U) { - if (ep_intr & 0x1) /* In ITR */ + if ((ep_intr & 0x1U) != 0U) /* In ITR */ { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << (epnum & 0xFU)); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; } - HAL_PCD_DataInStageCallback(hpcd, epnum); + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) { /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { - PCD_WriteEmptyTxFifo(hpcd , epnum); + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -491,6 +534,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { HAL_PCD_ResumeCallback(hpcd); } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } @@ -512,7 +556,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if( hpcd->LPM_State == LPM_L0) { hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); } else @@ -525,26 +569,29 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance, 0x10); + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { - USBx_INEP(i)->DIEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; + USBx_DEVICE->DAINTMSK |= 0x10001U; - if(hpcd->Init.use_dedicated_ep1) + if (hpcd->Init.use_dedicated_ep1 != 0U) { USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } else { +#ifdef USB_OTG_DOEPINT_OTEPSPR USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); +#else + USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); +#endif /* USB_OTG_DOEPINT_OTEPSPR */ USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); } @@ -552,7 +599,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } @@ -560,19 +607,19 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Enumeration done Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { - USB_ActivateSetup(hpcd->Instance); + (void)USB_ActivateSetup(hpcd->Instance); hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) { hpcd->Init.speed = USB_OTG_SPEED_HIGH; - hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE; + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT); } else { hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; + hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE; /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response @@ -582,64 +629,64 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - if((hclk >= 14200000)&&(hclk < 15000000)) + if((hclk >= 14200000U) && (hclk < 15000000U)) { /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 15000000)&&(hclk < 16000000)) + else if((hclk >= 15000000U) && (hclk < 16000000U)) { /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 16000000)&&(hclk < 17200000)) + else if((hclk >= 16000000U) && (hclk < 17200000U)) { /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 17200000)&&(hclk < 18500000)) + else if((hclk >= 17200000U) && (hclk < 18500000U)) { /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 18500000)&&(hclk < 20000000)) + else if((hclk >= 18500000U) && (hclk < 20000000U)) { /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 20000000)&&(hclk < 21800000)) + else if((hclk >= 20000000U) && (hclk < 21800000U)) { /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 21800000)&&(hclk < 24000000)) + else if((hclk >= 21800000U) && (hclk < 24000000U)) { /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 24000000)&&(hclk < 27700000)) + else if((hclk >= 24000000U) && (hclk < 27700000U)) { /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT); } - else if((hclk >= 27700000)&&(hclk < 32000000)) + else if((hclk >= 27700000U) && (hclk < 32000000U)) { /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT); } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT); } } @@ -652,23 +699,29 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + temp = USBx->GRXSTSP; + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) + if((temp & USB_OTG_GRXSTSP_BCNT) != 0U) { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); + (void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; } + else + { + /* ... */ + } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -682,14 +735,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO IN Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } /* Handle Incomplete ISO OUT Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -713,6 +766,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } } +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** * @brief Data OUT stage callback. @@ -720,42 +775,44 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataOutStageCallback could be implemented in the user file */ } /** - * @brief Data IN stage callback. + * @brief Data IN stage callback * @param hpcd PCD handle * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataInStageCallback could be implemented in the user file */ } /** - * @brief Setup stage callback. + * @brief Setup stage callback * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SetupStageCallback could be implemented in the user file */ } @@ -765,12 +822,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SOFCallback could be implemented in the user file */ } @@ -780,12 +837,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResetCallback could be implemented in the user file */ } @@ -795,12 +852,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SuspendCallback could be implemented in the user file */ } @@ -810,12 +867,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResumeCallback could be implemented in the user file */ } @@ -826,28 +883,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file */ } /** - * @brief Incomplete ISO IN callback. + * @brief Incomplete ISO IN callback. * @param hpcd PCD handle * @param epnum endpoint number * @retval None */ - __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(epnum); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file */ } @@ -857,12 +916,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ConnectCallback could be implemented in the user file */ } @@ -872,12 +931,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval None */ - __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DisconnectCallback could be implemented in the user file */ } @@ -902,14 +961,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) */ /** - * @brief Connect the USB device. + * @brief Connect the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -922,7 +981,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -936,7 +995,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { __HAL_LOCK(hpcd); - USB_SetDevAddress(hpcd->Instance, address); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -951,39 +1011,41 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; + ep->num = ep_addr & 0xFU; ep->maxpacket = ep_mps; ep->type = ep_type; - if (ep->is_in) + + if (ep->is_in != 0U) { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } /* Set initial data PID. */ - if (ep_type == EP_TYPE_BULK ) + if (ep_type == EP_TYPE_BULK) { - ep->data_pid_start = 0; + ep->data_pid_start = 0U; } __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); __HAL_UNLOCK(hpcd); + return ret; } - /** * @brief Deactivate an endpoint. * @param hpcd PCD handle @@ -992,22 +1054,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); + (void)USB_DeactivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1023,46 +1085,46 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0xFU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0xFU; - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & 0x7F) == 0) + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } return HAL_OK; } /** - * @brief Get Received Data Size. + * @brief Get Received Data Size * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0xF].xfer_count; + return (uint16_t)hpcd->OUT_ep[ep_addr & 0xFU].xfer_count; } /** - * @brief Send an amount of data. + * @brief Send an amount of data * @param hpcd PCD handle * @param ep_addr endpoint address * @param pBuf pointer to the transmission buffer @@ -1071,68 +1133,69 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0xFU; - if (hpcd->Init.dma_enable == 1) + if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & 0x7F) == 0) + if ((ep_addr & 0xFU) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); } return HAL_OK; } /** - * @brief Set a STALL condition over an endpoint. + * @brief Set a STALL condition over an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + if (((uint32_t)ep_addr & 0xFU) > hpcd->Init.dev_endpoints) { return HAL_ERROR; } - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; } - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - + ep->is_stall = 1U; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) + + (void)USB_EPSetStall(hpcd->Instance, ep); + if((ep_addr & 0xFU) == 0U) { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } __HAL_UNLOCK(hpcd); @@ -1140,42 +1203,43 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Clear a STALL condition over in an endpoint. + * @brief Clear a STALL condition over in an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - USB_OTG_EPTypeDef *ep; + PCD_EPTypeDef *ep; - if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) { return HAL_ERROR; } - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0xFU]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr &0xFU]; + ep->is_in = 0U; } - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 0U; + ep->num = ep_addr & 0xFU; __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); + (void)USB_EPClearStall(hpcd->Instance, ep); __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Flush an endpoint. + * @brief Flush an endpoint * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status @@ -1184,13 +1248,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { __HAL_LOCK(hpcd); - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & 0xFU); } else { - USB_FlushRxFifo(hpcd->Instance); + (void)USB_FlushRxFifo(hpcd->Instance); } __HAL_UNLOCK(hpcd); @@ -1199,20 +1263,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief Activate remote wakeup signalling. + * @brief Activate remote wakeup signalling * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* Activate Remote wakeup signaling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - return HAL_OK; + return(USB_ActivateRemoteWakeup(hpcd->Instance)); } /** @@ -1222,12 +1279,9 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - /* De-activate Remote wakeup signaling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - return HAL_OK; + return(USB_DeActivateRemoteWakeup(hpcd->Instance)); } + /** * @} */ @@ -1256,6 +1310,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) { return hpcd->State; } + /** * @} */ @@ -1268,20 +1323,21 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** @addtogroup PCD_Private_Functions * @{ */ - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Check FIFO for the next packet to be loaded. * @param hpcd PCD handle - * @param epnum endpoint number + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; USB_OTG_EPTypeDef *ep; - int32_t len = 0; + uint32_t len; uint32_t len32b; - uint32_t fifoemptymsk = 0; + uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; len = ep->xfer_len - ep->xfer_count; @@ -1291,12 +1347,10 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t len = ep->maxpacket; } + len32b = (len + 3U) / 4U; - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; @@ -1305,29 +1359,31 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t { len = ep->maxpacket; } - len32b = (len + 3) / 4; + len32b = (len + 3U) / 4U; - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable); ep->xfer_buff += len; ep->xfer_count += len; } - if(len <= 0) + if(len <= 0U) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = (uint32_t)(0x1UL << epnum); USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - } return HAL_OK; } +#endif /* USB_OTG_FS || USB_OTG_HS */ + /** * @} */ #endif /* HAL_PCD_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c index 2c241741ce..c1c3e82c5f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Extended features functions * @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -48,6 +48,7 @@ * @brief PCD Extended HAL module driver * @{ */ + #ifdef HAL_PCD_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ @@ -62,19 +63,19 @@ */ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Update FIFO configuration @endverbatim * @{ */ - +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set Tx FIFO * @param hpcd PCD handle @@ -84,37 +85,37 @@ */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { - uint8_t i = 0; - uint32_t Tx_Offset = 0; + uint8_t i; + uint32_t Tx_Offset; /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) + + if(fifo == 0U) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0; i < (fifo - 1); i++) + for (i = 0U; i < (fifo - 1U); i++) { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; } - + return HAL_OK; } @@ -127,177 +128,77 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { hpcd->Instance->GRXFSIZ = size; - + return HAL_OK; } /** - * @brief Activate LPM Feature + * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; + + return HAL_OK; } /** - * @brief DeActivate LPM feature. + * @brief Deactivate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -#if defined (USB_OTG_GCCFG_BCDEN) -/** - * @brief Handle BatteryCharging Process. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - /* Right response got */ - HAL_Delay(100); - - /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - - /*Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) - { - /* Case of Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { - /* case Dedicated Charging Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* case Charging Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - } - } - /* Battery Charging capability discovery finished */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } -} -/** - * @brief Activate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->battery_charging_active = ENABLE; - USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; + return HAL_OK; } +#endif /* USB_OTG_FS || USB_OTG_HS */ /** - * @brief Send BatteryCharging message to user layer callback. + * @brief Send LPM message to user layer callback. * @param hpcd PCD handle * @param msg LPM message * @retval HAL status */ -__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(msg); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ } -#endif /* USB_OTG_GCCFG_BCDEN */ /** - * @brief Send LPM message to user layer callback. + * @brief Send BatteryCharging message to user layer callback. * @param hpcd PCD handle * @param msg LPM message * @retval HAL status */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(msg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ } /** @@ -309,6 +210,7 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m */ #endif /* HAL_PCD_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c index cfdc545795..82bca93f9b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -3,10 +3,10 @@ * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -35,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -84,37 +84,38 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register will be set to their reset values. - + @endverbatim * @{ */ #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ + defined (STM32F750xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @retval HAL status @@ -126,88 +127,88 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t tmpreg1 = 0; uint32_t plli2sused = 0; uint32_t pllsaiused = 0; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - + /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } } - + /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - plli2sused = 1; - } - + { + plli2sused = 1; + } + /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) { @@ -237,8 +238,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -256,47 +257,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - + /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } - + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - + /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } - + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - + /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } - + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - + /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } - + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - + /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); } @@ -306,7 +307,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - + /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } @@ -316,7 +317,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - + /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } @@ -326,7 +327,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - + /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } @@ -336,7 +337,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - + /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } @@ -346,7 +347,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - + /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } @@ -356,7 +357,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - + /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); } @@ -366,7 +367,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - + /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); } @@ -376,76 +377,76 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - + /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); } - + /*--------------------------------------- CEC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - + /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } - + /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) { - pllsaiused = 1; + pllsaiused = 1; } } /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { - pllsaiused = 1; + pllsaiused = 1; } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } - + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - + /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - + /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); } - + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) { @@ -455,7 +456,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } - + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) { @@ -464,38 +465,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the DFSDM interface clock source */ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } + } #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - + __HAL_RCC_PLLI2S_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); @@ -504,35 +505,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); @@ -540,9 +541,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -554,11 +555,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -567,19 +568,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - } - + } + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - + __HAL_RCC_PLLSAI_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -587,16 +588,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } - + } + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -604,7 +605,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); @@ -612,13 +613,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } + } - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) { /* check for Parameters */ @@ -626,37 +627,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - + /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - } + } -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -664,8 +665,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } @@ -682,9 +683,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg = 0; - + /* Set all possible values for the extended clock type parameter------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ @@ -697,7 +698,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; -#else +#else PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ @@ -709,20 +710,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48; -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); @@ -730,76 +731,76 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the SAI1 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S clock configuration ------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - + /* Get the I2C1 clock configuration ------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - + /* Get the I2C2 clock configuration ------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - + /* Get the I2C3 clock configuration ------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - + /* Get the I2C4 clock configuration ------------------------------------------*/ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); - + /* Get the USART1 clock configuration ------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - + /* Get the USART2 clock configuration ------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - + /* Get the USART3 clock configuration ------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - + /* Get the UART4 clock configuration ------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - + /* Get the UART5 clock configuration ------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - + /* Get the USART6 clock configuration ------------------------------------------*/ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - + /* Get the UART7 clock configuration ------------------------------------------*/ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - + /* Get the UART8 clock configuration ------------------------------------------*/ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - + /* Get the LPTIM1 clock configuration ------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the CEC clock configuration -----------------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - + /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /* Get the SDMMC2 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - + /* Get the DFSDM clock configuration -----------------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the TIM Prescaler configuration --------------------------------------------*/ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) { @@ -810,19 +811,19 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } } -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @retval HAL status @@ -833,82 +834,82 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t tmpreg0 = 0; uint32_t plli2sused = 0; uint32_t pllsaiused = 0; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - + /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } } - + /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1; + plli2sused = 1; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) { @@ -938,8 +939,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -957,37 +958,37 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - + /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } - + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - + /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } - + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - + /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } - + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - + /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } @@ -997,7 +998,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - + /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } @@ -1007,7 +1008,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - + /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } @@ -1017,7 +1018,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - + /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } @@ -1027,7 +1028,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - + /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } @@ -1037,7 +1038,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - + /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } @@ -1047,7 +1048,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - + /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); } @@ -1057,7 +1058,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - + /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); } @@ -1067,86 +1068,86 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - + /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); } - + /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) { - pllsaiused = 1; + pllsaiused = 1; } } - + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } - + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - + /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); } - + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - + /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); } - + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - + __HAL_RCC_PLLI2S_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Configure the PLLI2S division factors */ @@ -1154,29 +1155,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -1186,11 +1187,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1199,19 +1200,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { - /* return in case of Timeout detected */ + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - } - + } + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - + __HAL_RCC_PLLSAI_DISABLE(); + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1219,16 +1220,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } - + } + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -1236,27 +1237,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } + } - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - + /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ @@ -1265,7 +1266,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); @@ -1273,8 +1274,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ + { + /* return in case of Timeout detected */ return HAL_TIMEOUT; } } @@ -1291,7 +1292,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg = 0; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ @@ -1303,79 +1304,79 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; - + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); /* Get the SAI1 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S clock configuration ------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - + /* Get the I2C1 clock configuration ------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - + /* Get the I2C2 clock configuration ------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - + /* Get the I2C3 clock configuration ------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - + /* Get the USART1 clock configuration ------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - + /* Get the USART2 clock configuration ------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - + /* Get the USART3 clock configuration ------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - + /* Get the UART4 clock configuration ------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - + /* Get the UART5 clock configuration ------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - + /* Get the USART6 clock configuration ------------------------------------------*/ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - + /* Get the UART7 clock configuration ------------------------------------------*/ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - + /* Get the UART8 clock configuration ------------------------------------------*/ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - + /* Get the LPTIM1 clock configuration ------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the CK48 clock configuration -----------------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); /* Get the SDMMC1 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the TIM Prescaler configuration --------------------------------------------*/ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) { @@ -1386,10 +1387,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } } -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: @@ -1406,17 +1407,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) uint32_t vcoinput = 0; /* This variable is used to store the SAI clock source */ uint32_t saiclocksource = 0; - + if (PeriphClk == RCC_PERIPHCLK_SAI1) { - saiclocksource = RCC->DCKCFGR1; + saiclocksource = RCC->DCKCFGR1; saiclocksource &= RCC_DCKCFGR1_SAI1SEL; switch (saiclocksource) { - case 0: /* PLLSAI is the clock source for SAI1 */ + case 0: /* PLLSAI is the clock source for SAI1 */ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1426,21 +1427,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; + frequency = frequency/(tmpreg); + break; } case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1451,23 +1452,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); frequency = frequency/(tmpreg); break; } case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ { if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) @@ -1480,26 +1481,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the main PLL Source is HSE */ frequency = HSE_VALUE; } - break; + break; } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; } } } - + if (PeriphClk == RCC_PERIPHCLK_SAI2) { - saiclocksource = RCC->DCKCFGR1; + saiclocksource = RCC->DCKCFGR1; saiclocksource &= RCC_DCKCFGR1_SAI2SEL; switch (saiclocksource) { - case 0: /* PLLSAI is the clock source for SAI*/ + case 0: /* PLLSAI is the clock source for SAI*/ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1509,21 +1510,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; + frequency = frequency/(tmpreg); + break; } case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -1534,21 +1535,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); frequency = frequency/(tmpreg); break; } case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ @@ -1563,16 +1564,16 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the main PLL Source is HSE */ frequency = HSE_VALUE; } - break; + break; } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ default : { break; } } } - + return frequency; } @@ -1583,12 +1584,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * -@verbatim +@verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the + This subsection provides a set of functions allowing to control the activation or deactivation of PLLI2S, PLLSAI. @endverbatim * @{ @@ -1627,7 +1628,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) } /* Configure the PLLI2S division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ @@ -1638,7 +1639,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); @@ -1715,7 +1716,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) } /* Configure the PLLSAI division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ @@ -1727,7 +1728,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ /* Enable the PLLSAI */ __HAL_RCC_PLLSAI_ENABLE(); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c index 02af81a3fd..626d47ca7e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c @@ -68,6 +68,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); #ifdef USB_HS_PHYC @@ -75,18 +76,17 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); #endif /* Exported functions --------------------------------------------------------*/ -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== - ##### Initialization/de-initialization functions ##### + ##### Initialization/de-initialization functions ##### =============================================================================== - [..] This section provides functions allowing to: @endverbatim * @{ @@ -95,7 +95,7 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); /** * @brief Initializes the USB Core * @param USBx USB Instance - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -103,7 +103,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { if (cfg.phy_itface == USB_OTG_ULPI_PHY) { - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); /* Init The ULPI Interface */ @@ -111,15 +110,14 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - if(cfg.use_external_vbus == 1) + if(cfg.use_external_vbus == 1U) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; } /* Reset after a PHY select */ - USB_CoreReset(USBx); + (void)USB_CoreReset(USBx); } #ifdef USB_HS_PHYC - else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -152,13 +150,13 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); + (void)USB_CoreReset(USBx); /* Deactivate the power down*/ USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; } - if(cfg.dma_enable == ENABLE) + if(cfg.dma_enable == 1U) { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; @@ -179,7 +177,6 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) return HAL_OK; } - /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg @@ -197,24 +194,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @param mode current core mode * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode) { USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - if ( mode == USB_OTG_HOST_MODE) + if (mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } - else if ( mode == USB_OTG_DEVICE_MODE) + else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } - HAL_Delay(50); + else + { + return HAL_ERROR; + } + HAL_Delay(50U); return HAL_OK; } @@ -229,15 +230,21 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT */ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - uint32_t i = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } /*Activate VBUS Sensing B */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - if (cfg.vbus_sensing_enable == 0) + if (cfg.vbus_sensing_enable == 0U) { /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; /* B-peripheral session valid override enable*/ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; @@ -245,120 +252,133 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - if(cfg.phy_itface == USB_OTG_ULPI_PHY) + if(cfg.phy_itface == USB_OTG_ULPI_PHY) { if(cfg.speed == USB_OTG_SPEED_HIGH) { /* Set High speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH); } else { /* set High speed phy in Full speed mode */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } - - else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { if(cfg.speed == USB_OTG_SPEED_HIGH) { /* Set High speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH); } else { /* set High speed phy in Full speed mode */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } - else { /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_FULL); } /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; - for (i = 0; i < cfg.dev_endpoints; i++) + for (i = 0U; i < cfg.dev_endpoints; i++) { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) { - USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } } else { - USBx_INEP(i)->DIEPCTL = 0; + USBx_INEP(i)->DIEPCTL = 0U; } - USBx_INEP(i)->DIEPTSIZ = 0; - USBx_INEP(i)->DIEPINT = 0xFF; + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; } - for (i = 0; i < cfg.dev_endpoints; i++) + for (i = 0U; i < cfg.dev_endpoints; i++) { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) { - USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } } else { - USBx_OUTEP(i)->DOEPCTL = 0; + USBx_OUTEP(i)->DOEPCTL = 0U; } - USBx_OUTEP(i)->DOEPTSIZ = 0; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - if (cfg.dma_enable == 1) + if (cfg.dma_enable == 1U) { /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); + USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 | + USB_OTG_DTHRCTL_RXTHRLEN_6; - i= USBx_DEVICE->DTHRCTL; + USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN | + USB_OTG_DTHRCTL_ISOTHREN | + USB_OTG_DTHRCTL_NONISOTHREN; } /* Disable all interrupts. */ - USBx->GINTMSK = 0; + USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; + USBx->GINTSTS = 0xBFFFFFFFU; /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) + if (cfg.dma_enable == 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; } /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM| + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - if(cfg.Sof_enable) + if(cfg.Sof_enable != 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - if (cfg.vbus_sensing_enable == ENABLE) + if (cfg.vbus_sensing_enable == 1U) { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } @@ -366,7 +386,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c return HAL_OK; } - /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO * @param USBx Selected device @@ -375,15 +394,15 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) +HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0; + uint32_t count = 0U; - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -393,7 +412,6 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) return HAL_OK; } - /** * @brief USB_FlushRxFifo : Flush Rx FIFO * @param USBx Selected device @@ -407,7 +425,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -431,6 +449,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG |= speed; return HAL_OK; } @@ -446,21 +466,27 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { - uint8_t speed = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + if(DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { speed = USB_OTG_SPEED_HIGH; } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USB_OTG_SPEED_FULL; } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ) { speed = USB_OTG_SPEED_LOW; } + else + { + speed = 0U; + } return speed; } @@ -473,29 +499,36 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; } - } else { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; } + /** * @brief Activate and configure a dedicated endpoint * @param USBx Selected device @@ -504,41 +537,37 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - static __IO uint32_t debug = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; } - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)); } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; } - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16); } return HAL_OK; } + /** * @brief De-activate and de-initialize an endpoint * @param USBx Selected device @@ -547,19 +576,30 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); } else { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); } + return HAL_OK; } @@ -571,17 +611,21 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU))); } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16)); } + return HAL_OK; } @@ -597,17 +641,19 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) { - uint16_t pktcnt = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -616,52 +662,52 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); } } - if (dma == 1) + if (dma == 1U) { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } else { if (ep->type != EP_TYPE_ISOC) { /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } } } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } else { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } } /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); if (ep->type == EP_TYPE_ISOC) { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); } } else /* OUT endpoint */ @@ -670,40 +716,41 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); } - if (dma == 1) + if (dma == 1U) { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff; + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)ep->xfer_buff; } if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; } else { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; } } /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } @@ -719,15 +766,18 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -736,33 +786,32 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); if(ep->xfer_len > ep->maxpacket) { ep->xfer_len = ep->maxpacket; } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); } - if (dma == 1) + if (dma == 1U) { - USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr); + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } else { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) { - USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num); + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU); } } /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -770,26 +819,26 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len > 0) + if (ep->xfer_len > 0U) { ep->xfer_len = ep->maxpacket; } - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - if (dma == 1) + if (dma == 1U) { - USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff); + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); } /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } @@ -808,16 +857,20 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD */ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { - uint32_t count32b= 0 , i= 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; - if (dma == 0) + if (dma == 0U) { - count32b = (len + 3) / 4; - for (i = 0; i < count32b; i++, src += 4) + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc); + pSrc++; } } + return HAL_OK; } @@ -825,8 +878,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx Selected device - * @param src source pointer - * @param ch_ep_num endpoint or host channel number + * @param dest source pointer * @param len Number of bytes to read * @param dma USB dma enabled or disabled * This parameter can be one of these values: @@ -836,15 +888,18 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; - for ( i = 0; i < count32b; i++, dest += 4 ) + for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - + *(__packed uint32_t *)pDest = USBx_DFIFO(0U); + pDest++; } - return ((void *)dest); + + return ((void *)pDest); } /** @@ -855,26 +910,29 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } + return HAL_OK; } - /** * @brief USB_EPClearStall : Clear a stall condition over an EP * @param USBx Selected device @@ -883,20 +941,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ } } return HAL_OK; @@ -909,24 +970,24 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; /* Clear Pending interrupt */ - for (i = 0; i < 15 ; i++) + for (i = 0U; i < 15U; i++) { - USBx_INEP(i)->DIEPINT = 0xFF; - USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); + (void)USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx , 0x10U); return HAL_OK; } @@ -940,8 +1001,10 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; return HAL_OK; } @@ -953,8 +1016,10 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + HAL_Delay(3U); return HAL_OK; } @@ -966,8 +1031,10 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + HAL_Delay(3U); return HAL_OK; } @@ -979,11 +1046,12 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v = 0; + uint32_t tmpreg; - v = USBx->GINTSTS; - v &= USBx->GINTMSK; - return v; + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; } /** @@ -993,10 +1061,13 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xffff0000) >> 16); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); } /** @@ -1006,10 +1077,13 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { - uint32_t v; - v = USBx_DEVICE->DAINT; - v &= USBx_DEVICE->DAINTMSK; - return ((v & 0xFFFF)); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); } /** @@ -1021,10 +1095,13 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { - uint32_t v; - v = USBx_OUTEP(epnum)->DOEPINT; - v &= USBx_DEVICE->DOEPMSK; - return v; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; } /** @@ -1036,13 +1113,15 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) */ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { - uint32_t v, msk, emp; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - v = USBx_INEP(epnum)->DIEPINT & msk; - return v; + msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; } /** @@ -1066,10 +1145,9 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx->GINTSTS ) & 0x1); + return ((USBx->GINTSTS ) & 0x1U); } - /** * @brief Activate EP0 for Setup transactions * @param USBx Selected device @@ -1077,19 +1155,20 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { - USBx_INEP(0)->DIEPCTL |= 3; + USBx_INEP(0U)->DIEPCTL |= 3U; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; } - /** * @brief Prepare the EP0 to start the first control setup * @param USBx Selected device @@ -1102,22 +1181,23 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) { - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + uint32_t USBx_BASE = (uint32_t)USBx; - if (dma == 1) + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) { - USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup; + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; /* EP enable */ - USBx_OUTEP(0)->DOEPCTL = 0x80008000; + USBx_OUTEP(0U)->DOEPCTL = 0x80008000U; } return HAL_OK; } - /** * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device @@ -1125,25 +1205,25 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Core Soft Reset */ - count = 0; + count = 0U; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } @@ -1162,7 +1242,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + uint32_t count = 0U; /* Enable LDO */ USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; @@ -1170,37 +1250,36 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) /* wait for LDO Ready */ while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET) { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } /* Controls PHY frequency operation selection */ - if (HSE_VALUE == 12000000) /* HSE = 12MHz */ + if (HSE_VALUE == 12000000U) /* HSE = 12MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x0 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); } - else if (HSE_VALUE == 12500000) /* HSE = 12.5MHz */ + else if (HSE_VALUE == 12500000U) /* HSE = 12.5MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x2 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); } - else if (HSE_VALUE == 16000000) /* HSE = 16MHz */ + else if (HSE_VALUE == 16000000U) /* HSE = 16MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x3 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); } - - else if (HSE_VALUE == 24000000) /* HSE = 24MHz */ + else if (HSE_VALUE == 24000000U) /* HSE = 24MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x4 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); } - else if (HSE_VALUE == 25000000) /* HSE = 25MHz */ + else if (HSE_VALUE == 25000000U) /* HSE = 25MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x5 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); } - else if (HSE_VALUE == 32000000) /* HSE = 32MHz */ + else if (HSE_VALUE == 32000000U) /* HSE = 32MHz */ { - USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x7 << 1); + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); } /* Control the tuning interface of the High Speed PHY */ @@ -1226,17 +1305,17 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) + if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS)) { USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; } @@ -1246,51 +1325,51 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef } /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); /* Clear all pending HC Interrupts */ - for (i = 0; i < cfg.Host_channels; i++) + for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFF; - USBx_HC(i)->HCINTMSK = 0; + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; } /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); + (void)USB_DriveVbus(USBx, 1U); - HAL_Delay(200); + HAL_Delay(200U); /* Disable all interrupts. */ - USBx->GINTMSK = 0; + USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; + USBx->GINTSTS = 0xFFFFFFFFU; if(USBx == USB_OTG_FS) { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); } else { /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x200; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200); - USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300); + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) + if (cfg.dma_enable == 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; } /* Enable interrupts matching to the Host mode ONLY */ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT|\ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); return HAL_OK; @@ -1308,17 +1387,24 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef */ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; - if (freq == HCFG_48_MHZ) + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = (uint32_t)48000; + USBx_HOST->HFIR = 6000U; } - else if (freq == HCFG_6_MHZ) + else { - USBx_HOST->HFIR = (uint32_t)6000; + /* ... */ } + return HAL_OK; } @@ -1326,12 +1412,14 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq * @brief USB_OTG_ResetPort : Reset Host Port * @param USBx Selected device * @retval HAL status - * @note : (1)The application must wait at least 10 ms + * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; @@ -1339,9 +1427,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (100); /* See Note #1 */ + HAL_Delay (100U); /* See Note #1 */ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - HAL_Delay (10); + HAL_Delay (10U); return HAL_OK; } @@ -1356,18 +1444,19 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); } @@ -1385,7 +1474,8 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) */ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); @@ -1398,6 +1488,8 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } @@ -1433,86 +1525,107 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_type, uint16_t mps) { + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; /* Enable channel interrupts required for this transfer. */ switch (ep_type) { case EP_TYPE_CTRL: case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } else { if(USBx != USB_OTG_FS) { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); } } break; case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; } break; - case EP_TYPE_ISOC: - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; - if (epnum & 0x80) + if ((epnum & 0x80U) == 0x80U) { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); } break; + + default: + ret = HAL_ERROR; + break; } /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); /* Make sure host channel interrupts are enabled. */ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); + if((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if(speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; if (ep_type == EP_TYPE_INTR) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; } - return HAL_OK; + return ret; } /** @@ -1527,67 +1640,73 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, */ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) { - static __IO uint32_t tmpreg = 0; - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH)) { - if((dma == 0) && (hc->do_ping == 1)) + if((dma == 0U) && (hc->do_ping == 1U)) { - USB_DoPing(USBx, hc->ch_num); + (void)USB_DoPing(USBx, hc->ch_num); return HAL_OK; } - else if(dma == 1) + else if(dma == 1U) { - USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - hc->do_ping = 0; + USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + hc->do_ping = 0U; + } + else + { + /* ... */ } } /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) + if (hc->xfer_len > 0U) { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } } else { - num_packets = 1; + num_packets = 1U; } - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); - if (dma) + if (dma != 0U) { /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; } - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; /* make sure to set the correct ep direction */ - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { tmpreg |= USB_OTG_HCCHAR_EPDIR; } @@ -1596,11 +1715,11 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe tmpreg &= ~USB_OTG_HCCHAR_EPDIR; } tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; - if (dma == 0) /* Slave mode */ + if (dma == 0U) /* Slave mode */ { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) + if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) { switch(hc->ep_type) { @@ -1608,21 +1727,22 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe case EP_TYPE_CTRL: case EP_TYPE_BULK: - len_words = (hc->xfer_len + 3) / 4; + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) + if(len_words > (USBx->HNPTXSTS & 0xFFFFU)) { /* need to process data in nptxfempty interrupt */ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; } break; + /* Periodic transfer */ case EP_TYPE_INTR: case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ + if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ { /* need to process data in ptxfempty interrupt */ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; @@ -1634,7 +1754,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe } /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); } } @@ -1648,7 +1768,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) { - return ((USBx_HOST->HAINT) & 0xFFFF); + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); } /** @@ -1660,54 +1782,56 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { - uint32_t count = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; /* Check for space in the request queue to issue the halt. */ - if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || - (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK))) + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx->HNPTXSTS & 0xFFFF) == 0) + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } @@ -1723,17 +1847,19 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) */ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) { - uint8_t num_packets = 1; - uint32_t tmpreg = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; return HAL_OK; } @@ -1745,21 +1871,22 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { - uint8_t i; - uint32_t count = 0; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; uint32_t value; + uint32_t i; + - USB_DisableGlobalInt(USBx); + (void)USB_DisableGlobalInt(USBx); /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); /* Flush out any leftover queued requests. */ - for (i = 0; i <= 15; i++) + for (i = 0U; i <= 15U; i++) { - - value = USBx_HC(i)->HCCHAR ; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; value &= ~USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; @@ -1767,18 +1894,17 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Halt all channels to put them into a known state. */ - for (i = 0; i <= 15; i++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(i)->HCCHAR ; - + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; + do { - if (++count > 1000) + if (++count > 1000U) { break; } @@ -1787,11 +1913,51 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); + return HAL_OK; } + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined USB_OTG_FS || defined USB_OTG_HS */ + + +/** + * @} + */ /** * @} */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 109c8de7b5..adc62a657b 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F2: 1.2.2 * STM32F3: 1.5.2 * STM32F4: 1.7.4 - * STM32F7: 1.2.5 + * STM32F7: 1.2.6 * STM32L0: 1.8.2 * STM32L1: 1.3.1 * STM32L4: 1.8.3 From 691fbce21e734a2358db815c25ffde3948e459ac Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 24 Jul 2018 17:53:03 +0200 Subject: [PATCH 012/109] Update STM32F7xx CMSIS to v1.2.3 Included in STM32CubeF7 FW V1.12.0 Signed-off-by: Frederic.Pillon --- .../Device/ST/STM32F7xx/Include/stm32f730xx.h | 15488 ++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f750xx.h | 17854 ++++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f7xx.h | 18 +- .../Device/ST/STM32F7xx/Release_Notes.html | 4 +- .../Templates/gcc/startup_stm32f730xx.s | 556 + .../Templates/gcc/startup_stm32f750xx.s | 592 + .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 7 files changed, 34507 insertions(+), 7 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h new file mode 100644 index 0000000000..664bb7ecf0 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h @@ -0,0 +1,15488 @@ +/** + ****************************************************************************** + * @file stm32f730xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

              © COPYRIGHT(c) 2016 STMicroelectronics

              + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f730xx + * @{ + */ + +#ifndef __STM32F730xx_H +#define __STM32F730xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + AES_IRQn = 79, /*!< AES global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ + __IO uint32_t OPTCR2; /*!< FLASH option control register 2 , Address offset: 0x1C */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_HS_PHY_Registers + */ +typedef struct +{ + +__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ +__IO uint32_t Reserved04; /*!< Reserved 004h */ +__IO uint32_t Reserved08; /*!< Reserved 008h */ +__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ +__IO uint32_t Reserved10; /*!< Reserved 010h */ +__IO uint32_t Reserved14; /*!< Reserved 014h */ +__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ +} USB_HS_PHYC_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20010000U /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2003C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x0800FFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF07800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF07A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define UID_BASE 0x1FF07A10U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF07A22U /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) +/*!< AHB2 peripherals */ +#define AES_BASE (AHB2PERIPH_BASE + 0x60000U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U +#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_HS_PHYC ((USB_HS_PHYC_GlobalTypeDef *) USB_HS_PHYC_CONTROLLER_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!
              © COPYRIGHT(c) 2016 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f750xx + * @{ + */ + +#ifndef __STM32F750xx_H +#define __STM32F750xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Crypto Processor + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief HASH + */ + +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ + +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x0800FFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100U) +#define ETH_PTP_BASE (ETH_BASE + 0x0700U) +#define ETH_DMA_BASE (ETH_BASE + 0x1000U) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) +#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U) +#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U) +#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!

          Update History

          -

          V1.2.2 +

          V1.2.3 +/ 29-June-2018

                Main +Changes
          • Add the support of STM32F730xx and  STM32F750xx  devices
            • Add "stm32f730xx.h" and "stm32f750xx.h" header files
            • Add startup files "startup_stm32f730xx.s" and "startup_stm32f750xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
            • Add Linker files "stm32f730xx_flash.icf", "stm32f730xx_sram.icf" and "stm32f730xx_ITCM_flash.icf" used within EWARM Workspaces
            • Add Linker files "stm32f750xx_flash.icf", "stm32f750xx_sram.icf" and "stm32f750xx_ITCM_flash.icf" used within EWARM Workspaces

          V1.2.2 / 26-December-2017

          Main Changes

          • Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.

          V1.2.1 diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s new file mode 100644 index 0000000000..5a8a2940ef --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s @@ -0,0 +1,556 @@ +/** + ****************************************************************************** + * @file startup_stm32f730xx.s + * @author MCD Application Team + * @brief STM32F730xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT 2016 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word 0 /* Reserved */ + .word AES_IRQHandler /* AES */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s new file mode 100644 index 0000000000..9e49650c0a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s @@ -0,0 +1,592 @@ +/** + ****************************************************************************** + * @file startup_stm32f750xx.s + * @author MCD Application Team + * @brief STM32F750xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT 2016 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* Crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 6580c5586c..e1c7df313c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -5,7 +5,7 @@ * STM32F2: 2.2.1 * STM32F3: 2.3.3 * STM32F4: 2.6.2 - * STM32F7: 1.2.2 + * STM32F7: 1.2.3 * STM32L0: 1.7.2 * STM32L1: 2.2.3 * STM32L4: 1.4.3 From 0f425f974446acb04686ffd098fbda36ad914ec3 Mon Sep 17 00:00:00 2001 From: Lann Date: Thu, 26 Jul 2018 15:20:13 +0200 Subject: [PATCH 013/109] Add Nucleo-L4R5ZI and Nucleo-L4R5ZI-P support Based on #284 from @Lannakin Signed-off-by: Lann Signed-off-by: Frederic.Pillon --- README.md | 4 + boards.txt | 24 + variants/NUCLEO_L4R5ZI/PeripheralPins.c | 404 +++++++++++++++++ variants/NUCLEO_L4R5ZI/PinNamesVar.h | 25 ++ variants/NUCLEO_L4R5ZI/ldscript.ld | 183 ++++++++ variants/NUCLEO_L4R5ZI/stm32l4xx_hal_conf.h | 475 ++++++++++++++++++++ variants/NUCLEO_L4R5ZI/variant.cpp | 291 ++++++++++++ variants/NUCLEO_L4R5ZI/variant.h | 252 +++++++++++ 8 files changed, 1658 insertions(+) create mode 100644 variants/NUCLEO_L4R5ZI/PeripheralPins.c create mode 100644 variants/NUCLEO_L4R5ZI/PinNamesVar.h create mode 100644 variants/NUCLEO_L4R5ZI/ldscript.ld create mode 100644 variants/NUCLEO_L4R5ZI/stm32l4xx_hal_conf.h create mode 100644 variants/NUCLEO_L4R5ZI/variant.cpp create mode 100644 variants/NUCLEO_L4R5ZI/variant.h diff --git a/README.md b/README.md index 2c67ea06bd..29af4d00e5 100644 --- a/README.md +++ b/README.md @@ -68,6 +68,10 @@ For advanced user, you can use the repository: see the [Using git repository](ht * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) ### Next release + * STM32L4 + * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) + * [NUCLEO-L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) + ## Troubleshooting diff --git a/boards.txt b/boards.txt index d04b2e6fe8..ff649c520b 100644 --- a/boards.txt +++ b/boards.txt @@ -73,6 +73,30 @@ Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.product_line=STM32L496xx Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.variant=NUCLEO_L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.cmsis_lib_gcc=arm_cortexM4l_math +# NUCLEO_L4R5ZI board +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI=Nucleo L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.node=NODE_L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.upload.maximum_data_size=655360 +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.board=NUCLEO_L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.series=STM32L4xx +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.product_line=STM32L4R5xx +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.variant=NUCLEO_L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.cmsis_lib_gcc=arm_cortexM4l_math + +# NUCLEO_L4R5ZI-P board +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P=Nucleo L4R5ZI-P +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.node=NODE_L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.upload.maximum_data_size=655360 +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.board=NUCLEO_L4R5ZI_P +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.series=STM32L4xx +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.product_line=STM32L4R5xx +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.variant=NUCLEO_L4R5ZI +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI-P.build.cmsis_lib_gcc=arm_cortexM4l_math + # Upload menu Nucleo_144.menu.upload_method.MassStorage=Mass Storage Nucleo_144.menu.upload_method.MassStorage.upload.protocol= diff --git a/variants/NUCLEO_L4R5ZI/PeripheralPins.c b/variants/NUCLEO_L4R5ZI/PeripheralPins.c new file mode 100644 index 0000000000..a3f1f86e94 --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/PeripheralPins.c @@ -0,0 +1,404 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32L4R5Z(G-I)Tx.xml + * Merged with STM32L4R5ZITxP.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // D14 +#ifdef ARDUINO_NUCLEO_L4R5ZI + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_11, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, +#endif + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PG_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // D15 + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_10, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PG_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PA_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 +// {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 +// {PB_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N +// {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 +// {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +#ifdef ARDUINO_NUCLEO_L4R5ZI + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +#endif +// {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_14, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 +// {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_15, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 +// {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PF_7, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PF_8, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PF_9, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PF_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PF_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PG_11, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +#ifdef ARDUINO_NUCLEO_L4R5ZI + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, +#endif + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_7, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // STLink Tx + {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, +#ifdef ARDUINO_NUCLEO_L4R5ZI + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +#endif + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // STLink Rx + {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D11 + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D12 + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D13 + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, +// {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, +// {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +//*** No Ethernet *** + +//*** QUADSPI *** + +//*** No QUADSPI *** diff --git a/variants/NUCLEO_L4R5ZI/PinNamesVar.h b/variants/NUCLEO_L4R5ZI/PinNamesVar.h new file mode 100644 index 0000000000..c4331ecd62 --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PE_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PC_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/NUCLEO_L4R5ZI/ldscript.ld b/variants/NUCLEO_L4R5ZI/ldscript.ld new file mode 100644 index 0000000000..56379c18ad --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/ldscript.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L4R5ZITx Device with +** 2048KByte FLASH, 640KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x200A0000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/variants/NUCLEO_L4R5ZI/stm32l4xx_hal_conf.h b/variants/NUCLEO_L4R5ZI/stm32l4xx_hal_conf.h new file mode 100644 index 0000000000..dab4dcf5b5 --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/stm32l4xx_hal_conf.h @@ -0,0 +1,475 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_CONF_H +#define __STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_FIREWALL_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LCD_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/* #define HAL_SWPMI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_TSC_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ + + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32l4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32l4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32l4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_L4R5ZI/variant.cpp b/variants/NUCLEO_L4R5ZI/variant.cpp new file mode 100644 index 0000000000..6ffe0ec7d9 --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/variant.cpp @@ -0,0 +1,291 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +// Match Table 11. NUCLEO-L4R5ZI, NUCLEO-L4R5ZI-P pin assignments +// from UM2179 STM32 Nucleo-144 board +const PinName digitalPin[] = { + PD_9, //D0 + PD_8, //D1 + PF_15, //D2 + PE_13, //D3 + PF_14, //D4 + PE_11, //D5 + PE_9, //D6 + PF_13, //D7 + PF_12, //D8 + PD_15, //D9 + PD_14, //D10 + PA_7, //D11 + PA_6, //D12 + PA_5, //D13 + PB_9, //D14 + PB_8, //D15 + PC_6, //D16 + PB_15, //D17 + PB_13, //D18 + PB_12, //D19 + PA_4, //D20 + PB_4, //D21 + PB_5, //D22 + PB_3, //D23 + PA_4, //D24 + PB_4, //D25 + PA_2, //D26 + PB_10, //D27 + PE_15, //D28 + PB_0, //D29 + PE_12, //D30 + PE_14, //D31 + PA_0, //D32 + PB_0, //D33 + PE_0, //D34 +#ifdef ARDUINO_NUCLEO_L4R5ZI + PB_11, //D35 +#else + NC, //D35 +#endif + PB_10, //D36 + PE_15, //D37 + PE_14, //D38 + PE_12, //D39 + PE_10, //D40 + PE_7, //D41 + PE_8, //D42 + PC_8, //D43 + PC_9, //D44 + PC_10, //D45 + PC_11, //D46 + PC_12, //D47 + PD_2, //D48 + PF_3, //D49 + PF_5, //D50 + PD_7, //D51 + PD_6, //D52 + PD_5, //D53 + PD_4, //D54 + PD_3, //D55 + PE_2, //D56 + PE_4, //D57 + PE_5, //D58 + PE_6, //D59 + PE_3, //D60 + PF_8, //D61 + PF_7, //D62 + PF_9, //D63 + PG_1, //D64 + PG_0, //D65 + PD_1, //D66 + PD_0, //D67 + PF_0, //D68 + PF_1, //D69 + PF_2, //D70 + PB_6, //D71 + PB_2, //D72 +// ST Morpho + PA_8, //D73 + PA_9, //D74 + PA_10, //D75 + PA_11, //D76 + PA_12, //D77 + PA_15, //D78 + PB_7, //D79 - LEDBLUE + PB_14, //D80 - LEDRED + PC_7, //D81 - LEDGREEN + PC_13, //D82 - USERBTN + PC_14, //D83 + PC_15, //D84 + PD_10, //D85 + PD_11, //D86 + PD_12, //D87 + PD_13, //D88 + PE_1, //D89 + PF_10, //D90 + PF_11, //D91 + PG_2, //D92 + PG_3, //D93 + PG_4, //D94 + PG_5, //D95 + PG_6, //D96 + PG_7, //D97 - Serial Tx + PG_8, //D98 - Serial Rx + PG_9, //D99 + PG_10, //D100 + PG_11, //D101 + PG_12, //D102 + PG_13, //D103 + PG_14, //D104 + PH_0, //D105 + PH_1, //D106 + // Analog pins + PA_3, //D107/A0 + PC_0, //D108/A1 + PC_3, //D109/A2 + PC_1, //D110/A3 + PC_4, //D111/A4 + PC_5, //D112/A5 + PB_1, //D113/A6 + PC_2, //D114/A7 + PA_1, //D115/A8 + // Duplicated pins in order to be aligned with PinMapADC + PA_7, //D116/A9 = D11 + PA_6, //D117/A10 = D12 + PA_5, //D118/A11 = D13 + PA_4, //D119/A12 = D20 + PA_2, //D120/A13 = D26 + PB_0, //D121/A14 = D29 + PA_0, //D122/A15 = D32 +#ifdef ARDUINO_NUCLEO_L4R5ZI + PG_15 //D123 +#endif +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 120000000 + * HCLK(Hz) = 120000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 2 + * APB2 Prescaler = 1 + * PLL_M = 1 + * PLL_N = 60 + * PLL_P = 2 + * PLL_Q = 2 + * PLL_R = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInit; + + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; + PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + PeriphClkInit.PLLSAI1.PLLSAI1N = 24; + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /**Enable MSI Auto calibration + */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/NUCLEO_L4R5ZI/variant.h b/variants/NUCLEO_L4R5ZI/variant.h new file mode 100644 index 0000000000..db2be985c3 --- /dev/null +++ b/variants/NUCLEO_L4R5ZI/variant.h @@ -0,0 +1,252 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +// Match Table 11. NUCLEO-L4R5ZI, NUCLEO-L4R5ZI-P pin assignments +// from UM2179 STM32 Nucleo-144 board +enum { + PD9, //D0 + PD8, //D1 + PF15, //D2 + PE13, //D3 + PF14, //D4 + PE11, //D5 + PE9, //D6 + PF13, //D7 + PF12, //D8 + PD15, //D9 + PD14, //D10 + PA7, //D11 + PA6, //D12 + PA5, //D13 + PB9, //D14 + PB8, //D15 + PC6, //D16 + PB15, //D17 + PB13, //D18 + PB12, //D19 + PA4, //D20 + PB4, //D21 + PB5, //D22 + PB3, //D23 + PA4_2,//D24 + PB4_2,//D25 + PA2, //D26 + PB10, //D27 + PE15, //D28 + PB0, //D29 + PE12, //D30 + PE14, //D31 + PA0, //D32 + PB0_2,//D33 + PE0, //D34 +#ifdef ARDUINO_NUCLEO_L4R5ZI + PB11, //D35 +#else + NC_1, //D35 +#endif + PB10_2,//D36 + PE15_2,//D37 + PE14_2,//D38 + PE12_2,//D39 + PE10, //D40 + PE7, //D41 + PE8, //D42 + PC8, //D43 + PC9, //D44 + PC10, //D45 + PC11, //D46 + PC12, //D47 + PD2, //D48 + PF3, //D49 + PF5, //D50 + PD7, //D51 + PD6, //D52 + PD5, //D53 + PD4, //D54 + PD3, //D55 + PE2, //D56 + PE4, //D57 + PE5, //D58 + PE6, //D59 + PE3, //D60 + PF8, //D61 + PF7, //D62 + PF9, //D63 + PG1, //D64 + PG0, //D65 + PD1, //D66 + PD0, //D67 + PF0, //D68 + PF1, //D69 + PF2, //D70 + PB6, //D71 + PB2, //D72 +// ST Morpho + PA8, //D73 + PA9, //D74 + PA10, //D75 + PA11, //D76 + PA12, //D77 + PA15, //D78 + PB7, //D79 - LEDBLUE + PB14, //D80 - LEDRED + PC7, //D81 - LEDGREEN + PC13, //D82 - USERBTN + PC14, //D83 + PC15, //D84 + PD10, //D85 + PD11, //D86 + PD12, //D87 + PD13, //D88 + PE1, //D89 + PF10, //D90 + PF11, //D91 + PG2, //D92 + PG3, //D93 + PG4, //D94 + PG5, //D95 + PG6, //D96 + PG7, //D97 - Serial Tx + PG8, //D98 - Serial Rx + PG9, //D99 + PG10, //D100 + PG11, //D101 + PG12, //D102 + PG13, //D103 + PG14, //D104 + PH0, //D105 + PH1, //D106 + // Analog pins + PA3, //D107/A0 + PC0, //D108/A1 + PC3, //D109/A2 + PC1, //D110/A3 + PC4, //D111/A4 + PC5, //D112/A5 + PB1, //D113/A6 + PC2, //D114/A7 + PA1, //D115/A8 + // Duplicated pins in order to be aligned with PinMapADC + PA7_3, //D116/A9 = D11 + PA6_2, //D117/A10 = D12 + PA5_2, //D118/A11 = D13 + PA4_3, //D119/A12 = D20 + PA2_2, //D120/A13 = D26 + PB0_3, //D121/A14 = D29 + PA0_2, //D122/A15 = D32 +#ifdef ARDUINO_NUCLEO_L4R5ZI + PG15, //D123 +#endif + // PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. + // If ST-LINK part is not cut, it is not recommended to use them as I/O pins. +//PA13, //D124 +//PA14, //D125 + PEND +}; + +// This must be a literal with the same value as PEND +#ifdef ARDUINO_NUCLEO_L4R5ZI +#define NUM_DIGITAL_PINS 124 +#else +#define NUM_DIGITAL_PINS 123 +#endif +// This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 16 +#define NUM_ANALOG_FIRST 107 + +// On-board LED pin number +#define LED_BUILTIN PC7 +#define LED_GREEN LED_BUILTIN +#define LED_BLUE PB7 +#define LED_RED PB14 + +// On-board user button +#define USER_BTN PC13 + +// Timer Definitions +// Do not use timer used by PWM pins when possible. See PinMap_PWM. +#define TIMER_TONE TIM6 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work + +// UART Definitions +#define SERIAL_UART_INSTANCE 0 //Connected to ST-Link - LPUART1 + +// Serial pin used for console (ex: stlink) +// Required by Firmata +#define PIN_SERIAL_RX PG8 +#define PIN_SERIAL_TX PG7 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From c322ae509c8b7c116be529d6b168ef917f043d8e Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 30 Jul 2018 09:06:26 +0200 Subject: [PATCH 014/109] [U(S)ART] Fix AF settings Since e02bc35d8844148c5d4157f9b88cae72d71520f2, some serial was not functional. Ex for Nucleo-L432KC, the AF of USART2 (used for STLink VCP) are not the same. Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/uart.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cores/arduino/stm32/uart.c b/cores/arduino/stm32/uart.c index 222526a654..034896896a 100644 --- a/cores/arduino/stm32/uart.c +++ b/cores/arduino/stm32/uart.c @@ -285,6 +285,9 @@ void uart_init(serial_t *obj) GPIO_InitStruct.Pin = STM_GPIO_PIN(obj->pin_tx); GPIO_InitStruct.Mode = STM_PIN_MODE(function); GPIO_InitStruct.Pull = STM_PIN_PUPD(function); +#ifndef STM32F1xx + GPIO_InitStruct.Alternate = STM_PIN_AFNUM(function); +#endif /* STM32F1xx */ HAL_GPIO_Init(port, &GPIO_InitStruct); From b7a4db95c8d6c86948df18a8182bd396e68b7ce1 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 26 Jul 2018 17:54:38 +0200 Subject: [PATCH 015/109] Remove useless build.flags for default optimization Since 5b811b459872a9474470987654d3d6fe57c5c7eb, those lines are useless Signed-off-by: Frederic.Pillon --- boards.txt | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/boards.txt b/boards.txt index d04b2e6fe8..192890bdbb 100644 --- a/boards.txt +++ b/boards.txt @@ -559,8 +559,6 @@ Disco.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE # Optimizations Nucleo_144.menu.opt.osstd=Smallest (-Os default) -Nucleo_144.menu.opt.osstd.build.flags.optimize=-Os -Nucleo_144.menu.opt.osstd.build.flags.ldspecs= Nucleo_144.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_144.menu.opt.oslto.build.flags.optimize=-Os -flto Nucleo_144.menu.opt.oslto.build.flags.ldspecs=-flto @@ -587,8 +585,6 @@ Nucleo_144.menu.opt.ogstd.build.flags.optimize=-g -Og Nucleo_144.menu.opt.ogstd.build.flags.ldspecs= Nucleo_64.menu.opt.osstd=Smallest (-Os default) -Nucleo_64.menu.opt.osstd.build.flags.optimize=-Os -Nucleo_64.menu.opt.osstd.build.flags.ldspecs= Nucleo_64.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_64.menu.opt.oslto.build.flags.optimize=-Os -flto Nucleo_64.menu.opt.oslto.build.flags.ldspecs=-flto @@ -615,8 +611,6 @@ Nucleo_64.menu.opt.ogstd.build.flags.optimize=-g -Og Nucleo_64.menu.opt.ogstd.build.flags.ldspecs= Nucleo_32.menu.opt.osstd=Smallest (-Os default) -Nucleo_32.menu.opt.osstd.build.flags.optimize=-Os -Nucleo_32.menu.opt.osstd.build.flags.ldspecs= Nucleo_32.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_32.menu.opt.oslto.build.flags.optimize=-Os -flto Nucleo_32.menu.opt.oslto.build.flags.ldspecs=-flto @@ -643,8 +637,6 @@ Nucleo_32.menu.opt.ogstd.build.flags.optimize=-g -Og Nucleo_32.menu.opt.ogstd.build.flags.ldspecs= Disco.menu.opt.osstd=Smallest (-Os default) -Disco.menu.opt.osstd.build.flags.optimize=-Os -Disco.menu.opt.osstd.build.flags.ldspecs= Disco.menu.opt.oslto=Smallest (-Os) with LTO Disco.menu.opt.oslto.build.flags.optimize=-Os -flto Disco.menu.opt.oslto.build.flags.ldspecs=-flto @@ -671,8 +663,6 @@ Disco.menu.opt.ogstd.build.flags.optimize=-g -Og Disco.menu.opt.ogstd.build.flags.ldspecs= GenF103.menu.opt.osstd=Smallest (-Os default) -GenF103.menu.opt.osstd.build.flags.optimize=-Os -GenF103.menu.opt.osstd.build.flags.ldspecs= GenF103.menu.opt.oslto=Smallest (-Os) with LTO GenF103.menu.opt.oslto.build.flags.optimize=-Os -flto GenF103.menu.opt.oslto.build.flags.ldspecs=-flto @@ -699,8 +689,6 @@ GenF103.menu.opt.ogstd.build.flags.optimize=-g -Og GenF103.menu.opt.ogstd.build.flags.ldspecs= Maple.menu.opt.osstd=Smallest (-Os default) -Maple.menu.opt.osstd.build.flags.optimize=-Os -Maple.menu.opt.osstd.build.flags.ldspecs= Maple.menu.opt.oslto=Smallest (-Os) with LTO Maple.menu.opt.oslto.build.flags.optimize=-Os -flto Maple.menu.opt.oslto.build.flags.ldspecs=-flto From 98efbe71d25dcb8bb7d998619e88834485c60341 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 30 Jul 2018 14:04:02 +0200 Subject: [PATCH 016/109] [U(S)ART] Add missing HAL_UART_MODULE_ENABLED guard If printf() function is used and HAL_UART_MODULE_ENABLED is disabled uart_debug_write() is not defined. Instead return len. Signed-off-by: Frederic.Pillon --- cores/arduino/syscalls_stm32.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cores/arduino/syscalls_stm32.c b/cores/arduino/syscalls_stm32.c index d71afd43a0..2631b78b30 100644 --- a/cores/arduino/syscalls_stm32.c +++ b/cores/arduino/syscalls_stm32.c @@ -75,7 +75,12 @@ int _read( UNUSED(int file), UNUSED(char *ptr), UNUSED(int len) ) { __attribute__((weak)) int _write( UNUSED(int file), char *ptr, int len ) { +#ifdef HAL_UART_MODULE_ENABLED return uart_debug_write((uint8_t *)ptr, (uint32_t)len); +#else + (void)ptr; + return len; +#endif } __attribute__((weak)) From c5e9af392648a506b438c0fc6093a77f54dd374e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Jul 2018 08:15:01 +0200 Subject: [PATCH 017/109] Update README.md --- CI/build/README.md | 85 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/CI/build/README.md b/CI/build/README.md index 8691ca373a..fdb8765c28 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -56,7 +56,90 @@ Sketch(es) options: ## Cores configuration files -ToDo +Script is able to uses a JSON configuration file containing the build configuration for one or more maintainer/architecture. +A default configuration file is provided: [cores_config.json](conf/cores_config.json) + + +#### Template +```json +{ + "cores": [ + { + "maintainer": "maintainer/vendor name", + "architecture": "architecture name", + "boards": [ + { + "name": "board1", + "options": "specific options for board1 to concatenate with the fqbn" + }, + { + "name": "board2", + "fqbn": "Fully Qualified Board Name and options, used instead of generated one" + } + ], + "sketches": [ + { + "pattern": "sketche(s) pattern", + "applicable": true, + "boards": [ "List of boards (comma separated) which can be built for the sketche(s) pattern. Only those listed board will be built." ], + "options": "specific options to build the matched sketch pattern to concatenate with the fqbn (optional)" + }, + { + "pattern": "sketche(s) pattern", + "applicable": false, + "boards": [ "List of boards (comma separated) which cannot be built for the sketche(s) pattern. All others available boards will be built." ] + } + ] + }, + { + "maintainer": "Other maintainer/vendor name", + "architecture": "Other architecture name", + "boards": [ + { + "name": "boardx", + "options": "specific options for board1 to concatenate with the fqbn" + } + ], + "sketches": [ + { + "pattern": "sketchbook", + "applicable": true, + "boards": [ "" ] + } + ] + } + ] +} +``` + +#### Template + +Will add `flash=C8` option to the fqbn of the BLUEPILL_F103C8 board +```json + { + "name": "BLUEPILL_F103C8", + "options": "flash=C8" + } +``` + +Will ignore `04.Communication/MultiSerial.ino` and `04.Communication/SerialPassthrough.ino` +```json + { + "pattern": "04.Communication/(Multi)?Serial(Passthrough)?", + "applicable": true, + "boards": [ "" ] + } +``` + +Will build all sketch available in `09.USB/*` for the listed boards and add `usb=HID` option to the fqbn +```json + { + "pattern": "09.USB", + "applicable": true, + "boards": [ "NUCLEO_F429ZI", "DISCO_L475VG_IOT", "DISCO_F407VG" ], + "options": "usb=HID" + } +``` ## Usage examples From 1c997bf0b249293a60fd5a9beb060b7cf8bd1332 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Jul 2018 08:34:08 +0200 Subject: [PATCH 018/109] Update README.md --- CI/build/README.md | 89 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/CI/build/README.md b/CI/build/README.md index fdb8765c28..d7c876d9b9 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -131,7 +131,7 @@ Will ignore `04.Communication/MultiSerial.ino` and `04.Communication/SerialPasst } ``` -Will build all sketch available in `09.USB/*` for the listed boards and add `usb=HID` option to the fqbn +Will build all sketches available in `09.USB/*` for the listed boards and add `usb=HID` option to the fqbn ```json { "pattern": "09.USB", @@ -143,5 +143,90 @@ Will build all sketch available in `09.USB/*` for the listed boards and add `us ## Usage examples -ToDo +* List all boards containing `F1` or `L4` (not case sensitive): +`python3 arduino-builder.py -l -b "F1|l4"` + +Will produce on the [stm32](https://github.com/stm32duino/Arduino_Core_STM32) core: +``` +Cores configuration JSON file that will be used: conf/cores_config.json +Build configuration for 'STM32' maintainer and 'stm32' architecture +9 board(s) available +BLUEPILL_F103C8 +DISCO_F100RB +DISCO_L475VG_IOT +MAPLEMINI_F103CB +NUCLEO_F103RB +NUCLEO_L432KC +NUCLEO_L476RG +NUCLEO_L496ZG +NUCLEO_L496ZG-P +``` + +* List all sketch containing `digital` or `analog` (not case sensitive): + +`python3 arduino-builder.py -l sketch -s "Digital|analog"` + +Will produce on the [stm32](https://github.com/stm32duino/Arduino_Core_STM32) core: +``` +Cores configuration JSON file that will be used: conf/cores_config.json +Build configuration for 'STM32' maintainer and 'stm32' architecture +/examples/01.Basics/AnalogReadSerial/AnalogReadSerial.ino +/examples/01.Basics/DigitalReadSerial/DigitalReadSerial.ino +/examples/01.Basics/ReadAnalogVoltage/ReadAnalogVoltage.ino +/examples/02.Digital/BlinkWithoutDelay/BlinkWithoutDelay.ino +/examples/02.Digital/Button/Button.ino +/examples/02.Digital/Debounce/Debounce.ino +/examples/02.Digital/DigitalInputPullup/DigitalInputPullup.ino +/examples/02.Digital/StateChangeDetection/StateChangeDetection.ino +/examples/02.Digital/toneKeyboard/toneKeyboard.ino +/examples/02.Digital/toneMelody/toneMelody.ino +/examples/02.Digital/toneMultiple/toneMultiple.ino +/examples/02.Digital/tonePitchFollower/tonePitchFollower.ino +/examples/03.Analog/AnalogInOutSerial/AnalogInOutSerial.ino +/examples/03.Analog/AnalogInput/AnalogInput.ino +/examples/03.Analog/AnalogWriteMega/AnalogWriteMega.ino +/examples/03.Analog/Calibration/Calibration.ino +/examples/03.Analog/Fading/Fading.ino +/examples/03.Analog/Smoothing/Smoothing.ino +/examples/10.StarterKit_BasicKit/p08_DigitalHourglass/p08_DigitalHourglass.ino +19 sketches found +``` + +* Build all sketches containing `digital` or `analog` for all boards containing `F1` or `L4` (not case sensitive): + +`python3 arduino-builder.py -s "Digital|analog"` + +* List all boards for STM32F1 core: + +`python3 arduino-builder.py -l --arch STM32F1` + +Will list: +``` +Cores configuration JSON file that will be used: conf/cores_config.json +Build configuration for 'Arduino_STM32' maintainer and 'STM32F1' architecture +23 board(s) available +NucleoF103_HSE +NucleoF103_HSI +STM32F103C8 +STM32F103CB +STM32F103R8 +STM32F103RB +STM32F103RC +STM32F103RE +STM32F103T8 +STM32F103TB +STM32F103VB +STM32F103VC +STM32F103VD +STM32F103VE +STM32F103ZC +STM32F103ZD +STM32F103ZE +STM32VLD +hytiny-stm32f103t +maple +mapleMini +mapleRET6 +microduino32_flash +``` From 61f0fa30a7d5e506dcf0506d3f344c8301862f78 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Jul 2018 08:35:42 +0200 Subject: [PATCH 019/109] Update README.md --- CI/build/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/build/README.md b/CI/build/README.md index d7c876d9b9..1105e27cdc 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -112,7 +112,7 @@ A default configuration file is provided: [cores_config.json](conf/cores_config. } ``` -#### Template +#### Examples Will add `flash=C8` option to the fqbn of the BLUEPILL_F103C8 board ```json From 089d5adb525f957445cf2a280be55bb21ca79bea Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Jul 2018 08:37:18 +0200 Subject: [PATCH 020/109] Update README.md --- CI/build/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/build/README.md b/CI/build/README.md index 1105e27cdc..f96254a169 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -195,7 +195,7 @@ Build configuration for 'STM32' maintainer and 'stm32' architecture * Build all sketches containing `digital` or `analog` for all boards containing `F1` or `L4` (not case sensitive): -`python3 arduino-builder.py -s "Digital|analog"` +`python3 arduino-builder.py -s "Digital|analog" -b "F1|l4"` * List all boards for STM32F1 core: From c70f367267c31c3807f0700eb3280242e9f0d06c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 31 Jul 2018 09:11:49 +0200 Subject: [PATCH 021/109] Update README.md --- CI/build/README.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/CI/build/README.md b/CI/build/README.md index f96254a169..69fea819fb 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -25,7 +25,7 @@ optional arguments: -b pattern, --board pattern pattern to find one or more board(s) to build -c, --clean clean output directory - /arduinoBuilderOutput + /arduinoBuilderOutput --arch architecture core architecture to build. Default build architecture is stm32 --config @@ -34,14 +34,13 @@ optional arguments: build, applicability of sketches for boards or required options. If sketch is not listed then applicable to all board. Default core configuration is - for 'stm32' architecture in: /arduino- - builder/conf/cores_config.json + for 'stm32' architecture in: conf/cores_config.json -v, --verbose enable arduino-builder verbose mode --bin save binaries --travis Custom configuration for Travis CI build Sketch(es) options: - By default build /arduino/examples/01.Basics/Blink/Blink.ino + By default build /examples/01.Basics/Blink/Blink.ino -i , --ino single ino file to build @@ -51,7 +50,7 @@ Sketch(es) options: pattern to find one or more sketch to build -e , --exclude file containing pattern of sketches to ignore. Default - path : /arduino-builder/conf/exclude_list.txt + path : conf/exclude_list.txt ``` ## Cores configuration files From 3ffba8ce85abd20cf33f05b9363c0c7a0e48b134 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 1 Aug 2018 21:48:23 +0200 Subject: [PATCH 022/109] Update README.md --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 29af4d00e5..7fbf6f42db 100644 --- a/README.md +++ b/README.md @@ -63,14 +63,14 @@ For advanced user, you can use the repository: see the [Using git repository](ht * STM32L4 * [Nucleo L432KC](http://www.st.com/en/evaluation-tools/nucleo-l432kc.html) * [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) - * [NUCLEO-L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) - * [NUCLEO-L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) + * [Nucleo-L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) + * [Nucleo-L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) ### Next release * STM32L4 * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) - * [NUCLEO-L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) + * [Nucleo-L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) From 280099e0f408bee27d6c5b452944f6a47da8713f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 2 Aug 2018 09:35:34 +0200 Subject: [PATCH 023/109] Add master build status --- README.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 7fbf6f42db..bf5d31e554 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,7 @@ # Arduino core support for STM32 based boards -### Latest release [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...master) +[![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) +[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...master) +[![Build Status](https://travis-ci.com/stm32duino/Arduino_Core_STM32.svg?branch=master)](https://travis-ci.com/stm32duino/Arduino_Core_STM32) **Warning**: release versioning has been changed from date versioning to semantic one. See [Release Versioning change](https://github.com/stm32duino/wiki/wiki/Release-Versioning-change) @@ -63,14 +65,14 @@ For advanced user, you can use the repository: see the [Using git repository](ht * STM32L4 * [Nucleo L432KC](http://www.st.com/en/evaluation-tools/nucleo-l432kc.html) * [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) - * [Nucleo-L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) - * [Nucleo-L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) + * [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) + * [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) ### Next release * STM32L4 * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) - * [Nucleo-L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) + * [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) From 8da63615cf3e3aac9d0b5e010e13c9eacfa85d66 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 1 Aug 2018 14:52:15 +0200 Subject: [PATCH 024/109] Update LL wrapper files management Move all LL wrapper file in LL/ directory instead of HAL Split stm32yyxx_ll.h file per feature (stm32yyxx_ll_*.h), this allow a better granularity and to include only the required LL header file instead of the full list. Anyway, it will be always possible to include all LL headers if needed using: stm32yyxx_ll.h Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/HAL/stm32yyxx_hal.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_adc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_adc_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_can.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_cec.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_comp.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_comp_ex.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_cortex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_crc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_crc_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_cryp.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_cryp_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dac.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_dac_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_dcmi_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm.c | 2 - .../stm32/HAL/stm32yyxx_hal_dfsdm_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dma.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dma2d.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_dma_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_dsi.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_eth.c | 2 - .../stm32/HAL/stm32yyxx_hal_firewall.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_flash.c | 2 - .../stm32/HAL/stm32yyxx_hal_flash_ex.c | 2 - .../stm32/HAL/stm32yyxx_hal_flash_ramfunc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_fmpi2c.c | 2 - .../stm32/HAL/stm32yyxx_hal_fmpi2c_ex.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_gfxmmu.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_gpio.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_gpio_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_hash.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_hash_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_hcd.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_hrtim.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_i2c.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_i2c_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_i2s.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_i2s_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_irda.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_iwdg.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_jpeg.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_lcd.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_lptim.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_ltdc_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_mdios.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_mmc.c | 2 - .../stm32/HAL/stm32yyxx_hal_msp_template.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_nand.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_nor.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_opamp.c | 2 - .../stm32/HAL/stm32yyxx_hal_opamp_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_ospi.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_pccard.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_pcd.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_pcd_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_pwr.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_pwr_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_qspi.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_rcc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_rcc_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_rng.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_rtc.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_rtc_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sai.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_sai_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sd.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sd_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sdadc.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sdram.c | 2 - .../stm32/HAL/stm32yyxx_hal_smartcard.c | 2 - .../stm32/HAL/stm32yyxx_hal_smartcard_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_smbus.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_spdifrx.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_spi.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_spi_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_sram.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_swpmi.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_tim.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_tim_ex.c | 2 - ...tm32yyxx_hal_timebase_rtc_alarm_template.c | 2 - ...m32yyxx_hal_timebase_rtc_wakeup_template.c | 2 - .../HAL/stm32yyxx_hal_timebase_tim_template.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_tsc.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_uart.c | 2 - .../arduino/stm32/HAL/stm32yyxx_hal_uart_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_usart.c | 2 - .../stm32/HAL/stm32yyxx_hal_usart_ex.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_hal_wwdg.c | 2 - cores/arduino/stm32/HAL/stm32yyxx_ll.h | 236 ------------------ cores/arduino/stm32/LL/stm32yyxx_ll.h | 43 ++++ .../stm32/{HAL => LL}/stm32yyxx_ll_adc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_adc.h | 31 +++ cores/arduino/stm32/LL/stm32yyxx_ll_bus.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_comp.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_comp.h | 19 ++ cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_crc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_crc.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_crs.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_crs.h | 13 + .../stm32/{HAL => LL}/stm32yyxx_ll_dac.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_dac.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_dma.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_dma.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_dma2d.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.h | 13 + cores/arduino/stm32/LL/stm32yyxx_ll_dmamux.h | 7 + .../stm32/{HAL => LL}/stm32yyxx_ll_exti.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_exti.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_fmc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h | 16 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_fsmc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.h | 16 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_gpio.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_hrtim.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.h | 7 + .../stm32/{HAL => LL}/stm32yyxx_ll_i2c.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h | 31 +++ cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_lptim.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h | 16 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_lpuart.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h | 10 + .../stm32/{HAL => LL}/stm32yyxx_ll_opamp.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_opamp.h | 13 + .../stm32/{HAL => LL}/stm32yyxx_ll_pwr.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_rcc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_rng.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_rng.h | 19 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_rtc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_sdmmc.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.h | 22 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_spi.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_spi.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_swpmi.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.h | 7 + cores/arduino/stm32/LL/stm32yyxx_ll_system.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_tim.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_tim.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_usart.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_usart.h | 31 +++ .../stm32/{HAL => LL}/stm32yyxx_ll_usb.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_usb.h | 19 ++ .../stm32/{HAL => LL}/stm32yyxx_ll_utils.c | 2 - cores/arduino/stm32/LL/stm32yyxx_ll_utils.h | 31 +++ cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h | 31 +++ cores/arduino/stm32/clock.c | 1 + cores/arduino/stm32/stm32_def.h | 8 - platform.txt | 2 +- 156 files changed, 831 insertions(+), 481 deletions(-) delete mode 100644 cores/arduino/stm32/HAL/stm32yyxx_ll.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_adc.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_adc.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_bus.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_comp.c (90%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_comp.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_crc.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_crc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_crs.c (84%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_crs.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_dac.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_dac.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_dma.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_dma.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_dma2d.c (84%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_dmamux.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_exti.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_exti.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_fmc.c (87%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_fsmc.c (88%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_gpio.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_hrtim.c (65%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_i2c.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_lptim.c (88%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_lpuart.c (79%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_opamp.c (84%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_opamp.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_pwr.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_rcc.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_rng.c (90%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_rng.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_rtc.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_sdmmc.c (91%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_spi.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_spi.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_swpmi.c (65%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_system.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_tim.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_tim.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_usart.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_usart.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_usb.c (90%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_usb.h rename cores/arduino/stm32/{HAL => LL}/stm32yyxx_ll_utils.c (94%) create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_utils.h create mode 100644 cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal.c b/cores/arduino/stm32/HAL/stm32yyxx_hal.c index de384ea765..55dcf1d237 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_adc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_adc.c index 39555652c0..98e34feaee 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_adc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_adc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_adc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_adc_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_adc_ex.c index c4a7f19fc8..82857d3425 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_adc_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_adc_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_adc_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_can.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_can.c index 9f97accdf7..95f533ae0a 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_can.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_can.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_can.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_cec.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_cec.c index c6b31cf69b..5f89cc0b66 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_cec.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_cec.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_cec.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_comp.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_comp.c index 8ed5f325b5..6e3b147e93 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_comp.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_comp.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_comp.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_comp_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_comp_ex.c index e9288166a1..dfbc055bc2 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_comp_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_comp_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L0xx #include "stm32l0xx_hal_comp_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_cortex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_cortex.c index c65b07fe49..31d161daf5 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_cortex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_cortex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_cortex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_crc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_crc.c index a39fa85cdd..5dbe638469 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_crc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_crc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_crc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_crc_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_crc_ex.c index 4197d76980..711272e9cb 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_crc_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_crc_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_crc_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp.c index a9d3f494f3..212e30e7aa 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_hal_cryp.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp_ex.c index 1807d1b397..3d7d13ee80 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_cryp_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_cryp_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dac.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dac.c index 22c94de3a3..d927e4c110 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dac.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dac.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_dac.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dac_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dac_ex.c index 706a6edab8..05d3537041 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dac_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dac_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_dac_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi.c index fdc04ffad2..2b1418ed11 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_hal_dcmi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi_ex.c index 5fb7d1f194..7430cb5102 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dcmi_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_dcmi_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm.c index b02272eee5..1a1bb9db46 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_dfsdm.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm_ex.c index a4701c44a0..01da7d2f52 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dfsdm_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_dfsdm_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma.c index 146038be85..172e287676 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_dma.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma2d.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma2d.c index 531fbd1894..872317cc61 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma2d.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma2d.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_dma2d.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma_ex.c index a27f2a4ec3..3a4f1e2eab 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dma_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dma_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_hal_dma_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_dsi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_dsi.c index bc57f14d55..9c63e2abf8 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_dsi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_dsi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_dsi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_eth.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_eth.c index 12f4e6d097..1944038333 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_eth.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_eth.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_eth.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_firewall.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_firewall.c index bd9366da91..c01670ea23 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_firewall.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_firewall.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L0xx #include "stm32l0xx_hal_firewall.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash.c index 7a1e804404..a01c38ba68 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_flash.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ex.c index 83cac34c53..75128fcfa8 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_flash_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ramfunc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ramfunc.c index a39f7094da..994c45a1a3 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ramfunc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_flash_ramfunc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_flash_ramfunc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c.c index 694618f09f..2af6d7351f 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_fmpi2c.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c_ex.c index 94b76d59ae..826a916356 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_fmpi2c_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_fmpi2c_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_gfxmmu.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_gfxmmu.c index 03424ac745..33359c97e9 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_gfxmmu.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_gfxmmu.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_gfxmmu.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio.c index 8fa52166e1..cae6c576c3 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_gpio.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio_ex.c index 927d53aea8..ed1024378e 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_gpio_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_gpio_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_hash.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_hash.c index 5d268c1794..f3f42e128f 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_hash.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_hash.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_hal_hash.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_hash_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_hash_ex.c index 4e785bfe62..c33dc5e341 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_hash_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_hash_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_hash_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_hcd.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_hcd.c index 7b191c83e1..60a24358e9 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_hcd.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_hcd.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_hcd.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_hrtim.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_hrtim.c index 5d3925c164..e94138fce4 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_hrtim.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_hrtim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_hal_hrtim.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c.c index 7510ffc4de..735434a112 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_i2c.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c_ex.c index 8a42fe5335..acb315d63f 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2c_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_i2c_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s.c index 98e61a036e..cd9b2bd0c3 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_i2s.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s_ex.c index 24bdc45a15..1b6ce9f256 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_i2s_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_hal_i2s_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_irda.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_irda.c index efcebe6310..850fae5738 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_irda.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_irda.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_irda.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_iwdg.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_iwdg.c index 6e812dbe3b..424e117653 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_iwdg.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_iwdg.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_iwdg.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_jpeg.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_jpeg.c index 52fa6ea9fb..454b37bac4 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_jpeg.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_jpeg.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F7xx #include "stm32f7xx_hal_jpeg.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_lcd.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_lcd.c index 178584b5c1..fb2c0a733c 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_lcd.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_lcd.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L0xx #include "stm32l0xx_hal_lcd.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_lptim.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_lptim.c index 9ddf4ae775..bea933ace8 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_lptim.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_lptim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_lptim.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc.c index c6f2541a3d..ef9235ee22 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_ltdc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc_ex.c index 783890b1dc..2c560b5617 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_ltdc_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_ltdc_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_mdios.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_mdios.c index 222a4fb95c..68bc819064 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_mdios.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_mdios.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F7xx #include "stm32f7xx_hal_mdios.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_mmc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_mmc.c index f747bc25ab..14967731b2 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_mmc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_mmc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_mmc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_msp_template.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_msp_template.c index 8ec98c00f5..0e14fa0268 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_msp_template.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_msp_template.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #if 0 #ifdef STM32F0xx #include "stm32f0xx_hal_msp_template.c" diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_nand.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_nand.c index 1cec28cbb5..b56f2ee792 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_nand.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_nand.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_nand.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_nor.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_nor.c index 726a1bcd37..fe80983805 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_nor.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_nor.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_nor.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp.c index 9997267429..17f860b600 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_hal_opamp.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp_ex.c index b90add7411..c36f622275 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_opamp_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_hal_opamp_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_ospi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_ospi.c index 9a506ce2ed..110c50b268 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_ospi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_ospi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_ospi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_pccard.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_pccard.c index 3bbe92f1d2..5e4aeb4011 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_pccard.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_pccard.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_pccard.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd.c index 0f4c57a2a8..10bd806eac 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_pcd.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd_ex.c index a1f44e3892..53878a5b30 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_pcd_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_pcd_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr.c index a4b14f507b..522a91c78f 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_pwr.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr_ex.c index 539cb6c303..38bdc37036 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_pwr_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_pwr_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_qspi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_qspi.c index ab41a63b7d..478b339578 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_qspi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_qspi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_qspi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc.c index 970dd0cadd..a6ada4cae4 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_rcc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc_ex.c index bb196b9457..a791c181a5 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_rcc_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_rcc_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_rng.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_rng.c index cac0bedf13..250610cc10 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_rng.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_rng.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_hal_rng.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc.c index 27dce042e2..4a2a82b2d8 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_rtc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc_ex.c index 6d2e672db1..9faeeac1e1 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_rtc_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_rtc_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sai.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sai.c index 0ce2fb018f..e5f08274a9 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sai.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sai.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_sai.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sai_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sai_ex.c index 58e82205a6..407c79f329 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sai_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sai_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_sai_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sd.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sd.c index 303b3a57d9..49f4f5fc7f 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sd.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sd.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_sd.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sd_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sd_ex.c index 98543c5d26..fd9acb5494 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sd_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sd_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_sd_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sdadc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sdadc.c index e0cd603eaf..2afb312bdf 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sdadc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sdadc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_hal_sdadc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sdram.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sdram.c index eda5bb2031..a027bf29d0 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sdram.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sdram.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_sdram.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard.c index ecda05fc87..f0872cdab3 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_smartcard.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard_ex.c index 92e41cb336..071bb1161c 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_smartcard_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_smartcard_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_smbus.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_smbus.c index 5b607cb6db..8aa5c3ec8b 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_smbus.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_smbus.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_smbus.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_spdifrx.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_spdifrx.c index 9e1a4b3ef8..0c15d0deb4 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_spdifrx.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_spdifrx.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_hal_spdifrx.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_spi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_spi.c index 17f91e843e..6c762aa71a 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_spi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_spi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_spi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_spi_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_spi_ex.c index df775bf7df..d6fb3133b1 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_spi_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_spi_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_spi_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_sram.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_sram.c index 3e6c783de2..e8309aaa4a 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_sram.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_sram.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_hal_sram.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_swpmi.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_swpmi.c index 1b09f2808b..b9ddf5e350 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_swpmi.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_swpmi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_swpmi.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_tim.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_tim.c index c7da2ee290..fab393a039 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_tim.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_tim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_tim.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_tim_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_tim_ex.c index ca181e29b8..aa136ee495 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_tim_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_tim_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_tim_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_alarm_template.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_alarm_template.c index 0e6904bb2a..3cc8f4e1b6 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_alarm_template.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_alarm_template.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #if 0 #ifdef STM32F0xx #include "stm32f0xx_hal_timebase_rtc_alarm_template.c" diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_wakeup_template.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_wakeup_template.c index 90ea46cdc3..0d40d22ffe 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_wakeup_template.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_rtc_wakeup_template.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #if 0 #ifdef STM32F0xx #include "stm32f0xx_hal_timebase_rtc_wakeup_template.c" diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_tim_template.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_tim_template.c index 2712481e8d..5496a31695 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_tim_template.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_timebase_tim_template.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #if 0 #ifdef STM32F0xx #include "stm32f0xx_hal_timebase_tim_template.c" diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_tsc.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_tsc.c index 404c6cd63a..6e9b44958a 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_tsc.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_tsc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_tsc.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_uart.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_uart.c index 99e6c44322..b15941870e 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_uart.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_uart.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_uart.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_uart_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_uart_ex.c index 5423c69593..68bdc52faa 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_uart_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_uart_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_uart_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_usart.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_usart.c index fff6748b31..853f5ab613 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_usart.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_usart.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_usart.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_usart_ex.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_usart_ex.c index ebe67b3c77..59c602ce98 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_usart_ex.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_usart_ex.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_hal_usart_ex.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_wwdg.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_wwdg.c index 3a7822fb5a..3be2f60b8e 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_hal_wwdg.c +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_wwdg.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_hal_wwdg.c" #endif diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll.h b/cores/arduino/stm32/HAL/stm32yyxx_ll.h deleted file mode 100644 index df8d2cb020..0000000000 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll.h +++ /dev/null @@ -1,236 +0,0 @@ -#ifdef STM32F0xx -#include "stm32f0xx_ll_adc.h" -#include "stm32f0xx_ll_bus.h" -#include "stm32f0xx_ll_comp.h" -#include "stm32f0xx_ll_cortex.h" -#include "stm32f0xx_ll_crc.h" -#include "stm32f0xx_ll_crs.h" -#include "stm32f0xx_ll_dac.h" -#include "stm32f0xx_ll_dma.h" -#include "stm32f0xx_ll_exti.h" -#include "stm32f0xx_ll_gpio.h" -#include "stm32f0xx_ll_i2c.h" -#include "stm32f0xx_ll_iwdg.h" -#include "stm32f0xx_ll_pwr.h" -#include "stm32f0xx_ll_rcc.h" -#include "stm32f0xx_ll_rtc.h" -#include "stm32f0xx_ll_spi.h" -#include "stm32f0xx_ll_system.h" -#include "stm32f0xx_ll_tim.h" -#include "stm32f0xx_ll_usart.h" -#include "stm32f0xx_ll_utils.h" -#include "stm32f0xx_ll_wwdg.h" -#endif -#ifdef STM32F1xx -#include "stm32f1xx_ll_adc.h" -#include "stm32f1xx_ll_bus.h" -#include "stm32f1xx_ll_cortex.h" -#include "stm32f1xx_ll_crc.h" -#include "stm32f1xx_ll_dac.h" -#include "stm32f1xx_ll_dma.h" -#include "stm32f1xx_ll_exti.h" -#include "stm32f1xx_ll_fsmc.h" -#include "stm32f1xx_ll_gpio.h" -#include "stm32f1xx_ll_i2c.h" -#include "stm32f1xx_ll_iwdg.h" -#include "stm32f1xx_ll_pwr.h" -#include "stm32f1xx_ll_rcc.h" -#include "stm32f1xx_ll_rtc.h" -#include "stm32f1xx_ll_sdmmc.h" -#include "stm32f1xx_ll_spi.h" -#include "stm32f1xx_ll_system.h" -#include "stm32f1xx_ll_tim.h" -#include "stm32f1xx_ll_usart.h" -#include "stm32f1xx_ll_usb.h" -#include "stm32f1xx_ll_utils.h" -#include "stm32f1xx_ll_wwdg.h" -#endif -#ifdef STM32F2xx -#include "stm32f2xx_ll_adc.h" -#include "stm32f2xx_ll_bus.h" -#include "stm32f2xx_ll_cortex.h" -#include "stm32f2xx_ll_crc.h" -#include "stm32f2xx_ll_dac.h" -#include "stm32f2xx_ll_dma.h" -#include "stm32f2xx_ll_exti.h" -#include "stm32f2xx_ll_fsmc.h" -#include "stm32f2xx_ll_gpio.h" -#include "stm32f2xx_ll_i2c.h" -#include "stm32f2xx_ll_iwdg.h" -#include "stm32f2xx_ll_pwr.h" -#include "stm32f2xx_ll_rcc.h" -#include "stm32f2xx_ll_rng.h" -#include "stm32f2xx_ll_rtc.h" -#include "stm32f2xx_ll_sdmmc.h" -#include "stm32f2xx_ll_spi.h" -#include "stm32f2xx_ll_system.h" -#include "stm32f2xx_ll_tim.h" -#include "stm32f2xx_ll_usart.h" -#include "stm32f2xx_ll_usb.h" -#include "stm32f2xx_ll_utils.h" -#include "stm32f2xx_ll_wwdg.h" -#endif -#ifdef STM32F3xx -#include "stm32f3xx_ll_adc.h" -#include "stm32f3xx_ll_bus.h" -#include "stm32f3xx_ll_comp.h" -#include "stm32f3xx_ll_cortex.h" -#include "stm32f3xx_ll_crc.h" -#include "stm32f3xx_ll_dac.h" -#include "stm32f3xx_ll_dma.h" -#include "stm32f3xx_ll_exti.h" -#include "stm32f3xx_ll_fmc.h" -#include "stm32f3xx_ll_gpio.h" -#include "stm32f3xx_ll_hrtim.h" -#include "stm32f3xx_ll_i2c.h" -#include "stm32f3xx_ll_iwdg.h" -#include "stm32f3xx_ll_opamp.h" -#include "stm32f3xx_ll_pwr.h" -#include "stm32f3xx_ll_rcc.h" -#include "stm32f3xx_ll_rtc.h" -#include "stm32f3xx_ll_spi.h" -#include "stm32f3xx_ll_system.h" -#include "stm32f3xx_ll_tim.h" -#include "stm32f3xx_ll_usart.h" -#include "stm32f3xx_ll_utils.h" -#include "stm32f3xx_ll_wwdg.h" -#endif -#ifdef STM32F4xx -#include "stm32f4xx_ll_adc.h" -#include "stm32f4xx_ll_bus.h" -#include "stm32f4xx_ll_cortex.h" -#include "stm32f4xx_ll_crc.h" -#include "stm32f4xx_ll_dac.h" -#include "stm32f4xx_ll_dma.h" -#include "stm32f4xx_ll_dma2d.h" -#include "stm32f4xx_ll_exti.h" -#include "stm32f4xx_ll_fmc.h" -#include "stm32f4xx_ll_fsmc.h" -#include "stm32f4xx_ll_gpio.h" -#include "stm32f4xx_ll_i2c.h" -#include "stm32f4xx_ll_iwdg.h" -#include "stm32f4xx_ll_lptim.h" -#include "stm32f4xx_ll_pwr.h" -#include "stm32f4xx_ll_rcc.h" -#include "stm32f4xx_ll_rng.h" -#include "stm32f4xx_ll_rtc.h" -#include "stm32f4xx_ll_sdmmc.h" -#include "stm32f4xx_ll_spi.h" -#include "stm32f4xx_ll_system.h" -#include "stm32f4xx_ll_tim.h" -#include "stm32f4xx_ll_usart.h" -#include "stm32f4xx_ll_usb.h" -#include "stm32f4xx_ll_utils.h" -#include "stm32f4xx_ll_wwdg.h" -#endif -#ifdef STM32F7xx -#include "stm32f7xx_ll_adc.h" -#include "stm32f7xx_ll_bus.h" -#include "stm32f7xx_ll_cortex.h" -#include "stm32f7xx_ll_crc.h" -#include "stm32f7xx_ll_dac.h" -#include "stm32f7xx_ll_dma.h" -#include "stm32f7xx_ll_dma2d.h" -#include "stm32f7xx_ll_exti.h" -#include "stm32f7xx_ll_fmc.h" -#include "stm32f7xx_ll_gpio.h" -#include "stm32f7xx_ll_i2c.h" -#include "stm32f7xx_ll_iwdg.h" -#include "stm32f7xx_ll_lptim.h" -#include "stm32f7xx_ll_pwr.h" -#include "stm32f7xx_ll_rcc.h" -#include "stm32f7xx_ll_rng.h" -#include "stm32f7xx_ll_rtc.h" -#include "stm32f7xx_ll_sdmmc.h" -#include "stm32f7xx_ll_spi.h" -#include "stm32f7xx_ll_system.h" -#include "stm32f7xx_ll_tim.h" -#include "stm32f7xx_ll_usart.h" -#include "stm32f7xx_ll_usb.h" -#include "stm32f7xx_ll_utils.h" -#include "stm32f7xx_ll_wwdg.h" -#endif -#ifdef STM32L0xx -#include "stm32l0xx_ll_adc.h" -#include "stm32l0xx_ll_bus.h" -#include "stm32l0xx_ll_comp.h" -#include "stm32l0xx_ll_cortex.h" -#include "stm32l0xx_ll_crc.h" -#include "stm32l0xx_ll_crs.h" -#include "stm32l0xx_ll_dac.h" -#include "stm32l0xx_ll_dma.h" -#include "stm32l0xx_ll_exti.h" -#include "stm32l0xx_ll_gpio.h" -#include "stm32l0xx_ll_i2c.h" -#include "stm32l0xx_ll_iwdg.h" -#include "stm32l0xx_ll_lptim.h" -#include "stm32l0xx_ll_lpuart.h" -#include "stm32l0xx_ll_pwr.h" -#include "stm32l0xx_ll_rcc.h" -#include "stm32l0xx_ll_rng.h" -#include "stm32l0xx_ll_rtc.h" -#include "stm32l0xx_ll_spi.h" -#include "stm32l0xx_ll_system.h" -#include "stm32l0xx_ll_tim.h" -#include "stm32l0xx_ll_usart.h" -#include "stm32l0xx_ll_utils.h" -#include "stm32l0xx_ll_wwdg.h" -#endif -#ifdef STM32L1xx -#include "stm32l1xx_ll_adc.h" -#include "stm32l1xx_ll_bus.h" -#include "stm32l1xx_ll_comp.h" -#include "stm32l1xx_ll_cortex.h" -#include "stm32l1xx_ll_crc.h" -#include "stm32l1xx_ll_dac.h" -#include "stm32l1xx_ll_dma.h" -#include "stm32l1xx_ll_exti.h" -#include "stm32l1xx_ll_fsmc.h" -#include "stm32l1xx_ll_gpio.h" -#include "stm32l1xx_ll_i2c.h" -#include "stm32l1xx_ll_iwdg.h" -#include "stm32l1xx_ll_opamp.h" -#include "stm32l1xx_ll_pwr.h" -#include "stm32l1xx_ll_rcc.h" -#include "stm32l1xx_ll_rtc.h" -#include "stm32l1xx_ll_sdmmc.h" -#include "stm32l1xx_ll_spi.h" -#include "stm32l1xx_ll_system.h" -#include "stm32l1xx_ll_tim.h" -#include "stm32l1xx_ll_usart.h" -#include "stm32l1xx_ll_utils.h" -#include "stm32l1xx_ll_wwdg.h" -#endif -#ifdef STM32L4xx -#include "stm32l4xx_ll_adc.h" -#include "stm32l4xx_ll_bus.h" -#include "stm32l4xx_ll_comp.h" -#include "stm32l4xx_ll_cortex.h" -#include "stm32l4xx_ll_crc.h" -#include "stm32l4xx_ll_crs.h" -#include "stm32l4xx_ll_dac.h" -#include "stm32l4xx_ll_dma.h" -#include "stm32l4xx_ll_dma2d.h" -#include "stm32l4xx_ll_dmamux.h" -#include "stm32l4xx_ll_exti.h" -#include "stm32l4xx_ll_fmc.h" -#include "stm32l4xx_ll_gpio.h" -#include "stm32l4xx_ll_i2c.h" -#include "stm32l4xx_ll_iwdg.h" -#include "stm32l4xx_ll_lptim.h" -#include "stm32l4xx_ll_lpuart.h" -#include "stm32l4xx_ll_opamp.h" -#include "stm32l4xx_ll_pwr.h" -#include "stm32l4xx_ll_rcc.h" -#include "stm32l4xx_ll_rng.h" -#include "stm32l4xx_ll_rtc.h" -#include "stm32l4xx_ll_sdmmc.h" -#include "stm32l4xx_ll_spi.h" -#include "stm32l4xx_ll_swpmi.h" -#include "stm32l4xx_ll_system.h" -#include "stm32l4xx_ll_tim.h" -#include "stm32l4xx_ll_usart.h" -#include "stm32l4xx_ll_usb.h" -#include "stm32l4xx_ll_utils.h" -#include "stm32l4xx_ll_wwdg.h" -#endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll.h b/cores/arduino/stm32/LL/stm32yyxx_ll.h new file mode 100644 index 0000000000..4fae97eb04 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll.h @@ -0,0 +1,43 @@ +#ifndef _STM32YYXX_LL_H_ +#define _STM32YYXX_LL_H_ + +/* Include Low Layers drivers */ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#include "stm32yyxx_ll_adc.h" +#include "stm32yyxx_ll_bus.h" +#include "stm32yyxx_ll_comp.h" +#include "stm32yyxx_ll_cortex.h" +#include "stm32yyxx_ll_crc.h" +#include "stm32yyxx_ll_crs.h" +#include "stm32yyxx_ll_dac.h" +#include "stm32yyxx_ll_dma.h" +#include "stm32yyxx_ll_dma2d.h" +#include "stm32yyxx_ll_dmamux.h" +#include "stm32yyxx_ll_exti.h" +#include "stm32yyxx_ll_fmc.h" +#include "stm32yyxx_ll_fsmc.h" +#include "stm32yyxx_ll_gpio.h" +#include "stm32yyxx_ll_hrtim.h" +#include "stm32yyxx_ll_i2c.h" +#include "stm32yyxx_ll_iwdg.h" +#include "stm32yyxx_ll_lptim.h" +#include "stm32yyxx_ll_lpuart.h" +#include "stm32yyxx_ll_opamp.h" +#include "stm32yyxx_ll_pwr.h" +#include "stm32yyxx_ll_rcc.h" +#include "stm32yyxx_ll_rng.h" +#include "stm32yyxx_ll_rtc.h" +#include "stm32yyxx_ll_sdmmc.h" +#include "stm32yyxx_ll_spi.h" +#include "stm32yyxx_ll_swpmi.h" +#include "stm32yyxx_ll_system.h" +#include "stm32yyxx_ll_tim.h" +#include "stm32yyxx_ll_usart.h" +#include "stm32yyxx_ll_usb.h" +#include "stm32yyxx_ll_utils.h" +#include "stm32yyxx_ll_wwdg.h" +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_adc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_adc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_adc.c index 896c502621..993cce0f54 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_adc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_adc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h new file mode 100644 index 0000000000..711513d111 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_ADC_H_ +#define _STM32YYXX_LL_ADC_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_adc.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_adc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_adc.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_adc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_adc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_adc.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_adc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_adc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_adc.h" +#endif +#endif /* _STM32YYXX_LL_ADC_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h b/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h new file mode 100644 index 0000000000..3255c41904 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_BUS_H_ +#define _STM32YYXX_LL_BUS_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_bus.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_bus.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_bus.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_bus.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_bus.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_bus.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_bus.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_bus.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_bus.h" +#endif +#endif /* _STM32YYXX_LL_BUS_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_comp.c b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.c similarity index 90% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_comp.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_comp.c index 3f56931034..a5e334406a 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_comp.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_comp.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h new file mode 100644 index 0000000000..b683133af7 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h @@ -0,0 +1,19 @@ +#ifndef _STM32YYXX_LL_COMP_H_ +#define _STM32YYXX_LL_COMP_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_comp.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_comp.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_comp.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_comp.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_comp.h" +#endif +#endif /* _STM32YYXX_LL_COMP_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h new file mode 100644 index 0000000000..3cac4cf2bc --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_CORTEX_H_ +#define _STM32YYXX_LL_CORTEX_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_cortex.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_cortex.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_cortex.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_cortex.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_cortex.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_cortex.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_cortex.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_cortex.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_cortex.h" +#endif +#endif /* _STM32YYXX_LL_CORTEX_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_crc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_crc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_crc.c index ca19d57aba..1148fb304b 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_crc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_crc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h new file mode 100644 index 0000000000..f23c38a1f4 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_CRC_H_ +#define _STM32YYXX_LL_CRC_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_crc.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_crc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_crc.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_crc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_crc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_crc.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_crc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_crc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_crc.h" +#endif +#endif /* _STM32YYXX_LL_CRC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_crs.c b/cores/arduino/stm32/LL/stm32yyxx_ll_crs.c similarity index 84% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_crs.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_crs.c index 0ece94d19a..58a8ac4425 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_crs.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_crs.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_crs.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_crs.h b/cores/arduino/stm32/LL/stm32yyxx_ll_crs.h new file mode 100644 index 0000000000..863425671c --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_crs.h @@ -0,0 +1,13 @@ +#ifndef _STM32YYXX_LL_CRS_H_ +#define _STM32YYXX_LL_CRS_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_crs.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_crs.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_crs.h" +#endif +#endif /* _STM32YYXX_LL_CRS_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_dac.c b/cores/arduino/stm32/LL/stm32yyxx_ll_dac.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_dac.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_dac.c index 46a83cb45b..81216129c7 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_dac.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dac.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_dac.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_dac.h b/cores/arduino/stm32/LL/stm32yyxx_ll_dac.h new file mode 100644 index 0000000000..66d28a9954 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dac.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_DAC_H_ +#define _STM32YYXX_LL_DAC_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_dac.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_dac.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_dac.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_dac.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_dac.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_dac.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_dac.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_dac.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_dac.h" +#endif +#endif /* _STM32YYXX_LL_DAC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_dma.c b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_dma.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_dma.c index 5f55e2aa93..c3edad5515 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_dma.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_dma.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h new file mode 100644 index 0000000000..271d801b62 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_DMA_H_ +#define _STM32YYXX_LL_DMA_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_dma.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_dma.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_dma.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_dma.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_dma.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_dma.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_dma.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_dma.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_dma.h" +#endif +#endif /* _STM32YYXX_LL_DMA_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_dma2d.c b/cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.c similarity index 84% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_dma2d.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.c index 0d0f782dd2..2d4a7168d6 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_dma2d.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_ll_dma2d.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.h b/cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.h new file mode 100644 index 0000000000..1ac95522dd --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dma2d.h @@ -0,0 +1,13 @@ +#ifndef _STM32YYXX_LL_DMA2D_H_ +#define _STM32YYXX_LL_DMA2D_H_ + +#ifdef STM32F4xx +#include "stm32f4xx_ll_dma2d.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_dma2d.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_dma2d.h" +#endif +#endif /* _STM32YYXX_LL_DMA2D_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_dmamux.h b/cores/arduino/stm32/LL/stm32yyxx_ll_dmamux.h new file mode 100644 index 0000000000..816a5be33b --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dmamux.h @@ -0,0 +1,7 @@ +#ifndef _STM32YYXX_LL_DMAMUX_H_ +#define _STM32YYXX_LL_DMAMUX_H_ + +#ifdef STM32L4xx +#include "stm32l4xx_ll_dmamux.h" +#endif +#endif /* _STM32YYXX_LL_DMAMUX_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_exti.c b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_exti.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_exti.c index e2253ed749..3e644083af 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_exti.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_exti.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h new file mode 100644 index 0000000000..e3e734a34f --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_EXTI_H_ +#define _STM32YYXX_LL_EXTI_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_exti.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_exti.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_exti.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_exti.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_exti.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_exti.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_exti.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_exti.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_exti.h" +#endif +#endif /* _STM32YYXX_LL_EXTI_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_fmc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.c similarity index 87% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_fmc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_fmc.c index f0f71aeb4f..12b4ab89e9 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_fmc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_ll_fmc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h new file mode 100644 index 0000000000..01c1dec114 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h @@ -0,0 +1,16 @@ +#ifndef _STM32YYXX_LL_FMC_H_ +#define _STM32YYXX_LL_FMC_H_ + +#ifdef STM32F3xx +#include "stm32f3xx_ll_fmc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_fmc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_fmc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_fmc.h" +#endif +#endif /* _STM32YYXX_LL_FMC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_fsmc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.c similarity index 88% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_fsmc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.c index 14dedb5c09..0394a1ce98 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_fsmc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_ll_fsmc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.h new file mode 100644 index 0000000000..84622208e4 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fsmc.h @@ -0,0 +1,16 @@ +#ifndef _STM32YYXX_LL_FSMC_H_ +#define _STM32YYXX_LL_FSMC_H_ + +#ifdef STM32F1xx +#include "stm32f1xx_ll_fsmc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_fsmc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_fsmc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_fsmc.h" +#endif +#endif /* _STM32YYXX_LL_FSMC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_gpio.c b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_gpio.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_gpio.c index c52fb6c016..5dc340d8a5 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_gpio.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_gpio.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h new file mode 100644 index 0000000000..4dc4410ef6 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_GPIO_H_ +#define _STM32YYXX_LL_GPIO_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_gpio.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_gpio.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_gpio.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_gpio.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_gpio.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_gpio.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_gpio.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_gpio.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_gpio.h" +#endif +#endif /* _STM32YYXX_LL_GPIO_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_hrtim.c b/cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.c similarity index 65% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_hrtim.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.c index 73550c57c3..b34dbd5d47 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_hrtim.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_ll_hrtim.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.h b/cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.h new file mode 100644 index 0000000000..d5fa3f6c12 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_hrtim.h @@ -0,0 +1,7 @@ +#ifndef _STM32YYXX_LL_HRTIM_H_ +#define _STM32YYXX_LL_HRTIM_H_ + +#ifdef STM32F3xx +#include "stm32f3xx_ll_hrtim.h" +#endif +#endif /* _STM32YYXX_LL_HRTIM_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_i2c.c b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_i2c.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_i2c.c index a3e3eabc20..0fb4c09eae 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_i2c.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_i2c.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h new file mode 100644 index 0000000000..da0989bd9a --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_I2C_H_ +#define _STM32YYXX_LL_I2C_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_i2c.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_i2c.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_i2c.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_i2c.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_i2c.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_i2c.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_i2c.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_i2c.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_i2c.h" +#endif +#endif /* _STM32YYXX_LL_I2C_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h b/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h new file mode 100644 index 0000000000..c60a1a10cb --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_IWDG_H_ +#define _STM32YYXX_LL_IWDG_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_iwdg.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_iwdg.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_iwdg.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_iwdg.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_iwdg.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_iwdg.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_iwdg.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_iwdg.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_iwdg.h" +#endif +#endif /* _STM32YYXX_LL_IWDG_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_lptim.c b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.c similarity index 88% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_lptim.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_lptim.c index 45bbdccd01..6c811650e1 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_lptim.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F4xx #include "stm32f4xx_ll_lptim.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h new file mode 100644 index 0000000000..e7fb968e92 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h @@ -0,0 +1,16 @@ +#ifndef _STM32YYXX_LL_LPTIM_H_ +#define _STM32YYXX_LL_LPTIM_H_ + +#ifdef STM32F4xx +#include "stm32f4xx_ll_lptim.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_lptim.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_lptim.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_lptim.h" +#endif +#endif /* _STM32YYXX_LL_LPTIM_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_lpuart.c b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.c similarity index 79% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_lpuart.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.c index f8892679ef..df39518d38 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_lpuart.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L0xx #include "stm32l0xx_ll_lpuart.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h new file mode 100644 index 0000000000..76816b9bc3 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h @@ -0,0 +1,10 @@ +#ifndef _STM32YYXX_LL_LPUART_H_ +#define _STM32YYXX_LL_LPUART_H_ + +#ifdef STM32L0xx +#include "stm32l0xx_ll_lpuart.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_lpuart.h" +#endif +#endif /* _STM32YYXX_LL_LPUART_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_opamp.c b/cores/arduino/stm32/LL/stm32yyxx_ll_opamp.c similarity index 84% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_opamp.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_opamp.c index 61a8b3b3d6..1da61e28e1 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_opamp.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_opamp.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F3xx #include "stm32f3xx_ll_opamp.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_opamp.h b/cores/arduino/stm32/LL/stm32yyxx_ll_opamp.h new file mode 100644 index 0000000000..0913178dd2 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_opamp.h @@ -0,0 +1,13 @@ +#ifndef _STM32YYXX_LL_OPAMP_H_ +#define _STM32YYXX_LL_OPAMP_H_ + +#ifdef STM32F3xx +#include "stm32f3xx_ll_opamp.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_opamp.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_opamp.h" +#endif +#endif /* _STM32YYXX_LL_OPAMP_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_pwr.c b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_pwr.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_pwr.c index 0dedc21584..66b84d17c3 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_pwr.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_pwr.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h new file mode 100644 index 0000000000..b947f342a6 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_PWR_H_ +#define _STM32YYXX_LL_PWR_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_pwr.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_pwr.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_pwr.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_pwr.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_pwr.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_pwr.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_pwr.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_pwr.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_pwr.h" +#endif +#endif /* _STM32YYXX_LL_PWR_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_rcc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_rcc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_rcc.c index 91f022444d..d070dc71ff 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_rcc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_rcc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h new file mode 100644 index 0000000000..d6a5de67e3 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_RCC_H_ +#define _STM32YYXX_LL_RCC_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_rcc.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_rcc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_rcc.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_rcc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_rcc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_rcc.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_rcc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_rcc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_rcc.h" +#endif +#endif /* _STM32YYXX_LL_RCC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_rng.c b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.c similarity index 90% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_rng.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_rng.c index e486b3c648..96c5e341ee 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_rng.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F2xx #include "stm32f2xx_ll_rng.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h new file mode 100644 index 0000000000..014c2c952f --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h @@ -0,0 +1,19 @@ +#ifndef _STM32YYXX_LL_RNG_H_ +#define _STM32YYXX_LL_RNG_H_ + +#ifdef STM32F2xx +#include "stm32f2xx_ll_rng.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_rng.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_rng.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_rng.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_rng.h" +#endif +#endif /* _STM32YYXX_LL_RNG_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_rtc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_rtc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_rtc.c index 1607a02f0e..a0a5c4ea4d 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_rtc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_rtc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h new file mode 100644 index 0000000000..aa14a1b86f --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_RTC_H_ +#define _STM32YYXX_LL_RTC_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_rtc.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_rtc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_rtc.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_rtc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_rtc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_rtc.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_rtc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_rtc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_rtc.h" +#endif +#endif /* _STM32YYXX_LL_RTC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_sdmmc.c b/cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.c similarity index 91% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_sdmmc.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.c index 71d8d17449..98f849b3cf 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_sdmmc.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_ll_sdmmc.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.h new file mode 100644 index 0000000000..77bed69e01 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_sdmmc.h @@ -0,0 +1,22 @@ +#ifndef _STM32YYXX_LL_SDMMC_H_ +#define _STM32YYXX_LL_SDMMC_H_ + +#ifdef STM32F1xx +#include "stm32f1xx_ll_sdmmc.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_sdmmc.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_sdmmc.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_sdmmc.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_sdmmc.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_sdmmc.h" +#endif +#endif /* _STM32YYXX_LL_SDMMC_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_spi.c b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_spi.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_spi.c index cf08a68db8..9883b57803 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_spi.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_spi.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h new file mode 100644 index 0000000000..dbfc0540d5 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_SPI_H_ +#define _STM32YYXX_LL_SPI_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_spi.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_spi.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_spi.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_spi.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_spi.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_spi.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_spi.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_spi.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_spi.h" +#endif +#endif /* _STM32YYXX_LL_SPI_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_swpmi.c b/cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.c similarity index 65% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_swpmi.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.c index cb8023b3f9..5c3e9528fe 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_swpmi.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32L4xx #include "stm32l4xx_ll_swpmi.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.h b/cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.h new file mode 100644 index 0000000000..2d49ae9310 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_swpmi.h @@ -0,0 +1,7 @@ +#ifndef _STM32YYXX_LL_SWPMI_H_ +#define _STM32YYXX_LL_SWPMI_H_ + +#ifdef STM32L4xx +#include "stm32l4xx_ll_swpmi.h" +#endif +#endif /* _STM32YYXX_LL_SWPMI_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_system.h b/cores/arduino/stm32/LL/stm32yyxx_ll_system.h new file mode 100644 index 0000000000..e92183b5d6 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_system.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_SYSTEM_H_ +#define _STM32YYXX_LL_SYSTEM_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_system.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_system.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_system.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_system.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_system.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_system.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_system.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_system.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_system.h" +#endif +#endif /* _STM32YYXX_LL_SYSTEM_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_tim.c b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_tim.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_tim.c index 5b91160d46..479e5f26af 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_tim.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_tim.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h new file mode 100644 index 0000000000..a86cbf9e16 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_TIM_H_ +#define _STM32YYXX_LL_TIM_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_tim.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_tim.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_tim.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_tim.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_tim.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_tim.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_tim.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_tim.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_tim.h" +#endif +#endif /* _STM32YYXX_LL_TIM_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_usart.c b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_usart.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_usart.c index 531dd236e4..20b8018759 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_usart.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_usart.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h new file mode 100644 index 0000000000..045cb8ec65 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_USART_H_ +#define _STM32YYXX_LL_USART_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_usart.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_usart.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_usart.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_usart.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_usart.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_usart.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_usart.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_usart.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_usart.h" +#endif +#endif /* _STM32YYXX_LL_USART_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_usb.c b/cores/arduino/stm32/LL/stm32yyxx_ll_usb.c similarity index 90% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_usb.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_usb.c index 111243b107..e8069b4e64 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_usb.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_usb.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F1xx #include "stm32f1xx_ll_usb.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_usb.h b/cores/arduino/stm32/LL/stm32yyxx_ll_usb.h new file mode 100644 index 0000000000..004d039834 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_usb.h @@ -0,0 +1,19 @@ +#ifndef _STM32YYXX_LL_USB_H_ +#define _STM32YYXX_LL_USB_H_ + +#ifdef STM32F1xx +#include "stm32f1xx_ll_usb.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_usb.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_usb.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_usb.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_usb.h" +#endif +#endif /* _STM32YYXX_LL_USB_H_ */ diff --git a/cores/arduino/stm32/HAL/stm32yyxx_ll_utils.c b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.c similarity index 94% rename from cores/arduino/stm32/HAL/stm32yyxx_ll_utils.c rename to cores/arduino/stm32/LL/stm32yyxx_ll_utils.c index 0a53ff0720..b89e04e6e7 100644 --- a/cores/arduino/stm32/HAL/stm32yyxx_ll_utils.c +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.c @@ -1,5 +1,3 @@ -#include "stm32_def_build.h" - #ifdef STM32F0xx #include "stm32f0xx_ll_utils.c" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h new file mode 100644 index 0000000000..63eb99fed5 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_UTILS_H_ +#define _STM32YYXX_LL_UTILS_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_utils.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_utils.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_utils.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_utils.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_utils.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_utils.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_utils.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_utils.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_utils.h" +#endif +#endif /* _STM32YYXX_LL_UTILS_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h b/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h new file mode 100644 index 0000000000..63eda2df9c --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h @@ -0,0 +1,31 @@ +#ifndef _STM32YYXX_LL_WWDG_H_ +#define _STM32YYXX_LL_WWDG_H_ + +#ifdef STM32F0xx +#include "stm32f0xx_ll_wwdg.h" +#endif +#ifdef STM32F1xx +#include "stm32f1xx_ll_wwdg.h" +#endif +#ifdef STM32F2xx +#include "stm32f2xx_ll_wwdg.h" +#endif +#ifdef STM32F3xx +#include "stm32f3xx_ll_wwdg.h" +#endif +#ifdef STM32F4xx +#include "stm32f4xx_ll_wwdg.h" +#endif +#ifdef STM32F7xx +#include "stm32f7xx_ll_wwdg.h" +#endif +#ifdef STM32L0xx +#include "stm32l0xx_ll_wwdg.h" +#endif +#ifdef STM32L1xx +#include "stm32l1xx_ll_wwdg.h" +#endif +#ifdef STM32L4xx +#include "stm32l4xx_ll_wwdg.h" +#endif +#endif /* _STM32YYXX_LL_WWDG_H_ */ diff --git a/cores/arduino/stm32/clock.c b/cores/arduino/stm32/clock.c index d66b240869..0088a61143 100644 --- a/cores/arduino/stm32/clock.c +++ b/cores/arduino/stm32/clock.c @@ -36,6 +36,7 @@ ****************************************************************************** */ #include "clock.h" +#include "stm32yyxx_ll_cortex.h" #ifdef __cplusplus extern "C" { diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 304488f8c6..9fac51eac1 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -26,14 +26,6 @@ #error "STM32YYxx chip series is not defined in boards.txt." #endif -// Include Low Layers drivers -// LL raised several warnings, ignore them -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wunused-parameter" -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#include "HAL/stm32yyxx_ll.h" -#pragma GCC diagnostic pop - // Here define some compatibility #ifndef CAN1 #define CAN1 CAN diff --git a/platform.txt b/platform.txt index ce94d61608..01ac507e35 100644 --- a/platform.txt +++ b/platform.txt @@ -9,7 +9,7 @@ version=1.0.0 # STM compile variables # ---------------------- -compiler.stm.extra_include="-I{build.source.path}" "-I{build.core.path}/avr" "-I{build.core.path}/stm32" "-I{build.system.path}/Drivers/{build.series}_HAL_Driver/Inc/" "-I{build.system.path}/Drivers/{build.series}_HAL_Driver/Src/" "-I{build.system.path}/{build.series}/" "-I{build.variant.path}/usb" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Core/Src" +compiler.stm.extra_include="-I{build.source.path}" "-I{build.core.path}/avr" "-I{build.core.path}/stm32" "-I{build.core.path}/stm32/LL" "-I{build.system.path}/Drivers/{build.series}_HAL_Driver/Inc/" "-I{build.system.path}/Drivers/{build.series}_HAL_Driver/Src/" "-I{build.system.path}/{build.series}/" "-I{build.variant.path}/usb" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Core/Inc" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Core/Src" # "-I{build.system.path}/Drivers/BSP/Components" "-I{build.system.path}/Middlewares/Third_Party/FatFs/src" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Core/Src" "-I{build.system.path}/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc" From 0ee453ee27af2150d6076c794a420b952611d093 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 2 Aug 2018 09:45:45 +0200 Subject: [PATCH 025/109] Add new CMSIS_STARTUP_FILE Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/stm32_def_build.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 5fe0d26ba1..1478742b7a 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -147,6 +147,8 @@ #define CMSIS_STARTUP_FILE "startup_stm32f722xx.s" #elif defined(STM32F723xx) #define CMSIS_STARTUP_FILE "startup_stm32f723xx.s" +#elif defined(STM32F730xx) +#define CMSIS_STARTUP_FILE "startup_stm32f730xx.s" #elif defined(STM32F732xx) #define CMSIS_STARTUP_FILE "startup_stm32f732xx.s" #elif defined(STM32F733xx) @@ -155,6 +157,8 @@ #define CMSIS_STARTUP_FILE "startup_stm32f745xx.s" #elif defined(STM32F746xx) #define CMSIS_STARTUP_FILE "startup_stm32f746xx.s" +#elif defined(STM32F750xx) +#define CMSIS_STARTUP_FILE "startup_stm32f750xx.s" #elif defined(STM32F756xx) #define CMSIS_STARTUP_FILE "startup_stm32f756xx.s" #elif defined(STM32F765xx) From c1b0daead9cc120768411c2fb78680fdd883c328 Mon Sep 17 00:00:00 2001 From: Venelin Efremov Date: Mon, 6 Aug 2018 08:31:55 +0200 Subject: [PATCH 026/109] Add built-in IWatchdog library to expose the IWDG component. Signed-off-by: Venelin Efremov Signed-off-by: Frederic.Pillon --- libraries/IWatchdog/README.md | 136 +++++++++++++++ .../examples/IWDG_Button/IWDG_Button.ino | 85 +++++++++ libraries/IWatchdog/keywords.txt | 29 +++ libraries/IWatchdog/library.properties | 9 + libraries/IWatchdog/src/IWatchdog.cpp | 165 ++++++++++++++++++ libraries/IWatchdog/src/IWatchdog.h | 30 ++++ 6 files changed, 454 insertions(+) create mode 100644 libraries/IWatchdog/README.md create mode 100644 libraries/IWatchdog/examples/IWDG_Button/IWDG_Button.ino create mode 100644 libraries/IWatchdog/keywords.txt create mode 100644 libraries/IWatchdog/library.properties create mode 100644 libraries/IWatchdog/src/IWatchdog.cpp create mode 100644 libraries/IWatchdog/src/IWatchdog.h diff --git a/libraries/IWatchdog/README.md b/libraries/IWatchdog/README.md new file mode 100644 index 0000000000..65bd3cf887 --- /dev/null +++ b/libraries/IWatchdog/README.md @@ -0,0 +1,136 @@ +## IWatchdog Library V1.0.0 for stm32 Arduino core + +**Written by:** _Venelin Efremov_ and _Frederic Pillon_ + +### Requirement +* [Arduino_Core_STM32](https://github.com/stm32duino/Arduino_Core_STM32) version > 1.3.0 + +### What is the IWatchdog library. + +Th IWatchdog library provides an interface to the independent watchdog module (IWDG) inside STM32 chips. +The IWDG module is used in production systems to generate a reset signal to the CPU in case some +catastrophic event causes the software to become "stuck" or unresponsive. + +The IWDG module contains a count-down timer. The module would generate a reset condition when the timer +reaches zero. In normal operation mode the software running on the CPU would reload the timer periodically to +prevent the reset condition from happening. However if a software bug or other error causes the CPU to +execute a different code path for too long, the reload would not happen and the IWDG module would reset the CPU. + +### How to use it +The IWatchdog is a built-in library included with the STM32 core package. To add its functionality to your sketch +you will need to reference the library header file. It is done by adding: `#include ` + +```Arduino +#include + +void setup() { + ... + // Initialize the IWDG with 4 seconds timeout. + // This would cause a CPU reset if the IWDG timer + // is not reloaded in approximately 4 seconds. + IWatchdog.begin(4000000); +} + +void loop() { + ...your code here... + // make sure the code in this loop is executed in + // less than 2 seconds to leave 50% headroom for + // the timer reload. + IWatchdog.reload(); +} + +``` + +### Library functions + +#### Preinstantiate Object + +A default instance is available: `IWatchdog` + +```Arduino +IWatchdogClass IWatchdog = IWatchdogClass(); +``` + +#### Predefined values + + * Minimal timeout in microseconds: `IWDG_TIMEOUT_MIN` + * Maximal timeout in microseconds: `IWDG_TIMEOUT_MAX` + +#### `void begin(uint32_t timeout, uint32_t window = IWDG_TIMEOUT_MAX)` + +The `begin()` function would initialize the IWDG hardware block. + +The `timeout` parameter is in microseconds and set the timer reset timeout. +When the timer reaches zero the hardware block would generate a reset signal +for the CPU. + +When specifying timeout value plan to refresh the timer at least twice +as often. The `reload()` operation is not expensive. + +The downside of selecting a very large timeout value is that your system +may be left in a "stuck" state for too long, before the reset is +generated. + +Valid timeout values depends of the LSI clock. Typically, it is 32kH value are between +125µs and 32,768ms (~32.8 seconds). The precision depends of the timeout values: + + | timeout value range | timeout value precision | + | ------------------- |:-----------------------:| + | 125µs - 512ms | 125µs + | 513ms - 1024ms | 250µs + | 1025ms - 2048ms | 500µs + | 2049ms - 4096ms | 1ms + | 4097ms - 8192ms | 2ms + | 8193ms - 16384ms | 4ms + | 16385ms - 32768ms | 8ms + +The optional `window` parameter is in microseconds and must be less than `timeout`. +If the window option is enabled, the counter must be refreshed inside the window; +otherwise, a system reset is generated. + +**Note:** +Window feature is not available for all STM32 series. + +Calling the `begin()` method with value outside of the valid range +would return without initializing the watchdog timer. + +**WARNING:** +*Once started the IWDG timer can not be stopped. If you are +planning to debug the live system, the watchdog timer may cause the +system to be reset while you are stopped in the debugger. Also consider +the iwatchdog timer implications if you are designing a system which puts +the CPU in sleep mode.* + +#### `void reload()` + +The `reload()` method reloads the counter value. + +Once you have initialized the IWDG you **HAVE** to call `reload()` +periodically to prevent the CPU being reset. + +#### `void set(uint32_t timeout, uint32_t window = IWDG_TIMEOUT_MAX)` + +The `set()` method allows to set the timeout and window values. + +The `timeout` and optional `window` parameters are the same than `begin()` method. + +#### `void get(uint32_t* timeout, uint32_t* window = NULL)` + +The `get()` method allows to get the current timeout and window values +currently set. + +The `timeout` and optional `window` pointers to get values are in microseconds. + +#### `bool isEnabled()` + +The `isEnabled()` method returns status of the IWDG block. If enabled or not. + +#### `bool isReset(bool clear)` + +The `isReset()` method checks if the system has resumed from IWDG reset. + +The optional `clear` parameter allow to clear IWDG reset flag if true. Default: false. + +#### `void clearReset()` + +The `clearReset()` method clears IWDG reset flag. diff --git a/libraries/IWatchdog/examples/IWDG_Button/IWDG_Button.ino b/libraries/IWatchdog/examples/IWDG_Button/IWDG_Button.ino new file mode 100644 index 0000000000..51d69adafb --- /dev/null +++ b/libraries/IWatchdog/examples/IWDG_Button/IWDG_Button.ino @@ -0,0 +1,85 @@ +/* + IWatchdog + Button + + This example code is in the public domain. + + The code demonstrates the use of a independent watchdog timer. + The watchdog timer is initialized with timeout of 10 seconds. + Every time the button is pressed, the watchdog timer is reset. + If left unattended the system would reset itself about every 10 seconds. + + You would have to keep pressing the button frequently (< 10 seconds apart) + to prevent the system from reseting itself. + + You would recognize the reset condition when the LED blinks few times quickly. + + This is not a practical example, in real code you would reset the watchdog + timer in the main loop without requiring user input. + + The code is modified version of the code from: + http://www.arduino.cc/en/Tutorial/Button +*/ + +#include + +#ifdef USER_BTN +const int buttonPin = USER_BTN; +#else +const int buttonPin = 2; +#endif + +#ifdef LED_BUILTIN +const int ledPin = LED_BUILTIN; +#else +const int ledPin = 13; +#endif + +static int default_buttonState = LOW; + +void setup() { + pinMode(ledPin, OUTPUT); + pinMode(buttonPin, INPUT); + + if (IWatchdog.isReset(true)) { + // LED blinks to indicate reset + for (uint8_t idx = 0; idx < 5; idx++) { + digitalWrite(ledPin, HIGH); + delay(100); + digitalWrite(ledPin, LOW); + delay(100); + } + } + + // Read default state of the pushbutton + default_buttonState = digitalRead(buttonPin); + + // Init the watchdog timer with 10 seconds timeout + IWatchdog.begin(10000000); + // or with a 2 seconds window + // IWatchdog.begin(10000000, 2000000); + + if (!IWatchdog.isEnabled()) { + // LED blinks indefinitely + while (1) { + digitalWrite(ledPin, HIGH); + delay(500); + digitalWrite(ledPin, LOW); + delay(500); + } + } +} + +void loop() { + // Compare current button state of the pushbutton value: + if (digitalRead(buttonPin) == default_buttonState) { + digitalWrite(ledPin, LOW); + } else { + digitalWrite(ledPin, HIGH); + + // Uncomment to change timeout value to 6 seconds + //IWatchdog.set(6000000); + + // Reload the watchdog only when the button is pressed + IWatchdog.reload(); + } +} diff --git a/libraries/IWatchdog/keywords.txt b/libraries/IWatchdog/keywords.txt new file mode 100644 index 0000000000..2647aa1c88 --- /dev/null +++ b/libraries/IWatchdog/keywords.txt @@ -0,0 +1,29 @@ +####################################### +# Syntax Coloring Map For IWatchdog +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +IWatchdog KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +set KEYWORD2 +get KEYWORD2 +reload KEYWORD2 +isEnabled KEYWORD2 +isReset KEYWORD2 +clearReset KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +IWDG_TIMEOUT_MIN LITERAL1 +IWDG_TIMEOUT_MAX LITERAL1 +IS_IWDG_TIMEOUT LITERAL1 diff --git a/libraries/IWatchdog/library.properties b/libraries/IWatchdog/library.properties new file mode 100644 index 0000000000..1f45ef1d2d --- /dev/null +++ b/libraries/IWatchdog/library.properties @@ -0,0 +1,9 @@ +name=IWatchdog +version=1.0.0 +author=Venelin Efremov, Frederic Pillon +maintainer=stm32duino +sentence=Enables support for independent watchdog (IWDG) hardware on STM32 processors. +paragraph=Independent watchdog (IWDG) is a hardware timer on the chip which would generate a reset condition if the time is not reloaded withing the specified time. It is generally used in production systems to reset the system if the CPU becomes "stuck". +category=Timing +url= +architectures=stm32 diff --git a/libraries/IWatchdog/src/IWatchdog.cpp b/libraries/IWatchdog/src/IWatchdog.cpp new file mode 100644 index 0000000000..4316009f19 --- /dev/null +++ b/libraries/IWatchdog/src/IWatchdog.cpp @@ -0,0 +1,165 @@ +#include "IWatchdog.h" +#include "stm32yyxx_ll_iwdg.h" +#include "stm32yyxx_ll_rcc.h" + +// Initialize static variable +bool IWatchdogClass::_enabled = false; + +/** + * @brief Enable IWDG, must be called once + * @param timeout: value in microseconds + * @param window: optional value in microseconds + * Default: IWDG_TIMEOUT_MAX + * @retval None + */ +void IWatchdogClass::begin(uint32_t timeout, uint32_t window) +{ + if(!IS_IWDG_TIMEOUT(timeout)) { + return; + } + + // Enable the peripheral clock IWDG + LL_RCC_LSI_Enable(); + while (LL_RCC_LSI_IsReady() != 1) { + } + + // Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register + LL_IWDG_Enable(IWDG); + _enabled = true; + + set(timeout, window); +} + +/** + * @brief Set the timeout and window values + * @param timeout: value in microseconds + * @param window: optional value in microseconds + * Default: IWDG_TIMEOUT_MAX + * @retval None + */ +void IWatchdogClass::set(uint32_t timeout, uint32_t window) +{ + if((isEnabled()) && (!IS_IWDG_TIMEOUT(timeout))) { + return; + } + + // Compute the prescaler value + uint16_t div = 0; + uint8_t prescaler = 0; + uint32_t reload = 0; + + // Convert timeout to seconds + float t_sec = (float)timeout / 1000000 * LSI_VALUE; + + do { + div = 4 << prescaler; + prescaler++; + } while ((t_sec / div) > IWDG_RLR_RL); + + // 'prescaler' value is one of the LL_IWDG_PRESCALER_XX define + if(--prescaler > LL_IWDG_PRESCALER_256) { + return; + } + reload = (uint32_t)(t_sec / div) - 1; + + // Enable register access by writing 0x0000 5555 in the IWDG_KR register + LL_IWDG_EnableWriteAccess(IWDG); + // Write the IWDG prescaler by programming IWDG_PR from 0 to 7 + // LL_IWDG_PRESCALER_4 (0) is lowest divider + LL_IWDG_SetPrescaler(IWDG, (uint32_t)prescaler); + // Write the reload register (IWDG_RLR) + LL_IWDG_SetReloadCounter(IWDG, reload); + +#ifdef IWDG_WINR_WIN + if((window != IWDG_TIMEOUT_MAX) && + (LL_IWDG_GetWindow(IWDG) != IWDG_WINR_WIN)) { + if (window >= timeout) { + // Reset window value + reload = IWDG_WINR_WIN; + } else { + reload = (uint32_t)(((float)window / 1000000 * LSI_VALUE) / div) - 1; + } + LL_IWDG_SetWindow(IWDG, reload); + } +#else + UNUSED(window); +#endif + + // Wait for the registers to be updated (IWDG_SR = 0x0000 0000) + while (LL_IWDG_IsReady(IWDG) != 1) { + } + + // Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA) + LL_IWDG_ReloadCounter(IWDG); +} + +/** + * @brief Get the current timeout and window values + * @param timeout: pointer to the get the value in microseconds + * @param window: optional pointer to the get the value in microseconds + * @retval None + */ +void IWatchdogClass::get(uint32_t* timeout, uint32_t* window) +{ + if(timeout != NULL) { + uint32_t prescaler = 0; + uint32_t reload = 0; + uint32_t win = 0; + float base = (1000000.0 / LSI_VALUE); + + while(LL_IWDG_IsActiveFlag_RVU(IWDG)); + reload = LL_IWDG_GetReloadCounter(IWDG); + + while(LL_IWDG_IsActiveFlag_PVU(IWDG)); + prescaler = LL_IWDG_GetPrescaler(IWDG); + + // Timeout given in microseconds + *timeout = (uint32_t)((4 << prescaler) * (reload + 1) * base); +#ifdef IWDG_WINR_WIN + if(window != NULL) { + while(LL_IWDG_IsActiveFlag_WVU(IWDG)); + win = LL_IWDG_GetWindow(IWDG); + *window = (uint32_t)((4 << prescaler) * (win + 1) * base); + } +#else + UNUSED(window); +#endif + } +} + +/** + * @brief Reload the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA) + * @retval None + */ +void IWatchdogClass::reload(void) +{ + if(isEnabled()) { + LL_IWDG_ReloadCounter(IWDG); + } +} + +/** + * @brief Check if the system has resumed from IWDG reset + * @param clear: if true clear IWDG reset flag. Default false + * @retval return reset flag status + */ +bool IWatchdogClass::isReset(bool clear) +{ + bool status = LL_RCC_IsActiveFlag_IWDGRST(); + if (status && clear) { + clearReset(); + } + return status; +} + +/** + * @brief Clear IWDG reset flag + * @retval None + */ +void IWatchdogClass::clearReset(void) +{ + LL_RCC_ClearResetFlags(); +} + +// Preinstantiate Object +IWatchdogClass IWatchdog = IWatchdogClass(); diff --git a/libraries/IWatchdog/src/IWatchdog.h b/libraries/IWatchdog/src/IWatchdog.h new file mode 100644 index 0000000000..f3a475f53c --- /dev/null +++ b/libraries/IWatchdog/src/IWatchdog.h @@ -0,0 +1,30 @@ +#ifndef __IWATCHDOG_H__ +#define __IWATCHDOG_H__ + +#include "Arduino.h" + +// Minimal timeout in microseconds +#define IWDG_TIMEOUT_MIN ((4*1000000)/LSI_VALUE) +// Maximal timeout in microseconds +#define IWDG_TIMEOUT_MAX (((256*1000000)/LSI_VALUE)*IWDG_RLR_RL) + +#define IS_IWDG_TIMEOUT(X) (((X) >= IWDG_TIMEOUT_MIN) &&\ + ((X) <= IWDG_TIMEOUT_MAX)) + +class IWatchdogClass { + +public: + void begin(uint32_t timeout, uint32_t window = IWDG_TIMEOUT_MAX); + void set(uint32_t timeout, uint32_t window = IWDG_TIMEOUT_MAX); + void get(uint32_t* timeout, uint32_t* window = NULL); + void reload(void); + bool isEnabled(void) {return _enabled;}; + bool isReset(bool clear = false); + void clearReset(void); + +private: + static bool _enabled; +}; + +extern IWatchdogClass IWatchdog; +#endif /* __IWATCHDOG_H__ */ From 10925a1b23b7ac8bae9db1f7c49c34b6cc3831f0 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 6 Aug 2018 09:47:52 +0200 Subject: [PATCH 027/109] [CI] Build BareMinimum instead of Blink by default As some variant could not have LED_BUILTIN use the bare example. See #293 Signed-off-by: Frederic.Pillon --- CI/build/README.md | 2 +- CI/build/arduino-builder.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CI/build/README.md b/CI/build/README.md index 69fea819fb..8d8f349558 100644 --- a/CI/build/README.md +++ b/CI/build/README.md @@ -40,7 +40,7 @@ optional arguments: --travis Custom configuration for Travis CI build Sketch(es) options: - By default build /examples/01.Basics/Blink/Blink.ino + By default build /examples/01.Basics/BareMinimum/BareMinimum.ino -i , --ino single ino file to build diff --git a/CI/build/arduino-builder.py b/CI/build/arduino-builder.py index da3767a841..42cdd2d4ee 100644 --- a/CI/build/arduino-builder.py +++ b/CI/build/arduino-builder.py @@ -122,7 +122,7 @@ # Default sketch_default = os.path.join( - arduino_sketchbook_path, "01.Basics", "Blink", "Blink.ino" + arduino_sketchbook_path, "01.Basics", "BareMinimum", "BareMinimum.ino" ) exclude_file_default = os.path.join("conf", "exclude_list.txt") cores_config_file_default = os.path.join("conf", "cores_config.json") From 54bc27d0bbeda88cf1dc0496a1147a50f74c1ef0 Mon Sep 17 00:00:00 2001 From: Testato Date: Fri, 10 Aug 2018 19:28:46 +0200 Subject: [PATCH 028/109] I2C Scanner examples Tested on Bluepill for all three I2c (TWI 1 - TWI 1 alternative pin - TWI 2) --- .../Wire/examples/i2c_scanner/i2c_scanner.ino | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 libraries/Wire/examples/i2c_scanner/i2c_scanner.ino diff --git a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino new file mode 100644 index 0000000000..bccea8dc39 --- /dev/null +++ b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino @@ -0,0 +1,89 @@ +// -------------------------------------- +// i2c_scanner +// +// Version 1 +// This program (or code that looks like it) +// can be found in many places. +// For example on the Arduino.cc forum. +// The original author is not know. +// Version 2, Juni 2012, Using Arduino 1.0.1 +// Adapted to be as simple as possible by Arduino.cc user Krodal +// Version 3, Feb 26 2013 +// V3 by louarnold +// Version 4, March 3, 2013, Using Arduino 1.0.3 +// by Arduino.cc user Krodal. +// Changes by louarnold removed. +// Scanning addresses changed from 0...127 to 1...119, +// according to the i2c scanner by Nick Gammon +// http://www.gammon.com.au/forum/?id=10896 +// Version 5, March 28, 2013 +// As version 4, but address scans now to 127. +// A sensor seems to use address 120. +// +// This sketch tests the standard 7-bit addresses +// Devices with higher bit address might not be seen properly. +// + + + +// Pinmap for Bluepill I2Cs (by Testato) +// +// I2C-1 standard pins: PB7(sda) PB6(scl) +// Use it by "Wire" without pin declaration +// +// I2C-1 alternative pins: PB9(sda) PB8(scl) +// TwoWire Wire_alt(PB9,PB8); +// +// I2C-2: PB9(sda) PB8(scl) +// TwoWire Wire2(PB11,PB10); + + + +#include + + +void setup() { + + Serial.begin(9600); + Wire.begin(); + Serial.println("\nI2C Scanner"); +} + + +void loop() { + byte error, address; + int nDevices; + + Serial.println("Scanning..."); + + nDevices = 0; + for(address = 1; address < 127; address++) { + // The i2c_scanner uses the return value of + // the Write.endTransmisstion to see if + // a device did acknowledge to the address. + + Wire.beginTransmission(address); + error = Wire.endTransmission(); + + if (error == 0) { + Serial.print("I2C device found at address 0x"); + if (address < 16) + Serial.print("0"); + Serial.println(address, HEX); + + nDevices++; + } + else if (error == 4) { + Serial.print("Unknown error at address 0x"); + if (address < 16) + Serial.print("0"); + Serial.println(address, HEX); + } + } + if (nDevices == 0) + Serial.println("No I2C devices found"); + else + Serial.println("done"); + + delay(5000); // wait 5 seconds for next scan +} From 230631eeb4f5c90adcc029c7f24608769b90e722 Mon Sep 17 00:00:00 2001 From: Testato Date: Fri, 10 Aug 2018 20:06:29 +0200 Subject: [PATCH 029/109] Wire1 do not exist on this core --- libraries/Wire/keywords.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/libraries/Wire/keywords.txt b/libraries/Wire/keywords.txt index 9bb1703584..30040d16d3 100644 --- a/libraries/Wire/keywords.txt +++ b/libraries/Wire/keywords.txt @@ -25,7 +25,6 @@ setSDA KEYWORD2 ####################################### Wire KEYWORD2 -Wire1 KEYWORD2 ####################################### # Constants (LITERAL1) From f8a5a29e6e38061646be18881ebba7fa4898a4bd Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Mon, 13 Aug 2018 10:33:37 +0200 Subject: [PATCH 030/109] Configure I2C Fast Mode when I2C freq is more than 100kHz For STM32 families that have a DutyCycle init parameter, we need to select the Fast Mode dedicated configuration which will set the fast mode bit in CCR register. --- cores/arduino/stm32/twi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index ccd633fb40..4ed2eb8e04 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -261,7 +261,12 @@ void i2c_custom_init(i2c_t *obj, i2c_timing_e timing, uint32_t addressingMode, u handle->Init.Timing = timing; #else handle->Init.ClockSpeed = timing; - handle->Init.DutyCycle = I2C_DUTYCYCLE_2; + /* Standard mode (sm) is up to 100kHz, then it's Fast mode (fm) */ + /* In fast mode duty cyble bit must be set in CCR register */ + if(timing > 100000) + handle->Init.DutyCycle = I2C_DUTYCYCLE_16_9; + else + handle->Init.DutyCycle = I2C_DUTYCYCLE_2; #endif handle->Init.OwnAddress1 = ownAddress; handle->Init.OwnAddress2 = 0xFF; @@ -326,6 +331,12 @@ void i2c_setTiming(i2c_t *obj, uint32_t frequency) obj->handle.Init.Timing = f; #else obj->handle.Init.ClockSpeed = f; + /* Standard mode (sm) is up to 100kHz, then it's Fast mode (fm) */ + /* In fast mode duty cyble bit must be set in CCR register */ + if(frequency > 100000) + obj->handle.Init.DutyCycle = I2C_DUTYCYCLE_16_9; + else + obj->handle.Init.DutyCycle = I2C_DUTYCYCLE_2; #endif /* else if(frequency <= 600000) From b0438381246d320d8aa080ee2ecf89d1491f5183 Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Mon, 13 Aug 2018 16:43:54 +0200 Subject: [PATCH 031/109] I2C Slave : rework slave receive data sequence This work includes some rework of the Slave RX path, which is based on below principle: - we don't know in advance how many bytes will be sent by the I2C master so we'll be listening to bytes 1 by 1 - in order to get them one by one, we're programing the I2C with HAL_I2C_Slave_Sequential_Receive_IT and 1 byte at a time and we're using the HAL_I2C_SlaveRxCpltCallback to store the byte then programing again for next byte. - this sequence is ended when the HAL_I2C_ListenCpltCallback is called, which happens when the master ends the ongoing sequence. We can then prepare for the next one. In order to implement this mecanism, we're introduced a local counter slaveRxNbData where we store the number of received bytes, as well as a new slave mode SLAVE_MODE_LISTEN which allows for extra checks. i2c_s structure members that can be modified from main context or under interrupt context have been marked as volatile. --- cores/arduino/stm32/twi.c | 62 +++++++++++++++++++++++++++++++++------ cores/arduino/stm32/twi.h | 7 +++-- 2 files changed, 57 insertions(+), 12 deletions(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index ccd633fb40..ce9500808f 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -75,6 +75,8 @@ #define SLAVE_MODE_TRANSMIT 0 #define SLAVE_MODE_RECEIVE 1 +#define SLAVE_MODE_LISTEN 2 + /** * @} @@ -283,6 +285,9 @@ void i2c_custom_init(i2c_t *obj, i2c_timing_e timing, uint32_t addressingMode, u HAL_I2C_Init(handle); obj->isMaster = master; + /* Initialize default values */ + obj->slaveRxNbData = 0; + obj->slaveMode = SLAVE_MODE_LISTEN; } /** @@ -395,9 +400,10 @@ i2c_status_e i2c_slave_write_IT(i2c_t *obj, uint8_t *data, uint16_t size) // Check the communication status for(i = 0; i < size; i++) { obj->i2cTxRxBuffer[i] = *(data+i); - obj->i2cTxRxBufferSize++; } + obj->i2cTxRxBufferSize = size; + return I2C_OK; } @@ -509,8 +515,6 @@ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, ui if(AddrMatchCode == hi2c->Init.OwnAddress1) { if(TransferDirection == I2C_DIRECTION_RECEIVE) { - - obj->i2cTxRxBufferSize = 0; obj->slaveMode = SLAVE_MODE_TRANSMIT; if(obj->i2c_onSlaveTransmit != NULL) { @@ -519,9 +523,12 @@ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, ui HAL_I2C_Slave_Sequential_Transmit_IT(hi2c, obj->i2cTxRxBuffer, obj->i2cTxRxBufferSize, I2C_LAST_FRAME); } else { + obj->slaveRxNbData = 0; obj->slaveMode = SLAVE_MODE_RECEIVE; - HAL_I2C_Slave_Sequential_Receive_IT(hi2c, obj->i2cTxRxBuffer, - I2C_TXRX_BUFFER_SIZE, I2C_LAST_FRAME); + /* We don't know in advance how many bytes will be sent by master so + * we'll fetch one by one until master ends the sequence */ + HAL_I2C_Slave_Sequential_Receive_IT(hi2c, &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), + 1, I2C_NEXT_FRAME); } } } @@ -534,19 +541,56 @@ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, ui */ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { - uint8_t nbData = 0; i2c_t *obj = get_i2c_obj(hi2c); + /* Previous master transaction now ended, so inform upper layer if needed + * then prepare for listeing to next request */ if((obj->i2c_onSlaveReceive != NULL) && (obj->slaveMode == SLAVE_MODE_RECEIVE)) { - nbData = I2C_TXRX_BUFFER_SIZE - obj->handle.XferSize; - if(nbData != 0) { - obj->i2c_onSlaveReceive(obj->i2cTxRxBuffer, nbData); + if(obj->slaveRxNbData != 0) { + obj->i2c_onSlaveReceive(obj->i2cTxRxBuffer, obj->slaveRxNbData); } } + obj->slaveMode = SLAVE_MODE_LISTEN; + obj->slaveRxNbData = 0; HAL_I2C_EnableListen_IT(hi2c); } +/** + * @brief Slave RX complete callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + i2c_t *obj = get_i2c_obj(hi2c); + /* One more byte was received, store it then prepare next */ + if(obj->slaveRxNbData < I2C_TXRX_BUFFER_SIZE) { + obj->slaveRxNbData++; + } else { + printf("ERROR: I2C Slave RX overflow\n"); + } + /* Restart interrupt mode for next Byte */ + if(obj->slaveMode == SLAVE_MODE_RECEIVE) { + HAL_I2C_Slave_Sequential_Receive_IT(hi2c, &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), + 1, I2C_NEXT_FRAME); + } +} + +/** + * @brief Slave TX complete callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + i2c_t *obj = get_i2c_obj(hi2c); + /* reset transmit buffer size */ + obj->i2cTxRxBufferSize = 0; +} + /** * @brief I2C error callback. * @note In master mode, the callback is not used because the error is reported diff --git a/cores/arduino/stm32/twi.h b/cores/arduino/stm32/twi.h index 809ac36d95..c347e872a8 100644 --- a/cores/arduino/stm32/twi.h +++ b/cores/arduino/stm32/twi.h @@ -91,12 +91,13 @@ struct i2c_s { #if !defined(STM32F0xx) && !defined(STM32L0xx) IRQn_Type irqER; #endif //!defined(STM32F0xx) && !defined(STM32L0xx) - uint8_t slaveMode; + volatile uint8_t slaveMode; uint8_t isMaster; + volatile int slaveRxNbData; // Number of accumulated bytes received in Slave mode void (*i2c_onSlaveReceive)(uint8_t *, int); void (*i2c_onSlaveTransmit)(void); - uint8_t i2cTxRxBuffer[I2C_TXRX_BUFFER_SIZE]; - uint8_t i2cTxRxBufferSize; + volatile uint8_t i2cTxRxBuffer[I2C_TXRX_BUFFER_SIZE]; + volatile uint8_t i2cTxRxBufferSize; }; ///@brief I2C state From 66f851ac99dd10e2cc15c09b8d489f2559e5bbf3 Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Mon, 13 Aug 2018 10:33:37 +0200 Subject: [PATCH 032/109] Configure I2C Fast Mode when I2C freq is more than 100kHz For STM32 families that have a DutyCycle init parameter, we need to select the Fast Mode dedicated configuration which will set the fast mode bit in CCR register. --- cores/arduino/stm32/twi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index ce9500808f..1e1a2047c3 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -263,7 +263,12 @@ void i2c_custom_init(i2c_t *obj, i2c_timing_e timing, uint32_t addressingMode, u handle->Init.Timing = timing; #else handle->Init.ClockSpeed = timing; - handle->Init.DutyCycle = I2C_DUTYCYCLE_2; + /* Standard mode (sm) is up to 100kHz, then it's Fast mode (fm) */ + /* In fast mode duty cyble bit must be set in CCR register */ + if(timing > 100000) + handle->Init.DutyCycle = I2C_DUTYCYCLE_16_9; + else + handle->Init.DutyCycle = I2C_DUTYCYCLE_2; #endif handle->Init.OwnAddress1 = ownAddress; handle->Init.OwnAddress2 = 0xFF; @@ -331,6 +336,12 @@ void i2c_setTiming(i2c_t *obj, uint32_t frequency) obj->handle.Init.Timing = f; #else obj->handle.Init.ClockSpeed = f; + /* Standard mode (sm) is up to 100kHz, then it's Fast mode (fm) */ + /* In fast mode duty cyble bit must be set in CCR register */ + if(frequency > 100000) + obj->handle.Init.DutyCycle = I2C_DUTYCYCLE_16_9; + else + obj->handle.Init.DutyCycle = I2C_DUTYCYCLE_2; #endif /* else if(frequency <= 600000) From bd0f1660692bfa34b1e479278500000ad3c88c00 Mon Sep 17 00:00:00 2001 From: Testato Date: Tue, 14 Aug 2018 15:57:32 +0200 Subject: [PATCH 033/109] Update i2c_scanner.ino --- libraries/Wire/examples/i2c_scanner/i2c_scanner.ino | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino index bccea8dc39..efcc07e48d 100644 --- a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino +++ b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino @@ -26,15 +26,22 @@ -// Pinmap for Bluepill I2Cs (by Testato) +// Example pinmap for Bluepill I2Cs (by Testato) // // I2C-1 standard pins: PB7(sda) PB6(scl) // Use it by "Wire" without pin declaration // // I2C-1 alternative pins: PB9(sda) PB8(scl) -// TwoWire Wire_alt(PB9,PB8); +// Remap the first I2C befoure call begin +// Wire.setSDA(PB9); +// Wire.setSCL(PB8); +// Wire.begin(); // -// I2C-2: PB9(sda) PB8(scl) +// I2C-2: PB11(sda) PB10(scl) +// Wire.setSDA(PB11); +// Wire.setSCL(PB10); +// +// If you want to use the two I2Cs simultaneously, create a new instance for the second I2C // TwoWire Wire2(PB11,PB10); From c7e96249ff13f6bb27ee8c65d99a6bfa81ccf065 Mon Sep 17 00:00:00 2001 From: Testato Date: Tue, 14 Aug 2018 16:01:07 +0200 Subject: [PATCH 034/109] Update i2c_scanner.ino --- libraries/Wire/examples/i2c_scanner/i2c_scanner.ino | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino index efcc07e48d..000c730cb8 100644 --- a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino +++ b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino @@ -32,7 +32,7 @@ // Use it by "Wire" without pin declaration // // I2C-1 alternative pins: PB9(sda) PB8(scl) -// Remap the first I2C befoure call begin +// Remap the first I2C before call begin() // Wire.setSDA(PB9); // Wire.setSCL(PB8); // Wire.begin(); From c431305544844c3483232a86c22509f9b629e089 Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Tue, 4 Sep 2018 09:39:08 +0200 Subject: [PATCH 035/109] I2C slave: Fix typos --- cores/arduino/stm32/twi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index 1e1a2047c3..82ab7df28d 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -555,7 +555,7 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) i2c_t *obj = get_i2c_obj(hi2c); /* Previous master transaction now ended, so inform upper layer if needed - * then prepare for listeing to next request */ + * then prepare for listening to next request */ if((obj->i2c_onSlaveReceive != NULL) && (obj->slaveMode == SLAVE_MODE_RECEIVE)) { if(obj->slaveRxNbData != 0) { @@ -598,7 +598,7 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { i2c_t *obj = get_i2c_obj(hi2c); - /* reset transmit buffer size */ + /* Reset transmit buffer size */ obj->i2cTxRxBufferSize = 0; } From 137ed6702935b6c43d027dcd49fa52dc101f8e6e Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Fri, 10 Aug 2018 10:15:47 +0200 Subject: [PATCH 036/109] Handle I2C scan with specific call to HAL_I2C_IsDeviceReady When size is 0, the objective is to check if device is there and ready. A typical use case is to scan through all addresses to check for available slaves. So we're checking the various error cases to report to application. --- cores/arduino/stm32/twi.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index ccd633fb40..c715f46808 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -355,6 +355,11 @@ i2c_status_e i2c_master_write(i2c_t *obj, uint8_t dev_address, uint32_t tickstart = HAL_GetTick(); uint32_t delta = 0; + /* When size is 0, this is usually an I2C scan / ping to check if device is there and ready */ + if (size == 0) { + return i2c_IsDeviceReady(obj, dev_address, 1); + } + do{ if(HAL_I2C_Master_Transmit_IT(&(obj->handle), dev_address, data, size) == HAL_OK){ ret = I2C_OK; @@ -447,8 +452,19 @@ i2c_status_e i2c_IsDeviceReady(i2c_t *obj, uint8_t devAddr, uint32_t trials) { i2c_status_e ret = HAL_OK; - if(HAL_I2C_IsDeviceReady( &(obj->handle), devAddr, trials, I2C_TIMEOUT_TICK) != HAL_OK) { - ret = I2C_BUSY; + switch (HAL_I2C_IsDeviceReady( &(obj->handle), devAddr, trials, I2C_TIMEOUT_TICK)) { + case HAL_OK: + ret = HAL_OK; + break; + case HAL_TIMEOUT: + ret = I2C_TIMEOUT; + break; + case HAL_BUSY: + ret = I2C_BUSY; + break; + default: + ret = I2C_TIMEOUT; + break; } return ret; From 69a2a52ac4d88725e62df34705154ff8b52a341b Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 4 Sep 2018 11:57:53 +0200 Subject: [PATCH 037/109] WString: add `toDouble` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `toFloat` internally converts into double and then truncates into a float, so why not add a method to return the double? Signed-off-by: Iván Pérez --- cores/arduino/WString.cpp | 7 ++++++- cores/arduino/WString.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/cores/arduino/WString.cpp b/cores/arduino/WString.cpp index 380a8e5033..6c341f89c5 100644 --- a/cores/arduino/WString.cpp +++ b/cores/arduino/WString.cpp @@ -742,6 +742,11 @@ long String::toInt(void) const float String::toFloat(void) const { - if (buffer) return float(atof(buffer)); + return float(toDouble()); +} + +double String::toDouble(void) const +{ + if (buffer) return atof(buffer); return 0; } diff --git a/cores/arduino/WString.h b/cores/arduino/WString.h index 5618c0c574..140e59656b 100644 --- a/cores/arduino/WString.h +++ b/cores/arduino/WString.h @@ -186,6 +186,7 @@ class String // parsing/conversion long toInt(void) const; float toFloat(void) const; + double toDouble(void) const; protected: char *buffer; // the actual char array From acbeffbbf7df9e3acb42daa74add999576ef2c07 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 4 Sep 2018 12:00:53 +0200 Subject: [PATCH 038/109] WString: Align with Arduino Add String iterators Signed-off-by: Frederic.Pillon --- cores/arduino/WString.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/WString.h b/cores/arduino/WString.h index 140e59656b..3dd590d129 100644 --- a/cores/arduino/WString.h +++ b/cores/arduino/WString.h @@ -161,6 +161,10 @@ class String void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const {getBytes((unsigned char *)buf, bufsize, index);} const char * c_str() const { return buffer; } + char* begin() { return buffer; } + char* end() { return buffer + length(); } + const char* begin() const { return c_str(); } + const char* end() const { return c_str() + length(); } // search int indexOf( char ch ) const; From 59f923dc10fcf8b3cc6794bf1a8b3c6222b01d2e Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 11 Sep 2018 17:34:59 +0200 Subject: [PATCH 039/109] [U(S)ART] Use RX/TX pins defined in the variant for specified peripheral Allow to use defined PIN_SERIALx_RX and PIN_SERIALx_TX in variant.h if user instanciate a hardware Serial using peripheral name. Example: HardwareSerial mySerial(USART3); will use PIN_SERIAL3_RX and PIN_SERIAL3_TX if defined. Signed-off-by: Frederic.Pillon --- cores/arduino/HardwareSerial.cpp | 100 ++++++++++++++++++++++++++++-- variants/board_template/variant.h | 9 +++ 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 83e998782a..2706ed05aa 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -166,12 +166,104 @@ HardwareSerial::HardwareSerial(void* peripheral) // If Serial is defined in variant set // the Rx/Tx pins for com port if defined #if defined(Serial) && defined(PIN_SERIAL_RX) && defined(PIN_SERIAL_TX) - if (this == &Serial) - { + if (this == &Serial) { setRx(PIN_SERIAL_RX); setTx(PIN_SERIAL_TX); - } - else + } else +#endif +#if defined(PIN_SERIAL1_RX) && defined(PIN_SERIAL1_TX) && defined(USART1_BASE) + if (peripheral == USART1) { + setRx(PIN_SERIAL1_RX); + setTx(PIN_SERIAL1_TX); + } else +#endif +#if defined(PIN_SERIAL2_RX) && defined(PIN_SERIAL2_TX) && defined(USART2_BASE) + if (peripheral == USART2) { + setRx(PIN_SERIAL2_RX); + setTx(PIN_SERIAL2_TX); + } else +#endif +#if defined(PIN_SERIAL3_RX) && defined(PIN_SERIAL3_TX) && defined(USART3_BASE) + if (peripheral == USART3) { + setRx(PIN_SERIAL3_RX); + setTx(PIN_SERIAL3_TX); + }else +#endif +#if defined(PIN_SERIAL4_RX) && defined(PIN_SERIAL4_TX) &&\ + (defined(USART4_BASE) || defined(UART4_BASE)) +#if defined(USART4_BASE) + if (peripheral == USART4) +#elif defined(UART4_BASE) + if (peripheral == UART4) +#endif + { + setRx(PIN_SERIAL4_RX); + setTx(PIN_SERIAL4_TX); + } else +#endif +#if defined(PIN_SERIAL5_RX) && defined(PIN_SERIAL5_TX) &&\ + (defined(USART5_BASE) || defined(UART5_BASE)) +#if defined(USART5_BASE) + if (peripheral == USART5) +#elif defined(UART5_BASE) + if (peripheral == UART5) +#endif + { + setRx(PIN_SERIAL5_RX); + setTx(PIN_SERIAL5_TX); + } else +#endif +#if defined(PIN_SERIAL6_RX) && defined(PIN_SERIAL6_TX) && defined(USART6_BASE) + if (peripheral == USART6) + { + setRx(PIN_SERIAL6_RX); + setTx(PIN_SERIAL6_TX); + } else +#endif +#if defined(PIN_SERIAL7_RX) && defined(PIN_SERIAL7_TX) &&\ + (defined(USART7_BASE) || defined(UART7_BASE)) +#if defined(USART7_BASE) + if (peripheral == USART7) +#elif defined(UART7_BASE) + if (peripheral == UART7) +#endif + { + setRx(PIN_SERIAL7_RX); + setTx(PIN_SERIAL7_TX); + } else +#endif +#if defined(PIN_SERIAL8_RX) && defined(PIN_SERIAL8_TX) &&\ + (defined(USART8_BASE) || defined(UART8_BASE)) +#if defined(USART8_BASE) + if (peripheral == USART8) +#elif defined(UART8_BASE) + if (peripheral == UART8) +#endif + { + setRx(PIN_SERIAL8_RX); + setTx(PIN_SERIAL8_TX); + } else +#endif +#if defined(PIN_SERIAL9_RX) && defined(PIN_SERIAL9_TX) && defined(UART9) + if (peripheral == UART9) + { + setRx(PIN_SERIAL9_RX); + setTx(PIN_SERIAL9_TX); + } else +#endif +#if defined(PIN_SERIAL10_RX) && defined(PIN_SERIAL10_TX) && defined(UART10) + if (peripheral == UART10) + { + setRx(PIN_SERIAL10_RX); + setTx(PIN_SERIAL10_TX); + } else +#endif +#if defined(PIN_SERIALLP1_RX) && defined(PIN_SERIALLP1_TX) && defined(LPUART1_BASE) + if (peripheral == LPUART1) + { + setRx(PIN_SERIALLP1_RX); + setTx(PIN_SERIALLP1_TX); + } else #endif // else get the pins of the first peripheral occurence in PinMap { diff --git a/variants/board_template/variant.h b/variants/board_template/variant.h index f2ef9cc409..da140889c4 100644 --- a/variants/board_template/variant.h +++ b/variants/board_template/variant.h @@ -135,6 +135,15 @@ enum { #define PIN_SERIAL_RX x #define PIN_SERIAL_TX x +// Optional PIN_SERIALn_RX and PIN_SERIALn_TX where 'n' is the U(S)ART number +// Used when user instanciate a hardware Serial using its peripheral name. +// Example: HardwareSerial mySerial(USART3); +// will use PIN_SERIAL3_RX and PIN_SERIAL3_TX if defined. +//#define PIN_SERIALn_RX x // For U(S)ARTn RX +//#define PIN_SERIALn_TX x // For U(S)ARTn TX +//#define PIN_SERIALLP1_RX x // For LPUART1 RX +//#define PIN_SERIALLP1_TX x // For LPUART1 TX + #ifdef __cplusplus } // extern "C" #endif From 3e4da5bb63a47834303d727ee5df8334265e4281 Mon Sep 17 00:00:00 2001 From: davidanger Date: Wed, 12 Sep 2018 12:05:30 +0200 Subject: [PATCH 040/109] Add NUCLEO F767ZI board Signed-off-by: davidanger --- boards.txt | 12 + variants/NUCLEO_F767ZI/PeripheralPins.c | 490 ++++++++++++++++++++ variants/NUCLEO_F767ZI/PinNamesVar.h | 25 + variants/NUCLEO_F767ZI/ldscript.ld | 165 +++++++ variants/NUCLEO_F767ZI/stm32f7xx_hal_conf.h | 459 ++++++++++++++++++ variants/NUCLEO_F767ZI/variant.cpp | 222 +++++++++ variants/NUCLEO_F767ZI/variant.h | 194 ++++++++ 7 files changed, 1567 insertions(+) create mode 100644 variants/NUCLEO_F767ZI/PeripheralPins.c create mode 100644 variants/NUCLEO_F767ZI/PinNamesVar.h create mode 100644 variants/NUCLEO_F767ZI/ldscript.ld create mode 100644 variants/NUCLEO_F767ZI/stm32f7xx_hal_conf.h create mode 100644 variants/NUCLEO_F767ZI/variant.cpp create mode 100644 variants/NUCLEO_F767ZI/variant.h diff --git a/boards.txt b/boards.txt index feb2709823..42ced4af32 100644 --- a/boards.txt +++ b/boards.txt @@ -49,6 +49,18 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant=NUCLEO_F429ZI Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.cmsis_lib_gcc=arm_cortexM4l_math +# NUCLEO_F767ZI board +Nucleo_144.menu.pnum.NUCLEO_F767ZI=Nucleo F767ZI +Nucleo_144.menu.pnum.NUCLEO_F767ZI.node=NODE_F767ZI +Nucleo_144.menu.pnum.NUCLEO_F767ZI.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_F767ZI.upload.maximum_data_size=524288 +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.mcu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.board=NUCLEO_F767ZI +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.series=STM32F7xx +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.product_line=STM32F767xx +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.variant=NUCLEO_F767ZI +Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.cmsis_lib_gcc=arm_cortexM7l_math + # NUCLEO_L496ZG board Nucleo_144.menu.pnum.NUCLEO_L496ZG=Nucleo L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG.node=NODE_L496ZG diff --git a/variants/NUCLEO_F767ZI/PeripheralPins.c b/variants/NUCLEO_F767ZI/PeripheralPins.c new file mode 100644 index 0000000000..27ab878b43 --- /dev/null +++ b/variants/NUCLEO_F767ZI/PeripheralPins.c @@ -0,0 +1,490 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32F767ZITx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { +// {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 - D32 + {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 - D32 +// {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 - D32 +// {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 +// {PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 +// {PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 +// {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 +// {PA_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 +// {PA_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0 +// {PA_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - A0 +// {PA_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 - A0 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - D24 +// {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - D24 +// {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - D13 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - D13 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - D12 +// {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - D12 +// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - D11(D71) + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - D11(D71) +// {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - D33 +// {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 - D33 +// {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - A6 + {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - A6 +// {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1 + {PC_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - A1 +// {PC_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 - A1 +// {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 +// {PC_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 +// {PC_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - A7 +// {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - A7 +// {PC_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 - A7 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2 +// {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - A2 +// {PC_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - A2 +// {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 +// {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 +// {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 +// {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PF_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 - A3 + {PF_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 - A8 + {PF_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 - A4 + {PF_6, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - A9 + {PF_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 - D62 + {PF_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 - D61 + {PF_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 - D63 + {PF_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 - A5 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { +// {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // D14 I2CA +// {PB_9, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C4)}, // D14 + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // D35 + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // D44 + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // D28 + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // D68 I2CB + {PF_15, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { +// {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // D26 +// {PB_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, // D26 + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // D15 I2CA +// {PB_8, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C4)}, // D15 + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // D36 + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // D29 + {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // D69 I2CB + {PF_14, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // D4 + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { +// {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - D32 + {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - D32 +// {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 +// {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - A0 +// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - A0 + {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - A0 +// {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - D13 + {PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - D13 +// {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - D12 + {PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - D12 +// {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - D11(D71) +// {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - D11(D71) +// {PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - D11(D71) + {PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - D11(D71) +// {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 +// {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - D20 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - D33 +// {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - D33 +// {PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N - D33 + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - A6 +// {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - A6 +// {PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - A6 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - D23 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - D25 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - D22 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - D26 +// {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - D15(A5) + {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - D15(A5) +// {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - D14(A4) + {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - D14(A4) + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - D36 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - D35 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - D18 +// {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 +// {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - D17 +// {PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - D17 + {PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 - D17 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - D16 +// {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 - D16 +// {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - D21 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - D21 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - D43 +// {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 - D43 +// {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - D44 + {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 - D44 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - D47 +// {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - D58 + {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - D59 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - D42 + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - D6 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N - D40 + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - D5 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - D39 + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - D3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - D38 +// {PF_6, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - D62 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - D61 + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 - D63 + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D32 +// {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, +// {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, // D20 + {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, // D25 +// {PB_6, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_UART5)}, // D26 + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // D26 + {PB_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // D14(A4) +// {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D36 + {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // D18 +// {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D16 + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D45 +// {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D45 + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // D47 + {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D66 + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // D53 USARTB_TX + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STLINK +// {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D42 + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D62 + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D1 USARTA_TX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { +// {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // A0 +// {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, +// {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, +// {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, // D23 + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_UART5)}, // D22(D11) +// {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // D15(A5) +// {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D35 + {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // D19 + {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // D17 + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D21 + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D46 +// {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D46 + {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D67 + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // D48 + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // D52 USARTB_RX + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STLINK + {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // D34 + {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D41 +// {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // D0 USARTA_RX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { +// {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D20 +// {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // D43 + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // D54 USARTB_RTS +// {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D29 + {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // D9 + {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D63 + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D61 +// {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, +// {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // D32 +// {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D33 +// {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D18 + {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // D17 + {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // D44 + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // D55 USARTB_CTS +// {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // D30 + {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // D10 + {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // A5 + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // D63 +// {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, +// {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D11(D71) SPI_A_MOSI +// {PA_7, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D11(D71) SPI_A_MOSI + {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, // D27 +// {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D22(D11) +// {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D22(D11) + {PB_5, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D22(D11) + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D17 +// {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // A2 + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D47 + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, // D52 + {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D51 + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D59 + {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D38 + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, // D63 +// {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_14, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, // D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D12 SPI_A_MISO +// {PA_6, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D12 SPI_A_MISO +// {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D25 SPI_B_MISO +// {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D25 SPI_B_MISO + {PB_4, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D25 SPI_B_MISO +// {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // A7 + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D46 + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D58 + {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D3 + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, // D61 + {PG_9, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D0 +// {PG_12, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D13 SPI_A_SCK +// {PA_5, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D13 SPI_A_SCK +// {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D23 SPI_B_SCK +// {PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D23 SPI_B_SCK + {PB_3, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D23 SPI_B_SCK + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D36 + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D18 + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D45 + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D55 + {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D31 & D56 + {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D39 + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, // D62 +// {PG_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PG_13, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D24 SPI_A_NSS +// {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D24 SPI_A_NSS +// {PA_4, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, // D24 SPI_A_NSS +// {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // D20 + {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // D20 + {PA_15, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, // D20 + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, // D25 + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D14(A4) + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // D19 + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D57 + {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, // D5 +// {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, +// {PG_8, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, +// {PG_10, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_RD[] = { +// {PA_8, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, +// {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_3, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // D23 + {PB_5, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // D22 (D11) + {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // D15 (A5) + {PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // D19 + {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // D67 CAN_RX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_TD[] = { +// {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_15, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // D20 + {PB_4, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, // D25 + {PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // D26 + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // D14 (A4) + {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // D18 + {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // D66 CAN_TX + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +const PinMap PinMap_Ethernet[] = { +// {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO +// {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV +// {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 +// {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 +// {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT +// {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 +// {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER +// {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN +// {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC +// {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 +// {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 +// {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 +// {PG_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 +// {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {NC, NP, 0} +}; +#endif + +//*** QUADSPI *** + +#ifdef HAL_QSPI_MODULE_ENABLED +const PinMap PinMap_QUADSPI[] = { +// {PA_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK - D27 QSPI_CLK + {PB_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS - D26 QSPI_CS + {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS - D36 + {PC_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 - D44 + {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - D45 + {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS - D46 + {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 - D30 QSPI_BK1_IO0 + {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - D29 QSPI_BK1_IO1 + {PD_13, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 - D28 QSPI_BK1_IO3 + {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - D32 QSPI_BK1_IO2 & D56 + {PE_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - D41 + {PE_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - D42 + {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - D6 + {PE_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 - D40 +// {PF_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - D62 + {PF_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 - D61 + {PF_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - D63 + {PF_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK - A5 + {PG_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 - D0 + {PG_14, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 - D1 + {NC, NP, 0} +}; +#endif diff --git a/variants/NUCLEO_F767ZI/PinNamesVar.h b/variants/NUCLEO_F767ZI/PinNamesVar.h new file mode 100644 index 0000000000..f1babffd8a --- /dev/null +++ b/variants/NUCLEO_F767ZI/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PI_8, /* manually updated */ +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PI_11, /* manually updated */ +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/NUCLEO_F767ZI/ldscript.ld b/variants/NUCLEO_F767ZI/ldscript.ld new file mode 100644 index 0000000000..8fab5559ec --- /dev/null +++ b/variants/NUCLEO_F767ZI/ldscript.ld @@ -0,0 +1,165 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F767ZITx Device with +** 2048KByte FLASH, 512KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20080000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text ALIGN(4): + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/NUCLEO_F767ZI/stm32f7xx_hal_conf.h b/variants/NUCLEO_F767ZI/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000..8e582bee68 --- /dev/null +++ b/variants/NUCLEO_F767ZI/stm32f7xx_hal_conf.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /* To enable prefetch */ +#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* LAN8742A PHY Address*/ +#define LAN8742A_PHY_ADDRESS 0x00U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x00000FFFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ + +#define PHY_ISFR ((uint16_t)0x01DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_IMR ((uint16_t)0x001E) /*!< PHY Interrupt Mask register Offset */ +#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_F767ZI/variant.cpp b/variants/NUCLEO_F767ZI/variant.cpp new file mode 100644 index 0000000000..fffabcaf7b --- /dev/null +++ b/variants/NUCLEO_F767ZI/variant.cpp @@ -0,0 +1,222 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +const PinName digitalPin[] = { + PG_9, //D0 + PG_14, //D1 + PF_15, //D2 + PE_13, //D3 + PF_14, //D4 + PE_11, //D5 + PE_9, //D6 + PF_13, //D7 + PF_12, //D8 + PD_15, //D9 + PD_14, //D10 + PA_7, //D11 + PA_6, //D12 + PA_5, //D13 + PB_9, //D14 + PB_8, //D15 + PC_6, //D16 + PB_15, //D17 + PB_13, //D18 + PB_12, //D19 + PA_15, //D20 + PC_7, //D21 + PB_5, //D22 + PB_3, //D23 + PA_4, //D24 + PB_4, //D25 + PB_6, //D26 + PB_2, //D27 + PD_13, //D28 + PD_12, //D29 + PD_11, //D30 + PE_2, //D31 + PA_0, //D32 + PB_0, //D33 - LED_GREEN + PE_0, //D34 + PB_11, //D35 + PB_10, //D36 + PE_15, //D37 + PE_14, //D38 + PE_12, //D39 + PE_10, //D40 + PE_7, //D41 + PE_8, //D42 + PC_8, //D43 + PC_9, //D44 + PC_10, //D45 + PC_11, //D46 + PC_12, //D47 + PD_2, //D48 + PG_2, //D49 + PG_3, //D50 + PD_7, //D51 + PD_6, //D52 + PD_5, //D53 + PD_4, //D54 + PD_3, //D55 + PE_2, //D56 + PE_4, //D57 + PE_5, //D58 + PE_6, //D59 + PE_3, //D60 + PF_8, //D61 + PF_7, //D62 + PF_9, //D63 + PG_1, //D64 + PG_0, //D65 + PD_1, //D66 + PD_0, //D67 + PF_0, //D68 + PF_1, //D69 + PF_2, //D70 + PA_7, //D71 + NC, //D72 + PB_7, //D73 - LED_BLUE + PB_14, //D74 - LED_RED + PC_13, //D75 - USER_BTN + PD_9, //D76 - Serial Rx + PD_8, //D77 - Serial Tx + PA_3, //D78/A0 + PC_0, //D79/A1 + PC_3, //D80/A2 + PF_3, //D81/A3 + PF_5, //D82/A4 + PF_10, //D83/A5 + PB_1, //D84/A6 + PC_2, //D85/A7 + PF_4, //D86/A8 + PF_6, //D87/A9 + // Duplicated pins in order to be aligned with PinMap_ADC + PA_7, //D88/A10 = D11 + PA_6, //D89/A11 = D12 + PA_5, //D90/A12 = D13 + PA_4, //D91/A13 = D24 + PA_0, //D92/A14 = D32 + PF_8, //D93/A15 = D61 + PF_7, //D94/A16 = D62 + PF_9 //D95/A17 = D63 +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSI) + * SYSCLK(Hz) = 216000000 + * HCLK(Hz) = 216000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 16000000 + * PLL_M = 8 + * PLL_N = 216 + * PLL_P = 2 + * PLL_Q = 9 + * PLLSAI_N = 192 + * PLLSAI_P = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 7 + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /* Activate the Over-Drive mode */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /* Configure the Systick interrupt time */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /* Configure the Systick */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/NUCLEO_F767ZI/variant.h b/variants/NUCLEO_F767ZI/variant.h new file mode 100644 index 0000000000..e5537dce51 --- /dev/null +++ b/variants/NUCLEO_F767ZI/variant.h @@ -0,0 +1,194 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +enum { + PG9, //D0 + PG14, //D1 + PF15, //D2 + PE13, //D3 + PF14, //D4 + PE11, //D5 + PE9, //D6 + PF13, //D7 + PF12, //D8 + PD15, //D9 + PD14, //D10 + PA7, //D11 + PA6, //D12 + PA5, //D13 + PB9, //D14 + PB8, //D15 + PC6, //D16 + PB15, //D17 + PB13, //D18 + PB12, //D19 + PA15, //D20 + PC7, //D21 + PB5, //D22 + PB3, //D23 + PA4, //D24 + PB4, //D25 + PB6, //D26 + PB2, //D27 + PD13, //D28 + PD12, //D29 + PD11, //D30 + PE2, //D31 + PA0, //D32 + PB0, //D33 - LED_GREEN + PE0, //D34 + PB11, //D35 + PB10, //D36 + PE15, //D37 + PE14, //D38 + PE12, //D39 + PE10, //D40 + PE7, //D41 + PE8, //D42 + PC8, //D43 + PC9, //D44 + PC10, //D45 + PC11, //D46 + PC12, //D47 + PD2, //D48 + PG2, //D49 + PG3, //D50 + PD7, //D51 + PD6, //D52 + PD5, //D53 + PD4, //D54 + PD3, //D55 + PE2_2,//D56 + PE4, //D57 + PE5, //D58 + PE6, //D59 + PE3, //D60 + PF8, //D61 + PF7, //D62 + PF9, //D63 + PG1, //D64 + PG0, //D65 + PD1, //D66 + PD0, //D67 + PF0, //D68 + PF1, //D69 + PF2, //D70 + PA7_2,//D71 + NC_1, //D72 + PB7, //D73 - LED_BLUE + PB14, //D74 - LED_RED + PC13, //D75 - USER_BTN + PD9, //D76 - Serial Rx + PD8, //D77 - Serial Tx + PA3, //D78/A0 + PC0, //D79/A1 + PC3, //D80/A2 + PF3, //D81/A3 + PF5, //D82/A4 + PF10, //D83/A5 + PB1, //D84/A6 + PC2, //D85/A7 + PF4, //D86/A8 + PF6, //D87/A9 + // Duplicated pins in order to be aligned with PinMap_ADC + PA7_3, //D88/A10 = D11 + PA6_2, //D89/A11 = D12 + PA5_2, //D90/A12 = D13 + PA4_2, //D91/A13 = D24 + PA0_2, //D92/A14 = D32 + PF8_2, //D93/A15 = D61 + PF7_2, //D94/A16 = D62 + PF9_2, //D95/A17 = D63 + PEND +}; + +// This must be a literal with the same value as PEND +#define NUM_DIGITAL_PINS 96 +// This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 18 +#define NUM_ANALOG_FIRST 78 + +// On-board LED pin number +#define LED_BUILTIN PB0 +#define LED_GREEN LED_BUILTIN +#define LED_BLUE PB7 +#define LED_RED PB14 + +// On-board user button +#define USER_BTN PC13 + +// Timer Definitions +// Do not use timer used by PWM pins when possible. See PinMap_PWM. +#define TIMER_TONE TIM6 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work + +// UART Definitions +#define SERIAL_UART_INSTANCE 3 //Connected to ST-Link + +// Serial pin used for console (ex: stlink) +// Rerquired by Firmata +#define PIN_SERIAL_RX PD9 +#define PIN_SERIAL_TX PD8 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From c5563f3448e856d535accfcfd3cf78687bc02d5e Mon Sep 17 00:00:00 2001 From: Nils Hasenbanck Date: Fri, 14 Sep 2018 15:19:22 +0200 Subject: [PATCH 041/109] Add RemRam v1 board variant (#287) Add RemRam v1 board variant RemRam is an open-source 3D printing controller. It's source files can be found at [1]. [1] https://github.com/hasenbanck/remram Signed-off-by: Nils Hasenbanck --- boards.txt | 71 ++++ variants/REMRAM_V1/PeripheralPins.c | 424 +++++++++++++++++++ variants/REMRAM_V1/PinNamesVar.h | 25 ++ variants/REMRAM_V1/ldscript.ld | 167 ++++++++ variants/REMRAM_V1/stm32f7xx_hal_conf.h | 450 ++++++++++++++++++++ variants/REMRAM_V1/usb/usbd_conf.c | 537 ++++++++++++++++++++++++ variants/REMRAM_V1/usb/usbd_conf.h | 107 +++++ variants/REMRAM_V1/usb/usbd_desc.c | 315 ++++++++++++++ variants/REMRAM_V1/usb/usbd_desc.h | 67 +++ variants/REMRAM_V1/variant.cpp | 238 +++++++++++ variants/REMRAM_V1/variant.h | 194 +++++++++ 11 files changed, 2595 insertions(+) create mode 100644 variants/REMRAM_V1/PeripheralPins.c create mode 100644 variants/REMRAM_V1/PinNamesVar.h create mode 100644 variants/REMRAM_V1/ldscript.ld create mode 100644 variants/REMRAM_V1/stm32f7xx_hal_conf.h create mode 100644 variants/REMRAM_V1/usb/usbd_conf.c create mode 100644 variants/REMRAM_V1/usb/usbd_conf.h create mode 100644 variants/REMRAM_V1/usb/usbd_desc.c create mode 100644 variants/REMRAM_V1/usb/usbd_desc.h create mode 100644 variants/REMRAM_V1/variant.cpp create mode 100644 variants/REMRAM_V1/variant.h diff --git a/boards.txt b/boards.txt index 42ced4af32..68482c0456 100644 --- a/boards.txt +++ b/boards.txt @@ -529,6 +529,45 @@ Maple.menu.upload_method.serialMethod=Serial Maple.menu.upload_method.serialMethod.upload.protocol=maple_serial Maple.menu.upload_method.serialMethod.upload.tool=serial_upload +############################### +# RemRam + +RemRam.name=RemRam series + +RemRam.build.vid=0x0483 +RemRam.build.pid=0x5711 +RemRam.vid.0=0x0483 +RemRam.pid.0=0x5711 + +RemRam.build.core=arduino +RemRam.build.board=RemRam +RemRam.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} + +# REMRAM_V1 board +# Support: Serial1 (USART1 on PA10, PA9) +RemRam.menu.pnum.REMRAM_V1=RemRam v1 +RemRam.menu.pnum.REMRAM_V1.upload.maximum_size=2097152 +RemRam.menu.pnum.REMRAM_V1.upload.maximum_data_size=524288 +RemRam.menu.pnum.REMRAM_V1.build.mcu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +RemRam.menu.pnum.REMRAM_V1.build.board=REMRAM_V1 +RemRam.menu.pnum.REMRAM_V1.build.series=STM32F7xx +RemRam.menu.pnum.REMRAM_V1.build.product_line=STM32F765xx +RemRam.menu.pnum.REMRAM_V1.build.variant=REMRAM_V1 +RemRam.menu.pnum.REMRAM_V1.build.cmsis_lib_gcc=arm_cortexM7l_math + +# Virtual COM port +#RemRam.menu.usb.none=None +#RemRam.menu.usb.CDC=CDC +#RemRam.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DUSE_USB_FS + +# Upload menu +RemRam.menu.upload_method.STLinkMethod=STLink +RemRam.menu.upload_method.STLinkMethod.upload.protocol=STLink +RemRam.menu.upload_method.STLinkMethod.upload.tool=stlink_upload + +RemRam.menu.upload_method.serialMethod=Serial +RemRam.menu.upload_method.serialMethod.upload.protocol=maple_serial +RemRam.menu.upload_method.serialMethod.upload.tool=serial_upload ################################################################################ # Serialx activation @@ -568,6 +607,12 @@ Maple.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE Maple.menu.xserial.disabled=Disabled (No Serial) Maple.menu.xserial.disabled.build.xSerial= +RemRam.menu.xserial.generic=Enabled with generic Serial +RemRam.menu.xserial.none=Enabled without generic Serial +RemRam.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +RemRam.menu.xserial.disabled=Disabled (No Serial) +RemRam.menu.xserial.disabled.build.xSerial= + # USB connectivity Nucleo_144.menu.usb.none=None Nucleo_144.menu.usb.HID=HID keyboard and mouse support (if available) @@ -749,3 +794,29 @@ Maple.menu.opt.o3lto.build.flags.ldspecs=-flto Maple.menu.opt.ogstd=Debug (-g) Maple.menu.opt.ogstd.build.flags.optimize=-g -Og Maple.menu.opt.ogstd.build.flags.ldspecs= + +RemRam.menu.opt.osstd=Smallest (-Os default) +RemRam.menu.opt.oslto=Smallest (-Os) with LTO +RemRam.menu.opt.oslto.build.flags.optimize=-Os -flto +RemRam.menu.opt.oslto.build.flags.ldspecs=-flto +RemRam.menu.opt.o1std=Fast (-O1) +RemRam.menu.opt.o1std.build.flags.optimize=-O1 +RemRam.menu.opt.o1std.build.flags.ldspecs= +RemRam.menu.opt.o1lto=Fast (-O1) with LTO +RemRam.menu.opt.o1lto.build.flags.optimize=-O1 -flto +RemRam.menu.opt.o1lto.build.flags.ldspecs=-flto +RemRam.menu.opt.o2std=Faster (-O2) +RemRam.menu.opt.o2std.build.flags.optimize=-O2 +RemRam.menu.opt.o2std.build.flags.ldspecs= +RemRam.menu.opt.o2lto=Faster (-O2) with LTO +RemRam.menu.opt.o2lto.build.flags.optimize=-O2 -flto +RemRam.menu.opt.o2lto.build.flags.ldspecs=-flto +RemRam.menu.opt.o3std=Fastest (-O3) +RemRam.menu.opt.o3std.build.flags.optimize=-O3 +RemRam.menu.opt.o3std.build.flags.ldspecs= +RemRam.menu.opt.o3lto=Fastest (-O3) with LTO +RemRam.menu.opt.o3lto.build.flags.optimize=-O3 -flto +RemRam.menu.opt.o3lto.build.flags.ldspecs=-flto +RemRam.menu.opt.ogstd=Debug (-g) +RemRam.menu.opt.ogstd.build.flags.optimize=-g -Og +RemRam.menu.opt.ogstd.build.flags.ldspecs= \ No newline at end of file diff --git a/variants/REMRAM_V1/PeripheralPins.c b/variants/REMRAM_V1/PeripheralPins.c new file mode 100644 index 0000000000..2c1d4a84de --- /dev/null +++ b/variants/REMRAM_V1/PeripheralPins.c @@ -0,0 +1,424 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32F765V(G-I)Tx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { + // {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + // {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 + // {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 + // {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + // {PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + // {PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + // {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + // {PA_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + // {PA_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + // {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + // {PA_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + // {PA_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + // {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + // {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + // {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + // {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + // {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + // {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + // {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + // {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + // {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + // {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + // {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + // {PC_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + // {PC_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + // {PC_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + // {PC_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + // {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + // {PC_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + // {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + // {PC_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 + // {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + // {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + // {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + // {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {NC, NP, 0}}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + // {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + // {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0}}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_7, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, + // {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_9, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C4)}, + // {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + // {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { + // {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_6, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, + // {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + // {PB_8, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C4)}, + // {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + // {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0}}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + // {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + // {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + // {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + // {PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + // {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + // {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + // {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + // {PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + // {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + // {PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + // {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + // {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + // {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + // {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + // {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + // {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + // {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + // {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + // {PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + // {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + // {PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + // {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + // {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + // {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + // {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + // {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + // {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + // {PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + // {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + // {PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + // {PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + // {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + // {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + // {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + // {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + // {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + // {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + // {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + // {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + // {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + // {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + // {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + // {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + // {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + // {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + // {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + // {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + // {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + // {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + // {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0}}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + // {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PA_12, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + // {PA_15, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, + // {PB_4, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, + // {PB_6, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_UART5)}, + // {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PB_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + // {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PB_13, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + // {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + // {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + // {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + // {PD_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { + // {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PA_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PA_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + // {PB_3, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_UART7)}, + // {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_UART5)}, + // {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PB_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + // {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PB_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + // {PB_15, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + // {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + // {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + // {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + // {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + // {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + // {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PB_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + // {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + // {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + // {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + // {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {NC, NP, 0}}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_7, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + // {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PB_5, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + // {PD_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_6, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PB_4, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_5, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PA_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PB_3, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + // {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PA_4, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_SPI6)}, + // {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + // {PA_15, SPI6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI6)}, + // {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI2)}, + // {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + // {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + // {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NP, 0}}; +#endif + +//*** CAN *** + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_RD[] = { + // {PA_8, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + // {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + // {PB_3, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + // {PB_5, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + // {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + // {PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + // {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0}}; +#endif + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_TD[] = { + // {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + // {PA_15, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + // {PB_4, CAN3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + // {PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + // {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + // {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + // {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0}}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +const PinMap PinMap_Ethernet[] = { + // {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + // {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK + // {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + // {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + // {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV + // {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + // {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + // {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + // {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + // {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + // {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + // {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + // {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + // {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + // {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + // {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + // {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + // {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + // {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {NC, NP, 0}}; +#endif + +//*** QUADSPI *** + +#ifdef HAL_QSPI_MODULE_ENABLED +const PinMap PinMap_QUADSPI[] = { + // {PA_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + // {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + // {PB_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + // {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + // {PC_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + // {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + // {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS + // {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + // {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + // {PD_13, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + // {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + // {PE_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 + // {PE_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 + // {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 + // {PE_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 + {NC, NP, 0}}; +#endif diff --git a/variants/REMRAM_V1/PinNamesVar.h b/variants/REMRAM_V1/PinNamesVar.h new file mode 100644 index 0000000000..6e0a8212ae --- /dev/null +++ b/variants/REMRAM_V1/PinNamesVar.h @@ -0,0 +1,25 @@ +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PC_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PI_8, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PI_11, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/REMRAM_V1/ldscript.ld b/variants/REMRAM_V1/ldscript.ld new file mode 100644 index 0000000000..48fcdf9add --- /dev/null +++ b/variants/REMRAM_V1/ldscript.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F765VITx Device with +** 2048KByte FLASH, 512KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20080000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/REMRAM_V1/stm32f7xx_hal_conf.h b/variants/REMRAM_V1/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000..095f069a4f --- /dev/null +++ b/variants/REMRAM_V1/stm32f7xx_hal_conf.h @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)24000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/REMRAM_V1/usb/usbd_conf.c b/variants/REMRAM_V1/usb/usbd_conf.c new file mode 100644 index 0000000000..d4c9e69281 --- /dev/null +++ b/variants/REMRAM_V1/usb/usbd_conf.c @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file USB_Device/HID_Standalone/Src/usbd_conf.c + * @author MCD Application Team + * @version V1.0.2 + * @date 06-May-2016 + * @brief This file implements the USB Device library callbacks and MSP + ****************************************************************************** + * @attention + * + *

          © Copyright � 2016 STMicroelectronics International N.V. + * All rights reserved.

          + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#ifdef USBCON + +#include "usbd_conf.h" +#include "usbd_core.h" +#include "hw_config.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +PCD_HandleTypeDef g_hpcd; + +/* Private function prototypes -----------------------------------------------*/ +//static void SystemClockConfig_STOP(void); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* + PCD BSP Routines +*******************************************************************************/ + +/** + * @brief Initializes the PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Configure USB FS GPIOs */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /* Configure DM DP Pins */ + GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Enable USB FS Clocks */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* Set USBFS Interrupt priority */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0); + + /* Enable USBFS Interrupt */ + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + + if(hpcd->Init.low_power_enable == 1) + { + /* Enable EXTI Line 18 for USB wakeup*/ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); + __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE(); + __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT(); + + /* Set EXTI Wakeup Interrupt priority*/ + HAL_NVIC_SetPriority(OTG_FS_WKUP_IRQn, 0, 0); + + /* Enable EXTI Interrupt */ + HAL_NVIC_EnableIRQ(OTG_FS_WKUP_IRQn); + } +} + +/** + * @brief De-Initializes the PCD MSP. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Disable USB FS Clock */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + __HAL_RCC_SYSCFG_CLK_DISABLE(); +} + +/******************************************************************************* + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ + +/** + * @brief SetupStage callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SetupStage(hpcd->pData, (uint8_t *)hpcd->Setup); +} + +/** + * @brief DataOut Stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataOutStage(hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); +} + +/** + * @brief DataIn Stage callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_DataInStage(hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); +} + +/** + * @brief SOF callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_SOF(hpcd->pData); +} + +/** + * @brief Reset callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + + /* Set USB Current Speed */ + switch(hpcd->Init.speed) + { + case PCD_SPEED_HIGH: + speed = USBD_SPEED_HIGH; + break; + + case PCD_SPEED_FULL: + speed = USBD_SPEED_FULL; + break; + + default: + speed = USBD_SPEED_FULL; + break; + } + + /* Reset Device */ + USBD_LL_Reset(hpcd->pData); + + USBD_LL_SetSpeed(hpcd->pData, speed); +} + +/** + * @brief Suspend callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + __HAL_PCD_GATE_PHYCLOCK(hpcd); + USBD_LL_Suspend(hpcd->pData); + + /*Enter in STOP mode */ + if (hpcd->Init.low_power_enable) + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + } +} + +/** + * @brief Resume callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_Resume(hpcd->pData); +} + +/** + * @brief ISOOUTIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoOUTIncomplete(hpcd->pData, epnum); +} + +/** + * @brief ISOINIncomplete callback. + * @param hpcd: PCD handle + * @param epnum: Endpoint Number + * @retval None + */ +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + USBD_LL_IsoINIncomplete(hpcd->pData, epnum); +} + +/** + * @brief ConnectCallback callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevConnected(hpcd->pData); +} + +/** + * @brief Disconnect callback. + * @param hpcd: PCD handle + * @retval None + */ +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + USBD_LL_DevDisconnected(hpcd->pData); +} + + + +/** + * @brief This function handles USB-On-The-Go FS global interrupt request. + * @param None + * @retval None + */ +void OTG_FS_IRQHandler(void) +{ + HAL_PCD_IRQHandler(&g_hpcd); +} + +/** + * @brief This function handles USB OTG FS Wakeup IRQ Handler. + * @param None + * @retval None + */ + +void OTG_FS_WKUP_IRQHandler(void) +{ + if((&g_hpcd)->Init.low_power_enable) + { + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + + /* Configures system clock after wake-up from STOP: enable HSE, PLL and select + PLL as system clock source (HSE and PLL are disabled in STOP mode) */ + SystemClock_Config(); + + /* ungate PHY clock */ + __HAL_PCD_UNGATE_PHYCLOCK((&g_hpcd)); + } + + /* Clear EXTI pending Bit*/ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); +} + +/******************************************************************************* + LL Driver Interface (USB Device Library --> PCD) +*******************************************************************************/ + +/** + * @brief Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + /* Set LL Driver parameters */ + g_hpcd.Instance = USB_OTG_FS; + g_hpcd.Init.dev_endpoints = 4; + g_hpcd.Init.use_dedicated_ep1 = 0; + g_hpcd.Init.ep0_mps = 0x40; + g_hpcd.Init.dma_enable = 0; + g_hpcd.Init.low_power_enable = 0; + g_hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; + g_hpcd.Init.Sof_enable = 0; + g_hpcd.Init.speed = PCD_SPEED_FULL; + g_hpcd.Init.vbus_sensing_enable = 0; + g_hpcd.Init.lpm_enable = 0; + /* Link The driver to the stack */ + g_hpcd.pData = pdev; + pdev->pData = &g_hpcd; + + /* Initialize LL Driver */ + HAL_PCD_Init(&g_hpcd); + + HAL_PCDEx_SetRxFiFo(&g_hpcd, 0x80); + HAL_PCDEx_SetTxFiFo(&g_hpcd, 0, 0x40); + HAL_PCDEx_SetTxFiFo(&g_hpcd, 1, 0x10); + HAL_PCDEx_SetTxFiFo(&g_hpcd, 2, 0x10); + + return USBD_OK; +} + +/** + * @brief De-Initializes the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) +{ + HAL_PCD_DeInit(pdev->pData); + return USBD_OK; +} + +/** + * @brief Starts the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + HAL_PCD_Start(pdev->pData); + return USBD_OK; +} + +/** + * @brief Stops the Low Level portion of the Device driver. + * @param pdev: Device handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) +{ + HAL_PCD_Stop(pdev->pData); + return USBD_OK; +} + +/** + * @brief Opens an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param ep_type: Endpoint Type + * @param ep_mps: Endpoint Max Packet Size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps) +{ + HAL_PCD_EP_Open(pdev->pData, + ep_addr, + ep_mps, + ep_type); + + return USBD_OK; +} + +/** + * @brief Closes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_PCD_EP_Close(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Flushes an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_PCD_EP_Flush(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + return USBD_OK; +} + +/** + * @brief Returns Stall condition. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + PCD_HandleTypeDef *hpcd = pdev->pData; + + if((ep_addr & 0x80) == 0x80) + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + } +} + +/** + * @brief Assigns a USB address to the device. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + HAL_PCD_SetAddress(pdev->pData, dev_addr); + return USBD_OK; +} + +/** + * @brief Transmits data over an endpoint. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + return USBD_OK; +} + +/** + * @brief Prepares an endpoint for reception. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size) +{ + HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + return USBD_OK; +} + +/** + * @brief Returns the last transferred packet size. + * @param pdev: Device handle + * @param ep_addr: Endpoint Number + * @retval Received Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr); +} + +/** + * @brief Delays routine for the USB Device Library. + * @param Delay: Delay in ms + * @retval None + */ +void USBD_LL_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +#endif // USBCON +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/REMRAM_V1/usb/usbd_conf.h b/variants/REMRAM_V1/usb/usbd_conf.h new file mode 100644 index 0000000000..cda1a9588e --- /dev/null +++ b/variants/REMRAM_V1/usb/usbd_conf.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file USB_Device/HID_Standalone/Inc/usbd_conf.h + * @author MCD Application Team + * @version V1.0.2 + * @date 06-May-2016 + * @brief General low level driver configuration + ****************************************************************************** + * @attention + * + *

          © Copyright © 2016 STMicroelectronics International N.V. + * All rights reserved.

          + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF_H +#define __USBD_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_def.h" +#include +#include +#include +#ifdef USBCON +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +#define USBD_LPM_ENABLED 0 + +/* Common Config */ +#define USBD_MAX_NUM_INTERFACES 1 +#define USBD_MAX_NUM_CONFIGURATION 1 +#define USBD_MAX_STR_DESC_SIZ 0x100 +#define USBD_SUPPORT_USER_STRING 0 +#define USBD_SELF_POWERED 1 +#define USBD_DEBUG_LEVEL 3 + +/* Exported macro ------------------------------------------------------------*/ +/* Memory management macros */ +#define USBD_malloc malloc +#define USBD_free free +#define USBD_memset memset +#define USBD_memcpy memcpy + +/* DEBUG macros */ +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n\r"); +#else +#define USBD_UsrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n\r"); +#else +#define USBD_ErrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n\r"); +#else +#define USBD_DbgLog(...) +#endif + +/* Exported functions ------------------------------------------------------- */ + +#endif // USBCON +#endif /* __USBD_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/REMRAM_V1/usb/usbd_desc.c b/variants/REMRAM_V1/usb/usbd_desc.c new file mode 100644 index 0000000000..27f8df5e35 --- /dev/null +++ b/variants/REMRAM_V1/usb/usbd_desc.c @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file USB_Device/HID_Standalone/Src/usbd_desc.c + * @author MCD Application Team + * @version V1.0.2 + * @date 06-May-2016 + * @brief This file provides the USBD descriptors and string formatting method. + ****************************************************************************** + * @attention + * + *

          © Copyright � 2016 STMicroelectronics International N.V. + * All rights reserved.

          + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#ifdef USBCON +#include "usbd_core.h" +#include "usbd_desc.h" +#include "usbd_conf.h" +#include "utils.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +//ID +#define USBD_LANGID_STRING 0x409 //1033 +#if USBD_VID == 0x2341 +#define USBD_MANUFACTURER_STRING "Arduino LLC" +#elif USBD_VID == 0x2A03 +#define USBD_MANUFACTURER_STRING "Arduino srl" +#elif USBD_VID == 0x0483 +#define USBD_MANUFACTURER_STRING "STMicroelectronics" +#elif !defined(USB_MANUFACTURER) +// Fall through to unknown if no manufacturer name was provided in a macro +#define USBD_MANUFACTURER_STRING "Unknown" +#else +#define USBD_MANUFACTURER_STRING USB_MANUFACTURER +#endif +#ifdef USBD_USE_HID_COMPOSITE +#define USBD_HID_PRODUCT_HS_STRING CONCATS(USB_PRODUCT, "HID in HS Mode") +#define USBD_HID_PRODUCT_FS_STRING CONCATS(USB_PRODUCT, "HID in FS Mode") +#define USBD_HID_CONFIGURATION_HS_STRING CONCATS(USB_PRODUCT, "HID Config") +#define USBD_HID_INTERFACE_HS_STRING CONCATS(USB_PRODUCT, "HID Interface") +#define USBD_HID_CONFIGURATION_FS_STRING CONCATS(USB_PRODUCT, "HID Config") +#define USBD_HID_INTERFACE_FS_STRING CONCATS(USB_PRODUCT, "HID Interface") + +/* Private macro -------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t *USBD_HID_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_ManufacturerStrDescriptor (USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_ProductStrDescriptor (USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +static uint8_t *USBD_HID_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +#ifdef USB_SUPPORT_USER_STRING_DESC +static uint8_t *USBD_HID_USRStringDesc (USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USB_SUPPORT_USER_STRING_DESC */ + +/* Private variables ---------------------------------------------------------*/ +USBD_DescriptorsTypeDef HID_Desc = { + USBD_HID_DeviceDescriptor, + USBD_HID_LangIDStrDescriptor, + USBD_HID_ManufacturerStrDescriptor, + USBD_HID_ProductStrDescriptor, + USBD_HID_SerialStrDescriptor, + USBD_HID_ConfigStrDescriptor, + USBD_HID_InterfaceStrDescriptor, +}; +#endif //USBD_USE_HID_COMPOSITE + +/* USB Standard Device Descriptor */ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { + 0x12, /* bLength */ + USB_DESC_TYPE_DEVICE, /* bDescriptorType */ + 0x00, /* bcdUSB */ + 0x02, + 0x00, /* bDeviceClass */ + 0x00, /* bDeviceSubClass */ + 0x00, /* bDeviceProtocol */ + USB_MAX_EP0_SIZE, /* bMaxPacketSize */ + LOBYTE(USBD_VID), /* idVendor */ + HIBYTE(USBD_VID), /* idVendor */ + LOBYTE(USBD_PID), /* idVendor */ + HIBYTE(USBD_PID), /* idVendor */ + 0x00, /* bcdDevice rel. 2.00 */ + 0x02, + USBD_IDX_MFC_STR, /* Index of manufacturer string */ + USBD_IDX_PRODUCT_STR, /* Index of product string */ + USBD_IDX_SERIAL_STR, /* Index of serial number string */ + USBD_MAX_NUM_CONFIGURATION /* bNumConfigurations */ +}; /* USB_DeviceDescriptor */ + +/* USB Standard Device Descriptor */ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, + LOBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING), +}; + +static uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] = +{ + USB_SIZ_STRING_SERIAL, + USB_DESC_TYPE_STRING, +}; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; + +/* Private functions ---------------------------------------------------------*/ +static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len); +static void Get_SerialNum(void); + +#ifdef USBD_USE_HID_COMPOSITE +/** + * @brief Returns the device descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + *length = sizeof(USBD_DeviceDesc); + return (uint8_t*)USBD_DeviceDesc; +} + +/** + * @brief Returns the LangID string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + *length = sizeof(USBD_LangIDDesc); + return (uint8_t*)USBD_LangIDDesc; +} + +/** + * @brief Returns the product string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_HID_PRODUCT_HS_STRING, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_HID_PRODUCT_FS_STRING, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** + * @brief Returns the manufacturer string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + return USBD_StrDesc; +} + +/** + * @brief Returns the serial number string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + *length = USB_SIZ_STRING_SERIAL; + + /* Update the serial number string descriptor with the data from the unique ID*/ + Get_SerialNum(); + + return (uint8_t*)USBD_StringSerial; +} + +/** + * @brief Returns the configuration string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_HID_CONFIGURATION_HS_STRING, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_HID_CONFIGURATION_FS_STRING, USBD_StrDesc, length); + } + return USBD_StrDesc; +} + +/** + * @brief Returns the interface string descriptor. + * @param speed: Current device speed + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_HID_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + if(speed == USBD_SPEED_HIGH) + { + USBD_GetString((uint8_t *)USBD_HID_INTERFACE_HS_STRING, USBD_StrDesc, length); + } + else + { + USBD_GetString((uint8_t *)USBD_HID_INTERFACE_FS_STRING, USBD_StrDesc, length); + } + return USBD_StrDesc; +} +#endif //USBD_USE_HID_COMPOSITE +/** + * @brief Create the serial number string descriptor + * @param None + * @retval None + */ +static void Get_SerialNum(void) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode (deviceserial0, (uint8_t*)&USBD_StringSerial[2] ,8); + IntToUnicode (deviceserial1, (uint8_t*)&USBD_StringSerial[18] ,4); + } +} + +/** + * @brief Convert Hex 32Bits value into char + * @param value: value to convert + * @param pbuf: pointer to the buffer + * @param len: buffer length + * @retval None + */ +static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0 ; idx < len ; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} +#endif // USBCON +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/REMRAM_V1/usb/usbd_desc.h b/variants/REMRAM_V1/usb/usbd_desc.h new file mode 100644 index 0000000000..455fcf1a4d --- /dev/null +++ b/variants/REMRAM_V1/usb/usbd_desc.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file USB_Device/HID_Standalone/Inc/usbd_desc.h + * @author MCD Application Team + * @version V1.0.2 + * @date 06-May-2016 + * @brief Header for usbd_desc.c module + ****************************************************************************** + * @attention + * + *

          © Copyright © 2016 STMicroelectronics International N.V. + * All rights reserved.

          + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted, provided that the following conditions are met: + * + * 1. Redistribution of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of other + * contributors to this software may be used to endorse or promote products + * derived from this software without specific written permission. + * 4. This software, including modifications and/or derivative works of this + * software, must execute solely and exclusively on microcontroller or + * microprocessor devices manufactured by or for STMicroelectronics. + * 5. Redistribution and use of this software other than as permitted under + * this license is void and will automatically terminate your rights under + * this license. + * + * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY + * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT + * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC_H +#define __USBD_DESC_H +#ifdef USBCON +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +#define USB_SIZ_STRING_SERIAL 0x1A +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +extern USBD_DescriptorsTypeDef HID_Desc; +#endif // USBCON +#endif /* __USBD_DESC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/REMRAM_V1/variant.cpp b/variants/REMRAM_V1/variant.cpp new file mode 100644 index 0000000000..1debb48b81 --- /dev/null +++ b/variants/REMRAM_V1/variant.cpp @@ -0,0 +1,238 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + // Pin number + // This array allows to wrap Arduino pin number(Dx or x) + // to STM32 PinName (PX_n) + const PinName digitalPin[] = { + // USART + PA_10, // D0 - RX + PA_9, // D1 - TX + + // SWD + PA_14, // D2 - SWCLK + PA_13, // D3 - SWDIO + + // EXT3 + PE_5, // D4 - EXT_D1 + PE_4, // D5 - EXT_D2 + PE_3, // D6 - EXT_D3 + PE_2, // D7 - EXT_D4 + PE_1, // D8 - EXT_D5 + + // SPI + PB_2, // D9 - SS_SD + PC_4, // D10 - SS_E + PA_7, // D11 - MOSI + PA_6, // D12 - MISO + PA_5, // D13 - SCK + PB_1, // D14 - SS_X + PB_0, // D15 - SS_Y + PC_5, // D16 - SS_Z + + // I2C + PB_6, // D17 - SCL + PB_7, // D18 - SDA + + // USB + PA_12, // D19 - DD+ + PA_11, // D20 - DD- + + // LED + PD_0, // D21 - STATUS_LED + + // PWM + // TIM2 + PA_15, // D22 - X_STEP + PB_3, // D23 - Y_STEP + PB_10, // D24 - Z_STEP + PB_11, // D25 - E_STEP + // TIM3 + PB_5, // D26 - PWM_EXT1 + PB_4, // D27 - PWM_EXT2 + PC_8, // D28 - PWM_EXT3 + PC_9, // D29 - PWM_EXT4 + // TIM5 + PA_0, // D30 - PWM_FAN1 + PA_1, // D31 - PWM_BED + PA_2, // D32 - PWM_FAN2 + PA_3, // D33 - PWM_HEAT + + // Stepper + PC_12, // D34 - X_EN + PC_10, // D35 - X_DIR + PC_11, // D36 - X_DIAG + PD_4, // D37 - Y_EN + PD_6, // D38 - Y_DIR + PD_5, // D39 - Y_DIAG + PE_15, // D40 - Z_EN + PE_13, // D41 - Z_DIR + PE_14, // D42 - Z_DIAG + PE_11, // D43 - E_EN + PE_10, // D44 - E_DIR + PE_12, // D45 - E_DIAG + + // EXT3 + PC_6, // D46 - LCD_BEEPER + PC_7, // D47 - BTN_ENC + PD_14, // D48 - LCD_EN + PD_15, // D49 - LCD_RS + PD_13, // D50 - LCD_D4 + PD_12, // D51 - LCD_D5 + PD_11, // D52 - LCD_D6 + PD_10, // D53 - LCD_D7 + + // EXT2 + PC_14, // D54 - BTN_EN1 + PC_15, // D55 - BTN_EN2 + PC_13, // D56 - SD_CARD_DET + PE_6, // D57 - KILL_PIN + + // Endstops + PB_12, // D58 - X_MIN + PB_13, // D59 - X_MAX + PB_14, // D60 - Y_MIN + PB_15, // D61 - Y_MAX + PD_8, // D62 - Z_MIN + PD_9, // D63 - Z_MAX + + // ADC + PC_0, // D64 - THERM_1 + PC_1, // D65 - THERM_2 + PC_2, // D66 - THERM_3 + PA_4, // D67 - FAN_SPEED1 + PC_3 // D68 - FAN_SPEED2 + }; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" +{ +#endif + /** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSE) + * SYSCLK(Hz) = 216000000 + * HCLK(Hz) = 216000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 24000000 + * PLL_M = 12 + * PLL_N = 216 + * PLL_P = 2 + * PLL_Q = 9 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 7 + * @param None + * @retval None + */ + WEAK void SystemClock_Config(void) + { + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /**Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /**Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Activate the Over-Drive mode */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Enables the Clock Security System */ + HAL_RCC_EnableCSS(); + + /**Configure the Systick interrupt time */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); + + /**Configure the Systick */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); + } + +#ifdef __cplusplus +} +#endif diff --git a/variants/REMRAM_V1/variant.h b/variants/REMRAM_V1/variant.h new file mode 100644 index 0000000000..14feeae82a --- /dev/null +++ b/variants/REMRAM_V1/variant.h @@ -0,0 +1,194 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C" +{ +#endif // __cplusplus + + /*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ + extern const PinName digitalPin[]; + + // Enum defining pin names to match digital pin number --> Dx + enum + { + // USART + PA10, // D0 - RX + PA9, // D1 - TX + + // SWD + PA14, // D2 - SWCLK + PA13, // D3 - SWDIO + + // EXT3 + PE5, // D4 - EXT_D1 + PE4, // D5 - EXT_D2 + PE3, // D6 - EXT_D3 + PE2, // D7 - EXT_D4 + PE1, // D8 - EXT_D5 + + // SPI + PB2, // D9 - SS_SD + PC4, // D10 - SS_E + PA7, // D11 - MOSI + PA6, // D12 - MISO + PA5, // D13 - SCK + PB1, // D14 - SS_X + PB0, // D15 - SS_Y + PC5, // D16 - SS_Z + + // I2C + PB6, // D17 - SCL + PB7, // D18 - SDA + + // USB + PA12, // D19 - DD+ + PA11, // D20 - DD- + + // LED + PD0, // D21 - STATUS_LED + + // PWM + // TIM2 + PA15, // D22 - X_STEP + PB3, // D23 - Y_STEP + PB10, // D24 - Z_STEP + PB11, // D25 - E_STEP + // TIM3 + PB5, // D26 - PWM_EXT1 + PB4, // D27 - PWM_EXT2 + PC8, // D28 - PWM_EXT3 + PC9, // D29 - PWM_EXT4 + // TIM5 + PA0, // D30 - PWM_FAN1 + PA1, // D31 - PWM_BED + PA2, // D32 - PWM_FAN2 + PA3, // D33 - PWM_HEAT + + // Stepper + PC12, // D34 - X_EN + PC10, // D35 - X_DIR + PC11, // D36 - X_DIAG + PD4, // D37 - Y_EN + PD6, // D38 - Y_DIR + PD5, // D39 - Y_DIAG + PE15, // D40 - Z_EN + PE13, // D41 - Z_DIR + PE14, // D42 - Z_DIAG + PE11, // D43 - E_EN + PE10, // D44 - E_DIR + PE12, // D45 - E_DIAG + + // EXT3 + PC6, // D46 - LCD_BEEPER + PC7, // D47 - BTN_ENC + PD14, // D48 - LCD_EN + PD15, // D49 - LCD_RS + PD13, // D50 - LCD_D4 + PD12, // D51 - LCD_D5 + PD11, // D52 - LCD_D6 + PD10, // D53 - LCD_D7 + + // EXT2 + PC14, // D54 - BTN_EN1 + PC15, // D55 - BTN_EN2 + PC13, // D56 - SD_CARD_DET + PE6, // D57 - KILL_PIN + + // Endstops + PB12, // D58 - X_MIN + PB13, // D59 - X_MAX + PB14, // D60 - Y_MIN + PB15, // D61 - Y_MAX + PD8, // D62 - Z_MIN + PD9, // D63 - Z_MAX + + // ADC + PC0, // D64 - THERM_1 + PC1, // D65 - THERM_2 + PC2, // D66 - THERM_3 + PA4, // D67 - FAN_SPEED1 + PC3, // D68 - FAN_SPEED2 + + PEND + }; + +// PIN definition +#define NUM_DIGITAL_PINS 69 +#define NUM_ANALOG_INPUTS 5 +#define NUM_ANALOG_FIRST 64 + +// PWM resolution +#define PWM_RESOLUTION 8 +#define PWM_FREQUENCY 20000 // >= 20 Khz => inaudible noise for fans +#define PWM_MAX_DUTY_CYCLE 255 + +// On-board LED pin number +#define LED_YELLOW PD0 +#define LED_BUILTIN LED_YELLOW + +// Timer Definitions + +// Do not use timer used by PWM pins when possible. See PinMap_PWM. +#define TIMER_TONE TIM6 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM3 //TODO: advanced-control timers don't work + +// UART Definitions +#define SERIAL_UART_INSTANCE 1 + +// Default pin used for 'Serial' instance +#define PIN_SERIAL_RX 0 +#define PIN_SERIAL_TX 1 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From 97719e399d3706e4cb646eccd7d0c5a562d0848e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 14 Sep 2018 15:30:35 +0200 Subject: [PATCH 042/109] Update README.md --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index bf5d31e554..c0d607db33 100644 --- a/README.md +++ b/README.md @@ -70,6 +70,11 @@ For advanced user, you can use the repository: see the [Using git repository](ht * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) ### Next release + + * STM32F7 + * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) + * [RemRam v1](https://github.com/hasenbanck/remram) + * STM32L4 * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) * [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) From 31b844b133845f8a8b4d710de5cdf3c367c8c6a5 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 17:28:21 +0200 Subject: [PATCH 043/109] Add debug(const char *format, ...) function This remove direct use of printf and allow to save more than several Kb of memory. By default, debug function does nothing. If __DEBUG is enabled this will call printf. Signed-off-by: Frederic.Pillon --- cores/arduino/debug.h | 33 +++++++++++++++++++++++++++++++++ cores/arduino/stm32/spi_com.c | 7 ++++--- cores/arduino/stm32/stm32_def.c | 15 ++++----------- cores/arduino/stm32/timer.c | 7 ++++--- cores/arduino/stm32/twi.c | 7 ++++--- cores/arduino/stm32/uart.c | 5 +++-- cores/arduino/stm32/uart_emul.c | 3 ++- 7 files changed, 54 insertions(+), 23 deletions(-) create mode 100644 cores/arduino/debug.h diff --git a/cores/arduino/debug.h b/cores/arduino/debug.h new file mode 100644 index 0000000000..88d447b84e --- /dev/null +++ b/cores/arduino/debug.h @@ -0,0 +1,33 @@ +#ifndef _DEBUG_H +#ifdef __DEBUG +#include +#include +#endif /* __DEBUG */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Output a debug message + * + * @param format printf-style format string, followed by variables + * Note: By using the printf function of the library C this inflates the size of + * the code, use a lot of stack. An alternative, will be to implement a tiny + * and limited functionality implementation of printf. + */ +static inline void debug(const char *format, ...) { +#ifdef __DEBUG + va_list args; + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +#else + (void)(format); +#endif /* __DEBUG */ +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DEBUG_H */ diff --git a/cores/arduino/stm32/spi_com.c b/cores/arduino/stm32/spi_com.c index eaca8c5a47..8b51fe0bb4 100644 --- a/cores/arduino/stm32/spi_com.c +++ b/cores/arduino/stm32/spi_com.c @@ -46,6 +46,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ +#include "debug.h" #include "stm32_def.h" #include "spi_com.h" #include "PinAF_STM32F1.h" @@ -149,7 +150,7 @@ uint32_t spi_getClkFreqInst(SPI_TypeDef * spi_inst) break; #endif default: - printf("CLK: SPI instance not set"); + debug("CLK: SPI instance not set"); break; } } @@ -203,7 +204,7 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) /* Pins MOSI/MISO/SCLK must not be NP. ssel can be NP. */ if(spi_mosi == NP || spi_miso == NP || spi_sclk == NP) { - printf("ERROR: at least one SPI pin has no peripheral\n"); + debug("ERROR: at least one SPI pin has no peripheral\n"); return; } @@ -214,7 +215,7 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) // Are all pins connected to the same SPI instance? if(obj->spi == NP) { - printf("ERROR: SPI pins mismatch\n"); + debug("ERROR: SPI pins mismatch\n"); return; } diff --git a/cores/arduino/stm32/stm32_def.c b/cores/arduino/stm32/stm32_def.c index 1c4069919b..b94cbdc6ec 100644 --- a/cores/arduino/stm32/stm32_def.c +++ b/cores/arduino/stm32/stm32_def.c @@ -1,4 +1,5 @@ #include "stm32_def.h" +#include "debug.h" #ifdef __cplusplus extern "C" { @@ -9,18 +10,10 @@ extern "C" { * @param None * @retval None */ -WEAK void _Error_Handler(const char * msg, int val) -{ +WEAK void _Error_Handler(const char * msg, int val) { /* User can add his own implementation to report the HAL error return state */ - /* By using the printf function of the library C this inflates the size of - * the code, use a lot of stack. An alternative, will be to implement a tiny - * and limited functionality implementation of printf. - */ - UNUSED(msg); - UNUSED(val); - /*printf("Error: %s (%i)\n", msg, val);*/ - while(1) - { + debug("Error: %s (%i)\n", msg, val); + while(1) { } } diff --git a/cores/arduino/stm32/timer.c b/cores/arduino/stm32/timer.c index dff17f6a33..656f4d9e32 100644 --- a/cores/arduino/stm32/timer.c +++ b/cores/arduino/stm32/timer.c @@ -46,6 +46,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ +#include "debug.h" #include "timer.h" #include "board.h" @@ -544,7 +545,7 @@ uint32_t getTimerIrq(TIM_TypeDef* tim) #endif break; default: - printf("TIM: Unknown timer IRQn"); + debug("TIM: Unknown timer IRQn"); break; } } @@ -652,7 +653,7 @@ uint8_t getTimerClkSrc(TIM_TypeDef* tim) clkSrc = 2; break; default: - printf("TIM: Unknown timer instance"); + debug("TIM: Unknown timer instance"); break; } } @@ -686,7 +687,7 @@ uint32_t getTimerClkFreq(TIM_TypeDef* tim) #endif default: case 0: - printf("TIM: Unknown clock source"); + debug("TIM: Unknown clock source"); break; } /* When TIMPRE bit of the RCC_DCKCFGR register is reset, diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index 25c138c13c..6133582778 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -47,6 +47,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ +#include "debug.h" #include "stm32_def.h" #include "twi.h" #include "PinAF_STM32F1.h" @@ -166,14 +167,14 @@ void i2c_custom_init(i2c_t *obj, i2c_timing_e timing, uint32_t addressingMode, u //Pins SDA/SCL must not be NP if(i2c_sda == NP || i2c_scl == NP) { - printf("ERROR: at least one I2C pin has no peripheral\n"); + debug("ERROR: at least one I2C pin has no peripheral\n"); return; } obj->i2c = pinmap_merge_peripheral(i2c_sda, i2c_scl); if(obj->i2c == NP) { - printf("ERROR: I2C pins mismatch\n"); + debug("ERROR: I2C pins mismatch\n"); return; } @@ -596,7 +597,7 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) if(obj->slaveRxNbData < I2C_TXRX_BUFFER_SIZE) { obj->slaveRxNbData++; } else { - printf("ERROR: I2C Slave RX overflow\n"); + debug("ERROR: I2C Slave RX overflow\n"); } /* Restart interrupt mode for next Byte */ if(obj->slaveMode == SLAVE_MODE_RECEIVE) { diff --git a/cores/arduino/stm32/uart.c b/cores/arduino/stm32/uart.c index 034896896a..1be5325797 100644 --- a/cores/arduino/stm32/uart.c +++ b/cores/arduino/stm32/uart.c @@ -33,6 +33,7 @@ * ****************************************************************************** */ +#include "debug.h" #include "uart.h" #include "Arduino.h" #include "PinAF_STM32F1.h" @@ -101,7 +102,7 @@ void uart_init(serial_t *obj) /* Pins Rx/Tx must not be NP */ if(uart_rx == NP || uart_tx == NP) { - printf("ERROR: at least one UART pin has no peripheral\n"); + debug("ERROR: at least one UART pin has no peripheral\n"); return; } @@ -112,7 +113,7 @@ void uart_init(serial_t *obj) obj->uart = pinmap_merge_peripheral(uart_tx, uart_rx); if(obj->uart == NP) { - printf("ERROR: U(S)ART pins mismatch\n"); + debug("ERROR: U(S)ART pins mismatch\n"); return; } diff --git a/cores/arduino/stm32/uart_emul.c b/cores/arduino/stm32/uart_emul.c index 1078e1bc95..79b77350a0 100644 --- a/cores/arduino/stm32/uart_emul.c +++ b/cores/arduino/stm32/uart_emul.c @@ -46,6 +46,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ +#include "debug.h" #include "uart_emul.h" #include "digital_io.h" #include "interrupt.h" @@ -402,7 +403,7 @@ void HAL_UART_Emul_RxCpltCallback(UART_Emul_HandleTypeDef *huart) /*void HAL_UART_Emul_ErrorCallback(UART_Emul_HandleTypeDef *huart) { - printf("UART EMUL RX ERROR\n"); + debug("UART EMUL RX ERROR\n"); }*/ /** From fbd7c4e171ba7127f83c2798f9618334bf00a3fb Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 17:05:55 +0200 Subject: [PATCH 044/109] Move _Static_assert to avoid build issue When HAL does not include stdio.h Moreover it allows to group all _Static_assert Signed-off-by: Frederic.Pillon --- cores/arduino/pins_arduino.h | 3 +++ cores/arduino/stm32/PortNames.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/cores/arduino/pins_arduino.h b/cores/arduino/pins_arduino.h index 9399f8cf1a..cf28def2a2 100644 --- a/cores/arduino/pins_arduino.h +++ b/cores/arduino/pins_arduino.h @@ -20,6 +20,9 @@ // Include board variant #include "variant.h" +// Avoid PortName issue +_Static_assert(LastPort <= 0x0F, "PortName must be less than 16"); + // Avoid pins number misalignment _Static_assert(NUM_DIGITAL_PINS==PEND, "NUM_DIGITAL_PINS and PEND differ!"); diff --git a/cores/arduino/stm32/PortNames.h b/cores/arduino/stm32/PortNames.h index 6b3df3d71a..a14d5b7233 100644 --- a/cores/arduino/stm32/PortNames.h +++ b/cores/arduino/stm32/PortNames.h @@ -71,8 +71,6 @@ typedef enum { LastPort = PortZ-1 } PortName; -_Static_assert (LastPort <= 0x0F, "PortName must be less than 16"); - #define MAX_NB_PORT (LastPort-FirstPort+1) GPIO_TypeDef *get_GPIO_Port(uint32_t port_idx); From 11deeab37d613bdfa95de6c961bbe9a3f306065b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 15 Sep 2018 14:29:22 +0200 Subject: [PATCH 045/109] [CI] Update to Arduino 1.8.6 Signed-off-by: Frederic Pillon --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index b6785dcd85..960fabddaa 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,7 +7,7 @@ matrix: include: - env: - NAME= arduinoCI - - IDE_VERSION=1.8.5 + - IDE_VERSION=1.8.6 # Use in CI/build/conf/path_config_travis.json - ARDUINO_IDE_PATH=$HOME/IDE/arduino install: From a320623be3d8a191e10140525a6aa6e05b7ff64c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 15 Sep 2018 14:30:38 +0200 Subject: [PATCH 046/109] [CI] Do not build Ethernet for Nucleo L031K6 Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index c64d36d004..53d53a26ae 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -56,6 +56,11 @@ "applicable": true, "boards": [ "DISCO_F746NG" ] }, + { + "pattern": "/Ethernet/", + "applicable": false, + "boards": [ "NUCLEO_L031K6" ] + }, { "pattern": "09.USB", "applicable": true, From 2cce44b739724513488d0ce280bcf09e49d2e76d Mon Sep 17 00:00:00 2001 From: Testato Date: Sun, 16 Sep 2018 16:36:46 +0200 Subject: [PATCH 047/109] comment updated --- .../Wire/examples/i2c_scanner/i2c_scanner.ino | 39 +++++++++++-------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino index 000c730cb8..3e503a8cae 100644 --- a/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino +++ b/libraries/Wire/examples/i2c_scanner/i2c_scanner.ino @@ -26,24 +26,29 @@ -// Example pinmap for Bluepill I2Cs (by Testato) -// -// I2C-1 standard pins: PB7(sda) PB6(scl) -// Use it by "Wire" without pin declaration -// -// I2C-1 alternative pins: PB9(sda) PB8(scl) -// Remap the first I2C before call begin() -// Wire.setSDA(PB9); -// Wire.setSCL(PB8); -// Wire.begin(); -// -// I2C-2: PB11(sda) PB10(scl) -// Wire.setSDA(PB11); -// Wire.setSCL(PB10); -// -// If you want to use the two I2Cs simultaneously, create a new instance for the second I2C -// TwoWire Wire2(PB11,PB10); +/* Example pinmap for Bluepill I2Cs (by Testato) + + I2C-1 standard pins: PB7(sda) PB6(scl) + Use it by "Wire" without pin declaration + Wire.begin(); + + I2C-1 alternative pins: PB9(sda) PB8(scl) + Remap the first I2C before call begin() + Wire.setSDA(PB9); + Wire.setSCL(PB8); + Wire.begin(); + + I2C-2: PB11(sda) PB10(scl) + Remap the second I2C before call begin() + Wire.setSDA(PB11); + Wire.setSCL(PB10); + Wire.begin(); + If you want to use the two I2Cs simultaneously, create a new instance for the second I2C + TwoWire Wire2(PB11,PB10); + Wire2.begin(); + +*/ #include From e31afc6d4a47495d1480d782747a3029a1ff0e2c Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 17 Sep 2018 16:51:40 +0200 Subject: [PATCH 048/109] Remove SD core dependencies STM32SD will be able to handle properly SD detect pin and FatFs options. SD_DETECT_PIN pinnumber definition could be added in variant.h SD_DATATIMEOUT could be redefined in variant.h Signed-off-by: Frederic.Pillon --- variants/DISCO_F746NG/ffconf.h | 247 ------------------------------ variants/DISCO_F746NG/sd_conf.h | 51 ------ variants/DISCO_F746NG/variant.cpp | 3 +- variants/DISCO_F746NG/variant.h | 6 +- variants/board_template/variant.h | 6 + 5 files changed, 13 insertions(+), 300 deletions(-) delete mode 100644 variants/DISCO_F746NG/ffconf.h delete mode 100644 variants/DISCO_F746NG/sd_conf.h diff --git a/variants/DISCO_F746NG/ffconf.h b/variants/DISCO_F746NG/ffconf.h deleted file mode 100644 index 6227bcf50f..0000000000 --- a/variants/DISCO_F746NG/ffconf.h +++ /dev/null @@ -1,247 +0,0 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module configuration file R0.11 (C)ChaN, 2015 -/----------------------------------------------------------------------------/ -/ -/ CAUTION! Do not forget to make clean the project after any changes to -/ the configuration options. -/ -/----------------------------------------------------------------------------*/ -#ifndef _FFCONF -#define _FFCONF 32020 /* Revision ID */ - -/*-----------------------------------------------------------------------------/ -/ Additional user header to be used -/-----------------------------------------------------------------------------*/ -#include "stm32_def.h" -#include "bsp_sd.h" -/*-----------------------------------------------------------------------------/ -/ Functions and Buffer Configurations -/-----------------------------------------------------------------------------*/ - -#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ -/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system -/ object instead of the sector buffer in the individual file object for file -/ data transfer. This reduces memory consumption 512 bytes each file object. */ - - -#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ -/* Setting _FS_READONLY to 1 defines read only configuration. This removes -/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, -/ f_truncate and useless f_getfree. */ - - -#define _FS_MINIMIZE 0 /* 0 to 3 */ -/* The _FS_MINIMIZE option defines minimization level to remove some functions. -/ -/ 0: Full function. -/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate, f_utime -/ and f_rename are removed. -/ 2: f_opendir and f_readdir are removed in addition to 1. -/ 3: f_lseek is removed in addition to 2. */ - - -#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */ -/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ - - -#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ -/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ - - -#define _USE_FASTSEEK 1 /* 0:Disable or 1:Enable */ -/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ - - -#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ -/* To enable volume label functions, set _USE_LAVEL to 1 */ - - -#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ -/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ - -#define _USE_FIND 0 -/* This option switches filtered directory read feature and related functions, -/� f_findfirst() and f_findnext(). (0:Disable or 1:Enable) */ - - -/* This option is available only for usbh diskio interface and allow to disable -/ the management of the unaligned buffer. -/ When STM32 USB OTG HS or FS IP is used with internal DMA enabled, this define -/ must be set to 0 to align data into 32bits through an internal scratch buffer -/ before being processed by the DMA . Otherwise (DMA not used), this define must -/ be set to 1 to avoid Data alignment and improve the performance. -/ Please note that if _USE_BUFF_WO_ALIGNMENT is set to 1 and an unaligned 32bits -/ buffer is forwarded to the FatFs Write/Read functions, an error will be returned. -/ (0: default value or 1: unaligned buffer return an error). */ - - -/*-----------------------------------------------------------------------------/ -/ Local and Namespace Configurations -/-----------------------------------------------------------------------------*/ - -#define _CODE_PAGE 1252 -/* The _CODE_PAGE specifies the OEM code page to be used on the target system. -/ Incorrect setting of the code page can cause a file open failure. -/ -/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) -/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) -/ 949 - Korean (DBCS, OEM, Windows) -/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) -/ 1250 - Central Europe (Windows) -/ 1251 - Cyrillic (Windows) -/ 1252 - Latin 1 (Windows) -/ 1253 - Greek (Windows) -/ 1254 - Turkish (Windows) -/ 1255 - Hebrew (Windows) -/ 1256 - Arabic (Windows) -/ 1257 - Baltic (Windows) -/ 1258 - Vietnam (OEM, Windows) -/ 437 - U.S. (OEM) -/ 720 - Arabic (OEM) -/ 737 - Greek (OEM) -/ 775 - Baltic (OEM) -/ 850 - Multilingual Latin 1 (OEM) -/ 858 - Multilingual Latin 1 + Euro (OEM) -/ 852 - Latin 2 (OEM) -/ 855 - Cyrillic (OEM) -/ 866 - Russian (OEM) -/ 857 - Turkish (OEM) -/ 862 - Hebrew (OEM) -/ 874 - Thai (OEM, Windows) -/ 1 - ASCII only (Valid for non LFN cfg.) -*/ - - -#define _USE_LFN 1 /* 0 to 3 */ -#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ -/* The _USE_LFN option switches the LFN feature. -/ -/ 0: Disable LFN feature. _MAX_LFN has no effect. -/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. -/ 2: Enable LFN with dynamic working buffer on the STACK. -/ 3: Enable LFN with dynamic working buffer on the HEAP. -/ -/ To enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper() -/ function must be added to the project. -/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the -/ working buffer, take care on stack overflow. When use heap memory for the working -/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added -/ to the project. */ - - -#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ -/* To switch the character encoding on the FatFs API to Unicode, enable LFN feature -/ and set _LFN_UNICODE to 1. */ - - -#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */ -/* When Unicode API is enabled, character encoding on the all FatFs API is switched -/ to Unicode. This option selects the character encoding on the file to be read/written -/ via string functions, f_gets(), f_putc(), f_puts and f_printf(). -/ This option has no effect when _LFN_UNICODE is 0. */ - - -#define _FS_RPATH 0/* 0 to 2 */ -/* The _FS_RPATH option configures relative path feature. -/ -/ 0: Disable relative path feature and remove related functions. -/ 1: Enable relative path. f_chdrive() and f_chdir() function are available. -/ 2: f_getcwd() function is available in addition to 1. -/ -/ Note that output of the f_readdir() fnction is affected by this option. */ - - -/*---------------------------------------------------------------------------/ -/ Drive/Volume Configurations -/----------------------------------------------------------------------------*/ - -#define _VOLUMES 1 -/* Number of volumes (logical drives) to be used. */ - - -#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */ -/* When set to 0, each volume is bound to the same physical drive number and -/ it can mount only first primaly partition. When it is set to 1, each volume -/ is tied to the partitions listed in VolToPart[]. */ - - -#define _MIN_SS 512 -#define _MAX_SS 512 -/* These options configure the range of sector size to be supported. (512, 1024, 2048 or -/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger -/ value may be required for on-board flash memory and some type of optical media. -/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and -/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */ - - -#define _USE_TRIM 0 /* 0:Disable or 1:Enable */ -/* To enable sector erase feature, set _USE_TRIM to 1. Also CTRL_ERASE_SECTOR command -/ should be added to the disk_ioctl() function. */ - - -#define _FS_NOFSINFO 0 /* 0 or 1 */ -/* If you need to know the correct free space on the FAT32 volume, set this -/ option to 1 and f_getfree() function at first time after volume mount will -/ force a full FAT scan. -/ -/ 0: Load all informations in the FSINFO if available. -/ 1: Do not trust free cluster count in the FSINFO. -*/ - - -/*---------------------------------------------------------------------------/ -/ System Configurations -/----------------------------------------------------------------------------*/ - -#define _WORD_ACCESS 0 /* 0 or 1 */ -/* The _WORD_ACCESS option is an only platform dependent option. It defines -/ which access method is used to the word data on the FAT volume. -/ -/ 0: Byte-by-byte access. Always compatible with all platforms. -/ 1: Word access. Do not choose this unless under both the following conditions. -/ -/ * Byte order on the memory is little-endian. -/ * Address miss-aligned word access is always allowed for all instructions. -/ -/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance -/ and reduce code size. -*/ - - -/* A header file that defines sync object types on the O/S, such as -/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */ - -#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ -#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ -#define _SYNC_t 0 /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ - -/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module. -/ -/ 0: Disable re-entrancy. _SYNC_t and _FS_TIMEOUT have no effect. -/ 1: Enable re-entrancy. Also user provided synchronization handlers, -/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() -/ function must be added to the project. */ - - -#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ -/* To enable file lock control feature, set _FS_LOCK to 1 or greater. - The value defines how many files can be opened simultaneously. */ - -#define _FS_NORTC 0 -#define _NORTC_MON 2 -#define _NORTC_MDAY 1 -#define _NORTC_YEAR 2015 -/* The _FS_NORTC option switches timestamp feature. If the system does not have -/� an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable -/� the timestamp feature. All objects modified by FatFs will have a fixed timestamp -/� defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR. -/� When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need -/� to be added to the project to read current time form RTC. _NORTC_MON, -/� _NORTC_MDAY and _NORTC_YEAR have no effect. -/� These options have no effect at read-only configuration (_FS_READONLY == 1). */ - -#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31 - #error Invalid _FS_NORTC settings -#endif - -#endif /* _FFCONFIG */ diff --git a/variants/DISCO_F746NG/sd_conf.h b/variants/DISCO_F746NG/sd_conf.h deleted file mode 100644 index 2e4d487fd1..0000000000 --- a/variants/DISCO_F746NG/sd_conf.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - ****************************************************************************** - * @file sd_conf.h - * @author fpiSTM - * @date 2017 - * @brief This file contains hw config for SD - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SD_CONF_H -#define __SD_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_def.h" - -#define SD_DATATIMEOUT ((uint32_t)100000000) - -/*SD-detect signal */ -#define SD_DETECT_PIN GPIO_PIN_13 -#define SD_DETECT_GPIO_PORT GPIOC -#define SD_DETECT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define SD_DETECT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() -#define SD_DETECT_EXTI_IRQn EXTI15_10_IRQn - -/* Definition for BSP SD */ -#define SD_INSTANCE SDMMC1 - -#define SD_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define SD_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define SD_CLK_EDGE SDMMC_CLOCK_EDGE_RISING -#define SD_CLK_BYPASS SDMMC_CLOCK_BYPASS_DISABLE -#define SD_CLK_PWR_SAVE SDMMC_CLOCK_POWER_SAVE_DISABLE -#define SD_BUS_WIDE_1B SDMMC_BUS_WIDE_1B -#define SD_BUS_WIDE_4B SDMMC_BUS_WIDE_4B -#define SD_HW_FLOW_CTRL SDMMC_HARDWARE_FLOW_CONTROL_DISABLE -#define SD_CLK_DIV SDMMC_TRANSFER_CLK_DIV - -/* Definition for MSP SD */ -#define SD_AF GPIO_AF12_SDMMC1 - - -#ifdef __cplusplus -} -#endif - -#endif /* __SD_CONF_H */ diff --git a/variants/DISCO_F746NG/variant.cpp b/variants/DISCO_F746NG/variant.cpp index 5f98190d2a..ee94372fd9 100644 --- a/variants/DISCO_F746NG/variant.cpp +++ b/variants/DISCO_F746NG/variant.cpp @@ -48,7 +48,8 @@ const PinName digitalPin[] = { PF_6, //D21/A5 PI_11, //D22 User btn PB_7, //D23 ST-Link Rx - PA_9 //D24 ST-Link Tx + PA_9, //D24 ST-Link Tx + PC_13 //D25 SD detect }; #ifdef __cplusplus diff --git a/variants/DISCO_F746NG/variant.h b/variants/DISCO_F746NG/variant.h index b4a27b20c2..55684879ce 100644 --- a/variants/DISCO_F746NG/variant.h +++ b/variants/DISCO_F746NG/variant.h @@ -59,11 +59,12 @@ enum { PI11, //D22 User btn PB7, //D23 ST-Link Rx PA9, //D24 ST-Link Tx + PC13, //D25 SD detect PEND }; // This must be a literal with the same value as PEND -#define NUM_DIGITAL_PINS 25 +#define NUM_DIGITAL_PINS 26 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 6 #define NUM_ANALOG_FIRST 16 @@ -89,6 +90,9 @@ enum { #define PIN_SERIAL_RX PB7 #define PIN_SERIAL_TX PA9 +// SD detect signal +#define SD_DETECT_PIN PC13 + #ifdef __cplusplus } // extern "C" #endif diff --git a/variants/board_template/variant.h b/variants/board_template/variant.h index da140889c4..018f98077d 100644 --- a/variants/board_template/variant.h +++ b/variants/board_template/variant.h @@ -144,6 +144,12 @@ enum { //#define PIN_SERIALLP1_RX x // For LPUART1 RX //#define PIN_SERIALLP1_TX x // For LPUART1 TX +// SD card slot Definitions +// SD detect signal can be defined if required +//#define SD_DETECT_PIN x +// SD Read/Write timeout, default value defined in STM32SD library +//#define SD_DATATIMEOUT x + #ifdef __cplusplus } // extern "C" #endif From 418e3f6638bfe319fd2c30a6c1aefb340207c0bd Mon Sep 17 00:00:00 2001 From: edogaldo Date: Sun, 16 Sep 2018 17:33:46 +0200 Subject: [PATCH 049/109] Add Black F407VE support Signed-off-by: edogaldo --- boards.txt | 76 +++- variants/BLACK_F407VE/PeripheralPins.c | 358 +++++++++++++++++ variants/BLACK_F407VE/PinNamesVar.h | 25 ++ variants/BLACK_F407VE/ldscript.ld | 189 +++++++++ variants/BLACK_F407VE/stm32f4xx_hal_conf.h | 443 +++++++++++++++++++++ variants/BLACK_F407VE/variant.cpp | 181 +++++++++ variants/BLACK_F407VE/variant.h | 211 ++++++++++ 7 files changed, 1482 insertions(+), 1 deletion(-) create mode 100644 variants/BLACK_F407VE/PeripheralPins.c create mode 100644 variants/BLACK_F407VE/PinNamesVar.h create mode 100644 variants/BLACK_F407VE/ldscript.ld create mode 100644 variants/BLACK_F407VE/stm32f4xx_hal_conf.h create mode 100644 variants/BLACK_F407VE/variant.cpp create mode 100644 variants/BLACK_F407VE/variant.h diff --git a/boards.txt b/boards.txt index 68482c0456..7b4b4e5f39 100644 --- a/boards.txt +++ b/boards.txt @@ -495,6 +495,46 @@ GenF103.menu.upload_method.bmpMethod=BMP (Black Magic Probe) GenF103.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp GenF103.menu.upload_method.bmpMethod.upload.tool=bmp_upload +################################################################################ +# Generic F4 + +GenF4.name=Generic STM32F4 series + +GenF4.build.vid=0x1EAF +GenF4.build.pid=0x0004 +GenF4.vid.0=0x1EAF +GenF4.pid.0=0x0004 + +GenF4.build.core=arduino +GenF4.build.board=GenF4 +GenF4.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} + +# Black F407VE +# Support: Serial1 (USART1 on PA10, PA9) +# Default SPI: SPI (SPI1 on PB3,PB4,PB5 - NRF24 connector and W25Q16 (on board flash)) +GenF4.menu.pnum.BLACK_F407VE=Black F407VE +GenF4.menu.pnum.BLACK_F407VE.upload.maximum_size=524288 +GenF4.menu.pnum.BLACK_F407VE.upload.maximum_data_size=131072 +GenF4.menu.pnum.BLACK_F407VE.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +GenF4.menu.pnum.BLACK_F407VE.build.board=BLACK_F407VE +GenF4.menu.pnum.BLACK_F407VE.build.series=STM32F4xx +GenF4.menu.pnum.BLACK_F407VE.build.product_line=STM32F407xx +GenF4.menu.pnum.BLACK_F407VE.build.variant=BLACK_F407VE +GenF4.menu.pnum.BLACK_F407VE.build.cmsis_lib_gcc=arm_cortexM4l_math + +# Upload menu +GenF4.menu.upload_method.STLink=STLink +GenF4.menu.upload_method.STLink.upload.protocol=STLink +GenF4.menu.upload_method.STLink.upload.tool=stlink_upload + +GenF4.menu.upload_method.serialMethod=Serial +GenF4.menu.upload_method.serialMethod.upload.protocol=maple_serial +GenF4.menu.upload_method.serialMethod.upload.tool=serial_upload + +GenF4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) +GenF4.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp +GenF4.menu.upload_method.bmpMethod.upload.tool=bmp_upload + ############################### # Maple Maple.name=Maple series @@ -601,6 +641,12 @@ GenF103.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NON GenF103.menu.xserial.disabled=Disabled (No Serial) GenF103.menu.xserial.disabled.build.xSerial= +GenF4.menu.xserial.generic=Enabled with generic Serial +GenF4.menu.xserial.none=Enabled without generic Serial +GenF4.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +GenF4.menu.xserial.disabled=Disabled (No Serial) +GenF4.menu.xserial.disabled.build.xSerial= + Maple.menu.xserial.generic=Enabled with generic Serial Maple.menu.xserial.none=Enabled without generic Serial Maple.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -769,6 +815,34 @@ GenF103.menu.opt.ogstd=Debug (-g) GenF103.menu.opt.ogstd.build.flags.optimize=-g -Og GenF103.menu.opt.ogstd.build.flags.ldspecs= +GenF4.menu.opt.osstd=Smallest (-Os default) +GenF4.menu.opt.osstd.build.flags.optimize=-Os +GenF4.menu.opt.osstd.build.flags.ldspecs= +GenF4.menu.opt.oslto=Smallest (-Os) with LTO +GenF4.menu.opt.oslto.build.flags.optimize=-Os -flto +GenF4.menu.opt.oslto.build.flags.ldspecs=-flto +GenF4.menu.opt.o1std=Fast (-O1) +GenF4.menu.opt.o1std.build.flags.optimize=-O1 +GenF4.menu.opt.o1std.build.flags.ldspecs= +GenF4.menu.opt.o1lto=Fast (-O1) with LTO +GenF4.menu.opt.o1lto.build.flags.optimize=-O1 -flto +GenF4.menu.opt.o1lto.build.flags.ldspecs=-flto +GenF4.menu.opt.o2std=Faster (-O2) +GenF4.menu.opt.o2std.build.flags.optimize=-O2 +GenF4.menu.opt.o2std.build.flags.ldspecs= +GenF4.menu.opt.o2lto=Faster (-O2) with LTO +GenF4.menu.opt.o2lto.build.flags.optimize=-O2 -flto +GenF4.menu.opt.o2lto.build.flags.ldspecs=-flto +GenF4.menu.opt.o3std=Fastest (-O3) +GenF4.menu.opt.o3std.build.flags.optimize=-O3 +GenF4.menu.opt.o3std.build.flags.ldspecs= +GenF4.menu.opt.o3lto=Fastest (-O3) with LTO +GenF4.menu.opt.o3lto.build.flags.optimize=-O3 -flto +GenF4.menu.opt.o3lto.build.flags.ldspecs=-flto +GenF4.menu.opt.ogstd=Debug (-g) +GenF4.menu.opt.ogstd.build.flags.optimize=-g -Og +GenF4.menu.opt.ogstd.build.flags.ldspecs= + Maple.menu.opt.osstd=Smallest (-Os default) Maple.menu.opt.oslto=Smallest (-Os) with LTO Maple.menu.opt.oslto.build.flags.optimize=-Os -flto @@ -819,4 +893,4 @@ RemRam.menu.opt.o3lto.build.flags.optimize=-O3 -flto RemRam.menu.opt.o3lto.build.flags.ldspecs=-flto RemRam.menu.opt.ogstd=Debug (-g) RemRam.menu.opt.ogstd.build.flags.optimize=-g -Og -RemRam.menu.opt.ogstd.build.flags.ldspecs= \ No newline at end of file +RemRam.menu.opt.ogstd.build.flags.ldspecs= diff --git a/variants/BLACK_F407VE/PeripheralPins.c b/variants/BLACK_F407VE/PeripheralPins.c new file mode 100644 index 0000000000..68e5b9684d --- /dev/null +++ b/variants/BLACK_F407VE/PeripheralPins.c @@ -0,0 +1,358 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32F407V(E-G)Tx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 -> BUT K_UP +// {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 -> BUT K_UP +// {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 -> BUT K_UP + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 +// {PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 +// {PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 +// {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 +// {PA_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 +// {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 +// {PA_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 +// {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 +// {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 +// {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 -> LED D2 +// {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 -> LED D2 +// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 -> LED D3 +// {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 -> LED D3 +// {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 +// {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 +// {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 +// {PC_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PC_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 +// {PC_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 +// {PC_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 +// {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 +// {PC_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 +// {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 +// {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 +// {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 +// {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {NC, NP, 0} +}; +#endif + +//*** QUADSPI *** + +//*** No QUADSPI *** diff --git a/variants/BLACK_F407VE/PinNamesVar.h b/variants/BLACK_F407VE/PinNamesVar.h new file mode 100644 index 0000000000..b65ff1991e --- /dev/null +++ b/variants/BLACK_F407VE/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = NC, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/BLACK_F407VE/ldscript.ld b/variants/BLACK_F407VE/ldscript.ld new file mode 100644 index 0000000000..9f411268a0 --- /dev/null +++ b/variants/BLACK_F407VE/ldscript.ld @@ -0,0 +1,189 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F407VETx Device with +** 512KByte FLASH, 128KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text ALIGN(8): + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata ALIGN(4): + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/variants/BLACK_F407VE/stm32f4xx_hal_conf.h b/variants/BLACK_F407VE/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..7df53b0435 --- /dev/null +++ b/variants/BLACK_F407VE/stm32f4xx_hal_conf.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/BLACK_F407VE/variant.cpp b/variants/BLACK_F407VE/variant.cpp new file mode 100644 index 0000000000..57cfff3b94 --- /dev/null +++ b/variants/BLACK_F407VE/variant.cpp @@ -0,0 +1,181 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +// This array allows to wrap Arduino pin number(Dx or x) +// to STM32 PinName (PX_n) +const PinName digitalPin[] = { + // Left Side + //Ext //Int + //5V //5V + //5V //5V + //3V3 //3V3 + //3V3 //3V3 + //GND //GND + PE_2, PE_3, // D0, D1 + PE_4, PE_5, // PE_4: BUT K0, PE_5: BUT K1 + PE_6, PC_13, + PC_0, PC_1, + PC_2, PC_3, + //VREF- //VREF+ + PA_0, PA_1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA_2, PA_3, + PA_4, PA_5, + PA_6, PA_7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PC_4, PC_5, + PB_0, PB_1, // D20, D21 + PE_7, PE_8, + PE_9, PE_10, + PE_11, PE_12, + PE_13, PE_14, + PE_15, PB_10, // D30, D31 + PB_11, PB_12, + PB_13, PB_14, + // Right Side + //Int //Ext + //3V3 //3V3 + //3V3 //3V3 + //BOOT0 //BOOT1 + //GND //GND + //GND //GND + PE_1, PE_0, + PB_9, PB_8, + PB_7, PB_6, // D40, D41 + PB_5, PB_3, + PD_7, PD_6, + PD_5, PD_4, + PD_3, PD_2, + PD_1, PD_0, // D50, D51 + PC_12, PC_11, + PC_10, PA_15, + PA_12, PA_11, // PA_11: USB_DM, PA_12: USB_DP + PA_10, PA_9, + PA_8, PC_9, // D60, D61 + PC_8, PC_7, + PC_6, PD_15, + PD_14, PD_13, + PD_12, PD_11, + PD_10, PD_9, // D70, D71 + PD_8, PB_15, + PB_4, + // Analog pins + PA_0, // D75 + PA_1, + PA_2, + PA_3, + PA_4, + PA_5, // D80 + PB_0, + PB_1, + PC_0, + PC_1, + PC_2, + PC_3, + PC_4, + PC_5 +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/BLACK_F407VE/variant.h b/variants/BLACK_F407VE/variant.h new file mode 100644 index 0000000000..6b7fabb4b3 --- /dev/null +++ b/variants/BLACK_F407VE/variant.h @@ -0,0 +1,211 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +enum { + // Left Side + //Ext //Int + //5V //5V + //5V //5V + //3V3 //3V3 + //3V3 //3V3 + //GND //GND + PE2, PE3, // D0, D1 + PE4, PE5, // PE_4: BUT K0, PE_5: BUT K1 + PE6, PC13, + PC0, PC1, + PC2, PC3, + //VREF- //VREF+ + PA0, PA1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA2, PA3, + PA4, PA5, + PA6, PA7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PC4, PC5, + PB0, PB1, // D20, D21 + PE7, PE8, + PE9, PE10, + PE11, PE12, + PE13, PE14, + PE15, PB10, // D30, D31 + PB11, PB12, + PB13, PB14, + // Right Side + //Int //Ext + //3V3 //3V3 + //3V3 //3V3 + //BOOT0 //BOOT1 + //GND //GND + //GND //GND + PE1, PE0, + PB9, PB8, + PB7, PB6, // D40, D41 + PB5, PB3, + PD7, PD6, + PD5, PD4, + PD3, PD2, + PD1, PD0, // D50, D51 + PC12, PC11, + PC10, PA15, + PA12, PA11, // PA_11: USB_DM, PA_12: USB_DP + PA10, PA9, + PA8, PC9, // D60, D61 + PC8, PC7, + PC6, PD15, + PD14, PD13, + PD12, PD11, + PD10, PD9, // D70, D71 + PD8, PB15, + PB4, + // Analog pins + PA0_A, // D75 + PA1_A, + PA2_A, + PA3_A, + PA4_A, + PA5_A, // D80 + PB0_A, + PB1_A, + PC0_A, + PC1_A, + PC2_A, + PC3_A, + PC4_A, + PC5_A, + PEND +}; + +// This must be a literal with the same value as PEND +#define NUM_DIGITAL_PINS 89 +// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 14 +#define NUM_ANALOG_FIRST 75 + +// Below ADC, DAC and PWM definitions already done in the core +// Could be redefined here if needed +// ADC resolution is 12bits +//#define ADC_RESOLUTION 12 +//#define DACC_RESOLUTION 12 + +// PWM resolution +//#define PWM_RESOLUTION 8 +//#define PWM_FREQUENCY 1000 +//#define PWM_MAX_DUTY_CYCLE 255 + +// On-board LED pin number +#define LED_D2 PA6 +#define LED_D3 PA7 +#define LED_BUILTIN LED_D2 +#define LED_GREEN LED_D2 + +// On-board user button +#define BTN_K_UP PA0 +#define BTN_K0 PE4 +#define BTN_K1 PE5 +#define USER_BTN BTN_K0 + +// Below SPI and I2C definitions already done in the core +// Could be redefined here if differs from the default one +// SPI Definitions +#define PIN_SPI_SS PB7 // NRF24 connector +#define PIN_SPI_SS1 PB0 // W25Q16 (on board flash) +#define PIN_SPI_MOSI PB5 // NRF24 connector & W25Q16 (on board flash) +#define PIN_SPI_MISO PB4 // NRF24 connector & W25Q16 (on board flash) +#define PIN_SPI_SCK PB3 // NRF24 connector & W25Q16 (on board flash) + +// I2C Definitions +#define PIN_WIRE_SDA PB9 +#define PIN_WIRE_SCL PB8 + +// Timer Definitions +//Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c +#define TIMER_TONE TIM6 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work + +// UART Definitions +// Define here Serial instance number to map on Serial generic name +#define SERIAL_UART_INSTANCE 1 //ex: 2 for Serial2 (USART2) +// DEBUG_UART could be redefined to print on another instance than 'Serial' +//#define DEBUG_UART ((USART_TypeDef *) U(S)ARTX) // ex: USART3 +// DEBUG_UART baudrate, default: 9600 if not defined +//#define DEBUG_UART_BAUDRATE x +// DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART +//#define DEBUG_PINNAME_TX PX_n // PinName used for TX + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#define PIN_SERIAL_RX PA10 +#define PIN_SERIAL_TX PA9 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial1 +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From f1b434c36ee06fef82f511d678bd78823c7e4b2b Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 19 Sep 2018 09:35:52 +0200 Subject: [PATCH 050/109] [CI] Allow STM32SD examples to build for Black F407VET Signed-off-by: Frederic.Pillon --- CI/build/conf/cores_config.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 53d53a26ae..f07d4736f3 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -54,7 +54,7 @@ { "pattern": "STM32SD", "applicable": true, - "boards": [ "DISCO_F746NG" ] + "boards": [ "DISCO_F746NG", "BLACK_F407VE" ] }, { "pattern": "/Ethernet/", From 471607530ba69634e4c388dd12ff4d709d0b4316 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 19 Sep 2018 10:10:27 +0200 Subject: [PATCH 051/109] [CI] Update to Arduino 1.8.7 Signed-off-by: Frederic.Pillon --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 960fabddaa..a56d4a9679 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,7 +7,7 @@ matrix: include: - env: - NAME= arduinoCI - - IDE_VERSION=1.8.6 + - IDE_VERSION=1.8.7 # Use in CI/build/conf/path_config_travis.json - ARDUINO_IDE_PATH=$HOME/IDE/arduino install: From 7eae3be750aa75a2790a307aa453fc8d0c6667da Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 19 Sep 2018 10:24:08 +0200 Subject: [PATCH 052/109] Update README.md --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index c0d607db33..a9f49e618c 100644 --- a/README.md +++ b/README.md @@ -70,6 +70,8 @@ For advanced user, you can use the repository: see the [Using git repository](ht * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) ### Next release + * STM32F4 + * [Black F407VET6](http://wiki.stm32duino.com/index.php?title=STM32F407#.22Black_VET6.22_STM32F407VET6_Variant) * STM32F7 * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) From f3598104cbfdd0d492cdc6f2c9c94d1f9e7c2202 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 15:44:46 +0200 Subject: [PATCH 053/109] Update STM32L4xx HAL Drivers to v1.9.0 Included in STM32CubeL4 FW V1.13.0 Signed-off-by: Frederic.Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 94 +- .../Inc/stm32_assert_template.h | 6 +- .../STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h | 40 +- .../Inc/stm32l4xx_hal_adc.h | 108 +- .../Inc/stm32l4xx_hal_adc_ex.h | 302 +-- .../Inc/stm32l4xx_hal_can.h | 2 + .../Inc/stm32l4xx_hal_comp.h | 85 +- .../Inc/stm32l4xx_hal_conf_template.h | 6 +- .../Inc/stm32l4xx_hal_cryp.h | 10 +- .../Inc/stm32l4xx_hal_dac.h | 188 +- .../Inc/stm32l4xx_hal_dac_ex.h | 89 +- .../Inc/stm32l4xx_hal_dcmi.h | 10 +- .../Inc/stm32l4xx_hal_def.h | 8 +- .../Inc/stm32l4xx_hal_dma.h | 92 +- .../Inc/stm32l4xx_hal_dma_ex.h | 18 +- .../Inc/stm32l4xx_hal_exti.h | 876 ++++++ .../Inc/stm32l4xx_hal_flash.h | 213 +- .../Inc/stm32l4xx_hal_gpio.h | 68 +- .../Inc/stm32l4xx_hal_gpio_ex.h | 175 +- .../Inc/stm32l4xx_hal_hash.h | 87 +- .../Inc/stm32l4xx_hal_hash_ex.h | 15 +- .../Inc/stm32l4xx_hal_i2c.h | 12 +- .../Inc/stm32l4xx_hal_irda.h | 118 +- .../Inc/stm32l4xx_hal_irda_ex.h | 24 +- .../Inc/stm32l4xx_hal_lptim.h | 170 +- .../Inc/stm32l4xx_hal_opamp.h | 195 +- .../Inc/stm32l4xx_hal_opamp_ex.h | 13 +- .../Inc/stm32l4xx_hal_ospi.h | 254 +- .../Inc/stm32l4xx_hal_pwr.h | 63 +- .../Inc/stm32l4xx_hal_pwr_ex.h | 177 +- .../Inc/stm32l4xx_hal_qspi.h | 4 +- .../Inc/stm32l4xx_hal_rcc.h | 774 +++--- .../Inc/stm32l4xx_hal_rcc_ex.h | 123 +- .../Inc/stm32l4xx_hal_rtc.h | 710 +++-- .../Inc/stm32l4xx_hal_rtc_ex.h | 1274 ++++++--- .../Inc/stm32l4xx_hal_sai.h | 19 +- .../Inc/stm32l4xx_hal_smartcard.h | 89 +- .../Inc/stm32l4xx_hal_smartcard_ex.h | 6 +- .../Inc/stm32l4xx_hal_smbus.h | 16 +- .../Inc/stm32l4xx_hal_spi.h | 40 +- .../Inc/stm32l4xx_hal_spi_ex.h | 6 +- .../Inc/stm32l4xx_hal_swpmi.h | 10 +- .../Inc/stm32l4xx_hal_tim_ex.h | 6 + .../Inc/stm32l4xx_hal_tsc.h | 86 +- .../Inc/stm32l4xx_hal_uart_ex.h | 3 +- .../Inc/stm32l4xx_hal_usart.h | 51 +- .../Inc/stm32l4xx_hal_usart_ex.h | 22 +- .../Inc/stm32l4xx_ll_adc.h | 658 ++--- .../Inc/stm32l4xx_ll_bus.h | 18 +- .../Inc/stm32l4xx_ll_comp.h | 34 +- .../Inc/stm32l4xx_ll_crs.h | 41 +- .../Inc/stm32l4xx_ll_dac.h | 361 +-- .../Inc/stm32l4xx_ll_dma.h | 572 ++-- .../Inc/stm32l4xx_ll_dmamux.h | 73 +- .../Inc/stm32l4xx_ll_exti.h | 24 +- .../Inc/stm32l4xx_ll_gpio.h | 16 +- .../Inc/stm32l4xx_ll_i2c.h | 88 +- .../Inc/stm32l4xx_ll_iwdg.h | 22 +- .../Inc/stm32l4xx_ll_lptim.h | 205 +- .../Inc/stm32l4xx_ll_opamp.h | 61 +- .../Inc/stm32l4xx_ll_pwr.h | 163 +- .../Inc/stm32l4xx_ll_rcc.h | 296 +- .../Inc/stm32l4xx_ll_rtc.h | 2390 ++++++++++++---- .../Inc/stm32l4xx_ll_spi.h | 17 +- .../Inc/stm32l4xx_ll_swpmi.h | 60 +- .../Inc/stm32l4xx_ll_system.h | 6 +- .../Inc/stm32l4xx_ll_tim.h | 5 +- .../Inc/stm32l4xx_ll_usart.h | 168 +- .../STM32L4xx_HAL_Driver/Release_Notes.html | 929 ++----- .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 127 +- .../Src/stm32l4xx_hal_adc.c | 741 +++-- .../Src/stm32l4xx_hal_adc_ex.c | 496 ++-- .../Src/stm32l4xx_hal_comp.c | 171 +- .../Src/stm32l4xx_hal_crc.c | 44 +- .../Src/stm32l4xx_hal_crc_ex.c | 2 +- .../Src/stm32l4xx_hal_cryp.c | 109 +- .../Src/stm32l4xx_hal_cryp_ex.c | 845 +++--- .../Src/stm32l4xx_hal_dac.c | 314 ++- .../Src/stm32l4xx_hal_dac_ex.c | 157 +- .../Src/stm32l4xx_hal_dcmi.c | 93 +- .../Src/stm32l4xx_hal_dma.c | 13 +- .../Src/stm32l4xx_hal_dma_ex.c | 4 +- .../Src/stm32l4xx_hal_exti.c | 659 +++++ .../Src/stm32l4xx_hal_firewall.c | 8 +- .../Src/stm32l4xx_hal_flash.c | 2 +- .../Src/stm32l4xx_hal_flash_ex.c | 4 +- .../Src/stm32l4xx_hal_gpio.c | 167 +- .../Src/stm32l4xx_hal_hash.c | 670 ++--- .../Src/stm32l4xx_hal_hash_ex.c | 16 +- .../Src/stm32l4xx_hal_hcd.c | 8 +- .../Src/stm32l4xx_hal_i2c.c | 660 +++-- .../Src/stm32l4xx_hal_irda.c | 407 ++- .../Src/stm32l4xx_hal_iwdg.c | 4 +- .../Src/stm32l4xx_hal_lptim.c | 229 +- .../Src/stm32l4xx_hal_opamp.c | 447 +-- .../Src/stm32l4xx_hal_opamp_ex.c | 490 ++-- .../Src/stm32l4xx_hal_ospi.c | 578 ++-- .../Src/stm32l4xx_hal_pcd.c | 5 + .../Src/stm32l4xx_hal_pwr.c | 275 +- .../Src/stm32l4xx_hal_pwr_ex.c | 547 ++-- .../Src/stm32l4xx_hal_qspi.c | 31 +- .../Src/stm32l4xx_hal_rcc.c | 313 ++- .../Src/stm32l4xx_hal_rcc_ex.c | 1754 ++++++------ .../Src/stm32l4xx_hal_rtc.c | 1039 +++---- .../Src/stm32l4xx_hal_rtc_ex.c | 2394 ++++++++++------- .../Src/stm32l4xx_hal_sai.c | 48 +- .../Src/stm32l4xx_hal_sai_ex.c | 6 + .../Src/stm32l4xx_hal_smartcard.c | 317 ++- .../Src/stm32l4xx_hal_smartcard_ex.c | 21 +- .../Src/stm32l4xx_hal_smbus.c | 248 +- .../Src/stm32l4xx_hal_spi.c | 430 +-- .../Src/stm32l4xx_hal_spi_ex.c | 2 +- .../Src/stm32l4xx_hal_swpmi.c | 275 +- .../Src/stm32l4xx_hal_tim.c | 5 +- .../Src/stm32l4xx_hal_tim_ex.c | 73 +- .../Src/stm32l4xx_hal_tsc.c | 14 +- .../Src/stm32l4xx_hal_usart.c | 819 ++++-- .../Src/stm32l4xx_hal_usart_ex.c | 35 +- .../Src/stm32l4xx_ll_adc.c | 44 +- .../Src/stm32l4xx_ll_comp.c | 38 +- .../Src/stm32l4xx_ll_dac.c | 55 +- .../Src/stm32l4xx_ll_dma.c | 10 +- .../Src/stm32l4xx_ll_exti.c | 19 +- .../Src/stm32l4xx_ll_gpio.c | 23 +- .../Src/stm32l4xx_ll_i2c.c | 4 +- .../Src/stm32l4xx_ll_lptim.c | 26 +- .../Src/stm32l4xx_ll_opamp.c | 10 +- .../Src/stm32l4xx_ll_rcc.c | 283 +- .../Src/stm32l4xx_ll_rtc.c | 23 +- .../Src/stm32l4xx_ll_swpmi.c | 19 +- .../Src/stm32l4xx_ll_utils.c | 44 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 132 files changed, 18050 insertions(+), 11630 deletions(-) create mode 100644 system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h create mode 100644 system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 79999700e8..9d667c8023 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -444,12 +444,16 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE + +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #endif /** @@ -494,12 +498,12 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 @@ -540,16 +544,25 @@ #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -605,7 +618,7 @@ #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -737,6 +750,16 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP + #define I2S_FLAG_FRE I2S_FLAG_TIFRE +#endif + #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif @@ -861,6 +884,21 @@ #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + /** * @} */ @@ -932,6 +970,10 @@ #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO #endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif /** * @} */ @@ -1288,6 +1330,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 */ /** * @} */ @@ -1770,6 +1820,10 @@ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + /** * @} */ @@ -2165,19 +2219,6 @@ #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE @@ -2849,7 +2890,6 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -2977,7 +3017,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) +#if defined (STM32L412xx) || defined (STM32L422xx) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3109,6 +3149,7 @@ #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} @@ -3298,10 +3339,7 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER -#if defined(STM32F7) -#else #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -#endif /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h index 343c959a03..736d722130 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h @@ -36,8 +36,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_ASSERT_H -#define __STM32_ASSERT_H +#ifndef STM32_ASSERT_H +#define STM32_ASSERT_H #ifdef __cplusplus extern "C" { @@ -67,7 +67,7 @@ } #endif -#endif /* __STM32_ASSERT_H */ +#endif /* STM32_ASSERT_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h index 310a2f080c..edda4b9eec 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h @@ -35,8 +35,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_H -#define __STM32L4xx_HAL_H +#ifndef STM32L4xx_HAL_H +#define STM32L4xx_HAL_H #ifdef __cplusplus extern "C" { @@ -62,7 +62,7 @@ /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_MAINFLASH 0U #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ @@ -72,7 +72,7 @@ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) @@ -188,8 +188,8 @@ /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ /** * @} @@ -198,8 +198,8 @@ /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance * @{ */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ /** * @} @@ -222,7 +222,7 @@ */ /** @brief Fast-mode Plus driving capability on a specific GPIO - */ + */ #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) @@ -491,16 +491,16 @@ * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of : + * @param __FASTMODEPLUS__ This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 - * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 */ @@ -533,7 +533,7 @@ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) -#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) +#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ @@ -542,7 +542,7 @@ #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) -#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) #endif /* VREFBUF */ #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) @@ -566,6 +566,16 @@ * @} */ +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions @@ -664,6 +674,6 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); } #endif -#endif /* __STM32L4xx_HAL_H */ +#endif /* STM32L4xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h index 6d137f361d..556bad3cca 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h @@ -131,7 +131,7 @@ typedef struct uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ - uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun @@ -143,7 +143,7 @@ typedef struct use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ - uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ @@ -153,7 +153,7 @@ typedef struct Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. @@ -172,7 +172,7 @@ typedef struct If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ @@ -188,7 +188,7 @@ typedef struct overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ - uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ @@ -284,20 +284,28 @@ typedef struct For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ - uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ }ADC_AnalogWDGConfTypeDef; /** @@ -322,37 +330,37 @@ typedef struct * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ @@ -460,10 +468,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ - -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ /** * @} */ @@ -491,8 +495,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ -#define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ /** * @} */ @@ -525,10 +529,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ @@ -647,7 +651,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ @@ -785,15 +789,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) - /** * @brief Return resolution bits in CFGR register RES[1:0] field. * @param __HANDLE__ ADC handle @@ -822,7 +817,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Check if conversion is on going on regular group. * @param __HANDLE__ ADC handle - * @retval SET (conversion is on going) or RESET (no conversion is on going) + * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) @@ -842,26 +837,23 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ -#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) ) +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) /** * @brief Verify the length of the scheduled regular conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ -#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U))) +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. * @param NUMBER number of scheduled regular conversions in discontinuous mode. - * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) + * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) /** @@ -1035,7 +1027,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ @@ -1526,7 +1518,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) + * @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield) */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h index 4571da5f9e..1677965201 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h @@ -92,7 +92,7 @@ typedef struct Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. - This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS. + This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ @@ -136,7 +136,7 @@ typedef struct Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. @@ -146,7 +146,7 @@ typedef struct Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) @@ -155,7 +155,7 @@ typedef struct Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. + FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function @@ -178,9 +178,9 @@ typedef struct Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. @@ -248,7 +248,7 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ @@ -277,7 +277,7 @@ typedef struct * @} */ -/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks +/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ @@ -304,7 +304,7 @@ typedef struct /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ -#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** @@ -403,7 +403,7 @@ typedef struct /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} @@ -421,7 +421,7 @@ typedef struct * @{ */ -/** @brief Force ADC instance in multimode mode independant (multimode disable). +/** @brief Force ADC instance in multimode mode independent (multimode disable). * @note This macro must be used only in case of transition from multimode * to mode independent and in case of unknown previous state, * to ensure ADC configuration is in mode independent. @@ -458,21 +458,21 @@ typedef struct * @retval SET (software start) or RESET (external trigger). */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) + (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) /** * @brief Check if conversion is on going on regular or injected groups. * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ -#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ +#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ + (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ ) ? RESET : SET) /** * @brief Check if conversion is on going on injected group. * @param __HANDLE__ ADC handle. - * @retval SET (conversion is on going) or RESET (no conversion is on going). + * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) @@ -493,12 +493,14 @@ typedef struct ) #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /** * @brief Set the selected injected Channel rank. * @param __CHANNELNB__ Channel number. - * @param __RANKNB__ Rank number. + * @param __RANKNB__ Rank number. * @retval None */ #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -529,7 +531,7 @@ typedef struct * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos) +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. @@ -564,7 +566,7 @@ typedef struct * @param __CHANNEL__ ADC Channel. * @retval None */ -#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) +#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) /** * @brief Configure calibration factor in differential mode to be set into calibration register. @@ -585,7 +587,7 @@ typedef struct * @param __THRESHOLD__ Threshold value. * @retval None */ -#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) +#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -595,45 +597,6 @@ typedef struct */ #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) #endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @brief Enable the ADC peripheral. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) - -/** - * @brief Verification of hardware constraints before ADC can be enabled. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) - */ -#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \ - ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ - ) == RESET \ - ) ? SET : RESET) - -/** - * @brief Disable the ADC peripheral. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#define ADC_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ - __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ - } while(0) - -/** - * @brief Verification of hardware constraints before ADC can be disabled. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) - */ -#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ - ) ? SET : RESET) /** * @brief Shift the offset with respect to the selected ADC resolution. @@ -648,8 +611,7 @@ typedef struct * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ - ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) - + ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. @@ -664,7 +626,7 @@ typedef struct * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) + ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. @@ -677,29 +639,11 @@ typedef struct * @param __THRESHOLD__ Value to be shifted * @retval None */ -#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ - ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ - (__THRESHOLD__) << 2 ) - -/** - * @brief Report Master Instance. - * @param __HANDLE__ ADC handle. - * @note Return same instance if ADC of input handle is independent ADC or if - * multimode feature is not available. - * @retval Master Instance - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MASTER_REGISTER(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ - )? \ - ((__HANDLE__)->Instance) \ - : \ - (ADC1) \ +#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ + ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ + ((__THRESHOLD__) << 2UL) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) -#endif /** * @brief Clear Common Control Register. @@ -725,132 +669,7 @@ typedef struct #endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @brief Check whether or not dual conversions are enabled. - * @param __HANDLE__ ADC handle. - * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. - * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) - */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ - )? \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \ - : \ - RESET \ - ) -#else -#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - -/** - * @brief Check whether or not dual regular conversions are enabled. - * @param __HANDLE__ ADC handle. - * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. - * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) - */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ - )? \ - ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ - (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ - (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ - : \ - RESET \ - ) -#else -#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - -/** - * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) -#endif - -/** - * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) -#endif - -/** - * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) -#endif - -/** - * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. - * @param __INSTANCE__ ADC instance. - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ - (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ - ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ - ) ? SET : RESET) - -/** - * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. - * @param __HANDLE__ ADC handle. - * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) \ - )? \ - (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ - : \ - ( ( ((__HANDLE__)->Instance == ADC2) \ - )? \ - (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ - : \ - ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -860,28 +679,15 @@ typedef struct */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ +#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ -/** - * @brief Check whether or not multimode is configured in DMA mode. - * @param __HANDLE__ ADC handle. - * @note Return RESET if multimode feature is not available. - * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \ - ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ - || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET) -#endif /** * @brief Verify the ADC instance connected to the temperature sensor. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* The temperature sensor measurement path (channel 17) is available on ADC1 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) @@ -894,7 +700,7 @@ typedef struct * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* The battery voltage measurement path (channel 18) is available on ADC1 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) @@ -956,7 +762,43 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) ))) +#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1025,7 +867,7 @@ typedef struct * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1281,7 +1123,7 @@ typedef struct #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) -#else +#else #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) #endif @@ -1296,7 +1138,7 @@ typedef struct #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) #else -#define ADC_CFGR_DFSDM(__HANDLE__) (0x0) +#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) #endif /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h index 445c2c4ebc..cc932c2b3e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h @@ -810,7 +810,9 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) #define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#if defined(CAN2) #define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#endif #define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h index bb5a94ae71..e21411197a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h @@ -65,13 +65,15 @@ extern "C" { typedef struct { +#if defined(COMP2) uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ +#endif /* COMP2 */ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. - Note: For the characteritics of comparator power modes + Note: For the characteristics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of @ref COMP_PowerMode */ @@ -156,30 +158,32 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Error_Code COMP Error Code * @{ */ -#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) -#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */ +#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */ #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @} */ +#if defined(COMP2) /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ /** * @} */ +#endif /** @defgroup COMP_PowerMode COMP power mode * @{ */ -/* Note: For the characteritics of comparator power modes */ +/* Note: For the characteristics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< High Speed */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ #define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ #define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */ /** @@ -189,7 +193,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_InputPlus COMP input plus (non-inverting input) * @{ */ -#define COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -223,7 +227,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ #define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -234,7 +238,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_OutputPolarity COMP output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ #define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ /** * @} @@ -243,7 +247,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_BlankingSrce COMP blanking source * @{ */ -#define COMP_BLANKINGSRC_NONE (0x00000000U) /*!State = HAL_COMP_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -443,6 +447,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1) +#if defined(COMP2) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None @@ -527,6 +532,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2) +#endif /* COMP2 */ /** * @} */ @@ -546,7 +552,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @{ */ #define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output */ +#if defined(COMP2) #define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ @@ -554,10 +562,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_IT (0x01U) /*!< EXTI line event with interruption */ -#define COMP_EXTI_EVENT (0x02U) /*!< EXTI line event only (without interruption) */ -#define COMP_EXTI_RISING (0x10U) /*!< EXTI line event on rising edge */ -#define COMP_EXTI_FALLING (0x20U) /*!< EXTI line event on falling edge */ +#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */ /** * @} */ @@ -579,8 +587,12 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ +#if defined(COMP2) #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ : COMP_EXTI_LINE_COMP2) +#else +#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1 +#endif /* COMP2 */ /** * @} */ @@ -588,8 +600,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters * @{ */ +#if defined(COMP2) #define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) ) +#endif #define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ @@ -658,6 +672,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ ((__POL__) == COMP_OUTPUTPOL_INVERTED)) +#if defined(COMP2) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ @@ -667,7 +682,24 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ ) +#else +#if defined(TIM3) +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) +#else +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + ) +#endif /* TIM3 */ +#endif /* COMP2 */ +#if defined(COMP2) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ @@ -680,7 +712,22 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - +#else +#if defined(TIM3) + #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) +#else + #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) )) +#endif /* TIM3 */ +#endif /* COMP2 */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h index 7e26da71bc..2e13a3d1a9 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h @@ -36,8 +36,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H +#ifndef STM32L4xx_HAL_CONF_H +#define STM32L4xx_HAL_CONF_H #ifdef __cplusplus extern "C" { @@ -469,7 +469,7 @@ } #endif -#endif /* __STM32L4xx_HAL_CONF_H */ +#endif /* STM32L4xx_HAL_CONF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h index 6f3eb3e872..cd509e6c96 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h @@ -41,8 +41,6 @@ extern "C" { #endif -#if defined(AES) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -50,6 +48,8 @@ * @{ */ +#if defined(AES) + /** @addtogroup CRYP * @{ */ @@ -734,12 +734,12 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); * @} */ +#endif /* AES */ + /** * @} */ - -#endif /* AES */ - + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h index ba2c7951a7..d3b2de1008 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2016 STMicroelectronics

          + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -34,20 +34,21 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DAC_H -#define __STM32L4xx_HAL_DAC_H +#ifndef STM32L4xx_HAL_DAC_H +#define STM32L4xx_HAL_DAC_H #ifdef __cplusplus extern "C" { #endif +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ +#if defined(DAC1) /** @addtogroup DAC * @{ @@ -64,18 +65,22 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; /** * @brief DAC handle Structure definition */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) typedef struct __DAC_HandleTypeDef +#else +typedef struct DAC_HandleTypeDef +#endif { DAC_TypeDef *Instance; /*!< Register base address */ @@ -214,53 +219,52 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ +#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -272,8 +276,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) -#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1) +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) /** * @} @@ -282,11 +286,11 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_1 0x00000000U #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_2 0x00000010U #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -298,9 +302,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_data_alignment DAC data alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U /** * @} @@ -309,8 +313,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_flags_definition DAC flags definition * @{ */ -#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} @@ -319,8 +323,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_IT_definition DAC IT definition * @{ */ -#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} @@ -329,8 +333,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000) -#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0) +#define DAC_CHIPCONNECT_DISABLE 0x00000000U +#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) /** * @} @@ -340,8 +344,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ -#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ -#define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */ +#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ +#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ /** * @} @@ -350,8 +354,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ -#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000) -#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2) +#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U +#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) /** * @} @@ -380,7 +384,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); */ /** @brief Reset DAC handle state. - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -394,42 +398,42 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** @brief Enable the DAC channel. - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) +((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Disable the DAC channel. - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) +((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Set DHR12R1 alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt. - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -438,8 +442,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt. - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -448,8 +452,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not. - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -458,8 +462,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to get. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag @@ -468,8 +472,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag @@ -506,9 +510,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) -#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) /** * @} @@ -594,6 +598,8 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); * @} */ +#endif /* DAC1 */ + /** * @} */ @@ -603,7 +609,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); #endif -#endif /*__STM32L4xx_HAL_DAC_H */ +#endif /*STM32L4xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h index 13e1680151..120fea6944 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h @@ -34,20 +34,22 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DAC_EX_H -#define __STM32L4xx_HAL_DAC_EX_H +#ifndef STM32L4xx_HAL_DAC_EX_H +#define STM32L4xx_HAL_DAC_EX_H #ifdef __cplusplus extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(DAC1) + /** @addtogroup DACEx * @{ */ @@ -67,30 +69,30 @@ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ +#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ /** * @} @@ -158,17 +160,16 @@ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF) +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) -#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF) +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) +#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) -#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) - -#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) +#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \ ((CONNECT) == DAC_CHIPCONNECT_ENABLE)) @@ -200,9 +201,6 @@ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) - - - /** * @} */ @@ -226,6 +224,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -240,8 +239,6 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue); /** * @} @@ -252,14 +249,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe */ /* Peripheral Control functions ***********************************************/ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ - /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); /** @@ -294,6 +285,8 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); * @} */ +#endif /* DAC1 */ + /** * @} */ @@ -302,6 +295,6 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); } #endif -#endif /*__STM32L4xx_HAL_DAC_EX_H */ +#endif /*STM32L4xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h index 7f128df3a7..179c671bff 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h @@ -452,8 +452,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); * @retval The state of FLAG. */ #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ -((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ - (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) + ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ + (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) /** * @brief Clear the DCMI pending flag. @@ -533,7 +533,7 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); /* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ @@ -595,8 +595,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /** @defgroup DCMI_Registers_Indices DCMI Registers Indices * @{ */ -#define DCMI_MIS_INDEX ((uint32_t)0x1000U) /*!< DCMI MIS register index */ -#define DCMI_SR_INDEX ((uint32_t)0x2000U) /*!< DCMI SR register index */ +#define DCMI_MIS_INDEX (0x1000U) /*!< DCMI MIS register index */ +#define DCMI_SR_INDEX (0x2000U) /*!< DCMI SR register index */ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h index dec652bcc3..a236557298 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h @@ -35,8 +35,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DEF -#define __STM32L4xx_HAL_DEF +#ifndef STM32L4xx_HAL_DEF_H +#define STM32L4xx_HAL_DEF_H #ifdef __cplusplus extern "C" { @@ -45,7 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx.h" #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ -#include +#include /* Exported types ------------------------------------------------------------*/ @@ -208,6 +208,6 @@ typedef enum } #endif -#endif /* ___STM32L4xx_HAL_DEF */ +#endif /* STM32L4xx_HAL_DEF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h index 0aa5c85b2e..54986d32f3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_H -#define __STM32L4xx_HAL_DMA_H +#ifndef STM32L4xx_HAL_DMA_H +#define STM32L4xx_HAL_DMA_H #ifdef __cplusplus extern "C" { @@ -367,9 +367,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** * @} */ @@ -377,9 +377,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** * @} */ @@ -387,8 +387,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ /** * @} */ @@ -396,10 +396,10 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Priority_level DMA Priority level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ /** * @} */ @@ -408,9 +408,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE /** * @} */ @@ -418,34 +418,34 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL1 DMA_ISR_GIF1 +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA_FLAG_GL2 DMA_ISR_GIF2 +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA_FLAG_GL3 DMA_ISR_GIF3 +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 +#define DMA_FLAG_GL4 DMA_ISR_GIF4 +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 +#define DMA_FLAG_GL5 DMA_ISR_GIF5 +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 +#define DMA_FLAG_GL6 DMA_ISR_GIF6 +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 +#define DMA_FLAG_GL7 DMA_ISR_GIF7 +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /** * @} */ @@ -761,6 +761,6 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); } #endif -#endif /* __STM32L4xx_HAL_DMA_H */ +#endif /* STM32L4xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h index 24071abfad..e4ba87e622 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_EX_H -#define __STM32L4xx_HAL_DMA_EX_H +#ifndef STM32L4xx_HAL_DMA_EX_H +#define STM32L4xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { @@ -253,7 +253,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) -#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ @@ -267,12 +267,12 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT) -#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) -#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) /** * @} @@ -293,6 +293,6 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); } #endif -#endif /* __STM32L4xx_HAL_DMA_H */ +#endif /* STM32L4xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h new file mode 100644 index 0000000000..3e017f22b4 --- /dev/null +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h @@ -0,0 +1,876 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_EXTI_H +#define STM32L4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L412xx || STM32L422xx */ + +#if defined(STM32L431xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L431xx */ + +#if defined(STM32L432xx) || defined(STM32L442xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L432xx || STM32L442xx */ + +#if defined(STM32L433xx) || defined(STM32L443xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L433xx || STM32L443xx */ + +#if defined(STM32L451xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L451xx */ + +#if defined(STM32L452xx) || defined(STM32L462xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L452xx || STM32L462xx */ + +#if defined(STM32L471xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L471xx */ + +#if defined(STM32L475xx) || defined(STM32L485xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L475xx || STM32L485xx */ + +#if defined(STM32L476xx) || defined(STM32L486xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L476xx || STM32L486xx */ + +#if defined(STM32L496xx) || defined(STM32L4A6xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L496xx || STM32L4A6xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000005u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOI 0x00000008u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28u +#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 41u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L412xx || STM32L422xx */ + +#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L431xx || STM32L433xx || STM32L443xx */ + +#if defined(STM32L432xx) || defined(STM32L442xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L432xx || STM32L442xx */ + +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ + +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ + +#if defined(STM32L496xx) || defined(STM32L4A6xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) + +#endif /* STM32L496xx || STM32L4A6xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h index fc6c2f2797..865c637281 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h @@ -50,7 +50,7 @@ /** @addtogroup FLASH * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types @@ -61,17 +61,17 @@ * @brief FLASH Erase structure definition */ typedef struct -{ +{ uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ uint32_t Banks; /*!< Select bank to erase. - This parameter must be a value of @ref FLASH_Banks - (FLASH_BANK_BOTH should be used only for mass erase) */ + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled - This parameter must be a value between 0 and (max number of pages in the bank - 1) + This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 255 for 1MB dual bank) */ uint32_t NbPages; /*!< Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ + This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ } FLASH_EraseInitTypeDef; /** @@ -96,16 +96,16 @@ typedef struct uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, - @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, - @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, - @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, + @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). - This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) + This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */ uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). - This parameter must be a value between begin and end of bank + This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address */ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank */ @@ -114,7 +114,7 @@ typedef struct /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, @@ -126,7 +126,7 @@ typedef enum /** * @brief FLASH Cache structure definition */ -typedef enum +typedef enum { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, @@ -134,8 +134,8 @@ typedef enum FLASH_CACHE_ICACHE_DCACHE_ENABLED } FLASH_CacheTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { @@ -160,7 +160,7 @@ typedef struct /** @defgroup FLASH_Error FLASH Error * @{ - */ + */ #define HAL_FLASH_ERROR_NONE 0x00000000U #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR @@ -173,18 +173,18 @@ typedef struct #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ + defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY -#endif +#endif /** * @} */ /** @defgroup FLASH_Type_Erase FLASH Erase Type * @{ - */ + */ #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!> 24) /*!< ECC Correction Interrupt source */ /** * @} - */ + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features + * @brief macros to control FLASH features * @{ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__: FLASH Latency * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @retval None - */ + */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states - */ + */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) /** * @brief Enable the FLASH prefetch buffer. * @retval None - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** @@ -614,30 +614,30 @@ typedef struct /** * @brief Enable the FLASH instruction cache. * @retval none - */ + */ #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Disable the FLASH instruction cache. * @retval none - */ + */ #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Enable the FLASH data cache. * @retval none - */ + */ #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Disable the FLASH data cache. * @retval none - */ + */ #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Reset the FLASH instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. + * @note This function must be used only when the Instruction Cache is disabled. * @retval None */ #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ @@ -646,7 +646,7 @@ typedef struct /** * @brief Reset the FLASH data Cache. - * @note This function must be used only when the data Cache is disabled. + * @note This function must be used only when the data Cache is disabled. * @retval None */ #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ @@ -676,48 +676,48 @@ typedef struct /** * @brief Enable the FLASH power down during Low-Power sleep mode * @retval none - */ + */ #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @brief Disable the FLASH power down during Low-Power sleep mode * @retval none - */ + */ #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @} - */ + */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros * @brief macros to handle FLASH interrupts * @{ - */ + */ /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt + * @param __INTERRUPT__: FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none - */ + */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt + * @param __INTERRUPT__: FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none - */ + */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) @@ -729,7 +729,7 @@ typedef struct * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag @@ -737,7 +737,7 @@ typedef struct * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected @@ -754,7 +754,7 @@ typedef struct * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag @@ -772,13 +772,13 @@ typedef struct } while(0) /** * @} - */ + */ /* Include FLASH HAL Extended module */ #include "stm32l4xx_hal_flash_ex.h" #include "stm32l4xx_hal_flash_ramfunc.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uin HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** @@ -830,13 +830,16 @@ uint32_t HAL_FLASH_GetError(void); * @{ */ #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) - + #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x800U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) #else #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x400U << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) @@ -861,14 +864,14 @@ uint32_t HAL_FLASH_GetError(void); /** * @} */ - + /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -887,7 +890,7 @@ uint32_t HAL_FLASH_GetError(void); #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) + ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) @@ -896,7 +899,7 @@ uint32_t HAL_FLASH_GetError(void); ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ - ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) + ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) #endif #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) @@ -971,16 +974,16 @@ uint32_t HAL_FLASH_GetError(void); #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) -#endif - +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ + defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) @@ -1008,19 +1011,19 @@ uint32_t HAL_FLASH_GetError(void); #endif /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h index c840c5c287..815a448ca3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h @@ -74,7 +74,7 @@ typedef struct uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed */ - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ }GPIO_InitTypeDef; @@ -83,7 +83,7 @@ typedef struct */ typedef enum { - GPIO_PIN_RESET = 0, + GPIO_PIN_RESET = 0U, GPIO_PIN_SET }GPIO_PinState; /** @@ -115,7 +115,7 @@ typedef enum #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ /** * @} */ @@ -130,19 +130,19 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ -#define GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B) /*!< Analog Mode for ADC conversion */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG_ADC_CONTROL (0x0000000Bu) /*!< Analog Mode for ADC conversion */ +#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -151,10 +151,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 5 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< range up to 5 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ /** * @} */ @@ -163,9 +163,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ /** * @} */ @@ -178,7 +178,7 @@ typedef enum /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ - + /** * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. @@ -229,8 +229,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ @@ -261,16 +261,16 @@ typedef enum /* Include GPIO HAL Extended module */ #include "stm32l4xx_hal_gpio_ex.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @{ */ - + /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); @@ -279,10 +279,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @} */ -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); @@ -301,12 +301,12 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h index 335859e30b..ad5c9c142b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h @@ -63,6 +63,100 @@ * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +/*--------------STM32L412xx/STM32L422xx---*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ + + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* STM32L412xx || STM32L422xx */ + #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) /*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/ /** @@ -730,69 +824,78 @@ /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL : 7uL) + +#endif /* STM32L412xx || STM32L422xx */ + #if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 7uL) #endif /* STM32L431xx || STM32L433xx || STM32L443xx */ #if defined(STM32L432xx) || defined(STM32L442xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL : 7uL) #endif /* STM32L432xx || STM32L442xx */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 7uL) #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL : 7uL) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ #if defined(STM32L496xx) || defined(STM32L4A6xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL :\ + ((__GPIOx__) == (GPIOH))? 7uL : 8uL) #endif /* STM32L496xx || STM32L4A6xx */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL :\ + ((__GPIOx__) == (GPIOH))? 7uL : 8uL) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h index f7747aac6c..60bd8f5997 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h @@ -34,22 +34,20 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_HASH_H -#define __STM32L4xx_HAL_HASH_H +#ifndef STM32L4xx_HAL_HASH_H +#define STM32L4xx_HAL_HASH_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - +#if defined (HASH) /** @addtogroup HASH * @{ */ @@ -78,12 +76,12 @@ typedef struct */ typedef enum { - HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_HASH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */ - HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */ - HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */ - HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */ + HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ + HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ + HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ + HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ }HAL_HASH_StateTypeDef; /** @@ -91,13 +89,13 @@ typedef enum */ typedef enum { - HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */ - HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in HASH processing phase */ - HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, /*!< HASH peripheral is in HMAC step 1 processing phase + HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ + HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ + HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase (step 1 consists in entering the inner hash function key) */ - HAL_HASH_PHASE_HMAC_STEP_2 = 0x04, /*!< HASH peripheral is in HMAC step 2 processing phase + HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase (step 2 consists in entering the message text) */ - HAL_HASH_PHASE_HMAC_STEP_3 = 0x05 /*!< HASH peripheral is in HMAC step 3 processing phase + HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key) */ }HAL_HASH_PhaseTypeDef; @@ -106,11 +104,11 @@ typedef enum */ typedef enum { - HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */ - HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */ + HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ + HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ }HAL_HASH_SuspendTypeDef; -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) /** * @brief HAL HASH common Callback ID enumeration definition */ @@ -180,7 +178,7 @@ typedef struct __HASH_HandleTypeDef #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ } HASH_HandleTypeDef; -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) /** * @brief HAL HASH Callback pointer definition */ @@ -200,10 +198,10 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_Algo_Selection HASH algorithm selection * @{ */ -#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ #define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ -#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ /** * @} */ @@ -211,7 +209,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_Algorithm_Mode HASH algorithm mode * @{ */ -#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ +#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */ #define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ /** * @} @@ -220,7 +218,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_Data_Type HASH input data type * @{ */ -#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ +#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */ #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ #define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ @@ -231,7 +229,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type * @{ */ -#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */ +#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */ #define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */ /** * @} @@ -259,7 +257,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** * @} */ - /** @defgroup HASH_alias HASH API alias * @{ */ @@ -268,15 +265,14 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @} */ - /** @defgroup HASH_Error_Definition HASH Error Definition * @{ */ -#define HAL_HASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_HASH_ERROR_IT ((uint32_t)0x00000001U) /*!< IT-based process error */ -#define HAL_HASH_ERROR_DMA ((uint32_t)0x00000002U) /*!< DMA-based process error */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -#define HAL_HASH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid Callback error */ +#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */ +#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */ #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /** * @} @@ -370,7 +366,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer #define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) - /** * @brief Start the digest computation. * @retval None @@ -382,7 +377,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__: size in bytes of last data written in Data register. * @retval None */ -#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4)) +#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) /** * @brief Reset the HASH core. @@ -399,20 +394,18 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_Private_Macros HASH Private Macros * @{ */ - /** * @brief Return digest length in bytes. * @retval Digest length */ -#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20 : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28 : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32 : 16 ) ) ) - +#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) /** * @brief Return number of words already pushed in the FIFO. * @retval Number of words already pushed in the FIFO */ -#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8) +#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U) /** * @brief Ensure that HASH input data type is valid. @@ -433,8 +426,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0) - +#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U) /** * @brief Ensure that input data buffer size is valid for multi-buffer HASH * processing in DMA mode. @@ -442,7 +434,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0)) +#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that input data buffer size is valid for multi-buffer HMAC @@ -452,8 +444,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0)) - +#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that handle phase is set to HASH processing. * @param __HANDLE__: HASH handle. @@ -474,7 +465,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @} */ - /* Include HASH HAL Extended module */ #include "stm32l4xx_hal_hash_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -627,18 +617,17 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} */ - +#endif /* HASH*/ /** * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_HASH_H */ +#endif /* STM32L4xx_HAL_HASH_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h index 1e34c3b1a6..86386ae1d4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h @@ -34,22 +34,20 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_HASH_EX_H -#define __STM32L4xx_HAL_HASH_EX_H +#ifndef STM32L4xx_HAL_HASH_EX_H +#define STM32L4xx_HAL_HASH_EX_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - +#if defined (HASH) /** @addtogroup HASHEx * @{ */ @@ -143,7 +141,6 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -151,7 +148,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - /** * @} */ @@ -163,18 +159,17 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} */ - +#endif /* HASH*/ /** * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_HASH_EX_H */ +#endif /* STM32L4xx_HAL_HASH_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h index 28dadb5e31..4fc93ac750 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h @@ -536,6 +536,7 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __FLAG__ (SET or RESET). */ +#define I2C_FLAG_MASK (0x0001FFFFU) #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. @@ -749,11 +750,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) @@ -763,6 +764,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h index 119e9ffbad..a1b18b516b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_IRDA_H -#define __STM32L4xx_HAL_IRDA_H +#ifndef STM32L4xx_HAL_IRDA_H +#define STM32L4xx_HAL_IRDA_H #ifdef __cplusplus extern "C" { @@ -95,8 +95,8 @@ typedef struct } IRDA_InitTypeDef; /** - * @brief HAL IRDA State structures definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. + * @brief HAL IRDA State definition + * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -133,44 +133,29 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -} HAL_IRDA_StateTypeDef; +typedef uint32_t HAL_IRDA_StateTypeDef; /** * @brief IRDA clock sources definition */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ } IRDA_ClockSourceTypeDef; /** * @brief IRDA handle Structure definition */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) typedef struct __IRDA_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ { USART_TypeDef *Instance; /*!< USART registers base address */ @@ -257,19 +242,6 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ -/** - * @brief IRDA Configuration enumeration values definition - */ -typedef enum -{ - IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */ - IRDA_PARITY = 0x01U, /*!< IRDA frame parity */ - IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */ - IRDA_MODE = 0x03U, /*!< IRDA communication mode */ - IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */ - IRDA_POWERMODE = 0x05U /*!< IRDA power mode */ -} IRDA_ControlTypeDef; - /** * @} */ @@ -279,6 +251,30 @@ typedef enum * @{ */ +/** @defgroup IRDA_State_Definition IRDA State Code Definition + * @{ + */ +#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ @@ -489,7 +485,11 @@ typedef enum /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask * @{ */ -#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */ +#define IRDA_CR_POS 5U /*!< IRDA control register position */ +#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */ +#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */ /** * @} */ @@ -610,9 +610,9 @@ typedef enum * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -626,9 +626,9 @@ typedef enum * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. @@ -645,7 +645,7 @@ typedef enum * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -659,9 +659,9 @@ typedef enum * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -763,19 +763,23 @@ typedef enum (__HANDLE__)->Mask = 0x003F ; \ } \ } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ } while(0) /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) /** * @brief Ensure that IRDA frame length is valid. @@ -976,6 +980,6 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); } #endif -#endif /* __STM32L4xx_HAL_IRDA_H */ +#endif /* STM32L4xx_HAL_IRDA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h index c9d2fac7fe..599444bf9a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_IRDA_EX_H -#define __STM32L4xx_HAL_IRDA_EX_H +#ifndef STM32L4xx_HAL_IRDA_EX_H +#define STM32L4xx_HAL_IRDA_EX_H #ifdef __cplusplus extern "C" { @@ -178,8 +178,12 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) +#elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -245,6 +249,10 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #elif defined (STM32L432xx) || defined (STM32L442xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -291,6 +299,10 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -379,6 +391,10 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #endif @@ -400,6 +416,6 @@ extern "C" { } #endif -#endif /* __STM32L4xx_HAL_IRDA_EX_H */ +#endif /* STM32L4xx_HAL_IRDA_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h index 4c87ae7f05..7b99b069c1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h @@ -52,13 +52,13 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types * @{ */ -/** - * @brief LPTIM Clock configuration definition +/** + * @brief LPTIM Clock configuration definition */ typedef struct { @@ -67,11 +67,11 @@ typedef struct uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. This parameter can be a value of @ref LPTIM_Clock_Prescaler */ - + }LPTIM_ClockConfigTypeDef; -/** - * @brief LPTIM Clock configuration definition +/** + * @brief LPTIM Clock configuration definition */ typedef struct { @@ -80,88 +80,97 @@ typedef struct Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. - This parameter can be a value of @ref LPTIM_Clock_Polarity */ - + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. - This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ - + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ + }LPTIM_ULPClockConfigTypeDef; -/** - * @brief LPTIM Trigger configuration definition +/** + * @brief LPTIM Trigger configuration definition */ typedef struct { uint32_t Source; /*!< Selects the Trigger source. This parameter can be a value of @ref LPTIM_Trigger_Source */ - + uint32_t ActiveEdge; /*!< Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ - + uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. - This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ }LPTIM_TriggerConfigTypeDef; -/** - * @brief LPTIM Initialization Structure definition +/** + * @brief LPTIM Initialization Structure definition */ typedef struct -{ +{ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ - + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - + uint32_t OutputPolarity; /*!< Specifies the Output polarity. This parameter can be a value of @ref LPTIM_Output_Polarity */ - + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of @ref LPTIM_Updating_Mode */ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + This parameter can be a value of @ref LPTIM_Counter_Source */ uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). - This parameter can be a value of @ref LPTIM_Input1_Source */ + This parameter can be a value of @ref LPTIM_Input1_Source */ uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). - Note: This parameter is used only for encoder feature so is used only + Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. - This parameter can be a value of @ref LPTIM_Input2_Source */ - + This parameter can be a value of @ref LPTIM_Input2_Source */ + +#if defined(LPTIM_RCR_REP) + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + Note: When using repetition counter the UpdateMode field must be set to + LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable bahavior may occur. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ +#endif + }LPTIM_InitTypeDef; -/** - * @brief HAL LPTIM State structure definition - */ +/** + * @brief HAL LPTIM State structure definition + */ typedef enum __HAL_LPTIM_StateTypeDef { HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ + HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ }HAL_LPTIM_StateTypeDef; -/** - * @brief LPTIM handle Structure definition - */ +/** + * @brief LPTIM handle Structure definition + */ typedef struct __LPTIM_HandleTypeDef { LPTIM_TypeDef *Instance; /*!< Register base address */ - + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ - - HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ - + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ - + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) @@ -174,6 +183,10 @@ typedef struct __LPTIM_HandleTypeDef void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ +#if defined(LPTIM_RCR_REP) + void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter underflow Callback */ + void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter successful write Callback */ +#endif /* LPTIM_RCR_REP */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ }LPTIM_HandleTypeDef; @@ -192,6 +205,10 @@ typedef enum HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ +#if defined(LPTIM_RCR_REP) + HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Repetition counter underflow Callback ID */ + HAL_LPTIM_REPETITION_WRITE_CB_ID = 0x0AU, /*!< Repetition counter successful write Callback ID */ +#endif /* LPTIM_RCR_REP */ } HAL_LPTIM_CallbackIDTypeDef; /** @@ -214,7 +231,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL -/** +/** * @} */ @@ -231,7 +248,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin #define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) /** * @} - */ + */ /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity * @{ @@ -320,7 +337,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** * @} */ - + /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source * @{ */ @@ -346,7 +363,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition * @{ */ - +#if defined(LPTIM_RCR_REP) +#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK +#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE +#endif #define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN #define LPTIM_FLAG_UP LPTIM_ISR_UP #define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK @@ -361,7 +381,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition * @{ */ - +#if defined(LPTIM_RCR_REP) +#define LPTIM_IT_REPOK LPTIM_IER_REPOKIE +#define LPTIM_IT_UPDATE LPTIM_IER_UEIE +#endif #define LPTIM_IT_DOWN LPTIM_IER_DOWNIE #define LPTIM_IT_UP LPTIM_IER_UPIE #define LPTIM_IT_ARROK LPTIM_IER_ARROKIE @@ -412,13 +435,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin /** * @brief Start the LPTIM peripheral in Continuous or in single mode. - * @param __HANDLE__: DMA handle + * @param __HANDLE__: LPTIM handle * @retval None */ #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) #define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) - - + + /** * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__: LPTIM handle @@ -435,11 +458,34 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) +#if defined(LPTIM_RCR_REP) +/** + * @brief Write the passed parameter in the Repetition register. + * @param __HANDLE__: LPTIM handle + * @param __VALUE__: Repetition value + * @retval None + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) \ + do { \ + (__HANDLE__)->Instance->RCR = (__VALUE__); \ + (__HANDLE__)->Init.RepetitionCounter = (__VALUE__); \ + } while(0) + +/** + * @brief Return the current Repetition value. + * @param __HANDLE__: LPTIM handle + * @retval Repetition register value + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR) +#endif + /** * @brief Check whether the specified LPTIM flag is set or not. * @param __HANDLE__: LPTIM handle * @param __FLAG__: LPTIM flag to check * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag (when available). + * @arg LPTIM_FLAG_UPDATE : Update event Flag (when available). * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. @@ -456,6 +502,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__: LPTIM handle. * @param __FLAG__: LPTIM flag to clear. * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag (when available). + * @arg LPTIM_FLAG_UPDATE : Update event Flag (when available). * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. @@ -472,6 +520,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__: LPTIM handle. * @param __INTERRUPT__: LPTIM interrupt to set. * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update Interrupt (when available). + * @arg LPTIM_IT_UPDATE : Update event Interrupt (when available). * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. @@ -513,13 +563,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval Interrupt status. */ - + #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions * @{ @@ -598,6 +648,10 @@ void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +#if defined(LPTIM_RCR_REP) +void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); +#endif /* LPTIM_RCR_REP */ /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) @@ -611,7 +665,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** * @} */ - + /* Private types -------------------------------------------------------------*/ /** @defgroup LPTIM_Private_Types LPTIM Private Types * @{ @@ -625,7 +679,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Variables LPTIM Private Variables * @{ */ - + /** * @} */ @@ -643,11 +697,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Macros LPTIM Private Macros * @{ */ - + #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) - + #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ @@ -704,6 +758,10 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF) +#if defined(LPTIM_RCR_REP) +#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FF) +#endif + #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) && \ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ @@ -722,7 +780,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup LPTIM_Private_Functions LPTIM Private Functions diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h index b0df3d1746..44813f2fea 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h @@ -30,17 +30,17 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OPAMP_H -#define __STM32L4xx_HAL_OPAMP_H +#ifndef STM32L4xx_HAL_OPAMP_H +#define STM32L4xx_HAL_OPAMP_H #ifdef __cplusplus extern "C" { #endif - + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -50,18 +50,18 @@ /** @addtogroup OPAMP * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Types OPAMP Exported Types * @{ */ -/** - * @brief OPAMP Init structure definition +/** + * @brief OPAMP Init structure definition */ - + typedef struct { uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V. @@ -70,89 +70,93 @@ typedef struct uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. This parameter must be a value of @ref OPAMP_PowerMode */ - + uint32_t Mode; /*!< Specifies the OPAMP mode - This parameter must be a value of @ref OPAMP_Mode + This parameter must be a value of @ref OPAMP_Mode mode is either Standalone, - Follower or PGA */ - + uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & PGA modes - In Standalone mode: i.e. when mode is OPAMP_STANDALONE_MODE & PGA mode: i.e. when mode is OPAMP_PGA_MODE - This parameter must be a value of @ref OPAMP_InvertingInput + This parameter must be a value of @ref OPAMP_InvertingInput - In Follower mode i.e. when mode is OPAMP_FOLLOWER_MODE - This parameter is Not Applicable */ + This parameter is Not Applicable */ - uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: - This parameter must be a value of @ref OPAMP_NonInvertingInput */ - - uint32_t PgaGain; /*!< Specifies the gain in PGA mode - i.e. when mode is OPAMP_PGA_MODE. + uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: + This parameter must be a value of @ref OPAMP_NonInvertingInput */ + + uint32_t PgaGain; /*!< Specifies the gain in PGA mode + i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */ - - uint32_t UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref OPAMP_UserTrimming + + uint32_t UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref OPAMP_UserTrimming UserTrimming is either factory or user trimming.*/ - + uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ - + uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ - + uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ }OPAMP_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPAMP is not yet Initialized */ - + HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */ - - HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ + + HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005 /*!< OPAMP is locked only system reset allows reconfiguring the opamp. */ - + }HAL_OPAMP_StateTypeDef; -/** +/** * @brief OPAMP Handle Structure definition - */ + */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) typedef struct __OPAMP_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ { OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ - + #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) void (* MspInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); -void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); -#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - -} OPAMP_HandleTypeDef; +void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ -/** - * @brief HAl_OPAMP_TrimmingValueTypeDef definition - */ +}OPAMP_HandleTypeDef; + +/** + * @brief HAl_OPAMP_TrimmingValueTypeDef definition + */ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; @@ -169,37 +173,37 @@ typedef enum HAL_OPAMP_MSP_INIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */ HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */ HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */ -}HAL_OPAMP_CallbackIDTypeDef; +}HAL_OPAMP_CallbackIDTypeDef; /** * @brief HAL OPAMP Callback pointer definition */ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - - + + /* Exported constants --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants * @{ - */ + */ /** @defgroup OPAMP_Mode OPAMP Mode * @{ */ -#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */ +#define OPAMP_STANDALONE_MODE 0x00000000U /*!< standalone mode */ #define OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1 /*!< PGA mode */ #define OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE /*!< follower mode */ - + /** * @} - */ - + */ + /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input * @{ */ -#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP non-inverting input connected to dedicated IO pin */ +#define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U /*!< OPAMP non-inverting input connected to dedicated IO pin */ #define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL /*!< OPAMP non-inverting input connected internally to DAC channel */ /** @@ -210,7 +214,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); * @{ */ -#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_INVERTINGINPUT_IO0 0x00000000U /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */ #define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */ #define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not connected externally (PGA mode only) */ @@ -222,7 +226,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); * @{ */ -#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */ +#define OPAMP_PGA_GAIN_2 0x00000000U /*!< PGA gain = 2 */ #define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */ #define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */ #define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */ @@ -234,7 +238,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_PowerMode OPAMP PowerMode * @{ */ -#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000) +#define OPAMP_POWERMODE_NORMAL 0x00000000U #define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM /** @@ -244,17 +248,17 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange * @{ */ -#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */ +#define OPAMP_POWERSUPPLY_LOW 0x00000000U /*!< Power supply range low (VDDA lower than 2.4V) */ #define OPAMP_POWERSUPPLY_HIGH OPAMP1_CSR_OPARANGE /*!< Power supply range high (VDDA higher than 2.4V) */ /** * @} - */ + */ /** @defgroup OPAMP_UserTrimming OPAMP User Trimming * @{ */ -#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ +#define OPAMP_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ #define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */ /** @@ -264,18 +268,17 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming * @{ */ -#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */ - -#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */ -#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */ +#define OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU /*!< Dummy value if trimming value could not be retrieved */ +#define OPAMP_FACTORYTRIMMING_N 0U /*!< Offset trimming N */ +#define OPAMP_FACTORYTRIMMING_P 1U /*!< Offset trimming P */ /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup OPAMP_Private_Constants OPAMP Private Constants @@ -283,8 +286,8 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); * @{ */ -/* NONINVERTING bit position in OTR & LPOTR */ -#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */ +/* NONINVERTING bit position in OTR & LPOTR */ +#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */ /* Offset trimming time: during calibration, minimum time needed between two */ /* steps to have 1 mV accuracy. */ @@ -319,7 +322,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ @@ -340,14 +343,30 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /* STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L412xx STM32L422xx */ + /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L451xx STM32L452xx STM32L462xx */ +#if defined (STM32L412xx) || defined (STM32L422xx) +#define IS_OPAMP_NONINVERTING_INPUT(INPUT) ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) +#endif /* STM32L412xx STM32L422xx */ + +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH)) +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -359,11 +378,13 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /* STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L412xx STM32L422xx */ + /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \ @@ -381,14 +402,14 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); ((TRIMMING) == OPAMP_TRIMMING_USER)) -#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) +#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 31U) #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P)) /** * @} - */ + */ /* Include OPAMP HAL Extended module */ #include "stm32l4xx_hal_opamp_ex.h" @@ -417,7 +438,7 @@ void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp); /* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp); HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp); -HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); /** * @} @@ -434,7 +455,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ -HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** @@ -458,16 +479,16 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_OPAMP_H */ +#endif /* STM32L4xx_HAL_OPAMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h index eb6c59aab4..7fbec9c257 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OPAMP_EX_H -#define __STM32L4xx_HAL_OPAMP_EX_H +#ifndef STM32L4xx_HAL_OPAMP_EX_H +#define STM32L4xx_HAL_OPAMP_EX_H #ifdef __cplusplus extern "C" { @@ -62,14 +62,14 @@ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - + /* I/O operation functions *****************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions * @{ */ -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); /** * @} @@ -80,7 +80,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /** @addtogroup OPAMPEx_Exported_Functions_Group2 * @{ */ -HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); /** * @} */ @@ -101,7 +101,6 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); } #endif - -#endif /* __STM32L4xx_HAL_OPAMP_EX_H */ +#endif /* STM32L4xx_HAL_OPAMP_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h index eef2f741b6..8d578fa7d2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -30,7 +30,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,32 +52,32 @@ /** @addtogroup OSPI * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup OSPI_Exported_Types OSPI Exported Types * @{ */ -/** - * @brief OSPI Init structure definition +/** + * @brief OSPI Init structure definition */ typedef struct { - uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt - indicating that data are available in reception or free place + uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt + indicating that data are available in reception or free place is available in transmission. This parameter can be a value between 1 and 32 */ - uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to + uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to quad mode on two different devices to increase the throughput. This parameter can be a value of @ref OSPI_DualQuad */ uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. This parameter can be a value of @ref OSPI_MemoryType */ - uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, - it corresponds to the number of address bits required to access + uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access the external device. This parameter can be a value between 1 and 32 */ - uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select + uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select must remain high between commands. This parameter can be a value between 1 and 8 */ uint32_t FreeRunningClock; /* It enables or not the free running clock. @@ -86,22 +86,22 @@ typedef struct This parameter can be a value of @ref OSPI_ClockMode */ uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. This parameter can be a value of @ref OSPI_WrapSize */ - uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating - the external clock based on the AHB clock. + uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating + the external clock based on the AHB clock. This parameter can be a value between 1 and 256 */ - uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order + uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order to take in account external signal delays. This parameter can be a value of @ref OSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. + uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ - uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and + uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and defines the boundary of bytes to release the chip select. This parameter can be a value between 0 and 31 */ }OSPI_InitTypeDef; -/** - * @brief HAL OSPI Handle Structure definition - */ +/** + * @brief HAL OSPI Handle Structure definition + */ typedef struct __OSPI_HandleTypeDef { OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ @@ -113,7 +113,7 @@ typedef struct __OSPI_HandleTypeDef __IO uint32_t State; /* Internal state of the OSPI HAL driver */ __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ uint32_t Timeout; /* Timeout used for the OSPI external device access */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); @@ -130,16 +130,16 @@ typedef struct __OSPI_HandleTypeDef #endif }OSPI_HandleTypeDef; -/** - * @brief HAL OSPI Regular Command Structure definition - */ +/** + * @brief HAL OSPI Regular Command Structure definition + */ typedef struct { - uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or - to the registers for the write operation (these registers are only + uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or + to the registers for the write operation (these registers are only used for memory-mapped mode). This parameter can be a value of @ref OSPI_OperationType */ - uint32_t FlashId; /* It indicates which external device is selected for this command (it + uint32_t FlashId; /* It indicates which external device is selected for this command (it applies only if Dualquad is disabled in the initialization structure). This parameter can be a value of @ref OSPI_FlashId */ uint32_t Instruction; /* It contains the instruction to be sent to the device. @@ -168,7 +168,7 @@ typedef struct This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ uint32_t DataMode; /* It indicates the mode of the data. This parameter can be a value of @ref OSPI_DataMode */ - uint32_t NbData; /* It indicates the number of data transferred with this command. + uint32_t NbData; /* It indicates the number of data transferred with this command. This field is only used for indirect mode. This parameter can be a value between 1 and 0xFFFFFFFF */ uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. @@ -181,9 +181,9 @@ typedef struct This parameter can be a value of @ref OSPI_SIOOMode */ }OSPI_RegularCmdTypeDef; -/** - * @brief HAL OSPI Hyperbus Configuration Structure definition - */ +/** + * @brief HAL OSPI Hyperbus Configuration Structure definition + */ typedef struct { uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. @@ -196,9 +196,9 @@ typedef struct This parameter can be a value of @ref OSPI_LatencyMode */ }OSPI_HyperbusCfgTypeDef; -/** - * @brief HAL OSPI Hyperbus Command Structure definition - */ +/** + * @brief HAL OSPI Hyperbus Command Structure definition + */ typedef struct { uint32_t AddressSpace; /* It indicates the address space accessed by the command. @@ -215,14 +215,14 @@ typedef struct This parameter can be a value of @ref OSPI_DQSMode */ }OSPI_HyperbusCmdTypeDef; -/** - * @brief HAL OSPI Auto Polling mode configuration structure definition +/** + * @brief HAL OSPI Auto Polling mode configuration structure definition */ typedef struct { uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t MatchMode; /* Specifies the method used for determining a match. This parameter can be a value of @ref OSPI_MatchMode */ @@ -232,19 +232,19 @@ typedef struct This parameter can be any value between 0 and 0xFFFF */ }OSPI_AutoPollingTypeDef; -/** - * @brief HAL OSPI Memory Mapped mode configuration structure definition +/** + * @brief HAL OSPI Memory Mapped mode configuration structure definition */ typedef struct { - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref OSPI_TimeOutActivation */ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ }OSPI_MemoryMappedTypeDef; -/** - * @brief HAL OSPI IO Manager Configuration structure definition +/** + * @brief HAL OSPI IO Manager Configuration structure definition */ typedef struct { @@ -260,7 +260,7 @@ typedef struct This parameter can be a value of @ref OSPIM_IOPort */ }OSPIM_CfgTypeDef; -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /** * @brief HAL OSPI Callback ID enumeration definition */ @@ -276,7 +276,7 @@ typedef enum HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ - + HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ }HAL_OSPI_CallbackIDTypeDef; @@ -297,7 +297,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @defgroup OSPI_State OSPI State * @{ - */ + */ #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ @@ -313,65 +313,68 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ /** * @} - */ + */ /** @defgroup OSPI_ErrorCode OSPI Error Code * @{ - */ + */ #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ #endif /** * @} - */ + */ /** @defgroup OSPI_DualQuad OSPI Dual-Quad * @{ - */ + */ #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ /** * @} - */ + */ /** @defgroup OSPI_MemoryType OSPI Memory Type * @{ - */ + */ #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx) +#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ +#endif #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ /** * @} - */ + */ /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock * @{ - */ + */ #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ /** * @} - */ + */ /** @defgroup OSPI_ClockMode OSPI Clock Mode * @{ - */ + */ #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ /** * @} - */ + */ /** @defgroup OSPI_WrapSize OSPI Wrap-Size * @{ - */ + */ #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ @@ -379,48 +382,48 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ /** * @} - */ + */ /** @defgroup OSPI_SampleShifting OSPI Sample Shifting * @{ - */ + */ #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ /** * @} - */ + */ /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle * @{ - */ + */ #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ /** * @} - */ + */ /** @defgroup OSPI_OperationType OSPI Operation Type * @{ - */ + */ #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ /** * @} - */ + */ /** @defgroup OSPI_FlashID OSPI Flash Id * @{ - */ + */ #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ /** * @} - */ + */ /** @defgroup OSPI_InstructionMode OSPI Instruction Mode * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ @@ -428,31 +431,31 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_InstructionSize OSPI Instruction Size * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ /** * @} - */ + */ /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ /** * @} - */ + */ /** @defgroup OSPI_AddressMode OSPI Address Mode * @{ - */ + */ #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ @@ -460,31 +463,31 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_AddressSize OSPI Address Size * @{ - */ + */ #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ /** * @} - */ + */ /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode * @{ - */ + */ #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ @@ -492,31 +495,31 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ /** * @} - */ + */ /** @defgroup OSPI_DataMode OSPI Data Mode * @{ - */ + */ #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ @@ -524,61 +527,61 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode * @{ - */ + */ #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ /** * @} - */ + */ /** @defgroup OSPI_DQSMode OSPI DQS Mode * @{ - */ + */ #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ /** * @} - */ + */ /** @defgroup OSPI_SIOOMode OSPI SIOO Mode * @{ - */ + */ #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ /** * @} - */ + */ /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation * @{ - */ + */ #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ /** * @} - */ + */ /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode * @{ - */ + */ #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ /** * @} - */ + */ /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space * @{ - */ + */ #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ /** * @} - */ + */ /** @defgroup OSPI_MatchMode OSPI Match Mode * @{ @@ -587,7 +590,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ /** * @} - */ + */ /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop * @{ @@ -596,7 +599,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ /** * @} - */ + */ /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation * @{ @@ -605,7 +608,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ /** * @} - */ + */ /** @defgroup OSPI_Flags OSPI Flags * @{ @@ -622,7 +625,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @defgroup OSPI_Interrupts OSPI Interrupts * @{ - */ + */ #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ @@ -634,22 +637,22 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @defgroup OSPI_Timeout_definition OSPI Timeout definition * @{ - */ + */ #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ /** * @} - */ + */ /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ - */ -#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ + */ +#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ +#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ /** * @} - */ + */ /** * @} */ @@ -662,7 +665,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @param __HANDLE__: OSPI handle. * @retval None */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ @@ -675,7 +678,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @brief Enable the OSPI peripheral. * @param __HANDLE__: specifies the OSPI Handle. * @retval None - */ + */ #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) /** @brief Disable the OSPI peripheral. @@ -722,7 +725,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the selected OSPI flag is set or not. @@ -755,7 +758,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup OSPI_Exported_Functions * @{ */ @@ -819,7 +822,7 @@ void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); /* OSPI memory-mapped mode functions */ void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /* OSPI callback registering/unregistering */ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); @@ -857,7 +860,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, /** * @} */ -/* End of exported functions -------------------------------------------------*/ +/* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @@ -868,9 +871,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) +#else #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) +#endif #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) @@ -985,10 +997,10 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) -#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) +#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) + ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) @@ -1008,11 +1020,11 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, /** * @} - */ + */ /** * @} - */ + */ #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h index 8462b94fff..98aadd2ed5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h @@ -52,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ @@ -106,12 +106,12 @@ typedef struct #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ - - + + /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode @@ -140,7 +140,7 @@ typedef struct /** * @} */ - + /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line * @{ @@ -152,7 +152,7 @@ typedef struct /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line * @{ - */ + */ #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ /** * @} @@ -179,16 +179,19 @@ typedef struct * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. + * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system * entered StandBy mode. + * @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates + * that external switch can be closed to connect to the external SMPS, when the Range 2 + * of internal regulator is ready. * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on * the internal wakeup line. - * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the + * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the * low-power regulator is ready. - * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the - * regulator is ready in main mode or is in low-power mode. - * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready * in the selected voltage range or is still changing to the required voltage level. * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is * below or above the selected PVD threshold. @@ -196,13 +199,13 @@ typedef struct * is below or above PVM1 threshold (applicable when USB feature is supported). @if STM32L486xx * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is - * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). + * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). @endif * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is - * is below or above PVM3 threshold. + * is below or above PVM3 threshold. * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is - * is below or above PVM4 threshold. - * + * is below or above PVM4 threshold. + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ @@ -225,7 +228,7 @@ typedef struct * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system * entered Standby mode. - * @retval None + * @retval None */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ (PWR->SCR = (__FLAG__)) :\ @@ -321,7 +324,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @addtogroup PWR_Private_Macros PWR Private Macros @@ -332,25 +335,25 @@ typedef struct ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - + #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) - + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - + #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) - + /** * @} - */ + */ /* Include PWR HAL Extended module */ #include "stm32l4xx_hal_pwr_ex.h" @@ -360,11 +363,11 @@ typedef struct /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); @@ -374,7 +377,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ @@ -404,10 +407,10 @@ void HAL_PWR_PVDCallback(void); /** * @} */ - + /** * @} - */ + */ /** * @} @@ -416,7 +419,7 @@ void HAL_PWR_PVDCallback(void); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h index 298092c24a..6c7072d164 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h @@ -65,13 +65,13 @@ */ typedef struct { - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). @if STM32L486xx - @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). + @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). @endif - @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. + @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. @@ -80,7 +80,7 @@ typedef struct /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ @@ -94,12 +94,12 @@ typedef struct #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ /** * @} - */ + */ /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins * @{ - */ + */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ @@ -122,18 +122,18 @@ typedef struct /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type * @{ */ -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ #endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) +#if defined(PWR_CR2_PVME2) #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ #endif /* PWR_CR2_PVME2 */ #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ /** * @} - */ - + */ + /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode * @{ */ @@ -147,8 +147,8 @@ typedef struct /** * @} */ - - + + /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale * @{ @@ -162,7 +162,7 @@ typedef struct * @} */ - + /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection * @{ */ @@ -171,7 +171,7 @@ typedef struct /** * @} */ - + /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging * @{ */ @@ -179,8 +179,8 @@ typedef struct #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE /** * @} - */ - + */ + /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode * @{ */ @@ -202,64 +202,64 @@ typedef struct #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ /** * @} - */ - + */ + /** @defgroup PWREx_GPIO GPIO port * @{ */ -#define PWR_GPIO_A 0x00000000 /*!< GPIO port A */ -#define PWR_GPIO_B 0x00000001 /*!< GPIO port B */ -#define PWR_GPIO_C 0x00000002 /*!< GPIO port C */ -#if defined(GPIOD_BASE) -#define PWR_GPIO_D 0x00000003 /*!< GPIO port D */ +#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ +#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ +#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ +#if defined(GPIOD_BASE) +#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ #endif -#if defined(GPIOE_BASE) -#define PWR_GPIO_E 0x00000004 /*!< GPIO port E */ +#if defined(GPIOE_BASE) +#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ #endif -#if defined(GPIOF_BASE) -#define PWR_GPIO_F 0x00000005 /*!< GPIO port F */ +#if defined(GPIOF_BASE) +#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ #endif -#if defined(GPIOG_BASE) -#define PWR_GPIO_G 0x00000006 /*!< GPIO port G */ +#if defined(GPIOG_BASE) +#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ #endif -#define PWR_GPIO_H 0x00000007 /*!< GPIO port H */ -#if defined(GPIOI_BASE) -#define PWR_GPIO_I 0x00000008 /*!< GPIO port I */ +#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ +#if defined(GPIOI_BASE) +#define PWR_GPIO_I 0x00000008U /*!< GPIO port I */ #endif /** * @} - */ - + */ + /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines * @{ - */ -#if defined(PWR_CR2_PVME1) + */ +#if defined(PWR_CR2_PVME1) #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ #endif /* PWR_CR2_PVME2 */ #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ -#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ +#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ /** * @} - */ - + */ + /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines * @{ - */ -#if defined(PWR_CR2_PVME1) + */ +#if defined(PWR_CR2_PVME1) #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ #endif /* PWR_CR2_PVME2 */ #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ -#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ +#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ /** * @} - */ - + */ + /** @defgroup PWREx_Flag PWR Status Flags * Elements values convention: 0000 0000 0XXY YYYYb * - Y YYYY : Flag position in the XX register (5 bits) @@ -267,9 +267,9 @@ typedef struct * - 01: SR1 register * - 10: SR2 register * The only exception is PWR_FLAG_WU, encompassing all - * wake-up flags and set to PWR_SR1_WUF. - * @{ - */ + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ @@ -277,6 +277,9 @@ typedef struct #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ +#if defined(PWR_SR1_EXT_SMPS_RDY) +#define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */ +#endif /* PWR_SR1_EXT_SMPS_RDY */ #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ @@ -293,11 +296,11 @@ typedef struct #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ /** * @} - */ + */ /** * @} - */ + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros @@ -456,7 +459,7 @@ typedef struct __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -547,7 +550,7 @@ typedef struct __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -638,7 +641,7 @@ typedef struct __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -674,14 +677,14 @@ typedef struct * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, + * typical output voltage at 1.2 V, * system frequency up to 80 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. + * typical output voltage at 1.0 V, + * system frequency up to 26 MHz. * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check * whether or not VOSF flag is cleared when moving from range 2 to range 1. User - * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. + * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. * @retval None */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ @@ -695,7 +698,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ @@ -716,7 +719,7 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN5_LOW)) - + #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) @@ -730,14 +733,14 @@ typedef struct ((TYPE) == PWR_PVM_4)) #endif -#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) -#endif +#endif #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ @@ -745,8 +748,8 @@ typedef struct ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + #if defined(PWR_CR5_R1MODE) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ @@ -754,20 +757,26 @@ typedef struct #else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#endif +#endif + - #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - + ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) + #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) - - -#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + + +#if defined (STM32L412xx) || defined (STM32L422xx) +#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ + ((GPIO) == PWR_GPIO_B) ||\ + ((GPIO) == PWR_GPIO_C) ||\ + ((GPIO) == PWR_GPIO_D) ||\ + ((GPIO) == PWR_GPIO_H)) +#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ @@ -804,14 +813,14 @@ typedef struct /** * @} - */ - + */ + /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ @@ -820,7 +829,7 @@ typedef struct uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); -void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_DisableBatteryCharging(void); #if defined(PWR_CR2_USV) void HAL_PWREx_EnableVddUSB(void); void HAL_PWREx_DisableVddUSB(void); @@ -860,6 +869,14 @@ void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#if defined(PWR_CR3_EN_ULP) +void HAL_PWREx_EnableBORPVD_ULP(void); +void HAL_PWREx_DisableBORPVD_ULP(void); +#endif /* PWR_CR3_EN_ULP */ +#if defined(PWR_CR4_EXT_SMPS_ON) +void HAL_PWREx_EnableExtSMPS_0V95(void); +void HAL_PWREx_DisableExtSMPS_0V95(void); +#endif /* PWR_CR4_EXT_SMPS_ON */ /* Low Power modes configuration functions ************************************/ @@ -871,7 +888,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h index fbcfabb45d..0438bb754b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h @@ -632,8 +632,8 @@ void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /* QSPI callback registering/unregistering */ -HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); #endif /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h index e2f0fa5deb..22bd438c4b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h @@ -75,8 +75,10 @@ typedef struct uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ +#if defined(RCC_PLLP_SUPPORT) uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ +#endif /* RCC_PLLP_SUPPORT */ uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ @@ -111,6 +113,11 @@ typedef struct uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ +#if defined(RCC_CSR_LSIPREDIV) + + uint32_t LSIDiv; /*!< The division factor of the LSI. + This parameter can be a value of @ref RCC_LSI_Div */ +#endif /* RCC_CSR_LSIPREDIV */ uint32_t MSIState; /*!< The new state of the MSI. This parameter can be a value of @ref RCC_MSI_Config */ @@ -197,9 +204,13 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +#if defined(RCC_BDCR_LSESYSDIS) +#define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ +#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ +#endif /* RCC_BDCR_LSESYSDIS */ /** * @} */ @@ -229,6 +240,17 @@ typedef struct /** * @} */ +#if defined(RCC_CSR_LSIPREDIV) + +/** @defgroup RCC_LSI_Div LSI Div + * @{ + */ +#define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ +#define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ +/** + * @} + */ +#endif /* RCC_CSR_LSIPREDIV */ /** @defgroup RCC_MSI_Config MSI Config * @{ @@ -270,6 +292,7 @@ typedef struct * @} */ +#if defined(RCC_PLLP_SUPPORT) /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ @@ -311,6 +334,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLP_SUPPORT */ /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ @@ -350,7 +374,7 @@ typedef struct */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ -#else +#elif defined(RCC_PLLSAI1_SUPPORT) #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ #endif /* RCC_PLLSAI2_SUPPORT */ #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ @@ -358,6 +382,7 @@ typedef struct /** * @} */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output * @{ @@ -368,6 +393,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) @@ -528,7 +554,9 @@ typedef struct #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -552,11 +580,13 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -1068,6 +1098,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ @@ -1075,6 +1106,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_ENABLE() do { \ @@ -1114,6 +1146,7 @@ typedef struct } while(0) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ @@ -1121,6 +1154,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1206,6 +1240,7 @@ typedef struct } while(0) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ @@ -1213,6 +1248,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ @@ -1242,6 +1278,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ @@ -1249,6 +1286,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1309,7 +1347,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); @@ -1323,7 +1363,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) @@ -1355,7 +1397,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) @@ -1367,7 +1411,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) @@ -1480,6 +1526,7 @@ typedef struct } while(0) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ @@ -1487,6 +1534,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ @@ -1553,7 +1601,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) @@ -1583,49 +1633,49 @@ typedef struct * @{ */ -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) -#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) +#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) #endif /* GFXMMU */ -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) -#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) #endif /* GFXMMU */ /** @@ -1640,102 +1690,102 @@ typedef struct * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) #endif /* GPIOI */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) #endif /* GPIOI */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) /** * @} @@ -1750,19 +1800,19 @@ typedef struct */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) #endif /* QUADSPI */ /** @@ -1777,186 +1827,202 @@ typedef struct * @{ */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) +#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) #endif /* LCD */ #if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) #endif /* RCC_APB1ENR1_RTCAPBEN */ -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) -#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) +#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) #endif /* LCD */ #if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) #endif /* RCC_APB1ENR1_RTCAPBEN */ -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) -#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) /** * @} @@ -1970,91 +2036,95 @@ typedef struct * @{ */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) -#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) +#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) #endif /* DSI */ -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) #endif /* DSI */ /** @@ -2309,7 +2379,9 @@ typedef struct #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) +#if defined(TIM7) #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) @@ -2319,7 +2391,9 @@ typedef struct #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) +#endif /* SPI3 */ #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) @@ -2351,7 +2425,9 @@ typedef struct #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) @@ -2363,7 +2439,9 @@ typedef struct #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) +#if defined(DAC1) #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) @@ -2396,7 +2474,9 @@ typedef struct #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) +#if defined(TIM7) #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) @@ -2406,7 +2486,9 @@ typedef struct #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) +#endif /* SPI3 */ #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) @@ -2438,7 +2520,9 @@ typedef struct #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) @@ -2450,7 +2534,9 @@ typedef struct #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) +#if defined(DAC1) #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) @@ -2498,7 +2584,9 @@ typedef struct #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) @@ -2543,7 +2631,9 @@ typedef struct #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) @@ -2835,7 +2925,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) @@ -2851,7 +2943,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) @@ -2883,7 +2977,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) @@ -2895,7 +2991,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) @@ -2926,7 +3024,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) @@ -2942,7 +3042,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) @@ -2974,7 +3076,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) @@ -2986,7 +3090,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) @@ -3037,7 +3143,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) @@ -3080,7 +3188,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) @@ -3111,53 +3221,53 @@ typedef struct * @{ */ -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) -#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) +#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) #endif /* GFXMMU */ -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) -#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) +#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) #endif /* GFXMMU */ /** @@ -3173,129 +3283,129 @@ typedef struct * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) #endif /* GPIOI */ -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) #if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) #endif /* SRAM3 */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) #endif /* OCTOSPIM */ #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) #endif /* GPIOI */ -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) #if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) #endif /* SRAM3 */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) #if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) #endif /* OCTOSPIM */ #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ /** @@ -3312,36 +3422,36 @@ typedef struct */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) #endif /* QUADSPI */ #if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) #endif /* OCTOSPI1 */ #if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) #endif /* OCTOSPI2 */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) #endif /* QUADSPI */ #if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) #endif /* OCTOSPI1 */ #if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) #endif /* OCTOSPI2 */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) #endif /* FMC_BANK1 */ /** @@ -3357,186 +3467,202 @@ typedef struct * @{ */ -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) #endif /* LCD */ #if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) #endif /* LCD */ #if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) /** * @} @@ -3551,89 +3677,93 @@ typedef struct * @{ */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) #endif /* DSI */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) #endif /* DSI */ /** @@ -3830,9 +3960,9 @@ typedef struct * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz */ #define __HAL_RCC_GET_MSI_RANGE() \ - ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ + ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ - READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) + (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -4043,7 +4173,7 @@ typedef struct * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * - * @param __PLLP__ specifies the division factor for SAI clock. + * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * else (2 to 31). * @@ -4062,14 +4192,21 @@ typedef struct #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - ((uint32_t)(__PLLP__) << 27U)) -#else + (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ + (uint32_t)((__PLLP__) << 27U)) + +#elif defined(RCC_PLLP_SUPPORT) #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + +#else + +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ + (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ + (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ @@ -4208,7 +4345,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @if STM32L443xx @@ -4230,7 +4367,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @if STM32L443xx @@ -4252,7 +4389,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @@ -4275,7 +4412,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @@ -4303,7 +4440,7 @@ typedef struct * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready - * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready + * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 @if STM32L443xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @@ -4329,12 +4466,12 @@ typedef struct ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ /** @@ -4387,8 +4524,13 @@ typedef struct #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ ((__HSE__) == RCC_HSE_BYPASS)) +#if defined(RCC_BDCR_LSESYSDIS) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) +#else #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSESYSDIS */ #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) @@ -4396,6 +4538,10 @@ typedef struct #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#if defined(RCC_CSR_LSIPREDIV) +#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) +#endif /* RCC_CSR_LSIPREDIV */ + #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) @@ -4432,10 +4578,12 @@ typedef struct #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h index 136881c73b..11438042cd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h @@ -58,6 +58,7 @@ * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief PLLSAI1 Clock structure definition */ @@ -90,9 +91,9 @@ typedef struct uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ }RCC_PLLSAI1InitTypeDef; +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) - /** * @brief PLLSAI2 Clock structure definition */ @@ -137,10 +138,11 @@ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ +#if defined(RCC_PLLSAI1_SUPPORT) RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ - +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. @@ -203,9 +205,11 @@ typedef struct uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#if defined(SAI1) uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ +#endif /* SAI1 */ #if defined(SAI2) @@ -231,8 +235,10 @@ typedef struct uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ +#if !defined(STM32L412xx) && !defined(STM32L422xx) uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) @@ -303,7 +309,8 @@ typedef struct This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise, + or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ }RCC_CRSInitTypeDef; @@ -316,7 +323,7 @@ typedef struct This parameter must be a number between 0 and 0xFFFF */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ + This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. @@ -370,7 +377,9 @@ typedef struct #define RCC_PERIPHCLK_I2C3 0x00000100U #define RCC_PERIPHCLK_LPTIM1 0x00000200U #define RCC_PERIPHCLK_LPTIM2 0x00000400U +#if defined(SAI1) #define RCC_PERIPHCLK_SAI1 0x00000800U +#endif #if defined(SAI2) #define RCC_PERIPHCLK_SAI2 0x00001000U #endif @@ -525,6 +534,7 @@ typedef struct */ #endif /* I2C4 */ +#if defined(SAI1) /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ @@ -547,6 +557,7 @@ typedef struct /** * @} */ +#endif /* SAI1 */ #if defined(SAI2) /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source @@ -618,7 +629,9 @@ typedef struct #else #define RCC_RNGCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL /** @@ -634,7 +647,9 @@ typedef struct #else #define RCC_USBCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL /** @@ -645,12 +660,18 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_NONE 0x00000000U +#define RCC_ADCCLKSOURCE_NONE 0x00000000U +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#if defined(RCC_CCIPR_ADCSEL) #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL +#else +#define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U +#endif /* RCC_CCIPR_ADCSEL */ /** * @} */ @@ -807,9 +828,15 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +#else +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +#endif /** * @} */ @@ -864,6 +891,7 @@ typedef struct * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. @@ -1075,6 +1103,8 @@ typedef struct */ #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -1318,6 +1348,8 @@ typedef struct #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + /** * @brief Macro to configure the SAI1 clock source. * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived @@ -1366,6 +1398,8 @@ typedef struct #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* SAI1 */ + #if defined(SAI2) /** @@ -1757,7 +1791,7 @@ typedef struct */ #if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) #else #define __HAL_RCC_GET_SDMMC1_SOURCE() \ (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) @@ -1837,6 +1871,8 @@ typedef struct #endif /* USB_OTG_FS || USB */ +#if defined(RCC_CCIPR_ADCSEL) + /** @brief Macro to configure the ADC interface clock. * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. * This parameter can be one of the following values: @@ -1861,6 +1897,16 @@ typedef struct * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock */ #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) +#else + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE) + +#endif /* RCC_CCIPR_ADCSEL */ #if defined(SWPMI1) @@ -2008,6 +2054,7 @@ typedef struct * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @brief Enable PLLSAI1RDY interrupt. * @retval None @@ -2034,6 +2081,8 @@ typedef struct */ #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @brief Enable PLLSAI2RDY interrupt. @@ -2189,7 +2238,7 @@ typedef struct * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) /** @brief Clear the CRS interrupt pending bits * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @@ -2206,7 +2255,7 @@ typedef struct #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ } \ @@ -2250,7 +2299,7 @@ typedef struct #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ } \ @@ -2339,10 +2388,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); @@ -2400,7 +2452,24 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) -#if defined(STM32L431xx) +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) + +#elif defined(STM32L431xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -2652,7 +2721,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) -#endif /* STM32L431xx */ +#endif /* STM32L412xx || STM32L422xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ @@ -2747,7 +2816,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#else +#elif defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ @@ -2817,11 +2886,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) +#else +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) +#endif /* RCC_PLLSAI1_SUPPORT */ #else @@ -2836,11 +2912,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(USB_OTG_FS) || defined(USB) #if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#endif /* RCC_PLLSAI1_SUPPORT */ #else @@ -2863,10 +2946,16 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #else +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#else +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#endif /* RCC_PLLSAI1_SUPPORT */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ @@ -2922,6 +3011,8 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(RCC_PLLSAI1_SUPPORT) + #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) @@ -2944,6 +3035,8 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h index bf202c75d0..c1c08888f4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_H -#define __STM32L4xx_HAL_RTC_H +#ifndef STM32L4xx_HAL_RTC_H +#define STM32L4xx_HAL_RTC_H #ifdef __cplusplus extern "C" { @@ -48,7 +48,7 @@ * @{ */ -/** @addtogroup RTC +/** @defgroup RTC RTC * @{ */ @@ -56,20 +56,21 @@ /** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ -/** - * @brief HAL State structures definition + +/** + * @brief HAL State structures definition */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ }HAL_RTCStateTypeDef; -/** +/** * @brief RTC Configuration Structure definition */ typedef struct @@ -79,25 +80,29 @@ typedef struct uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ +#if defined(STM32L412xx) || defined(STM32L422xx) + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ +#endif }RTC_InitTypeDef; -/** - * @brief RTC Time structure definition +/** + * @brief RTC Time structure definition */ typedef struct { @@ -113,26 +118,26 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity */ - + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit in CR register to store the operation. This parameter can be a value of @ref RTC_StoreOperation_Definitions */ }RTC_TimeTypeDef; -/** +/** * @brief RTC Date structure definition */ typedef struct @@ -151,7 +156,7 @@ typedef struct }RTC_DateTypeDef; -/** +/** * @brief RTC Alarm structure definition */ typedef struct @@ -160,7 +165,7 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ @@ -175,13 +180,16 @@ typedef struct This parameter can be a value of @ref RTC_Alarms_Definitions */ }RTC_AlarmTypeDef; -/** +/** * @brief RTC Handle Structure definition */ typedef struct __RTC_HandleTypeDef { RTC_TypeDef *Instance; /*!< Register base address */ +#if defined(STM32L412xx) || defined(STM32L422xx) + uint32_t TampOffset; /*!< Offset to TAMP instance */ +#endif RTC_InitTypeDef Init; /*!< RTC required parameters */ HAL_LockTypeDef Lock; /*!< RTC locking object */ @@ -189,58 +197,49 @@ typedef struct __RTC_HandleTypeDef __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ - - void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ - - void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ - - void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ - + void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ #if defined(RTC_TAMPER1_SUPPORT) - void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ #endif /* RTC_TAMPER1_SUPPORT */ - - void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ - + void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ #if defined(RTC_TAMPER3_SUPPORT) - void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */ + void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */ #endif /* RTC_TAMPER3_SUPPORT */ - - void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ - - void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ - -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ }RTC_HandleTypeDef; #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /** - * @brief HAL LPTIM Callback ID enumeration definition + * @brief HAL RTC Callback ID enumeration definition */ typedef enum { - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ - HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */ - HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */ #if defined(RTC_TAMPER1_SUPPORT) - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, /*!< RTC Tamper 1 Callback ID */ #endif /* RTC_TAMPER1_SUPPORT */ - HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, /*!< RTC Tamper 2 Callback ID */ #if defined(RTC_TAMPER3_SUPPORT) - HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, /*!< RTC Tamper 3 Callback ID */ #endif /* RTC_TAMPER3_SUPPORT */ - HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ + HAL_RTC_MSPINIT_CB_ID = 7u, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 8u /*!< RTC Msp DeInit callback ID */ }HAL_RTC_CallbackIDTypeDef; /** * @brief HAL RTC Callback pointer definition */ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ /** * @} @@ -251,11 +250,25 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ -/** @defgroup RTC_Hour_Formats RTC Hour Formats +/** @defgroup RTC_Hour_Formats_Definitions RTC Hour Formats Definitions + * @{ + */ +#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definitions * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) +#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +#endif /** * @} */ @@ -263,8 +276,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} */ @@ -272,8 +285,24 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +#else +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMOUTTYPE +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000u +#endif +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +#endif /** * @} */ @@ -281,8 +310,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000) -#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +#else +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_OR_OUT_RMP +#endif /** * @} */ @@ -291,26 +325,26 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) /** * @} */ -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0x00000000u /** * @} */ -/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) +#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} */ @@ -318,29 +352,30 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x00000000) -#define RTC_FORMAT_BCD ((uint32_t)0x00000001) +#define RTC_FORMAT_BIN 0x00000000u +#define RTC_FORMAT_BCD 0x00000001u /** * @} */ -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format) * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + /** * @} */ @@ -348,36 +383,38 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + /** * @} */ -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + /** * @} */ - -/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + /** * @} */ @@ -385,48 +422,50 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions * @{ */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + /** * @} */ + /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison. Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison. Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match + to activate alarm. */ /** * @} */ @@ -434,41 +473,86 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ -#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask + * @{ + */ +#define RTC_IT_MASK 0x001Fu /*!< RTC interruptions flags mask */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * Elements values convention: 000000XX000YYYYYb + * - YYYYY : Interrupt flag position in the XX register (5bits) + * - XX : Interrupt status register (2bits) + * - 01: ICSR register + * - 10: SR register + * @{ + */ +#define RTC_FLAG_RECALPF 0x00000110u /*!< Recalibration pending Flag */ +#define RTC_FLAG_INITF 0x00000106u /*!< Initialization flag */ +#define RTC_FLAG_RSF 0x00000105u /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS 0x00000104u /*!< Initialization status flag */ +#define RTC_FLAG_SHPF 0x00000103u /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF 0x00000102u /*!< Wakeup timer write flag */ +#define RTC_FLAG_ALRBWF 0x00000101u /*!< Alarm B write flag */ +#define RTC_FLAG_ALRAWF 0x00000100u /*!< Alarm A write flag */ +#define RTC_FLAG_ITSF 0x00000205u /*!< Clear Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF 0x00000204u /*!< Clear Time-stamp overflow flag */ +#define RTC_FLAG_TSF 0x00000203u /*!< Clear Time-stamp flag */ +#define RTC_FLAG_WUTF 0x00000202u /*!< Clear Wakeup timer flag */ +#define RTC_FLAG_ALRBF 0x00000201u /*!< Clear Alarm B flag */ +#define RTC_FLAG_ALRAF 0x00000200u /*!< Clear Alarm A flag */ /** * @} */ +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ + +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_ITSF RTC_ISR_ITSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /** * @} */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} @@ -479,8 +563,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ -/** @brief Reset RTC handle state. - * @param __HANDLE__: RTC handle. +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. * @retval None */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -488,128 +572,173 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ (__HANDLE__)->MspInitCallback = NULL;\ (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) + }while(0u) #else #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0u) /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0u) +/** + * @brief Add 1 hour (summer time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H); \ + MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0u); /** + * @brief Subtract 1 hour (winter time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H); \ + MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0u); + + /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U) +#else +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U) +#endif /** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @arg @ref RTC_FLAG_ALRAWF + * @arg @ref RTC_FLAG_ALRBWF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** - * @brief Check whether the specified RTC Alarm interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \ + ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF))) +#else +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))) +#endif /** * @brief Enable interrupt on the RTC Alarm associated Exti line. @@ -625,13 +754,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** * @brief Enable event on the RTC Alarm associated Exti line. - * @retval None + * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) /** * @brief Disable event on the RTC Alarm associated Exti line. - * @retval None + * @retval None. */ #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) @@ -666,7 +795,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0u) /** * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. @@ -675,7 +804,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0u) /** * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. @@ -703,30 +832,30 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to #include "stm32l4xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions +/** @defgroup RTC_Exported_Functions RTC Exported Functions * @{ */ -/** @addtogroup RTC_Exported_Functions_Group1 +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group2 +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions * @{ */ /* RTC Time and Date functions ************************************************/ @@ -738,7 +867,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @addtogroup RTC_Exported_Functions_Group3 +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions * @{ */ /* RTC Alarm functions ********************************************************/ @@ -747,27 +876,26 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group4 +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group5 +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); - /** * @} */ @@ -776,21 +904,31 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @} */ -/* Private types -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup RTC_Private_Constants RTC Private Constants * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) -#define RTC_TIMEOUT_VALUE 1000 - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) + +#define RTC_INIT_MASK 0xFFFFFFFFu +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) +#else +#define RTC_RSF_MASK (~(RTC_ISR_INIT | RTC_ISR_RSF)) +#endif + +#define RTC_TIMEOUT_VALUE 1000u + +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */ /** * @} @@ -803,7 +941,19 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters * @{ - */ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) +#else +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +#endif #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) @@ -814,10 +964,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) +#endif + #define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ ((REMAP) == RTC_OUTPUT_REMAP_POS1)) -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ @@ -826,13 +982,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ ((OPERATION) == RTC_STOREOPERATION_SET)) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -842,7 +999,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -855,40 +1012,27 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0u) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) /** * @} @@ -898,14 +1042,17 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup RTC_Private_Functions +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions * @{ */ - HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + /** * @} @@ -923,6 +1070,7 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); } #endif -#endif /* __STM32L4xx_HAL_RTC_H */ +#endif /* STM32L4xx_HAL_RTC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h index 35f2ddcf3b..a683157af4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h @@ -31,11 +31,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_EX_H -#define __STM32L4xx_HAL_RTC_EX_H +#ifndef STM32L4xx_HAL_RTC_EX_H +#define STM32L4xx_HAL_RTC_EX_H #ifdef __cplusplus extern "C" { @@ -48,7 +48,7 @@ * @{ */ -/** @addtogroup RTCEx +/** @defgroup RTCEx RTCEx * @{ */ @@ -56,27 +56,28 @@ /** @defgroup RTCEx_Exported_Types RTCEx Exported Types * @{ */ -/** - * @brief RTC Tamper structure definition + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ */ typedef struct { uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. @@ -91,264 +92,442 @@ typedef struct uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ }RTC_TamperTypeDef; +/** + * @} + */ /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants * @{ */ -/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions +/* ========================================================================== */ +/* ##### RTC TimeStamp exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges Definitions + * * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) +#define RTC_TIMESTAMPEDGE_RISING 0x00000000u +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions +/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u /** * @} */ -/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions +/* ========================================================================== */ +/* ##### RTC Wake-up exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} */ -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection +/* ========================================================================== */ +/* ##### Extended RTC Peripheral Control exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 8s, else 2exp18 RTCCLK pulses */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ -#if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E -#endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E -#endif /* RTC_TAMPER3_SUPPORT */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ /** * @} */ -/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTCEx_Smooth_Calib_Low_Power_Definitions RTCEx Smooth Calib Low Power Definitions + * @{ + */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre, + which is the required configuration for + ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK, + which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ +/** + * @} + */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0x00000000u +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL +/** + * @} + */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0x00000000u +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + + +/* ========================================================================== */ +/* ##### RTC Tamper exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) #if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E #endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E #if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E #endif /* RTC_TAMPER3_SUPPORT */ -#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE +#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#if defined(RTC_TAMPER1_SUPPORT) +#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#endif /* RTC_TAMPER1_SUPPORT */ +#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#if defined(RTC_TAMPER3_SUPPORT) +#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E +#endif /* RTC_TAMPER3_SUPPORT */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#else +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE +#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE +#endif /** * @} */ -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions -* @{ -*/ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) +/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper Mask Flag Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +#else +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x00040000u +#endif /** * @} */ -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions +/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions * @{ */ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#else +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x00020000u +#endif /** * @} */ -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000u /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level. */ +#endif /*#if defined(STM32L412xx) || defined(STM32L422xx) */ -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ /** * @} */ -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ[2:0]*/ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000u /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAMPCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ[2:0]*/ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000u /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAMPCR_TAMPPRCH /*!< Masking all bits except those of + field TAMPPRCH[1:0] */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions +/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull Up Definitions * @{ */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +#else +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< TimeStamp on Tamper Detection event is not saved */ +#endif + /** * @} */ -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#else +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#endif /** * @} */ -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_IT_TAMP (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE) /*!< Enable all Tamper Interrupt */ +#define RTC_IT_TAMP1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#define RTC_IT_TAMPALL RTC_IT_TAMP +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable all Tamper Interrupt */ +#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ +#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ +#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ +#define RTC_IT_TAMPALL RTC_IT_TAMP +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions +/** @defgroup RTCEx_Flags RTCEx Flags * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_FLAG_TAMP1F TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP2F TAMP_SR_TAMP2F +#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions +/* ========================================================================== */ +/* ##### Extended RTC Backup registers exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Backup_Data_Registers_Number_Definitions RTC Backup Data Registers Number Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ +#if defined(RTC_BKP_NUMBER) +#define BKP_REG_NUMBER RTC_BKP_NUMBER +#endif /* RTC_BKP_NUMBER */ +#if defined(TAMP_BKP_NUMBER) +#define BKP_REG_NUMBER TAMP_BKP_NUMBER +#endif /* TAMP_BKP_NUMBER */ /** * @} */ -/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions +/** @defgroup RTCEx_Backup_Data_Registers_Definitions RTCEx Backup Data Registers Definitions * @{ */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) +#define RTC_BKP_DR0 0x00u +#define RTC_BKP_DR1 0x01u +#define RTC_BKP_DR2 0x02u +#define RTC_BKP_DR3 0x03u +#define RTC_BKP_DR4 0x04u +#define RTC_BKP_DR5 0x05u +#define RTC_BKP_DR6 0x06u +#define RTC_BKP_DR7 0x07u +#define RTC_BKP_DR8 0x08u +#define RTC_BKP_DR9 0x09u +#define RTC_BKP_DR10 0x0Au +#define RTC_BKP_DR11 0x0Bu +#define RTC_BKP_DR12 0x0Cu +#define RTC_BKP_DR13 0x0Du +#define RTC_BKP_DR14 0x0Eu +#define RTC_BKP_DR15 0x0Fu +#define RTC_BKP_DR16 0x10u +#define RTC_BKP_DR17 0x11u +#define RTC_BKP_DR18 0x12u +#define RTC_BKP_DR19 0x13u +#define RTC_BKP_DR20 0x14u +#define RTC_BKP_DR21 0x15u +#define RTC_BKP_DR22 0x16u +#define RTC_BKP_DR23 0x17u +#define RTC_BKP_DR24 0x18u +#define RTC_BKP_DR25 0x19u +#define RTC_BKP_DR26 0x1Au +#define RTC_BKP_DR27 0x1Bu +#define RTC_BKP_DR28 0x1Cu +#define RTC_BKP_DR29 0x1Du +#define RTC_BKP_DR30 0x1Eu +#define RTC_BKP_DR31 0x1Fu /** * @} */ -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions + + + +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER1_INTERRUPT TAMP_IER_TAMP1IE +#define RTC_TAMPER2_INTERRUPT TAMP_IER_TAMP2IE +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#if defined(RTC_TAMPER1_SUPPORT) +#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE +#endif /* RTC_TAMPER1_SUPPORT */ +#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE +#if defined(RTC_TAMPER3_SUPPORT) +#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE +#endif /* RTC_TAMPER3_SUPPORT */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + /** * @} */ @@ -362,440 +541,616 @@ typedef struct * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag + * @retval None + */ +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__)) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_ALRBWF Alarm B write flag + * @arg @ref RTC_FLAG_ALRAWF Alarm A write flag + * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval None + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) : \ + ((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK)))) +#endif /*#if defined(STM32L412xx) || defined(STM32L422xx) */ + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4)) != 0U) ? 1U : 0U) +#endif /** - * @brief Check whether the specified RTC Wake Up timer interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval Flag status */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: - * @arg RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) +#else +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif -#if defined(RTC_TAMPER1_SUPPORT) + +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ /** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPER1_SUPPORT */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) /** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Enable event on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Disable event on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) -#if defined(RTC_TAMPER3_SUPPORT) /** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPER3_SUPPORT */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) /** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) /** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None */ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) -#else -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) /** - * @brief Check whether the specified RTC Tamper interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * This parameter can be: * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) /** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC WakeUp Timer associated Exti line flag. * @retval None */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. * @retval None */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +/** + * @} + */ + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt + * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt + * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to check. * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt + * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4)) != 0U) ? 1U : 0U) +#endif /** - * @brief Check whether the specified RTC Time Stamp interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt + * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval Flag status */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#else +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF * @retval None */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \ + (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF))) +#else #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif /** * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) /** * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) /** * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_ITSF + * @arg @ref RTC_FLAG_ITSF * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#else +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. - * This parameter can be: - * @arg RTC_FLAG_ITSF + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF * @retval None */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF)) +#else #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS)) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS)) + +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE)) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE)) + + +/** + * @} + */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_SHPF + * @arg @ref RTC_FLAG_SHPF * @retval None */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** - * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None + * @} */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ +#if defined(RTC_TAMPER1_SUPPORT) /** - * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @brief Enable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (TAMP_CR1_TAMP1E)) +#else +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) +#endif /** - * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @brief Disable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(RTC_TAMPCR_TAMP1E)) +#else +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) +#endif +#endif /* RTC_TAMPER1_SUPPORT */ /** - * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @brief Enable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (TAMP_CR1_TAMP2E)) +#else +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) +#endif /** - * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Disable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(RTC_TAMPCR_TAMP2E)) +#else +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) +#endif +#if defined(RTC_TAMPER3_SUPPORT) /** - * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Enable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) /** - * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Disable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) +#endif /* RTC_TAMPER3_SUPPORT */ +/**************************************************************************************************/ /** - * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__)) +#else +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) +#endif /** - * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__)) +#else +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) +#endif + +/**************************************************************************************************/ /** - * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * This parameter can be: + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->MISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** - * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. - * @retval Line Status. + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#endif /** - * @brief Clear the RTC WakeUp Timer associated Exti line flag. + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U) +#else +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** - * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) = (__FLAG__)) +#else +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif /** * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. @@ -822,7 +1177,7 @@ typedef struct #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) /** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) @@ -856,7 +1211,6 @@ typedef struct /** * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * This parameter can be: * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ @@ -882,17 +1236,27 @@ typedef struct */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +/** + * @} + */ + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group1 +/* ========================================================================== */ +/* ##### RTC TimeStamp exported functions ##### */ +/* ========================================================================== */ + +/* RTC TimeStamp functions ****************************************************/ + +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions * @{ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); @@ -901,39 +1265,29 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -#if defined(RTC_TAMPER1_SUPPORT) -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER1_SUPPORT */ -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(RTC_TAMPER3_SUPPORT) -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER3_SUPPORT */ void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER1_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER1_SUPPORT */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER3_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER3_SUPPORT */ /** * @} */ +/* ========================================================================== */ +/* ##### RTC Wake-up exported functions ##### */ +/* ========================================================================== */ + /* RTC Wake-up functions ******************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ + +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr); +#else HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +#endif +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); @@ -942,14 +1296,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ -/* Extended Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/* ========================================================================== */ +/* ##### Extended RTC Peripheral Control exported functions ##### */ +/* ========================================================================== */ +/* Extended RTC Peripheral Control functions **********************************/ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); +#endif HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); @@ -962,27 +1321,65 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); */ /* Extended RTC features functions *******************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group4 +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions * @{ */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} */ +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); + +#if defined(RTC_TAMPER1_SUPPORT) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER1_SUPPORT */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER3_SUPPORT) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER3_SUPPORT */ + +#if defined(RTC_TAMPER1_SUPPORT) +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER1_SUPPORT */ +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER3_SUPPORT) +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER3_SUPPORT */ + + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/** + * @} + */ + /** * @} */ -/* Private types -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */ /** * @} @@ -995,68 +1392,22 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters * @{ - */ - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) - + */ #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET)) +#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != 0U)) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ - ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) - -#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \ - ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE)) - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ @@ -1065,12 +1416,63 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) +#endif + +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) +#else +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != 0U)) +#endif + + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ ((SEL) == RTC_SHIFTADD1S_SET)) -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) @@ -1093,8 +1495,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ -#endif /* __STM32L4xx_HAL_RTC_EX_H */ +#endif /* STM32L4xx_HAL_RTC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h index b8a1bae50f..6d8767741e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h @@ -41,6 +41,8 @@ extern "C" { #endif +#if !defined(STM32L412xx) && !defined(STM32L422xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -137,10 +139,11 @@ typedef struct uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. This parameter can be a value of @ref SAI_Audio_Frequency */ - uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for - AudioFrequency the user choice + uint32_t Mckdiv; /*!< Specifies the master clock divider. This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. - This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. @@ -842,7 +845,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); */ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup SAI_Private_Macros +/** @defgroup SAI_Private_Macros SAI Private Macros * @{ */ #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ @@ -951,7 +954,11 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) +#else +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) +#endif #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) @@ -978,6 +985,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); * @} */ +#endif /* !STM32L412xx && !STM32L422xx */ + #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h index 090e4c438d..48fca03a43 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMARTCARD_H -#define __STM32L4xx_HAL_SMARTCARD_H +#ifndef STM32L4xx_HAL_SMARTCARD_H +#define STM32L4xx_HAL_SMARTCARD_H #ifdef __cplusplus extern "C" { @@ -165,8 +165,8 @@ typedef struct } SMARTCARD_AdvFeatureInitTypeDef; /** - * @brief HAL SMARTCARD State structures definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. + * @brief HAL SMARTCARD State definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -203,26 +203,7 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -} HAL_SMARTCARD_StateTypeDef; +typedef uint32_t HAL_SMARTCARD_StateTypeDef; /** * @brief SMARTCARD handle Structure definition @@ -349,6 +330,30 @@ typedef enum * @{ */ +/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition + * @{ + */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ @@ -554,7 +559,11 @@ typedef enum /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask * @{ */ -#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */ +#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */ +#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */ +#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */ /** * @} */ @@ -694,9 +703,9 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -719,9 +728,9 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. @@ -745,7 +754,7 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -768,9 +777,9 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. @@ -886,6 +895,10 @@ typedef enum break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #else #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -953,6 +966,10 @@ typedef enum break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #endif /* STM32L432xx || STM32L442xx */ @@ -1251,6 +1268,6 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar } #endif -#endif /* __STM32L4xx_HAL_SMARTCARD_H */ +#endif /* STM32L4xx_HAL_SMARTCARD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h index 1f246ddbcc..25d30535b3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMARTCARD_EX_H -#define __STM32L4xx_HAL_SMARTCARD_EX_H +#ifndef STM32L4xx_HAL_SMARTCARD_EX_H +#define STM32L4xx_HAL_SMARTCARD_EX_H #ifdef __cplusplus extern "C" { @@ -403,6 +403,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs } #endif -#endif /* __STM32L4xx_HAL_SMARTCARD_EX_H */ +#endif /* STM32L4xx_HAL_SMARTCARD_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h index c3b63d2f8f..6d2f5e5556 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h @@ -471,7 +471,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable * - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -496,10 +496,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) * - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -598,13 +598,13 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ ((REQUEST) == SMBUS_NEXT_FRAME) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ - IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ @@ -623,8 +623,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h index c34a4e9918..8d72e4a134 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SPI_H -#define __STM32L4xx_HAL_SPI_H +#ifndef STM32L4xx_HAL_SPI_H +#define STM32L4xx_HAL_SPI_H #ifdef __cplusplus extern "C" { @@ -367,13 +367,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be one of the following values: * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : * RXNE event is generated if the FIFO - * level is greater or equal to 1/2(16-bits). + * level is greater or equal to 1/4(8-bits). * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/4(8 bits). */ + * level is greater or equal to 1/2(16 bits). */ #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) - /** * @} */ @@ -400,6 +399,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) /** * @} */ @@ -595,6 +595,34 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode @@ -829,6 +857,6 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); } #endif -#endif /* __STM32L4xx_HAL_SPI_H */ +#endif /* STM32L4xx_HAL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h index 0c0d517f74..cce1d50ffd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SPI_EX_H -#define __STM32L4xx_HAL_SPI_EX_H +#ifndef STM32L4xx_HAL_SPI_EX_H +#define STM32L4xx_HAL_SPI_EX_H #ifdef __cplusplus extern "C" { @@ -86,6 +86,6 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); } #endif -#endif /* __STM32L4xx_HAL_SPI_EX_H */ +#endif /* STM32L4xx_HAL_SPI_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h index 29669d233f..647aab414c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SWPMI_H -#define __STM32L4xx_HAL_SWPMI_H +#ifndef STM32L4xx_HAL_SWPMI_H +#define STM32L4xx_HAL_SWPMI_H #ifdef __cplusplus extern "C" { @@ -68,7 +68,7 @@ typedef struct This parameter can be a value of @ref SWPMI_Voltage_Class */ uint32_t BitRate; /*!< Specifies the SWPMI Bitrate. - This parameter must be a number between 0 and 63. + This parameter must be a number between 0 and 63U. The Bitrate is computed using the following formula: SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) */ @@ -478,7 +478,7 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); #define IS_SWPMI_VOLTAGE_CLASS(__CLASS__) (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \ ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B)) -#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63)) +#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63U)) #define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \ @@ -506,6 +506,6 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); } #endif -#endif /* __STM32L4xx_HAL_SWPMI_H */ +#endif /* STM32L4xx_HAL_SWPMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h index 62e507e946..757c64649e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h @@ -118,7 +118,9 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #if defined (USB_OTG_FS) #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ @@ -135,11 +137,15 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ #define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ #define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP2 */ #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ #define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ +#if defined(COMP2) #define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ +#endif /* COMP2 */ #if defined (TIM3) #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h index 57b5ba877b..117682db78 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TSC_H -#define __STM32L4xx_HAL_TSC_H +#ifndef STM32L4xx_HAL_TSC_H +#define STM32L4xx_HAL_TSC_H #ifdef __cplusplus extern "C" { @@ -62,10 +62,10 @@ extern "C" { */ typedef enum { - HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ - HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ - HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ - HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ + HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ } HAL_TSC_StateTypeDef; /** @@ -73,8 +73,8 @@ typedef enum */ typedef enum { - TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ - TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ + TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ } TSC_GroupStatusTypeDef; /** @@ -145,7 +145,7 @@ typedef struct __TSC_HandleTypeDef */ typedef enum { - TSC_GROUP1_IDX = 0x00U, + TSC_GROUP1_IDX = 0x00UL, TSC_GROUP2_IDX, TSC_GROUP3_IDX, TSC_GROUP4_IDX, @@ -170,11 +170,11 @@ typedef enum */ typedef enum { - HAL_TSC_CONV_COMPLETE_CB_ID = 0x00U, /*!< TSC Conversion completed callback ID */ - HAL_TSC_ERROR_CB_ID = 0x01U, /*!< TSC Error callback ID */ + HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ + HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ - HAL_TSC_MSPINIT_CB_ID = 0x02U, /*!< TSC Msp Init callback ID */ - HAL_TSC_MSPDEINIT_CB_ID = 0x03U /*!< TSC Msp DeInit callback ID */ + HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ + HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ } HAL_TSC_CallbackIDTypeDef; @@ -198,9 +198,9 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to * @brief TSC Error Code definition * @{ */ -#define HAL_TSC_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) -#define HAL_TSC_ERROR_INVALID_CALLBACK (0x00000001U) /*!< Invalid Callback error */ +#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ /** * @} @@ -209,7 +209,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_CTPulseHL_Config CTPulse High Length * @{ */ -#define TSC_CTPH_1CYCLE 0x00000000U /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ +#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ @@ -232,7 +232,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length * @{ */ -#define TSC_CTPL_1CYCLE 0x00000000U /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ +#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ @@ -255,7 +255,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler * @{ */ -#define TSC_SS_PRESC_DIV1 0x00000000U /*!< Spread Spectrum Prescaler Div1 */ +#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ /** * @} @@ -264,7 +264,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler * @{ */ -#define TSC_PG_PRESC_DIV1 0x00000000U /*!< Pulse Generator HCLK Div1 */ +#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ @@ -279,7 +279,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_MaxCount_Value Max Count Value * @{ */ -#define TSC_MCV_255 0x00000000U /*!< 255 maximum number of charge transfer pulses */ +#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ @@ -293,7 +293,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_IO_Default_Mode IO Default Mode * @{ */ -#define TSC_IODEF_OUT_PP_LOW 0x00000000U /*!< I/Os are forced to output push-pull low */ +#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ /** * @} @@ -302,7 +302,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity * @{ */ -#define TSC_SYNC_POLARITY_FALLING 0x00000000U /*!< Falling edge only */ +#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ /** * @} @@ -311,8 +311,8 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_Acquisition_Mode Acquisition Mode * @{ */ -#define TSC_ACQ_MODE_NORMAL 0x00000000U /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ -#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ +#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ +#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ /** * @} */ @@ -338,24 +338,24 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to /** @defgroup TSC_Group_definition Group definition * @{ */ -#define TSC_GROUP1 (uint32_t)(0x1U << TSC_GROUP1_IDX) -#define TSC_GROUP2 (uint32_t)(0x1U << TSC_GROUP2_IDX) -#define TSC_GROUP3 (uint32_t)(0x1U << TSC_GROUP3_IDX) -#define TSC_GROUP4 (uint32_t)(0x1U << TSC_GROUP4_IDX) +#define TSC_GROUP1 (uint32_t)(0x1UL << TSC_GROUP1_IDX) +#define TSC_GROUP2 (uint32_t)(0x1UL << TSC_GROUP2_IDX) +#define TSC_GROUP3 (uint32_t)(0x1UL << TSC_GROUP3_IDX) +#define TSC_GROUP4 (uint32_t)(0x1UL << TSC_GROUP4_IDX) #if defined(TSC_IOCCR_G5_IO1) -#define TSC_GROUP5 (uint32_t)(0x1U << TSC_GROUP5_IDX) +#define TSC_GROUP5 (uint32_t)(0x1UL << TSC_GROUP5_IDX) #endif #if defined(TSC_IOCCR_G6_IO1) -#define TSC_GROUP6 (uint32_t)(0x1U << TSC_GROUP6_IDX) +#define TSC_GROUP6 (uint32_t)(0x1UL << TSC_GROUP6_IDX) #endif #if defined(TSC_IOCCR_G7_IO1) -#define TSC_GROUP7 (uint32_t)(0x1U << TSC_GROUP7_IDX) +#define TSC_GROUP7 (uint32_t)(0x1UL << TSC_GROUP7_IDX) #endif #if defined(TSC_IOCCR_G8_IO1) -#define TSC_GROUP8 (uint32_t)(0x1U << TSC_GROUP8_IDX) +#define TSC_GROUP8 (uint32_t)(0x1UL << TSC_GROUP8_IDX) #endif -#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000U /*!< TSC GroupX not supported */ +#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ @@ -384,7 +384,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ #else -#define TSC_GROUP5_IO1 (uint32_t)(0x00000010U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ +#define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ @@ -397,7 +397,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ #else -#define TSC_GROUP6_IO1 (uint32_t)(0x00000020U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ +#define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ @@ -410,7 +410,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ #else -#define TSC_GROUP7_IO1 (uint32_t)(0x00000040U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ +#define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ @@ -423,7 +423,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ #else -#define TSC_GROUP8_IO1 (uint32_t)(0x00000080U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ @@ -637,7 +637,7 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ -((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & (uint32_t)TSC_NB_OF_GROUPS) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & (uint32_t)TSC_NB_OF_GROUPS) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) /** * @} @@ -683,9 +683,9 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to ((__VALUE__) == TSC_CTPL_15CYCLES) || \ ((__VALUE__) == TSC_CTPL_16CYCLES)) -#define IS_TSC_SS(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) +#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) -#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < 128U))) +#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) @@ -712,9 +712,9 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) -#define IS_TSC_MCE_IT(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) +#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) -#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < TSC_NB_OF_GROUPS))) +#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ @@ -839,6 +839,6 @@ void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); } #endif -#endif /* __STM32L4xx_HAL_TSC_H */ +#endif /* STM32L4xx_HAL_TSC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h index 6daebd17ee..2dbadf1c90 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h @@ -347,7 +347,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 } \ } \ } while(0U) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) +#elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) \ + || defined (STM32L433xx) || defined (STM32L443xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h index 47df742f8d..819de7fcdc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_USART_H -#define __STM32L4xx_HAL_USART_H +#ifndef STM32L4xx_HAL_USART_H +#define STM32L4xx_HAL_USART_H #ifdef __cplusplus extern "C" { @@ -67,7 +67,7 @@ typedef struct Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. + where fclk_pres is the USART input clock frequency (fclk) (divided by a prescaler if applicable) @note Oversampling by 8 is systematically applied to achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. @@ -130,13 +130,12 @@ typedef enum USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } USART_ClockSourceTypeDef; - /** * @brief USART handle Structure definition */ typedef struct __USART_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ USART_InitTypeDef Init; /*!< USART communication parameters */ @@ -158,31 +157,31 @@ typedef struct __USART_HandleTypeDef uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ -#endif +#endif #if defined(USART_CR2_SLVEN) uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ -#endif +#endif #if defined(USART_CR1_FIFOEN) uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value of @ref USARTEx_FIFO_mode. */ -#endif - void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ +#endif + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ - void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ - DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ - __IO uint32_t ErrorCode; /*!< USART Error code */ + __IO uint32_t ErrorCode; /*!< USART Error code */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ @@ -467,6 +466,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @{ */ #define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ /** * @} */ @@ -600,9 +603,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -622,9 +625,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. @@ -647,7 +650,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -671,7 +674,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != RESET) ? SET : RESET) + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. @@ -968,6 +971,6 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); } #endif -#endif /* __STM32L4xx_HAL_USART_H */ +#endif /* STM32L4xx_HAL_USART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h index e10439ff77..295568ccd6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_USART_EX_H -#define __STM32L4xx_HAL_USART_EX_H +#ifndef STM32L4xx_HAL_USART_EX_H +#define STM32L4xx_HAL_USART_EX_H #ifdef __cplusplus extern "C" { @@ -189,6 +189,10 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #else #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -256,6 +260,10 @@ extern "C" { break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0) #endif /* STM32L432xx || STM32L442xx */ @@ -303,6 +311,10 @@ extern "C" { (__HANDLE__)->Mask = 0x003FU; \ } \ } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ } while(0U) @@ -375,7 +387,7 @@ extern "C" { * @{ */ -/** @addtogroup USARTEx_Exported_Functions_Group2 +/** @addtogroup USARTEx_Exported_Functions_Group1 * @{ */ @@ -389,7 +401,7 @@ void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); * @} */ -/** @addtogroup USARTEx_Exported_Functions_Group3 +/** @addtogroup USARTEx_Exported_Functions_Group2 * @{ */ @@ -426,6 +438,6 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui } #endif -#endif /* __STM32L4xx_HAL_USART_EX_H */ +#endif /* STM32L4xx_HAL_USART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h index 344a784773..b86fb350c0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h @@ -69,35 +69,33 @@ extern "C" { /* Internal register offset for ADC group regular sequencer configuration */ /* (offset placed into a spare area of literal definition) */ -#define ADC_SQR1_REGOFFSET (0x00000000U) -#define ADC_SQR2_REGOFFSET (0x00000100U) -#define ADC_SQR3_REGOFFSET (0x00000200U) -#define ADC_SQR4_REGOFFSET (0x00000300U) +#define ADC_SQR1_REGOFFSET (0x00000000UL) +#define ADC_SQR2_REGOFFSET (0x00000100UL) +#define ADC_SQR3_REGOFFSET (0x00000200UL) +#define ADC_SQR4_REGOFFSET (0x00000300UL) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#if defined(CORE_CM0PLUS) -#define ADC_SQRX_REGOFFSET_POS (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ -#endif +#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */ -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */ -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */ -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */ -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */ -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */ -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */ @@ -108,23 +106,21 @@ extern "C" { /* Internal register offset for ADC group injected data register */ /* (offset placed into a spare area of literal definition) */ -#define ADC_JDR1_REGOFFSET (0x00000000U) -#define ADC_JDR2_REGOFFSET (0x00000100U) -#define ADC_JDR3_REGOFFSET (0x00000200U) -#define ADC_JDR4_REGOFFSET (0x00000300U) +#define ADC_JDR1_REGOFFSET (0x00000000UL) +#define ADC_JDR2_REGOFFSET (0x00000100UL) +#define ADC_JDR3_REGOFFSET (0x00000200UL) +#define ADC_JDR4_REGOFFSET (0x00000300UL) #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) -#if defined(CORE_CM0PLUS) -#define ADC_JDRX_REGOFFSET_POS (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ -#endif +#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ -#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ -#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ -#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ -#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ +#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */ +#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */ +#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */ +#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */ @@ -137,22 +133,22 @@ extern "C" { /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 3U)) ) +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */ @@ -165,22 +161,22 @@ extern "C" { /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3U)) ) +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ -#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */ -#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */ @@ -197,31 +193,29 @@ extern "C" { /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /* Internal register offset for ADC channel sampling time configuration */ /* (offset placed into a spare area of literal definition) */ -#define ADC_SMPR1_REGOFFSET (0x00000000U) -#define ADC_SMPR2_REGOFFSET (0x02000000U) +#define ADC_SMPR1_REGOFFSET (0x00000000UL) +#define ADC_SMPR2_REGOFFSET (0x02000000UL) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) -#if defined(CORE_CM0PLUS) -#define ADC_SMPRX_REGOFFSET_POS (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ -#endif +#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ -#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER (0x00000000U) +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) @@ -265,25 +259,25 @@ extern "C" { /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */ -#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */ +#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ /* Internal mask for ADC mode single or differential ended: */ @@ -295,12 +289,10 @@ extern "C" { #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ -#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ -#if defined(CORE_CM0PLUS) -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000U) /* Selection of 1 bit to discriminate differential mode: mask of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16U) /* Selection of 1 bit to discriminate differential mode: position of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ -#endif +#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ @@ -312,14 +304,14 @@ extern "C" { /* selection on groups. */ /* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET (0x00000000U) -#define ADC_AWD_CR2_REGOFFSET (0x00100000U) -#define ADC_AWD_CR3_REGOFFSET (0x00200000U) +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) -#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) @@ -327,35 +319,33 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) -#define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#if defined(CORE_CM0PLUS) #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000U) /* Selection of 1 bit to discriminate threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16U) /* Selection of 1 bit to discriminate threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ -#endif +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset number configuration */ -#define ADC_OFR1_REGOFFSET (0x00000000U) -#define ADC_OFR2_REGOFFSET (0x00000001U) -#define ADC_OFR3_REGOFFSET (0x00000002U) -#define ADC_OFR4_REGOFFSET (0x00000003U) +#define ADC_OFR1_REGOFFSET (0x00000000UL) +#define ADC_OFR2_REGOFFSET (0x00000001UL) +#define ADC_OFR3_REGOFFSET (0x00000002UL) +#define ADC_OFR4_REGOFFSET (0x00000003UL) #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ -#define ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */ -#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */ -#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */ -#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */ -#define ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */ +#define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */ +#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */ +#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */ +#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ /* ADC registers bits groups */ @@ -364,18 +354,18 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #else -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #endif -#define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ /** @@ -388,17 +378,6 @@ extern "C" { * @{ */ -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits - */ -#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset @@ -408,7 +387,7 @@ extern "C" { * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -686,9 +665,9 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ #endif /** * @} @@ -700,7 +679,7 @@ typedef struct #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock without prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ @@ -724,7 +703,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ @@ -735,7 +714,7 @@ typedef struct /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ @@ -746,7 +725,7 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} @@ -755,7 +734,7 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} @@ -775,7 +754,7 @@ typedef struct /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state * @{ */ -#define LL_ADC_OFFSET_DISABLE (0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} @@ -784,9 +763,9 @@ typedef struct /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /*!< ADC both groups regular and injected */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ /** * @} */ @@ -834,7 +813,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ @@ -868,7 +847,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -877,9 +856,9 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ @@ -888,7 +867,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} @@ -899,7 +878,7 @@ typedef struct /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration * @{ */ -#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000U) /*!< ADC sampling time let to default settings. */ +#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ /** * @} @@ -909,7 +888,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -918,7 +897,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ @@ -941,7 +920,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ @@ -980,7 +959,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ -#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ @@ -1014,7 +993,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} @@ -1023,7 +1002,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** @@ -1033,7 +1012,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ @@ -1044,7 +1023,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -1064,7 +1043,7 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U) /*!< Sampling time 2.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ @@ -1099,7 +1078,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ @@ -1209,7 +1188,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ @@ -1221,7 +1200,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} @@ -1230,7 +1209,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ @@ -1245,7 +1224,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ @@ -1262,7 +1241,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ @@ -1277,7 +1256,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ @@ -1289,7 +1268,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ @@ -1381,19 +1360,19 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12U) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 120U) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ @@ -1402,7 +1381,7 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -1496,7 +1475,7 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ ? ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ ) \ @@ -1555,19 +1534,19 @@ typedef struct * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9U) \ - ? ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9UL) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ ) /** @@ -1629,7 +1608,7 @@ typedef struct * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) /** * @brief Helper macro to convert a channel defined from parameter @@ -1765,7 +1744,7 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \ ) \ : \ - (0U) \ + (0UL) \ ) #elif defined (ADC1) && defined (ADC2) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ @@ -1783,7 +1762,7 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ ) \ : \ - (0U) \ + (0UL) \ ) #elif defined (ADC1) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ @@ -2015,13 +1994,8 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#if defined(CORE_CM0PLUS) #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) -#else -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) -#endif /** * @brief Helper macro to set the ADC calibration value with both single ended @@ -2036,13 +2010,8 @@ typedef struct * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -#if defined(CORE_CM0PLUS) #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) -#else -#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ - (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) -#endif #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2058,8 +2027,35 @@ typedef struct * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#endif + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to select, from a ADC instance, to which ADC instance + * it has a dependence in multimode (ADC master of the corresponding + * ADC common instance). + * @note In case of device with multimode available and a mix of + * ADC instances compliant and not compliant with multimode feature, + * ADC instances not compliant with multimode feature are + * considered as master instances (do not depend to + * any other ADC instance). + * @param __ADCx__ ADC instance + * @retval __ADCx__ ADC instance master of the corresponding ADC common instance + */ +#if defined(ADC2) +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ + ( ( ((__ADCx__) == ADC2) \ + )? \ + (ADC1) \ + : \ + (__ADCx__) \ + ) +#else +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ + (__ADCx__) +#endif #endif /** @@ -2125,10 +2121,10 @@ typedef struct * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) /** * @brief Helper macro to convert the ADC conversion data from @@ -2152,8 +2148,8 @@ typedef struct __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ ) /** @@ -2327,13 +2323,13 @@ typedef struct ((( ( \ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000) \ + * 1000UL) \ - \ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000) \ + * 1000UL) \ ) \ - ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ ) /** @@ -2390,7 +2386,7 @@ typedef struct #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2588,15 +2584,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { -#if defined(CORE_CM0PLUS) MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); -#else - MODIFY_REG(ADCx->CALFACT, - SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, - CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); -#endif } /** @@ -2621,11 +2611,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); -#else - return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); -#endif } /** @@ -2728,7 +2714,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). @@ -2781,7 +2767,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). @@ -2964,7 +2950,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -2990,7 +2976,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3023,8 +3009,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register uint32_t *preg = (uint32_t *)((uint32_t) - ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, @@ -3050,7 +3035,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3182,7 +3167,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -3205,7 +3190,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); + return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } /** @@ -3511,11 +3496,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); -#endif MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -3620,11 +3601,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t) ((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -3916,7 +3893,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); + register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -3939,7 +3916,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); + return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } /** @@ -4553,7 +4530,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - register uint32_t is_trigger_not_sw = (uint32_t)(TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE); + register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR , ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -4685,19 +4662,11 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), - SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); -#endif } /** @@ -4785,21 +4754,12 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) - >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) - ); -#endif } /** @@ -4857,7 +4817,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK, - (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); + (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } /** @@ -5063,21 +5023,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - - MODIFY_REG(*preg, - (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), - AWDChannelGroup & AWDy); -#endif } /** @@ -5204,7 +5155,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -5213,11 +5164,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if(AnalogWDMonitChannels != 0) + if(AnalogWDMonitChannels != 0UL) { if(AWDy == LL_ADC_AWD1) { - if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0) + if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ AnalogWDMonitChannels = (( AnalogWDMonitChannels @@ -5288,6 +5239,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -5314,11 +5269,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); -#endif MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5354,6 +5305,10 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -5382,19 +5337,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - AWDThresholdsHighLow, - AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); -#endif } /** @@ -5427,21 +5374,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) ); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - (AWDThresholdsHighLow | ADC_TR1_LT1)) - >> POSITION_VAL(AWDThresholdsHighLow) - ); -#endif } /** @@ -5940,7 +5878,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); + return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } /** @@ -5989,7 +5927,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } /** @@ -6049,7 +5987,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } /** @@ -6060,7 +5998,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } /** @@ -6104,7 +6042,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD */ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } /** @@ -6171,7 +6109,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } /** @@ -6182,7 +6120,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } /** @@ -6285,7 +6223,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) - >> POSITION_VAL(ConversionData) + >> (POSITION_VAL(ConversionData) & 0x1FUL) ); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -6354,7 +6292,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } /** @@ -6365,7 +6303,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } /** @@ -6387,11 +6325,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6418,11 +6352,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6449,11 +6379,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6480,11 +6406,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6511,11 +6433,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif + register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6541,7 +6459,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } /** @@ -6552,7 +6470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } /** @@ -6563,7 +6481,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } /** @@ -6574,7 +6492,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } /** @@ -6585,7 +6503,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } /** @@ -6596,7 +6514,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } /** @@ -6607,7 +6525,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } /** @@ -6618,7 +6536,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } /** @@ -6629,7 +6547,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } /** @@ -6640,7 +6558,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } /** @@ -6651,7 +6569,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } /** @@ -6788,7 +6706,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } /** @@ -6800,7 +6718,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } /** @@ -6812,7 +6730,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** @@ -6824,7 +6742,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** @@ -6836,7 +6754,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } /** @@ -6848,7 +6766,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } /** @@ -6860,7 +6778,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } /** @@ -6872,7 +6790,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } /** @@ -6884,7 +6802,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } /** @@ -6896,7 +6814,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } /** @@ -6908,7 +6826,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } /** @@ -6920,7 +6838,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } /** @@ -6932,7 +6850,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } /** @@ -6944,7 +6862,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } /** @@ -6956,7 +6874,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } /** @@ -6968,7 +6886,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } /** @@ -6980,7 +6898,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } /** @@ -6992,7 +6910,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } /** @@ -7004,7 +6922,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } /** @@ -7016,7 +6934,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } /** @@ -7028,7 +6946,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } /** @@ -7040,7 +6958,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -7303,7 +7221,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } /** @@ -7315,7 +7233,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } /** @@ -7327,7 +7245,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } /** @@ -7339,7 +7257,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } /** @@ -7351,7 +7269,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } /** @@ -7363,7 +7281,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } /** @@ -7375,7 +7293,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } /** @@ -7387,7 +7305,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } /** @@ -7399,7 +7317,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } /** @@ -7411,7 +7329,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } /** @@ -7423,7 +7341,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) { - return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h index 0b08bfaaa2..ab14b52cec 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h @@ -51,8 +51,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_BUS_H -#define __STM32L4xx_LL_BUS_H +#ifndef STM32L4xx_LL_BUS_H +#define STM32L4xx_LL_BUS_H #ifdef __cplusplus extern "C" { @@ -373,7 +373,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -627,7 +627,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -923,7 +923,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1193,7 +1193,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1213,7 +1213,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1733,7 +1733,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1965,6 +1965,6 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) } #endif -#endif /* __STM32L4xx_LL_BUS_H */ +#endif /* STM32L4xx_LL_BUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h index d9e204422e..0659e911cb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h @@ -62,7 +62,7 @@ extern "C" { */ /* COMP registers bits positions */ -#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ +#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ /** * @} @@ -125,8 +125,10 @@ typedef struct /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ -#define LL_COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ +#if defined(COMP2) +#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#endif /* COMP2 */ /** * @} */ @@ -134,7 +136,7 @@ typedef struct /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ -#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ #define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** @@ -144,7 +146,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -204,7 +206,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis * @{ */ -#define LL_COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ #define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -215,7 +217,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity * @{ */ -#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ #define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */ /** * @} @@ -224,7 +226,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source * @{ */ -#define LL_COMP_BLANKINGSRC_NONE (0x00000000U) /*!__REG__, (__VALUE__)) +#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in COMP register @@ -312,7 +314,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -346,6 +348,7 @@ typedef struct * @{ */ +#if defined(COMP2) /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances * @{ */ @@ -387,6 +390,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy * @} */ +#endif /* COMP2 */ /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes * @{ */ @@ -793,7 +797,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) { - return (READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)); + return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } /** @@ -820,7 +824,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) { - return (READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)); + return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h index 4818f11f4a..cbad5301ef 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h @@ -143,24 +143,29 @@ extern "C" { * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz * and a synchronization signal frequency of 1 kHz (SOF signal from USB) */ -#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) /** * @brief Reset value of Frequency error limit. */ -#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) /** * @brief Reset value of the HSI48 Calibration field - * @note The default value is 32, which corresponds to the middle of the trimming interval. - * The trimming step is around 67 kHz between two consecutive TRIM steps. + * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds + * to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. * A higher TRIM value corresponds to a higher output frequency */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) +#if defined (STM32L412xx) || defined (STM32L422xx) +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U) +#else +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U) +#endif /** * @} - */ - + */ + /** * @} */ @@ -200,7 +205,7 @@ extern "C" { /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between + * @note The RELOAD value should be selected according to the ratio between * the target frequency and the frequency of the synchronization source after * prescaling. It is then decreased by one in order to reach the expected * synchronization on the zero value. The formula is the following: @@ -293,8 +298,8 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) * @brief Set HSI48 oscillator smooth trimming * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 63 - * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT * @retval None */ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) @@ -305,7 +310,7 @@ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) /** * @brief Get HSI48 oscillator smooth trimming * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 63 + * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise */ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) { @@ -316,7 +321,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) * @brief Set counter reload value * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF - * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) * @retval None */ @@ -339,7 +344,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) * @brief Set frequency error limit * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit * @param Value a number between Min_Data = 0 and Max_Data = 255 - * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT * @retval None */ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) @@ -467,8 +472,8 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) { MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); - MODIFY_REG(CRS->CFGR, - CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); } @@ -491,7 +496,7 @@ __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) } /** - * @brief Get the frequency error direction latched in the time of the last + * @brief Get the frequency error direction latched in the time of the last * SYNC event * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection * @retval Returned value can be one of the following values: @@ -612,7 +617,7 @@ __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) } /** - * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also * the ERR flag * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR * @retval None @@ -768,7 +773,7 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions * @{ */ - + ErrorStatus LL_CRS_DeInit(void); /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h index eb45ab695f..7944c8f04c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DAC_H -#define __STM32L4xx_LL_DAC_H +#ifndef STM32L4xx_LL_DAC_H +#define STM32L4xx_LL_DAC_H #ifdef __cplusplus extern "C" { @@ -74,9 +74,9 @@ extern "C" { #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) -#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) #else #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) @@ -86,18 +86,18 @@ extern "C" { #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) @@ -105,17 +105,27 @@ extern "C" { #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_SHSR2_REGOFFSET 0x00001000U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */ +#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */ #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) #else #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) #endif /* DAC_CHANNEL2_SUPPORT */ +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ + /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ @@ -131,17 +141,6 @@ extern "C" { * @{ */ -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits -*/ -#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset @@ -171,34 +170,35 @@ typedef struct { uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE @note If waveform automatic generation mode is disabled, this parameter is discarded. - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() + depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ } LL_DAC_InitTypeDef; @@ -254,6 +254,18 @@ typedef struct /** * @} */ +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode + * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode + * @{ + */ +#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ +/** + * @} + */ +#endif /* High frequency interface mode */ /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode * @{ @@ -271,13 +283,13 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ #else @@ -370,28 +382,6 @@ typedef struct * @} */ -/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming - * @{ - */ -#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE) -#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO) -#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO) -#define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) -#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO) -#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO) -#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO) -#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9) - -#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE) -#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE) -#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) - -#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO) -#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL) -/** - * @} - */ - /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ @@ -407,9 +397,9 @@ typedef struct /* List of DAC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ -#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ -#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ -#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ /** * @} */ @@ -448,7 +438,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 2U /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */ /** * @} @@ -502,11 +492,8 @@ typedef struct * number is returned. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. - * @retval 1...2 (value "2" depending on DAC channel 2 availability) + * @arg @ref LL_DAC_CHANNEL_2 + * @retval 1...2 */ #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((__CHANNEL__) & DAC_SWTR_CHX_MASK) @@ -519,13 +506,10 @@ typedef struct * will return a data equivalent to "LL_DAC_CHANNEL_1". * @note If the input parameter does not correspond to a DAC channel, * this macro returns value '0'. - * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) + * @param __DECIMAL_NB__ 1...2 * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 */ #if defined(DAC_CHANNEL2_SUPPORT) #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ @@ -609,6 +593,46 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC instance + * @{ + */ + + +/** + * @brief Set the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode + * @param DACx DAC instance + * @param HighFreqMode This parameter can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode) +{ + MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode); +} + +/** + * @brief Get the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode + * @param DACx DAC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + */ +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL)); +} +/** + * @} + */ + +#endif /* High frequency interface mode */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -621,10 +645,7 @@ typedef struct * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * - * @arg @ref LL_DAC_CHANNEL_2 (1) - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param ChannelMode This parameter can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION @@ -645,10 +666,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION @@ -669,10 +687,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F * @retval None */ @@ -692,10 +707,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -718,19 +730,21 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + * @retval None */ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) @@ -752,18 +766,23 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_DAC_TRIGGER_EXT_IT9 + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) { @@ -781,7 +800,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: @@ -806,7 +825,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -835,7 +854,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: @@ -869,7 +888,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -907,7 +926,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: @@ -941,7 +960,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -988,7 +1007,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * (both connections to GPIO pin and internal path). * @note Mode sample-and-hold requires an external capacitor * to be connected between DAC channel output and ground. - * Capacitor value depends on load on DAC channel output and + * Capacitor value depends on load on DAC channel output and * sample-and-hold timings configured. * As indication, capacitor typical value is 100nF * (refer to device datasheet, parameter "CSH"). @@ -998,7 +1017,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: @@ -1024,7 +1043,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel * for the selected DAC channel. * @note Mode sample-and-hold requires an external capacitor * to be connected between DAC channel output and ground. - * Capacitor value depends on load on DAC channel output and + * Capacitor value depends on load on DAC channel output and * sample-and-hold timings configured. * As indication, capacitor typical value is 100nF * (refer to device datasheet, parameter "CSH"). @@ -1034,7 +1053,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: @@ -1045,7 +1064,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1057,7 +1076,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1066,7 +1085,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe */ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1083,7 +1102,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: @@ -1094,7 +1113,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1106,7 +1125,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1115,7 +1134,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan */ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1138,7 +1157,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputConnection This parameter can be one of the following values: @@ -1149,7 +1168,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1171,7 +1190,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1180,7 +1199,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ */ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1198,7 +1217,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1206,8 +1225,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); - + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); @@ -1222,15 +1241,15 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); - + register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1243,7 +1262,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, ui * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1265,7 +1284,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1286,7 +1305,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF @@ -1308,7 +1327,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x00 and Max_Data=0xFF @@ -1320,24 +1339,6 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, u ); } -/** - * @} - */ - -/** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name - * @{ - */ -/* Old functions name kept for legacy purpose, to be replaced by the */ -/* current functions name. */ -__STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode) -{ - LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode); -} -__STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel); -} - /** * @} */ @@ -1356,7 +1357,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Chan * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1377,7 +1378,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1397,16 +1398,16 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -1434,7 +1435,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: @@ -1447,7 +1448,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -1468,7 +1469,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1487,7 +1488,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1507,16 +1508,16 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -1535,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1554,7 +1555,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1574,22 +1575,24 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** * @brief Trig DAC conversion by software for the selected DAC channel. * @note Preliminarily, DAC trigger must be set to software trigger - * using function @ref LL_DAC_SetTriggerSource() + * using function + * @ref LL_DAC_Init() + * @ref LL_DAC_SetTriggerSource() * with parameter "LL_DAC_TRIGGER_SOFTWARE". * and DAC trigger must be enabled using * function @ref LL_DAC_EnableTrigger(). @@ -1603,7 +1606,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can a combination of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1624,7 +1627,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF @@ -1632,8 +1635,8 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); - + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); @@ -1649,7 +1652,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF @@ -1657,8 +1660,8 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); - + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); @@ -1674,7 +1677,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF @@ -1682,8 +1685,8 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); - + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); @@ -1760,15 +1763,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); - + register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } @@ -1787,7 +1790,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1799,7 +1802,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1811,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1823,7 +1826,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1835,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1847,7 +1850,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1939,7 +1942,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1951,7 +1954,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1991,6 +1994,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); } #endif -#endif /* __STM32L4xx_LL_DAC_H */ +#endif /* STM32L4xx_LL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h index e875fd5d85..f5bf5bdefc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2016 STMicroelectronics

          + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMA_H -#define __STM32L4xx_LL_DMA_H +#ifndef STM32L4xx_LL_DMA_H +#define STM32L4xx_LL_DMA_H #ifdef __cplusplus extern "C" { @@ -106,7 +106,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). */ #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ -(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) +(((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7) /** * @} @@ -379,108 +379,7 @@ typedef struct * @} */ -#if defined(DMAMUX1) -/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request - * @{ - */ -#define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ -#define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ -#define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ -#define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ -#define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ -#define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ -#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ -#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ -#define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ -#define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ -#define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ -#define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ -#define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ -#define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ -#define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ -#define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ -#define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ -#define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ -#define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ -#define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ -#define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ -#define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ -#define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ -#define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ -#define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ -#define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ -#define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ -#define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ -#define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ -#define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ -#define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ -#define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ -#define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ -#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ -#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ -#define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ -#define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ -#define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ -#define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ -#define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ -#define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ -#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ -#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ -#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ -#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ -#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ -#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ -#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ -#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ -#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ -#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ -#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ -#define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ -#define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ -#define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ -#define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ -/** - * @} - */ -#else +#if !defined (DMAMUX1) /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request * @{ */ @@ -495,7 +394,7 @@ typedef struct /** * @} */ -#endif /* DMAMUX1 */ +#endif /* !defined DMAMUX1 */ /** * @} @@ -710,8 +609,8 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } /** @@ -1348,105 +1247,105 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Request This parameter can be one of the following values: - * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 - * @arg @ref LL_DMAMUX_REQUEST_ADC1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP - * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX - * @arg @ref LL_DMAMUX_REQUEST_USART1_RX - * @arg @ref LL_DMAMUX_REQUEST_USART1_TX - * @arg @ref LL_DMAMUX_REQUEST_USART2_RX - * @arg @ref LL_DMAMUX_REQUEST_USART2_TX - * @arg @ref LL_DMAMUX_REQUEST_USART3_RX - * @arg @ref LL_DMAMUX_REQUEST_USART3_TX - * @arg @ref LL_DMAMUX_REQUEST_UART4_RX - * @arg @ref LL_DMAMUX_REQUEST_UART4_TX - * @arg @ref LL_DMAMUX_REQUEST_UART5_RX - * @arg @ref LL_DMAMUX_REQUEST_UART5_TX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX - * @arg @ref LL_DMAMUX_REQUEST_SAI1_A - * @arg @ref LL_DMAMUX_REQUEST_SAI1_B - * @arg @ref LL_DMAMUX_REQUEST_SAI2_A - * @arg @ref LL_DMAMUX_REQUEST_SAI2_B - * @arg @ref LL_DMAMUX_REQUEST_OSPI1 - * @arg @ref LL_DMAMUX_REQUEST_OSPI2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 - * @arg @ref LL_DMAMUX_REQUEST_DCMI - * @arg @ref LL_DMAMUX_REQUEST_AES_IN - * @arg @ref LL_DMAMUX_REQUEST_AES_OUT - * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN * @retval None */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); + MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1U)) + (DMAMUX_CCR_SIZE * __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** @@ -1464,104 +1363,104 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: - * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 - * @arg @ref LL_DMAMUX_REQUEST_ADC1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP - * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX - * @arg @ref LL_DMAMUX_REQUEST_USART1_RX - * @arg @ref LL_DMAMUX_REQUEST_USART1_TX - * @arg @ref LL_DMAMUX_REQUEST_USART2_RX - * @arg @ref LL_DMAMUX_REQUEST_USART2_TX - * @arg @ref LL_DMAMUX_REQUEST_USART3_RX - * @arg @ref LL_DMAMUX_REQUEST_USART3_TX - * @arg @ref LL_DMAMUX_REQUEST_UART4_RX - * @arg @ref LL_DMAMUX_REQUEST_UART4_TX - * @arg @ref LL_DMAMUX_REQUEST_UART5_RX - * @arg @ref LL_DMAMUX_REQUEST_UART5_TX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX - * @arg @ref LL_DMAMUX_REQUEST_SAI1_A - * @arg @ref LL_DMAMUX_REQUEST_SAI1_B - * @arg @ref LL_DMAMUX_REQUEST_SAI2_A - * @arg @ref LL_DMAMUX_REQUEST_SAI2_B - * @arg @ref LL_DMAMUX_REQUEST_OSPI1 - * @arg @ref LL_DMAMUX_REQUEST_OSPI2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 - * @arg @ref LL_DMAMUX_REQUEST_DCMI - * @arg @ref LL_DMAMUX_REQUEST_AES_IN - * @arg @ref LL_DMAMUX_REQUEST_AES_OUT - * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1U)) + (DMAMUX_CCR_SIZE * __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } #else /** @@ -1651,7 +1550,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } /** @@ -1662,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } /** @@ -1673,7 +1572,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } /** @@ -1684,7 +1583,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } /** @@ -1695,7 +1594,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } /** @@ -1706,7 +1605,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } /** @@ -1717,7 +1616,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } /** @@ -1728,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } /** @@ -1739,7 +1638,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } /** @@ -1750,7 +1649,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } /** @@ -1761,7 +1660,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } /** @@ -1772,7 +1671,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } /** @@ -1783,7 +1682,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } /** @@ -1794,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } /** @@ -1805,7 +1704,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } /** @@ -1816,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } /** @@ -1827,7 +1726,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } /** @@ -1838,7 +1737,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } /** @@ -1849,7 +1748,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } /** @@ -1860,7 +1759,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } /** @@ -1871,7 +1770,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } /** @@ -1882,7 +1781,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } /** @@ -1893,7 +1792,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } /** @@ -1904,7 +1803,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } /** @@ -1915,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } /** @@ -1926,7 +1825,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } /** @@ -1937,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } /** @@ -1948,7 +1847,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } /** @@ -2396,8 +2295,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } /** @@ -2416,8 +2315,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } /** @@ -2436,8 +2335,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } /** @@ -2448,9 +2347,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Chann /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions * @{ */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); /** @@ -2476,6 +2374,6 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); } #endif -#endif /* __STM32L4xx_LL_DMA_H */ +#endif /* STM32L4xx_LL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h index fa0d0f018f..dbcff2e2dd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMAMUX_H -#define __STM32L4xx_LL_DMAMUX_H +#ifndef STM32L4xx_LL_DMAMUX_H +#define STM32L4xx_LL_DMAMUX_H #ifdef __cplusplus extern "C" { @@ -61,10 +61,10 @@ extern "C" { * @{ */ /* Define used to get DMAMUX CCR register size */ -#define DMAMUX_CCR_SIZE 0x00000004U +#define DMAMUX_CCR_SIZE 0x00000004UL /* Define used to get DMAMUX RGCR register size */ -#define DMAMUX_RGCR_SIZE 0x00000004U +#define DMAMUX_RGCR_SIZE 0x00000004UL /** * @} */ @@ -133,9 +133,6 @@ extern "C" { */ #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ -/** - * @} - */ /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request * @{ @@ -238,6 +235,10 @@ extern "C" { * @} */ +/** + * @} + */ + /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel * @{ */ @@ -644,7 +645,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel-1)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -671,7 +672,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ, RequestNb - 1); + MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); } /** @@ -697,7 +698,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ) + 1); + return (uint32_t)(((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); } /** @@ -836,7 +837,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)); + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); } /** @@ -914,7 +915,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)); + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); } /** @@ -1067,7 +1068,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); } /** @@ -1126,7 +1127,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef */ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1) << DMAMUX_RGxCR_GNBREQ_Pos); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } /** @@ -1142,7 +1143,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } /** @@ -1246,7 +1247,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); } /** @@ -1257,7 +1258,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);; } /** @@ -1268,7 +1269,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);; } /** @@ -1279,7 +1280,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);; } /** @@ -1290,7 +1291,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);; } /** @@ -1301,7 +1302,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);; } /** @@ -1312,7 +1313,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } /** @@ -1323,7 +1324,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } /** @@ -1334,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } /** @@ -1345,7 +1346,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } /** @@ -1356,7 +1357,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } /** @@ -1367,7 +1368,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } /** @@ -1378,7 +1379,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); } /** @@ -1389,7 +1390,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); } /** @@ -1400,7 +1401,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);; } /** @@ -1411,7 +1412,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);; } /** @@ -1422,7 +1423,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);; } /** @@ -1433,7 +1434,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);; } /** @@ -1717,7 +1718,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE)); + return (((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); } /** @@ -1765,7 +1766,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); } /** @@ -1790,6 +1791,6 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU } #endif -#endif /* __STM32L4xx_LL_DMAMUX_H */ +#endif /* STM32L4xx_LL_DMAMUX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h index ba9eb4c88b..3d7ab6c441 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h @@ -200,6 +200,8 @@ typedef struct /** * @} */ + + #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_EC_MODE Mode @@ -464,7 +466,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -489,7 +491,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -677,7 +679,7 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } @@ -700,7 +702,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -878,7 +880,7 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -893,7 +895,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1068,7 +1070,7 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1083,7 +1085,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1200,7 +1202,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1217,7 +1219,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1259,7 +1261,6 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); } - /** * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 * @note This bit is set when the selected edge event arrives on the interrupt @@ -1333,6 +1334,7 @@ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) WRITE_REG(EXTI->PR2, ExtiLine); } + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h index ab615e73ab..6cdb9048aa 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h @@ -53,6 +53,14 @@ extern "C" { /** @defgroup GPIO_LL GPIO * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -823,7 +831,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) */ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** @@ -834,7 +842,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa */ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) { - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } /** @@ -882,7 +890,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) */ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** @@ -934,7 +942,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) */ __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h index 24ed3bc019..bedf0a733c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_I2C_H -#define __STM32L4xx_LL_I2C_H +#ifndef STM32L4xx_LL_I2C_H +#define STM32L4xx_LL_I2C_H #ifdef __cplusplus extern "C" { @@ -431,7 +431,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } /** @@ -513,7 +513,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } /** @@ -546,7 +546,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } /** @@ -579,7 +579,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } /** @@ -642,7 +642,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } /** @@ -675,7 +675,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } /** @@ -715,7 +715,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } /** @@ -750,7 +750,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } /** @@ -827,7 +827,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)); + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } /** @@ -883,7 +883,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)); + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } /** @@ -1038,7 +1038,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } /** @@ -1077,7 +1077,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } /** @@ -1242,7 +1242,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1283,7 +1283,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } /** @@ -1316,7 +1316,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } /** @@ -1349,7 +1349,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } /** @@ -1382,7 +1382,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } /** @@ -1415,7 +1415,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } /** @@ -1454,7 +1454,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } /** @@ -1505,7 +1505,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } /** @@ -1526,7 +1526,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } /** @@ -1539,7 +1539,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } /** @@ -1552,7 +1552,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } /** @@ -1565,7 +1565,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } /** @@ -1578,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } /** @@ -1591,7 +1591,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } /** @@ -1604,7 +1604,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } /** @@ -1617,7 +1617,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } /** @@ -1630,7 +1630,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } /** @@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } /** @@ -1656,7 +1656,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } /** @@ -1671,7 +1671,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } /** @@ -1686,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } /** @@ -1702,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } /** @@ -1715,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } /** @@ -1876,7 +1876,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } /** @@ -1911,7 +1911,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } /** @@ -2010,7 +2010,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } /** @@ -2163,7 +2163,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } /** @@ -2211,8 +2211,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); @@ -2239,6 +2239,6 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); } #endif -#endif /* __STM32L4xx_LL_I2C_H */ +#endif /* STM32L4xx_LL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h index e8598f1ae2..f0efeb3f97 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h @@ -160,7 +160,7 @@ extern "C" { */ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); } /** @@ -171,7 +171,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); } /** @@ -182,7 +182,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); } /** @@ -193,7 +193,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); } /** @@ -230,7 +230,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale */ __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->PR)); + return (READ_REG(IWDGx->PR)); } /** @@ -253,7 +253,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun */ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->RLR)); + return (READ_REG(IWDGx->RLR)); } /** @@ -276,7 +276,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) */ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->WINR)); + return (READ_REG(IWDGx->WINR)); } /** @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); + return (uint32_t)(READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); } /** @@ -306,7 +306,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); + return (uint32_t)(READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); } /** @@ -317,7 +317,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)); + return (uint32_t)(READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)); } /** @@ -330,7 +330,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U); + return (uint32_t)(READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h index 38eca67b59..affc996845 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h @@ -48,7 +48,7 @@ extern "C" { * @{ */ #if defined (LPTIM1) || defined (LPTIM2) - + /** @defgroup LPTIM_LL LPTIM * @{ */ @@ -121,6 +121,10 @@ typedef struct #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +#if defined(LPTIM_RCR_REP) +#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */ +#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */ +#endif /** * @} */ @@ -136,6 +140,10 @@ typedef struct #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#if defined(LPTIM_RCR_REP) +#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event Interrupt Enable */ +#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK Interrupt Enable */ +#endif /** * @} */ @@ -295,7 +303,7 @@ typedef struct /** * @} */ - + /** * @} */ @@ -396,6 +404,59 @@ __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t Opera MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); } +#if defined(LPTIM_CR_RSTARE) +/** + * @brief Enable reset after read. + * @note After calling this function any read access to LPTIM_CNT + * register will asynchronously reset the LPTIM_CNT register content. + * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Disable reset after read. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Indicate whether the reset after read feature is enabled. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == (LPTIM_CR_RSTARE)); +} +#endif + +#if defined(LPTIM_CR_COUNTRST) +/** + * @brief Reset of the LPTIM_CNT counter register (synchronous). + * @note Due to the synchronous nature of this reset, it only takes + * place after a synchronization delay of 3 LPTIM core clock cycles + * (LPTIM core clock may be different from APB clock). + * @note COUNTRST is automatically cleared by hardware + * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); +} +#endif /** * @brief Set the LPTIM registers update mode (enable/disable register preload) @@ -454,6 +515,32 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } +#if defined(LPTIM_RCR_REP) +/** + * @brief Set the repetition value + * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled + * @rmtoll RCR REP LL_LPTIM_SetRepetition + * @param LPTIMx Low-Power Timer instance + * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition) +{ + MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition); +} + +/** + * @brief Get the repetition value + * @rmtoll RCR REP LL_LPTIM_GetRepetition + * @param LPTIMx Low-Power Timer instance + * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); +} +#endif + /** * @brief Set the compare value * @note After a write to the LPTIMx_CMP register a new write operation to the @@ -1150,6 +1237,52 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN)); } +#if defined(LPTIM_RCR_REP) +/** + * @brief Clear the repetition register update interrupt flag (REPOKCF). + * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully completed; If so, a new one can be initiated. + * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)); +} + +/** + * @brief Clear the update event flag (UECF). + * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF); +} + +/** + * @brief Informs application whether the LPTIMx update event has occurred. + * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)); +} +#endif + /** * @} */ @@ -1389,6 +1522,74 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE)); } +#if defined(LPTIM_RCR_REP) +/** + * @brief Enable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE); +} + +/** + * @brief Disable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE); +} + +/** + * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. + * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)); +} + +/** + * @brief Enable update event interrupt (UEIE). + * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE); +} + +/** + * @brief Disable update event interrupt (UEIE). + * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE); +} + +/** + * @brief Indicates whether the update event interrupt (UEIE) is enabled. + * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx) +{ + return (READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)); +} +#endif + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h index b06d3771b6..b11ce8af2b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_OPAMP_H -#define __STM32L4xx_LL_OPAMP_H +#ifndef STM32L4xx_LL_OPAMP_H +#define STM32L4xx_LL_OPAMP_H #ifdef __cplusplus extern "C" { @@ -68,8 +68,8 @@ extern "C" { /* - OPAMP trimming register offset */ /* Internal register offset for OPAMP trimming configuration */ -#define OPAMP_POWERMODE_OTR_REGOFFSET ((uint32_t)0x00000000U) -#define OPAMP_POWERMODE_LPOTR_REGOFFSET ((uint32_t)0x00000001U) +#define OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U +#define OPAMP_POWERMODE_LPOTR_REGOFFSET 0x00000001U #define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET) /* Mask for OPAMP power mode into control register */ @@ -125,24 +125,24 @@ typedef struct { uint32_t PowerMode; /*!< Set OPAMP power mode. This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */ uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ... This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain(). - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */ uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection. This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */ uint32_t InputInverting; /*!< Set OPAMP inverting input connection. This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded. - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */ } LL_OPAMP_InitTypeDef; @@ -160,7 +160,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range * @{ */ -#define LL_OPAMP_POWERSUPPLY_RANGE_LOW ((uint32_t)0x00000000U) /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */ +#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */ #define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE) /*!< Power supply range high. On STM32L4 serie: Vdda higher than 2.4V. */ /** * @} @@ -178,7 +178,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional. * @{ */ -#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U) /*!< OPAMP functional mode */ +#define LL_OPAMP_MODE_FUNCTIONAL 0x00000000U /*!< OPAMP functional mode */ #define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */ /** * @} @@ -187,7 +187,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode * @{ */ -#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */ +#define LL_OPAMP_MODE_STANDALONE 0x00000000U /*!< OPAMP functional mode, OPAMP operation in standalone */ #define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */ #define LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1) /*!< OPAMP functional mode, OPAMP operation in PGA */ /** @@ -197,7 +197,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA) * @{ */ -#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U) /*!< OPAMP PGA gain 2 */ +#define LL_OPAMP_PGA_GAIN_2 0x00000000U /*!< OPAMP PGA gain 2 */ #define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */ #define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */ #define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */ @@ -208,7 +208,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting * @{ */ -#define LL_OPAMP_INPUT_NONINVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ #define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP1_CSR_VPSEL) /*!< OPAMP non inverting input connected to DAC1 channel1 output */ /** * @} @@ -217,7 +217,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting * @{ */ -#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ +#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ #define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ #define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */ /** @@ -242,7 +242,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode * @{ */ -#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */ +#define LL_OPAMP_TRIMMING_FACTORY 0x00000000U /*!< OPAMP trimming factors set to factory values */ #define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */ /** * @} @@ -299,7 +299,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in OPAMP register @@ -307,7 +307,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -444,8 +444,8 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) { register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM)); - - return (uint32_t)(power_mode | (power_mode >> (POSITION_VAL(OPAMP_CSR_OPALPM)))); + + return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPALPM_Pos))); } /** @@ -718,9 +718,9 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) { register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); - + return (CalibrationSelection | - ((OPAMP_OTR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_OTR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL)))); + (((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP)); } /** @@ -734,7 +734,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) */ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) { - return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT); + return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL); } /** @@ -758,14 +758,14 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue) { register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); - + /* Set bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ /* containing other bits reserved for other purpose. */ MODIFY_REG(*preg, - (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK), - TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))); + (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK), + TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)); } /** @@ -787,15 +787,14 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P */ __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { - register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); - + register const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); + /* Retrieve bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) - >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) - ); + >> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)); } /** @@ -839,7 +838,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) */ __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) { - return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)); + return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL); } /** @@ -878,6 +877,6 @@ void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct); } #endif -#endif /* __STM32L4xx_LL_OPAMP_H */ +#endif /* STM32L4xx_LL_OPAMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h index 67f3c63a86..083962b54c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h @@ -87,6 +87,9 @@ extern "C" { * @{ */ #define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#if defined(PWR_SR1_EXT_SMPS_RDY) +#define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY +#endif /* PWR_SR1_EXT_SMPS_RDY */ #define LL_PWR_SR1_SBF PWR_SR1_SBF #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 @@ -152,7 +155,7 @@ extern "C" { /** * @} */ - + /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL * @{ */ @@ -328,7 +331,7 @@ __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); + return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); } /** @@ -359,7 +362,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) #if defined(PWR_CR5_R1MODE) /** - * @brief Enable main regulator voltage range 1 boost mode + * @brief Enable main regulator voltage range 1 boost mode * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode * @retval None */ @@ -369,7 +372,7 @@ __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) } /** - * @brief Disable main regulator voltage range 1 boost mode + * @brief Disable main regulator voltage range 1 boost mode * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode * @retval None */ @@ -385,7 +388,7 @@ __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) { - return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); + return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL); } #endif /* PWR_CR5_R1MODE */ @@ -416,7 +419,7 @@ __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); } /** @@ -478,7 +481,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); + return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL); } #endif /* PWR_CR1_RRSTP */ @@ -510,7 +513,7 @@ __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); } #endif /* PWR_CR3_DSIPDEN */ @@ -542,7 +545,7 @@ __STATIC_INLINE void LL_PWR_DisableVddUSB(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); + return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); } #endif @@ -574,7 +577,7 @@ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); + return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); } #endif @@ -635,7 +638,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) { - return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); + return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); } /** @@ -702,7 +705,7 @@ __STATIC_INLINE void LL_PWR_DisablePVD(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); } /** @@ -732,7 +735,7 @@ __STATIC_INLINE void LL_PWR_DisableInternWU(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); + return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL); } /** @@ -762,7 +765,7 @@ __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); + return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); } #if defined(PWR_CR3_DSIPDEN) @@ -793,10 +796,42 @@ __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); } #endif /* PWR_CR3_DSIPDEN */ +#if defined(PWR_CR3_EN_ULP) +/** + * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 EN_ULP LL_PWR_EnableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EN_ULP); +} + +/** + * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 EN_ULP LL_PWR_DisableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EN_ULP); +} + +/** + * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled + * @rmtoll CR3 EN_ULP LL_PWR_IsEnabledBORPVD_ULP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_EN_ULP) == (PWR_CR3_EN_ULP)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_EN_ULP */ + /** * @brief Enable SRAM2 content retention in Standby mode * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention @@ -824,7 +859,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); + return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); } /** @@ -884,9 +919,47 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) { - return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); + return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } +#if defined(PWR_CR4_EXT_SMPS_ON) +/** + * @brief Enable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Disable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Check if CFLDO is working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL); +} +#endif /* PWR_CR4_EXT_SMPS_ON */ + /** * @brief Set the resistor impedance * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor @@ -939,7 +1012,7 @@ __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) { - return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); + return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); } /** @@ -999,7 +1072,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) { - return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); + return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } /** @@ -1140,7 +1213,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); + return ((READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1187,7 +1260,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIO */ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; + register uint32_t temp = (uint32_t)(GPIO) + 4U; SET_BIT(*((uint32_t *)(temp)), GPIONumber); } @@ -1235,7 +1308,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe */ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; + register uint32_t temp = (uint32_t)(GPIO) + 4U; CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); } @@ -1283,8 +1356,8 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; - return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); + register uint32_t temp = (uint32_t)(GPIO) + 4U; + return ((READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1302,8 +1375,20 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GP */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); +} + +#if defined(PWR_SR1_EXT_SMPS_RDY) +/** + * @brief Get Ready Flag for switching to external SMPS + * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL); } +#endif /* PWR_SR1_EXT_SMPS_RDY */ /** * @brief Get Stand-By Flag @@ -1312,7 +1397,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); + return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); } /** @@ -1322,7 +1407,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } /** @@ -1332,7 +1417,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); } /** @@ -1342,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } /** @@ -1352,7 +1437,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); } /** @@ -1362,7 +1447,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); } /** @@ -1442,7 +1527,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); } /** @@ -1452,7 +1537,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); } #if defined(PWR_SR2_PVMO2) @@ -1463,7 +1548,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL); } #endif /* PWR_SR2_PVMO2 */ @@ -1475,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); } #endif /* PWR_SR2_PVMO1 */ @@ -1486,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); } /** @@ -1496,7 +1581,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); + return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); } /** @@ -1507,7 +1592,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); } /** @@ -1517,7 +1602,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h index bf732f43d6..2a6e16a21c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_RCC_H -#define __STM32L4xx_LL_RCC_H +#ifndef STM32L4xx_LL_RCC_H +#define STM32L4xx_LL_RCC_H #ifdef __cplusplus extern "C" { @@ -56,18 +56,6 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -#if defined(RCC_CCIPR2_PLLSAI2DIVR) -static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16}; -#endif /* RCC_CCIPR2_PLLSAI2DIVR */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Constants RCC Private Constants * @{ @@ -178,7 +166,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -201,7 +191,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -232,7 +224,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -503,7 +497,7 @@ typedef struct #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ -#else +#elif defined(RCC_CCIPR_SAI1SEL) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ @@ -541,6 +535,7 @@ typedef struct */ #endif /* RCC_CCIPR2_SDMMCSEL */ +#if defined(SDMMC1) /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection * @{ */ @@ -549,12 +544,15 @@ typedef struct #else #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */ #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */ /** * @} */ +#endif /* SDMMC1 */ /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection * @{ @@ -564,7 +562,9 @@ typedef struct #else #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */ #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */ /** @@ -580,7 +580,9 @@ typedef struct #else #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */ #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */ /** @@ -593,11 +595,17 @@ typedef struct * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(RCC_CCIPR_ADCSEL) #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ +#else +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */ +#endif /** * @} */ @@ -736,6 +744,7 @@ typedef struct * @} */ +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source * @{ */ @@ -752,7 +761,9 @@ typedef struct /** * @} */ +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source * @{ @@ -770,6 +781,7 @@ typedef struct /** * @} */ +#endif /* SDMMC1 */ /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source * @{ @@ -792,7 +804,11 @@ typedef struct /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source * @{ */ +#if defined(RCC_CCIPR_ADCSEL) #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +#else +#define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */ +#endif /** * @} */ @@ -921,6 +937,7 @@ typedef struct * @} */ +#if defined(RCC_PLLP_SUPPORT) /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) * @{ */ @@ -962,6 +979,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLP_SUPPORT */ /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) * @{ @@ -999,6 +1017,7 @@ typedef struct */ #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) * @{ */ @@ -1062,6 +1081,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) @@ -1178,6 +1198,17 @@ typedef struct * @} */ +#if defined(RCC_CSR_LSIPREDIV) +/** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor + * @{ + */ +#define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */ +#define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */ +/** + * @} + */ +#endif /* RCC_CSR_LSIPREDIV */ + /** Legacy definitions for compatibility purpose @cond 0 */ @@ -1264,6 +1295,7 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) +#if defined(RCC_PLLSAI1_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain @@ -1351,6 +1383,7 @@ typedef struct (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain @@ -1387,6 +1420,7 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) +#if defined(RCC_PLLSAI1_SUPPORT) #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain @@ -1655,6 +1689,7 @@ typedef struct ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** @@ -1835,8 +1870,8 @@ typedef struct */ #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ - (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos]))) -#else + (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos)))) +#elif defined(RCC_PLLSAI2_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -2056,7 +2091,7 @@ __STATIC_INLINE void LL_RCC_HSE_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); } /** @@ -2095,7 +2130,7 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); } /** @@ -2125,7 +2160,7 @@ __STATIC_INLINE void LL_RCC_HSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); } /** @@ -2219,7 +2254,7 @@ __STATIC_INLINE void LL_RCC_HSI48_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) { - return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL); } /** @@ -2340,7 +2375,7 @@ __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); } /** @@ -2350,9 +2385,43 @@ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); +} + +#if defined(RCC_BDCR_LSESYSDIS) +/** + * @brief Disable LSE oscillator propagation + * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked + * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); } +/** + * @brief Enable LSE oscillator propagation + * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +} + +/** + * @brief Check if LSE oscillator propagation is enabled + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0x0); +} +#endif /* RCC_BDCR_LSESYSDIS */ /** * @} */ @@ -2388,9 +2457,36 @@ __STATIC_INLINE void LL_RCC_LSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); } +#if defined(RCC_CSR_LSIPREDIV) +/** + * @brief Set LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv + * @param LSI_PREDIV This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV); +} + +/** + * @brief Get LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV)); +} +#endif /* RCC_CSR_LSIPREDIV */ + /** * @} */ @@ -2426,7 +2522,7 @@ __STATIC_INLINE void LL_RCC_MSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); } /** @@ -2475,7 +2571,7 @@ __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) { - return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)); + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL); } /** @@ -2869,7 +2965,7 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale */ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) { - MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF)); + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); } #if defined(UART4) || defined(UART5) @@ -2889,7 +2985,7 @@ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) */ __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) { - MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF)); + MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); } #endif /* UART4 || UART5 */ @@ -2931,7 +3027,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U))); + MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U))); } /** @@ -2953,6 +3049,7 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** * @brief Configure SAIx clock source @if STM32L4S9xx @@ -2981,6 +3078,7 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); #endif /* RCC_CCIPR2_SAI1SEL */ } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ #if defined(RCC_CCIPR2_SDMMCSEL) /** @@ -3023,7 +3121,7 @@ __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) * @param RNGxSource This parameter can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI * @@ -3042,7 +3140,7 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_MSI * @@ -3055,12 +3153,13 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) } #endif /* USB_OTG_FS || USB */ +#if defined(RCC_CCIPR_ADCSEL) /** * @brief Configure ADC clock source * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK * @@ -3071,6 +3170,7 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); } +#endif /* RCC_CCIPR_ADCSEL */ #if defined(SWPMI1) /** @@ -3271,8 +3371,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); - return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); } /** @@ -3293,9 +3393,10 @@ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) */ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) { - return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U | LPTIMx); + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** * @brief Get SAIx clock source @if STM32L4S9xx @@ -3328,7 +3429,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); #endif /* RCC_CCIPR2_SAI1SEL */ } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** * @brief Get SDMMCx kernel clock source @@ -3365,6 +3468,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) { return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); } +#endif /* SDMMC1 */ /** * @brief Get RNGx clock source @@ -3374,7 +3478,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI * @@ -3394,7 +3498,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_MSI * @@ -3413,7 +3517,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK * @@ -3421,7 +3525,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { +#if defined(RCC_CCIPR_ADCSEL) return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +#else + return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE); +#endif /* RCC_CCIPR_ADCSEL */ } #if defined(SWPMI1) @@ -3598,7 +3706,7 @@ __STATIC_INLINE void LL_RCC_DisableRTC(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); } /** @@ -3658,7 +3766,7 @@ __STATIC_INLINE void LL_RCC_PLL_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); } /** @@ -3705,9 +3813,10 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); } +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Configure PLL used for SAI domain clock @@ -3813,12 +3922,13 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, { #if defined(RCC_PLLP_DIV_2_31_SUPPORT) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Configure PLL used for 48Mhz domain clock @@ -3865,7 +3975,7 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); } /** @@ -3907,6 +4017,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); } +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Get Main PLL division factor for PLLP @@ -3962,6 +4073,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); } #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Get Main PLL division factor for PLLQ @@ -4021,6 +4133,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); } +#if defined(RCC_PLLP_SUPPORT) /** * @brief Enable PLL output mapped on SAI domain clock * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI @@ -4044,6 +4157,7 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) { CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Enable PLL output mapped on 48MHz domain clock @@ -4097,6 +4211,7 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) * @} */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 * @{ */ @@ -4128,7 +4243,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL); } #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) @@ -4175,7 +4290,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ); } #else /** @@ -4287,7 +4402,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP); } #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** @@ -4436,7 +4551,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR); } #else /** @@ -4671,6 +4786,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 @@ -4704,7 +4820,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL); } #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) @@ -4777,7 +4893,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, - PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); + PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP); } #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** @@ -4924,7 +5040,8 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM); } #endif /* DSI */ @@ -4977,7 +5094,8 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t P __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM); MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); } #else @@ -5338,6 +5456,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Clear PLLSAI1 ready interrupt flag * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY @@ -5347,6 +5466,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) { SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5387,7 +5507,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); } /** @@ -5397,7 +5517,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); } /** @@ -5407,7 +5527,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); } /** @@ -5417,7 +5537,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); } /** @@ -5427,7 +5547,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); } /** @@ -5437,7 +5557,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL); } #if defined(RCC_HSI48_SUPPORT) @@ -5448,10 +5568,11 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Check if PLLSAI1 ready interrupt occurred or not * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY @@ -5459,8 +5580,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5470,7 +5592,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL); } #endif /* RCC_PLLSAI2_SUPPORT */ @@ -5481,7 +5603,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); } /** @@ -5491,7 +5613,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); } /** @@ -5501,7 +5623,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL); } /** @@ -5511,7 +5633,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); } /** @@ -5521,7 +5643,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); } /** @@ -5531,7 +5653,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); } /** @@ -5541,7 +5663,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); } /** @@ -5551,7 +5673,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); } /** @@ -5561,7 +5683,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); } /** @@ -5571,7 +5693,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); } /** @@ -5664,6 +5786,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Enable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY @@ -5673,6 +5796,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) { SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5768,6 +5892,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Disable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY @@ -5777,6 +5902,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) { CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5807,7 +5933,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); } /** @@ -5817,7 +5943,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); } /** @@ -5827,7 +5953,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); } /** @@ -5837,7 +5963,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); } /** @@ -5847,7 +5973,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); } /** @@ -5857,7 +5983,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL); } #if defined(RCC_HSI48_SUPPORT) @@ -5868,10 +5994,11 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY @@ -5879,8 +6006,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5890,7 +6018,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL); } #endif /* RCC_PLLSAI2_SUPPORT */ @@ -5901,7 +6029,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); } /** @@ -5928,11 +6056,15 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#if defined(SAI1) uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); #endif uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +#endif /* SDMMC1 */ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #if defined(USB_OTG_FS) || defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); @@ -5979,6 +6111,6 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); } #endif -#endif /* __STM32L4xx_LL_RCC_H */ +#endif /* STM32L4xx_LL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h index 98f992311e..2dd56855b1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_RTC_H -#define __STM32L4xx_LL_RTC_H +#ifndef STM32L4xx_LL_RTC_H +#define STM32L4xx_LL_RTC_H #ifdef __cplusplus extern "C" { @@ -61,13 +61,13 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ -#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) -#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) -#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) +#define RTC_WRITE_PROTECTION_DISABLE 0xFFU +#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU +#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U /* Defines used to combine date & time */ #define RTC_OFFSET_WEEKDAY 24U @@ -103,19 +103,19 @@ typedef struct { uint32_t HourFormat; /*!< Specifies the RTC Hours Format. This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetHourFormat(). */ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetAsynchPrescaler(). */ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetSynchPrescaler(). */ } LL_RTC_InitTypeDef; @@ -183,7 +183,7 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A or @ref LL_RTC_ALMB_SetMask() for ALARM B */ @@ -221,8 +221,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ /** * @} */ @@ -251,6 +251,23 @@ typedef struct * @brief Flags defines which can be used with LL_RTC_ReadReg function * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +#define LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF +#define LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F @@ -268,6 +285,7 @@ typedef struct #define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF #define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF #define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -280,10 +298,13 @@ typedef struct #define LL_RTC_CR_WUTIE RTC_CR_WUTIE #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +#if defined(STM32L412xx) || defined(STM32L422xx) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -291,13 +312,13 @@ typedef struct /** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY * @{ */ -#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */ -#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ /** * @} */ @@ -305,18 +326,18 @@ typedef struct /** @defgroup RTC_LL_EC_MONTH MONTH * @{ */ -#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */ -#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */ -#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */ -#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */ -#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */ -#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */ -#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */ -#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */ -#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */ -#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */ -#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */ -#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ /** * @} */ @@ -344,8 +365,12 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -439,6 +464,82 @@ typedef struct * @} */ +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** @defgroup RTC_LL_EC_TAMPER TAMPER * @{ */ @@ -546,14 +647,16 @@ typedef struct * @} */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ */ #define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ /** * @} @@ -613,12 +716,12 @@ typedef struct */ #define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ #define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ /** * @} */ -/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ #define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ @@ -793,7 +896,7 @@ typedef struct * @brief Set Hours format (24 hour/day or AM/PM hour format) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR FMT LL_RTC_SetHourFormat + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat * @param RTCx RTC Instance * @param HourFormat This parameter can be one of the following values: * @arg @ref LL_RTC_HOURFORMAT_24HOUR @@ -807,7 +910,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat /** * @brief Get Hours format (24 hour/day or AM/PM hour format) - * @rmtoll CR FMT LL_RTC_GetHourFormat + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_HOURFORMAT_24HOUR @@ -821,7 +924,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) /** * @brief Select the flag to be routed to RTC_ALARM output * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent * @param RTCx RTC Instance * @param AlarmOutput This parameter can be one of the following values: * @arg @ref LL_RTC_ALARMOUT_DISABLE @@ -837,7 +940,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu /** * @brief Get the flag to be routed to RTC_ALARM output - * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALARMOUT_DISABLE @@ -850,6 +953,63 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); +} + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note Used only when RTC_ALARM is mapped on PC13 @@ -891,7 +1051,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) { /* Set the Initialization mode */ - WRITE_REG(RTCx->ISR, RTC_INIT_MASK); + WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK); } /** @@ -905,11 +1065,12 @@ __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) /* Exit Initialization mode */ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR POL LL_RTC_SetOutputPolarity + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity * @param RTCx RTC Instance * @param Polarity This parameter can be one of the following values: * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH @@ -923,7 +1084,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari /** * @brief Get Output polarity - * @rmtoll CR POL LL_RTC_GetOutputPolarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH @@ -937,7 +1098,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) /** * @brief Enable Bypass the shadow registers * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass * @param RTCx RTC Instance * @retval None */ @@ -948,7 +1109,7 @@ __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) /** * @brief Disable Bypass the shadow registers - * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass * @param RTCx RTC Instance * @retval None */ @@ -959,7 +1120,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) /** * @brief Check if Shadow registers bypass is enabled or not. - * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -972,7 +1133,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_EnableRefClock + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock * @param RTCx RTC Instance * @retval None */ @@ -985,7 +1146,7 @@ __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_DisableRefClock + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock * @param RTCx RTC Instance * @retval None */ @@ -996,7 +1157,7 @@ __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) /** * @brief Set Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler * @param RTCx RTC Instance * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F * @retval None @@ -1008,7 +1169,7 @@ __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t Async /** * @brief Set Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler * @param RTCx RTC Instance * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF * @retval None @@ -1020,7 +1181,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP /** * @brief Get Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ @@ -1031,7 +1192,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) /** * @brief Get Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ @@ -1042,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) /** * @brief Enable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_EnableWriteProtection + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection * @param RTCx RTC Instance * @retval None */ @@ -1053,7 +1214,7 @@ __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) /** * @brief Disable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_DisableWriteProtection + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection * @param RTCx RTC Instance * @retval None */ @@ -1063,6 +1224,113 @@ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); } +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)); +} + +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 isn't available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)); +} + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** * @brief Enable RTC_OUT remap * @rmtoll OR OUT_RMP LL_RTC_EnableOutRemap @@ -1084,6 +1352,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP); } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} @@ -1097,7 +1366,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) * @brief Set time format (AM/24-hour or PM notation) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll TR PM LL_RTC_TIME_SetFormat + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1115,7 +1384,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @rmtoll TR PM LL_RTC_TIME_GetFormat + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1131,8 +1400,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format - * @rmtoll TR HT LL_RTC_TIME_SetHour\n - * TR HU LL_RTC_TIME_SetHour + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -1151,8 +1420,8 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to * Binary format - * @rmtoll TR HT LL_RTC_TIME_GetHour\n - * TR HU LL_RTC_TIME_GetHour + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ @@ -1166,8 +1435,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n - * TR MNU LL_RTC_TIME_SetMinute + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute * @param RTCx RTC Instance * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1186,8 +1455,8 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD * to Binary format - * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n - * TR MNU LL_RTC_TIME_GetMinute + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -1201,8 +1470,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll TR ST LL_RTC_TIME_SetSecond\n - * TR SU LL_RTC_TIME_SetSecond + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1221,8 +1490,8 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD * to Binary format - * @rmtoll TR ST LL_RTC_TIME_GetSecond\n - * TR SU LL_RTC_TIME_GetSecond + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -1236,13 +1505,13 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note TimeFormat and Hours should follow the same format - * @rmtoll TR PM LL_RTC_TIME_Config\n - * TR HT LL_RTC_TIME_Config\n - * TR HU LL_RTC_TIME_Config\n - * TR MNT LL_RTC_TIME_Config\n - * TR MNU LL_RTC_TIME_Config\n - * TR ST LL_RTC_TIME_Config\n - * TR SU LL_RTC_TIME_Config + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1271,19 +1540,19 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll TR HT LL_RTC_TIME_Get\n - * TR HU LL_RTC_TIME_Get\n - * TR MNT LL_RTC_TIME_Get\n - * TR MNU LL_RTC_TIME_Get\n - * TR ST LL_RTC_TIME_Get\n - * TR SU LL_RTC_TIME_Get + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { register uint32_t temp = 0U; - + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ @@ -1293,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) /** * @brief Memorize whether the daylight saving time change has been performed * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore * @param RTCx RTC Instance * @retval None */ @@ -1305,7 +1574,7 @@ __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) /** * @brief Disable memorization whether the daylight saving time change has been performed. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore * @param RTCx RTC Instance * @retval None */ @@ -1316,7 +1585,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) /** * @brief Check if RTC Day Light Saving stored operation has been enabled or not - * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -1328,7 +1597,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) /** * @brief Subtract 1 hour (winter time change) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR SUB1H LL_RTC_TIME_DecHour + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour * @param RTCx RTC Instance * @retval None */ @@ -1340,7 +1609,7 @@ __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) /** * @brief Add 1 hour (summer time change) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ADD1H LL_RTC_TIME_IncHour + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour * @param RTCx RTC Instance * @retval None */ @@ -1358,7 +1627,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending * (ie. SHFP=0) when PREDIV_S >= SS. - * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ @@ -1372,8 +1641,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note When REFCKON is set, firmware must not write to Shift control register. - * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n - * SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize * @param RTCx RTC Instance * @param ShiftSecond This parameter can be one of the following values: * @arg @ref LL_RTC_SHIFT_SECOND_DELAY @@ -1397,8 +1666,8 @@ __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSe /** * @brief Set Year in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format - * @rmtoll DR YT LL_RTC_DATE_SetYear\n - * DR YU LL_RTC_DATE_SetYear + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear * @param RTCx RTC Instance * @param Year Value between Min_Data=0x00 and Max_Data=0x99 * @retval None @@ -1414,8 +1683,8 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format - * @rmtoll DR YT LL_RTC_DATE_GetYear\n - * DR YU LL_RTC_DATE_GetYear + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ @@ -1426,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) /** * @brief Set Week day - * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1447,7 +1716,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @brief Get Week day * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit - * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1466,8 +1735,8 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set Month in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format - * @rmtoll DR MT LL_RTC_DATE_SetMonth\n - * DR MU LL_RTC_DATE_SetMonth + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth * @param RTCx RTC Instance * @param Month This parameter can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -1495,8 +1764,8 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll DR MT LL_RTC_DATE_GetMonth\n - * DR MU LL_RTC_DATE_GetMonth + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -1520,8 +1789,8 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) /** * @brief Set Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll DR DT LL_RTC_DATE_SetDay\n - * DR DU LL_RTC_DATE_SetDay + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -1537,8 +1806,8 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll DR DT LL_RTC_DATE_GetDay\n - * DR DU LL_RTC_DATE_GetDay + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ @@ -1549,13 +1818,13 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) /** * @brief Set date (WeekDay, Day, Month and Year) in BCD format - * @rmtoll DR WDU LL_RTC_DATE_Config\n - * DR MT LL_RTC_DATE_Config\n - * DR MU LL_RTC_DATE_Config\n - * DR DT LL_RTC_DATE_Config\n - * DR DU LL_RTC_DATE_Config\n - * DR YT LL_RTC_DATE_Config\n - * DR YU LL_RTC_DATE_Config + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1600,20 +1869,20 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll DR WDU LL_RTC_DATE_Get\n - * DR MT LL_RTC_DATE_Get\n - * DR MU LL_RTC_DATE_Get\n - * DR DT LL_RTC_DATE_Get\n - * DR DU LL_RTC_DATE_Get\n - * DR YT LL_RTC_DATE_Get\n - * DR YU LL_RTC_DATE_Get + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { register uint32_t temp = 0U; - + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ @@ -1632,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) /** * @brief Enable Alarm A * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Enable + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable * @param RTCx RTC Instance * @retval None */ @@ -1644,7 +1913,7 @@ __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Alarm A * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Disable + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable * @param RTCx RTC Instance * @retval None */ @@ -1655,10 +1924,10 @@ __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) /** * @brief Specify the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: * @arg @ref LL_RTC_ALMA_MASK_NONE @@ -1676,10 +1945,10 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Get the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask * @param RTCx RTC Instance * @retval Returned value can be can be a combination of the following values: * @arg @ref LL_RTC_ALMA_MASK_NONE @@ -1696,7 +1965,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) /** * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday * @param RTCx RTC Instance * @retval None */ @@ -1707,7 +1976,7 @@ __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) /** * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday * @param RTCx RTC Instance * @retval None */ @@ -1719,8 +1988,8 @@ __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n - * ALRMAR DU LL_RTC_ALMA_SetDay + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -1734,8 +2003,8 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get ALARM A Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n - * ALRMAR DU LL_RTC_ALMA_GetDay + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ @@ -1746,7 +2015,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1765,7 +2034,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1783,7 +2052,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set Alarm A time format (AM/24-hour or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1797,7 +2066,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF /** * @brief Get Alarm A time format (AM or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1811,8 +2080,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n - * ALRMAR HU LL_RTC_ALMA_SetHour + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -1826,8 +2095,8 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get ALARM A Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n - * ALRMAR HU LL_RTC_ALMA_GetHour + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ @@ -1839,8 +2108,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n - * ALRMAR MNU LL_RTC_ALMA_SetMinute + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute * @param RTCx RTC Instance * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1854,8 +2123,8 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get ALARM A Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n - * ALRMAR MNU LL_RTC_ALMA_GetMinute + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -1867,8 +2136,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n - * ALRMAR SU LL_RTC_ALMA_SetSecond + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1882,8 +2151,8 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get ALARM A Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n - * ALRMAR SU LL_RTC_ALMA_GetSecond + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -1894,13 +2163,13 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) /** * @brief Set Alarm A Time (hour, minute and second) in BCD format - * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n - * ALRMAR HT LL_RTC_ALMA_ConfigTime\n - * ALRMAR HU LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n - * ALRMAR ST LL_RTC_ALMA_ConfigTime\n - * ALRMAR SU LL_RTC_ALMA_ConfigTime + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1925,12 +2194,12 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @brief Get Alarm B Time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n - * ALRMAR HU LL_RTC_ALMA_GetTime\n - * ALRMAR MNT LL_RTC_ALMA_GetTime\n - * ALRMAR MNU LL_RTC_ALMA_GetTime\n - * ALRMAR ST LL_RTC_ALMA_GetTime\n - * ALRMAR SU LL_RTC_ALMA_GetTime + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -1943,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) * @brief Set Alarm A Mask the most-significant bits starting at this bit * @note This register can be written only when ALRAE is reset in RTC_CR register, * or in initialization mode. - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask * @param RTCx RTC Instance * @param Mask Value between Min_Data=0x00 and Max_Data=0xF * @retval None @@ -1955,7 +2224,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma /** * @brief Get Alarm A Mask the most-significant bits starting at this bit - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ @@ -1966,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) /** * @brief Set Alarm A Sub seconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF * @retval None @@ -1978,7 +2247,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec /** * @brief Get Alarm A Sub seconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ @@ -1998,7 +2267,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) /** * @brief Enable Alarm B * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Enable + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable * @param RTCx RTC Instance * @retval None */ @@ -2010,7 +2279,7 @@ __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Alarm B * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Disable + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable * @param RTCx RTC Instance * @retval None */ @@ -2021,10 +2290,10 @@ __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) /** * @brief Specify the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: * @arg @ref LL_RTC_ALMB_MASK_NONE @@ -2042,10 +2311,10 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Get the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask * @param RTCx RTC Instance * @retval Returned value can be can be a combination of the following values: * @arg @ref LL_RTC_ALMB_MASK_NONE @@ -2062,7 +2331,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) /** * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday * @param RTCx RTC Instance * @retval None */ @@ -2073,7 +2342,7 @@ __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) /** * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday * @param RTCx RTC Instance * @retval None */ @@ -2085,8 +2354,8 @@ __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n - * ALRMBR DU LL_RTC_ALMB_SetDay + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -2100,8 +2369,8 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get ALARM B Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n - * ALRMBR DU LL_RTC_ALMB_GetDay + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ @@ -2112,7 +2381,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2131,7 +2400,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2149,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set ALARM B time format (AM/24-hour or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2163,7 +2432,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF /** * @brief Get ALARM B time format (AM or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2177,8 +2446,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n - * ALRMBR HU LL_RTC_ALMB_SetHour + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -2192,8 +2461,8 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get ALARM B Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n - * ALRMBR HU LL_RTC_ALMB_GetHour + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ @@ -2205,8 +2474,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n - * ALRMBR MNU LL_RTC_ALMB_SetMinute + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute * @param RTCx RTC Instance * @param Minutes between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -2220,8 +2489,8 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get ALARM B Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n - * ALRMBR MNU LL_RTC_ALMB_GetMinute + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2233,8 +2502,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n - * ALRMBR SU LL_RTC_ALMB_SetSecond + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -2248,8 +2517,8 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get ALARM B Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n - * ALRMBR SU LL_RTC_ALMB_GetSecond + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2260,13 +2529,13 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) /** * @brief Set Alarm B Time (hour, minute and second) in BCD format - * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n - * ALRMBR HT LL_RTC_ALMB_ConfigTime\n - * ALRMBR HU LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n - * ALRMBR ST LL_RTC_ALMB_ConfigTime\n - * ALRMBR SU LL_RTC_ALMB_ConfigTime + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2291,12 +2560,12 @@ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @brief Get Alarm B Time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n - * ALRMBR HU LL_RTC_ALMB_GetTime\n - * ALRMBR MNT LL_RTC_ALMB_GetTime\n - * ALRMBR MNU LL_RTC_ALMB_GetTime\n - * ALRMBR ST LL_RTC_ALMB_GetTime\n - * ALRMBR SU LL_RTC_ALMB_GetTime + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -2309,7 +2578,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) * @brief Set Alarm B Mask the most-significant bits starting at this bit * @note This register can be written only when ALRBE is reset in RTC_CR register, * or in initialization mode. - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask * @param RTCx RTC Instance * @param Mask Value between Min_Data=0x00 and Max_Data=0xF * @retval None @@ -2321,7 +2590,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma /** * @brief Get Alarm B Mask the most-significant bits starting at this bit - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ @@ -2332,7 +2601,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) /** * @brief Set Alarm B Sub seconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF * @retval None @@ -2344,7 +2613,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec /** * @brief Get Alarm B Sub seconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ @@ -2364,7 +2633,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) /** * @brief Enable internal event timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_EnableInternalEvent + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent * @param RTCx RTC Instance * @retval None */ @@ -2376,7 +2645,7 @@ __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) /** * @brief Disable internal event timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_DisableInternalEvent + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent * @param RTCx RTC Instance * @retval None */ @@ -2388,7 +2657,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) /** * @brief Enable Timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Enable + * @rmtoll RTC_CR ITSE LL_RTC_TS_Enable * @param RTCx RTC Instance * @retval None */ @@ -2400,7 +2669,7 @@ __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Disable + * @rmtoll RTC_CR ITSE LL_RTC_TS_Disable * @param RTCx RTC Instance * @retval None */ @@ -2413,7 +2682,7 @@ __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) * @brief Set Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting - * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge + * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge * @param RTCx RTC Instance * @param Edge This parameter can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2428,7 +2697,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) /** * @brief Get Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge + * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2441,7 +2710,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) /** * @brief Get Timestamp AM/PM notation (AM or 24-hour format) - * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TS_TIME_FORMAT_AM @@ -2455,8 +2724,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll TSTR HT LL_RTC_TS_GetHour\n - * TSTR HU LL_RTC_TS_GetHour + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ @@ -2468,8 +2737,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n - * TSTR MNU LL_RTC_TS_GetMinute + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR HU LL_RTC_TS_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2481,8 +2750,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n - * TSTR SU LL_RTC_TS_GetSecond + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR HU LL_RTC_TS_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2495,12 +2764,12 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @brief Get Timestamp time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll TSTR HT LL_RTC_TS_GetTime\n - * TSTR HU LL_RTC_TS_GetTime\n - * TSTR MNT LL_RTC_TS_GetTime\n - * TSTR MNU LL_RTC_TS_GetTime\n - * TSTR ST LL_RTC_TS_GetTime\n - * TSTR SU LL_RTC_TS_GetTime + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -2512,7 +2781,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Week day - * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2531,8 +2800,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Month in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n - * TSDR MU LL_RTC_TS_GetMonth + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -2556,8 +2825,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll TSDR DT LL_RTC_TS_GetDay\n - * TSDR DU LL_RTC_TS_GetDay + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ @@ -2570,11 +2839,11 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n - * TSDR MT LL_RTC_TS_GetDate\n - * TSDR MU LL_RTC_TS_GetDate\n - * TSDR DT LL_RTC_TS_GetDate\n - * TSDR DU LL_RTC_TS_GetDate + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ @@ -2585,7 +2854,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) /** * @brief Get time-stamp sub second value - * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond + * @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ @@ -2594,104 +2863,1328 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } -#if defined(RTC_TAMPCR_TAMPTS) /** - * @brief Activate timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper + * @} + */ + +#if defined(RTC_WAKEUP_SUPPORT) +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) { - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); + SET_BIT(RTCx->CR, RTC_CR_WUTE); } /** - * @brief Disable timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) { - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); } -#endif /* RTC_TAMPCR_TAMPTS */ /** - * @} - */ - -/** @defgroup RTC_LL_EF_Tamper Tamper - * @{ + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); +} /** - * @brief Enable RTC_TAMPx input detection - * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable\n - * TAMPCR TAMP2E LL_RTC_TAMPER_Enable\n - * TAMPCR TAMP3E LL_RTC_TAMPER_Enable + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) { - SET_BIT(RTCx->TAMPCR, Tamper); + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); } /** - * @brief Clear RTC_TAMPx input detection - * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable\n - * TAMPCR TAMP2E LL_RTC_TAMPER_Disable\n - * TAMPCR TAMP3E LL_RTC_TAMPER_Disable + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * - * @retval None + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) { - CLEAR_BIT(RTCx->TAMPCR, Tamper); + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } /** - * @brief Enable Tamper mask flag - * @note Associated Tamper IT must not enabled when tamper mask is set. - * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask\n - * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask\n - * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload * @param RTCx RTC Instance - * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) { - SET_BIT(RTCx->TAMPCR, Mask); + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); } /** - * @brief Disable Tamper mask flag - * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask\n + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set Wakeup auto-clear value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll RTC_WUTR WUTOCLR LL_RTC_WAKEUP_SetAutoClr + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoClr(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUTOCLR, (Value << RTC_WUTR_WUTOCLR_Pos)); +} + +/** + * @brief Get Wakeup auto-clear value + * @rmtoll RTC_WUTR WUTOCLR LL_RTC_WAKEUP_GetAutoClr + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoClr(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->WUTR, RTC_WUTR_WUTOCLR)) >> RTC_WUTR_WUTOCLR_Pos); +} +#endif /* defined(STM32L412xx) || defined(STM32L422xx) */ + +/** + * @} + */ +#endif /* RTC_WAKEUP_SUPPORT */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check if Calibration Low Power is enabled or not + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)); +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_EnableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + SET_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_DisableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + CLEAR_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param TAMPx TAMP Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param TAMPx TAMP Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param TAMPx TAMP Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)); +} + +/** + * @brief Get Alarm B write flag + * @rmtoll RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)); +} + +/** + * @brief Get Alarm A write flag + * @rmtoll RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)); +} + + + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)); +} + +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#if defined(RTC_TAMPCR_TAMPTS) +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} +#endif /* RTC_TAMPCR_TAMPTS */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable\n + * TAMPCR TAMP2E LL_RTC_TAMPER_Enable\n + * TAMPCR TAMP3E LL_RTC_TAMPER_Enable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Clear RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable\n + * TAMPCR TAMP2E LL_RTC_TAMPER_Disable\n + * TAMPCR TAMP3E LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask\n + * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + SET_BIT(RTCx->TAMPCR, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask\n * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask\n * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) @@ -2706,10 +4199,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2724,10 +4217,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2873,10 +4366,10 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2891,10 +4384,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2906,112 +4399,6 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * @} */ -#if defined(RTC_WAKEUP_SUPPORT) -/** @defgroup RTC_LL_EF_Wakeup Wakeup - * @{ - */ - -/** - * @brief Enable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Disable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Check if Wakeup timer is enabled or not - * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); -} - -/** - * @brief Select Wakeup clock - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock - * @param RTCx RTC Instance - * @param WakeupClock This parameter can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) -{ - MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); -} - -/** - * @brief Get Wakeup clock - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); -} - -/** - * @brief Set Wakeup auto-reload value - * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR - * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload - * @param RTCx RTC Instance - * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) -{ - MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); -} - -/** - * @brief Get Wakeup auto-reload value - * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); -} - -/** - * @} - */ -#endif /* RTC_WAKEUP_SUPPORT */ - #if defined(RTC_BACKUP_SUPPORT) /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers * @{ @@ -3123,138 +4510,13 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back */ #endif /* RTC_BACKUP_SUPPORT */ -/** @defgroup RTC_LL_EF_Calibration Calibration - * @{ - */ - -/** - * @brief Set Calibration output frequency (1 Hz or 512 Hz) - * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n - * CR COSEL LL_RTC_CAL_SetOutputFreq - * @param RTCx RTC Instance - * @param Frequency This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) -{ - MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); -} - -/** - * @brief Get Calibration output frequency (1 Hz or 512 Hz) - * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n - * CR COSEL LL_RTC_CAL_GetOutputFreq - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); -} - -/** - * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALP LL_RTC_CAL_SetPulse - * @param RTCx RTC Instance - * @param Pulse This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE - * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); -} - -/** - * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) - * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); -} - -/** - * @brief Set the calibration cycle period - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n - * CALR CALW16 LL_RTC_CAL_SetPeriod - * @param RTCx RTC Instance - * @param Period This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); -} - -/** - * @brief Get the calibration cycle period - * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n - * CALR CALW16 LL_RTC_CAL_GetPeriod - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); -} - -/** - * @brief Set Calibration minus - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALM LL_RTC_CAL_SetMinus - * @param RTCx RTC Instance - * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); -} - -/** - * @brief Get Calibration minus - * @rmtoll CALR CALM LL_RTC_CAL_GetMinus - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); -} - -/** - * @} - */ - /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Get Internal Time-stamp flag - * @rmtoll ISR ITSF LL_RTC_IsActiveFlag_ITS + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -3578,7 +4840,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) /** * @brief Enable Time-stamp interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_EnableIT_TS + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS * @param RTCx RTC Instance * @retval None */ @@ -3590,7 +4852,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) /** * @brief Disable Time-stamp interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_DisableIT_TS + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS * @param RTCx RTC Instance * @retval None */ @@ -3603,7 +4865,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) /** * @brief Enable Wakeup timer interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT * @param RTCx RTC Instance * @retval None */ @@ -3615,7 +4877,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) /** * @brief Disable Wakeup timer interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT * @param RTCx RTC Instance * @retval None */ @@ -3628,7 +4890,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) /** * @brief Enable Alarm B interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB * @param RTCx RTC Instance * @retval None */ @@ -3640,7 +4902,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) /** * @brief Disable Alarm B interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB * @param RTCx RTC Instance * @retval None */ @@ -3652,7 +4914,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) /** * @brief Enable Alarm A interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA * @param RTCx RTC Instance * @retval None */ @@ -3664,7 +4926,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) /** * @brief Disable Alarm A interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA * @param RTCx RTC Instance * @retval None */ @@ -3872,6 +5134,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) * @} */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -3915,6 +5179,6 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); } #endif -#endif /* __STM32L4xx_LL_RTC_H */ +#endif /* STM32L4xx_LL_RTC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h index a7cf4d52bd..a169b42ad4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SPI_H -#define __STM32L4xx_LL_SPI_H +#ifndef STM32L4xx_LL_SPI_H +#define STM32L4xx_LL_SPI_H #ifdef __cplusplus extern "C" { @@ -1048,11 +1048,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) { - __IO uint32_t tmpreg; - tmpreg = SPIx->SR; - (void) tmpreg; - tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); - (void) tmpreg; + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); } /** @@ -1394,7 +1393,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); *spidr = TxData; #else - *((__IO uint16_t *)&SPIx->DR) = TxData; + SPIx->DR = TxData; #endif } @@ -1432,6 +1431,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); } #endif -#endif /* __STM32L4xx_LL_SPI_H */ +#endif /* STM32L4xx_LL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h index 6bef2dfa2c..48e0aea0c9 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SWPMI_H -#define __STM32L4xx_LL_SWPMI_H +#ifndef STM32L4xx_LL_SWPMI_H +#define STM32L4xx_LL_SWPMI_H #ifdef __cplusplus extern "C" { @@ -84,7 +84,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=63. + This parameter must be a number between Min_Data=0 and Max_Data=63U. The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER @@ -366,7 +366,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } /** @@ -397,7 +397,7 @@ __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx) * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler * @param SWPMIx SWPMI Instance - * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63 + * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63U * @retval None */ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler) @@ -409,7 +409,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @brief Get Bitrate prescaler * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler * @param SWPMIx SWPMI Instance - * @retval A number between Min_Data=0 and Max_Data=63 + * @retval A number between Min_Data=0 and Max_Data=63U */ __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) { @@ -459,7 +459,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } /** @@ -470,7 +470,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } /** @@ -481,7 +481,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } /** @@ -492,7 +492,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } /** @@ -503,7 +503,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } /** @@ -515,7 +515,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } /** @@ -527,7 +527,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } /** @@ -539,7 +539,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } /** @@ -551,7 +551,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } /** @@ -562,7 +562,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } /** @@ -573,7 +573,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } /** @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } /** @@ -878,7 +878,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } /** @@ -889,7 +889,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } /** @@ -900,7 +900,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } /** @@ -911,7 +911,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } /** @@ -922,7 +922,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } /** @@ -933,7 +933,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } /** @@ -944,7 +944,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } /** @@ -955,7 +955,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } /** @@ -996,7 +996,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } /** @@ -1029,7 +1029,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } /** @@ -1044,7 +1044,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) { - register uint32_t data_reg_addr = 0; + uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { @@ -1164,6 +1164,6 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); } #endif -#endif /* __STM32L4xx_LL_SWPMI_H */ +#endif /* STM32L4xx_LL_SWPMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h index fb235a3fd6..cc812f4c9f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h @@ -47,8 +47,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SYSTEM_H -#define __STM32L4xx_LL_SYSTEM_H +#ifndef STM32L4xx_LL_SYSTEM_H +#define STM32L4xx_LL_SYSTEM_H #ifdef __cplusplus extern "C" { @@ -1639,6 +1639,6 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) } #endif -#endif /* __STM32L4xx_LL_SYSTEM_H */ +#endif /* STM32L4xx_LL_SYSTEM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h index 45a01baeb5..bce81c4dcf 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h @@ -1171,7 +1171,7 @@ typedef struct #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ @@ -1187,8 +1187,11 @@ typedef struct */ #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ +#if defined (STM32L412xx) || defined (STM32L422xx) +#else #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ +#endif /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h index e1232c9e21..825a4a0efe 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h @@ -34,8 +34,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_USART_H -#define __STM32L4xx_LL_USART_H +#ifndef STM32L4xx_LL_USART_H +#define STM32L4xx_LL_USART_H #ifdef __cplusplus extern "C" { @@ -719,7 +719,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -759,7 +759,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } /** @@ -865,7 +865,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); } #endif @@ -908,7 +908,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } #if defined(USART_CR3_UCESM) @@ -1148,7 +1148,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } /** @@ -1389,7 +1389,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } /** @@ -1634,7 +1634,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } /** @@ -1702,7 +1702,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } /** @@ -1881,7 +1881,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } /** @@ -1914,7 +1914,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } /** @@ -1989,8 +1989,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph uint32_t BaudRate) #endif { - register uint32_t usartdiv = 0x0U; - register uint32_t brrtemp = 0x0U; + register uint32_t usartdiv; + register uint32_t brrtemp; if (OverSampling == LL_USART_OVERSAMPLING_8) { @@ -2047,7 +2047,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) #endif { - register uint32_t usartdiv = 0x0U; + register uint32_t usartdiv; register uint32_t brrresult = 0x0U; #if defined(USART_PRESC_PRESCALER) register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); @@ -2055,11 +2055,15 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe usartdiv = USARTx->BRR; - if (OverSampling == LL_USART_OVERSAMPLING_8) + if(usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) { - if ((usartdiv & 0xFFF7U) != 0U) + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if(usartdiv != 0U) { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; #if defined(USART_PRESC_PRESCALER) brrresult = (periphclkpresc * 2U) / usartdiv; #else @@ -2171,7 +2175,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } /** @@ -2278,7 +2282,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } /** @@ -2317,7 +2321,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } /** @@ -2454,7 +2458,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } /** @@ -2501,7 +2505,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } /** @@ -2543,7 +2547,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)); + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } /** @@ -2622,7 +2626,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } /** @@ -2723,7 +2727,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } /** @@ -3050,7 +3054,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } /** @@ -3061,18 +3065,18 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } /** * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll ISR NF LL_USART_IsActiveFlag_NE + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE * @param USARTx USART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } /** @@ -3083,7 +3087,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } /** @@ -3094,7 +3098,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -3111,7 +3115,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } #else @@ -3123,7 +3127,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); } #endif @@ -3135,7 +3139,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -3152,7 +3156,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } #else @@ -3164,7 +3168,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); } #endif @@ -3178,7 +3182,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } /** @@ -3191,7 +3195,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } /** @@ -3204,7 +3208,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } /** @@ -3215,7 +3219,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } /** @@ -3228,7 +3232,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } #if defined(USART_CR2_SLVEN) @@ -3242,7 +3246,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } #endif @@ -3256,7 +3260,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } /** @@ -3269,7 +3273,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } /** @@ -3280,7 +3284,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } /** @@ -3291,7 +3295,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } /** @@ -3302,7 +3306,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } /** @@ -3313,7 +3317,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } /** @@ -3326,7 +3330,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } /** @@ -3337,7 +3341,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } /** @@ -3348,7 +3352,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -3362,7 +3366,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } /** @@ -3375,7 +3379,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } #endif @@ -3389,7 +3393,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } #endif @@ -3404,7 +3408,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } /** @@ -3417,7 +3421,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } #endif @@ -4131,7 +4135,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -4148,7 +4152,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } #else @@ -4160,7 +4164,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); } #endif @@ -4172,7 +4176,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -4189,7 +4193,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } #else @@ -4201,7 +4205,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); } #endif @@ -4213,7 +4217,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } /** @@ -4224,7 +4228,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } /** @@ -4235,7 +4239,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } /** @@ -4248,7 +4252,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -4262,7 +4266,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } /** @@ -4275,7 +4279,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } #endif @@ -4289,7 +4293,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } /** @@ -4300,7 +4304,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } /** @@ -4313,7 +4317,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } /** @@ -4326,7 +4330,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -4340,7 +4344,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } #endif @@ -4356,7 +4360,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } #endif @@ -4371,7 +4375,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } #endif @@ -4413,7 +4417,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } /** @@ -4446,7 +4450,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } /** @@ -4479,7 +4483,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } /** @@ -4494,7 +4498,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { @@ -4561,7 +4565,7 @@ __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value */ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) { - USARTx->TDR = Value & 0x1FFU; + USARTx->TDR = Value & 0x1FFUL; } /** @@ -4679,6 +4683,6 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS } #endif -#endif /* __STM32L4xx_LL_USART_H */ +#endif /* STM32L4xx_LL_USART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html index 9bb389971b..d1d3705160 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html @@ -1,670 +1,206 @@ -Release Notes for STM32L4xx HAL Drivers + + + + +Release Notes for STM32L4xx HAL Drivers + + -
          -

           

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          Back to Release page

          -
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          Release -Notes for STM32L4xx HAL Drivers

          -

          Copyright -2017 STMicroelectronics

          -

          -
          -

           

          - - - - - - -
          -

          Update History

          + +
          Back to Release page + +
          +

          License

          +This software component is licensed by ST under BSD 3-Clause +license, the "License"; You may not use this component except in +compliance with +the License. You may obtain a copy of the License at: +

          https://opensource.org/licenses/BSD-3-Clause

          +
          +
          +
          +
          +

          V1.9.0 / 27-July-2018

          +
          +
          +

          Main +Changes +

          • Release of HAL and Low Layer drivers to add support of STM32L412xx/STM32L422xx
          • Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm)  
          • MISRA C:2012 corrections

          HAL Drivers changes 

          + +
          • MISRA C:2012 corrections listed hereafter are applicable to LL driver as well
          • HAL ADC driver 
            • Replace private macro using concurrent volatile access (generating MIRSA errors) by temporary variables or LL helper macro
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.13, 10.1_R2, 10.1_R3, 10.1_R6, 10.4_a, 10.4_b, 10.5, 14.4_c, 12.2, 15.7
            • stm32l4xx_hal_adc.c and stm32l4xx_hal_adc_ex.c
              • Change of time-out duration computation when expressed in microseconds to manage low system clock frequencies
            • stm32l4xx_hal_adc.c
              • Remove useless stabilization delay in ADC_Enable() when enabling ADC
              • In HAL_ADC_Stop_DMA(), HAL_DMA_Abort() API is called only if DMA is busy 
            • stm32l4xx_hal_adc.h
              • Typo correction in ADC_AnalogWDGConfTypeDef FilteringConfig field description
            • stm32l4xx_hal_adc.c, stm32l4xx_hal_adc.h
              • Clarify comments in HAL_ADC_AnalogWDGConfig for analog watchdog thresholds checks when oversampling is enabled
          • HAL CAN driver 
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.3, 10.4_a, 10.6, 12.2, 13.3, 13.5, 15.7, 17.7, 18.1_b
            • stm32l4xx_hal_can.c, stm32l4xx_hal_can.h
              • Tx abort procedure correction
            • stm32l4xx_hal_can.c
              • Correct implementation of test on pending message in HAL_CAN_IsTxMessagePending() 
              • Update HAL_CAN_Stop() to reset any previous sleep mode request to avoid maintaining the sleep mode request active at next
                HAL_CAN_Start()
          • HAL COMP driver 
            • Correct MISRA C:2012 warnings reported by rules 10.1, 10.3, 10.4, 13.5
            • stm32l4xx_hal_comp.c
              • Change of time-out duration computation when expressed in microseconds to manage low system clock frequencies
          • HAL CRC driver 
            • Correct MISRA C:2012 warnings reported by rules 10.3, 12.1, 12.2
          • HAL CRYP driver 
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.13, 10.3, 10.4, 10.6, 10.7, 10.8, 12.1, 13.5, 15.7, 17.7, 18.4
            • stm32l4xx_hal_cryp_ex.c: CodeSonar warnings correction
          • HAL DAC driver 
            • Correct MISRA C:2012 warnings
          • HAL DCMI driver 
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 8.4, 10.4_a, 12.1, 17.7, 18.4
          • HAL DMA driver 
            • Correct MISRA C:2012 warnings
          • HAL DSI driver 
            • stm32l4xx_hal_dsi.h: add __HAL_DSI_RESET_HANDLE_STATE() macro
          • HAL EXTI driver (NEW)
            • New +stm32l4xx_hal_exti.h and stm32l4xx_hal_exti.c files  (driver +enabled with HAL_EXTI_MODULE_ENABLED in stm32l4xx_hal_conf.h file)
          • HAL FIREWALL driver 
            • Correct MISRA C:2012 warnings reported by rules 10.4
          • HAL GPIO driver 
            • Correct MISRA C:2012 warnings reported by rules 10.3, 21.1
          • HAL HASH driver 
            • Correct MISRA C:2012 warnings reported by rules 1.3_k, 2.2_c, 9.1_f, 10.3, 12.1, 13.4_b, 13.5, 15.7, 17.7, 21.1
            • stm32l4xx_hal_hash.c: 
              • in HASH_Start_DMA(), test on HASH_CR_MDMAT bit before checking input buffer length in case of multi-buffer processing
              • Fill-up empty statement in HAL_HASH_DMAFeed_ProcessSuspend() to correct CodeSonar warning
          • HAL I2C driver 
            • Correct MISRA C:2012 warnings
            • stm32l4xx_hal_i2c.c: remove extra definition of I2C_GET_DMA_REMAIN_DATA() macro
          • HAL IRDA driver 
            • Correct MISRA C:2012 +warnings reported by rules 2.1, 2.2_c, 2.4, 2.3, 8.9_a, 10.3, 10.4_a, +10.5, 10.6, 10.7, 11.3, 13.3, 13.5, 15.7, 17.7, 17.8, 18.4, 21.1
          • HAL IWDG driver 
            • Correct MISRA C:2012 warnings reported by rules 2.7, 10.3, 10.4_a
          • HAL LPTIM driver
            • Add repetition counter management for STM32L412xx/L422xx devices
              • New field RepetitionCounter added in LPTIM_InitTypeDef structure
          • HAL OSPI driver 
            • stm32l4xx_hal_ospi.h: update memory type definition to support new octal PSRAM from APMemory
          • HAL OPAMP driver 
            • Correct MISRA C:2012 warnings
          • HAL PWR driver 
            • Update conversion mechanism from duration in us in number of cycles to manage low system frequencies
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.3, 10.4_a, 13.5, 16.3, 17.7
          • HAL RCC driver 
            • stm32l4xx_hal_rcc.c, stm32l4xx_hal_rcc.h: compilation switches update to ensure full STM32L412xx/L422xx devices support
            • Correct MISRA C:2012 +warnings reported by rules 2.2_c, 8.13, 8.9_a, 10.1_R2, 10.4_a, 10.3, 10.7, 11.9, 12.1, 12.2, 13.5, 14.4_c, 15.7, 21.2
          • HAL RTC driver 
            • New HAL_RTCEx_SetLowPowerCalib() +API for STM32L412xx/L422xx devices
            • HAL_RTC_AlarmIRQHandler() API +optimization +
          • HAL SAI driver 
            • stm32l4xx_hal_sai.c: remove empty if statements to fix CodeSonar wanring
            • stm32l4xx_hal_sai.h, stm32l4xx_hal_sai.c: add check on master clock divider parameter, remove SAI_FIFO_SIZE definition
          • HAL SMARTCARD driver 
            • Correct MISRA C:2012 +warnings reported by rules 2.2_c, 8.9_a, 10.3, 10.4_a, 10.5, 10.6, +10.7, 12.1, 12.2, 13.3, 13.5, 15.7, 17.7, 17.8, 18.1, 21.1
          • HAL SPI driver 
            • Correct MISRA C:2012 warnings
          • HAL SWPMI driver 
            • Correct MISRA C:2012 warnings reported by rules 2.2_c, 2.7, 10.3, 10.4_a, 13.3, 13.5, 15.7, 17.7, 17.8, 21.1
          • HAL TSC driver 
            • Correct MISRA C:2012 warnings reported by rule 21.1
          • HAL USART driver 
            • Correct MISRA C:2012 warnings reported by rule 10.4_a, 10.6, 12.2

          LL Drivers changes

          +
          • LL ADC driver
            • stm32l4xx_ll_dmamux.h: clarify comments when oversampling is enabled
          • LL DMA driver 
            • stm32l4xx_ll_dmamux.h: remove test on DMAMUX1
          • LL RCC driver
            • stm32l4xx_ll_rcc.c, stm32l4xx_ll_rcc.h: compilation switches update to ensure full STM32L412xx/L422xx devices support
          • LL RTC driver
            • stm32l4xx_ll_rtc.h: add new macros LL_RTC_WAKEUP_SetAutoClr(), LL_RTC_WAKEUP_GetAutoClr() applicable to STM32L412xx/L422xx devices only
          +
          +
          +

          +
          +
          -

          -
          +
          • First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/ STM32L476xx/ STM32L485xx and STM32L486xx devices.

           +
          +
          +
          +

          For complete +documentation on STM32 Microcontrollers, +visit: www.st.com/STM32

          +
          -

           

          \ No newline at end of file diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index 27702e3ee8..e045a89782 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -67,17 +67,17 @@ /** * @brief STM32L4xx HAL Driver version number */ -#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L4xx_HAL_VERSION_RC)) +#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define STM32L4XX_HAL_VERSION_SUB1 (0x09U) /*!< [23:16] sub1 version */ +#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ + |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ + |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\ + |(STM32L4XX_HAL_VERSION_RC)) #if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */ +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */ #endif /* VREFBUF */ /* ------------ SYSCFG registers bit address in the alias region ------------ */ @@ -85,20 +85,29 @@ /* --- MEMRMP Register ---*/ /* Alias word address of FB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET -#define FB_MODE_BitNumber ((uint8_t)0x8) -#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) +#define FB_MODE_BitNumber 8U +#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U)) /* --- SCSR Register ---*/ /* Alias word address of SRAM2ER bit */ -#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) -#define BRER_BitNumber ((uint8_t)0x0) -#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4)) +#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U) +#define BRER_BitNumber 0U +#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ __IO uint32_t uwTick; +/** + * @} + */ -/* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions @@ -139,23 +148,25 @@ __IO uint32_t uwTick; /** * @brief Configure the Flash prefetch, the Instruction and Data caches, - * the time base source, NVIC and any required global low level hardware - * by calling the HAL_MspInit() callback function to be optionally defined in user file + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file * stm32l4xx_hal_msp.c. * - * @note HAL_Init() function is called at the beginning of program after reset and before + * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. - * + * * @note In the default implementation the System Timer (Systick) is used as source of time base. * The Systick configuration is based on MSI clock, as MSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented + * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { + HAL_StatusTypeDef status = HAL_OK; + /* Configure Flash prefetch, Instruction cache, Data cache */ /* Default configuration at reset is: */ /* - Prefetch disabled */ @@ -177,13 +188,18 @@ HAL_StatusTypeDef HAL_Init(void) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -256,14 +272,21 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); + HAL_StatusTypeDef status = HAL_OK; - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock/1000UL) != 0U) + { + status = HAL_ERROR; + } + else + { + /*Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -316,8 +339,8 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. @@ -335,7 +358,7 @@ __weak void HAL_Delay(uint32_t Delay) if (wait < HAL_MAX_DELAY) { wait++; - } + } while((HAL_GetTick() - tickstart) < wait) { @@ -380,7 +403,7 @@ __weak void HAL_ResumeTick(void) */ uint32_t HAL_GetHalVersion(void) { - return __STM32L4xx_HAL_VERSION; + return STM32L4XX_HAL_VERSION; } /** @@ -389,7 +412,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); + return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); } /** @@ -398,7 +421,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); + return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } /** @@ -407,7 +430,7 @@ uint32_t HAL_GetDEVID(void) */ uint32_t HAL_GetUIDw0(void) { - return(READ_REG(*((uint32_t *)UID_BASE))); + return(READ_REG(*((uint32_t *)UID_BASE))); } /** @@ -416,7 +439,7 @@ uint32_t HAL_GetUIDw0(void) */ uint32_t HAL_GetUIDw1(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** @@ -425,7 +448,7 @@ uint32_t HAL_GetUIDw1(void) */ uint32_t HAL_GetUIDw2(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** @@ -536,7 +559,7 @@ void HAL_SYSCFG_SRAM2Erase(void) SYSCFG->SKR = 0xCA; SYSCFG->SKR = 0x53; /* Starts a hardware SRAM2 erase operation*/ - *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001; + *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL; } /** @@ -551,7 +574,7 @@ void HAL_SYSCFG_SRAM2Erase(void) */ void HAL_SYSCFG_EnableMemorySwappingBank(void) { - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE; + *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL; } /** @@ -567,7 +590,7 @@ void HAL_SYSCFG_EnableMemorySwappingBank(void) void HAL_SYSCFG_DisableMemorySwappingBank(void) { - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE; + *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL; } #if defined(VREFBUF) @@ -575,9 +598,9 @@ void HAL_SYSCFG_DisableMemorySwappingBank(void) * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling specifies the output voltage to achieve * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @retval None */ @@ -585,7 +608,7 @@ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); } @@ -601,7 +624,7 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); } @@ -613,7 +636,7 @@ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); } @@ -623,22 +646,22 @@ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) */ HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) { - uint32_t tickstart = 0; - + uint32_t tickstart; + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET) + while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) { if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } - + return HAL_OK; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c index a7543d8b73..03d9628cf5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c @@ -336,18 +336,18 @@ * @{ */ -#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES | ADC_CFGR_ALIGN |\ - ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ - ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated - when no regular conversion is on-going */ +#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ + ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ + ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated + when no regular conversion is on-going */ /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ -#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ -#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ +#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ +#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ @@ -357,7 +357,7 @@ /* - ADC oversampling ratio 256 */ /* Calculation: 653 * 4096 * 256 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 653U * 4096U * 256U) /*!< ADC conversion completion time-out value */ +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ /** @@ -418,8 +418,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR = 0U; + uint32_t tmpCFGR; + uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if(hadc == NULL) @@ -431,7 +434,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) assert_param(IS_ADC_DFSDMCFG_MODE(hadc)); +#endif assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); @@ -493,7 +498,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U) + if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); @@ -503,17 +508,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) re-applied once the ADC voltage regulator is enabled */ } - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } @@ -522,7 +526,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -537,8 +541,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ - if( (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if( ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) ) { /* Set ADC state */ @@ -551,27 +557,29 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) - { - /* Reset configuration of ADC common register CCR: */ - /* */ - /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ - /* according to adc->Init.ClockPrescaler. It selects the clock */ - /* source and sets the clock division factor. */ - /* */ - /* Some parameters of this register are not reset, since they are set */ - /* by other functions and must be kept in case of usage of this */ - /* function on the fly (update of a parameter of ADC_InitTypeDef */ - /* without needing to reconfigure all other ADC groups/channels */ - /* parameters): */ - /* - when multimode feature is available, multimode-related */ - /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ - /* HAL_ADCEx_MultiModeConfigChannel() ) */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ - /* (set into HAL_ADC_ConfigChannel() or */ - /* HAL_ADCEx_InjectedConfigChannel() ) */ - LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + /* Reset configuration of ADC common register CCR: */ + /* */ + /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ + /* according to adc->Init.ClockPrescaler. It selects the clock */ + /* source and sets the clock division factor. */ + /* */ + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - when multimode feature is available, multimode-related */ + /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ + /* HAL_ADCEx_MultiModeConfigChannel() ) */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() or */ + /* HAL_ADCEx_InjectedConfigChannel() ) */ + LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); + } } /* Configuration of ADC: */ @@ -583,11 +591,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ - tmpCFGR = (ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) | - hadc->Init.Overrun | - hadc->Init.DataAlign | - hadc->Init.Resolution | - ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) ); + tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + hadc->Init.Overrun | + hadc->Init.DataAlign | + hadc->Init.Resolution | + ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) ); if (hadc->Init.DiscontinuousConvMode == ENABLE) { @@ -615,13 +623,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { - tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | - ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); + tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); if (hadc->Init.OversamplingMode == ENABLE) { @@ -653,7 +665,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ + } /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ @@ -710,6 +722,8 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { + HAL_StatusTypeDef tmp_hal_status; + /* Check ADC handle */ if(hadc == NULL) { @@ -722,11 +736,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - /* Stop potential conversion on going, on regular and injected groups */ - /* Note: No check on ADC_ConversionStop() return status, */ - /* if the conversion stop failed, it is up to */ - /* HAL_ADC_MspDeInit() to reset the ADC IP. */ - ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + /* Stop potential conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ @@ -736,11 +747,25 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); - /* Disable the ADC peripheral */ - /* No check on ADC_Disable() return status, if the ADC disabling process - failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */ - ADC_Disable(hadc); + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ /* ========== Reset ADC registers ========== */ /* Reset register IER */ @@ -839,8 +864,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE, PRESCEN @@ -890,7 +914,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -961,7 +985,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call return HAL_ERROR; } - if ((hadc->State & HAL_ADC_STATE_READY) != 0) + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { @@ -1077,7 +1101,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca { HAL_StatusTypeDef status = HAL_OK; - if ((hadc->State & HAL_ADC_STATE_READY) != 0) + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { @@ -1206,14 +1230,17 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_TypeDef *tmpADC_Master; + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); @@ -1231,14 +1258,18 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - +#endif + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) @@ -1269,12 +1300,15 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Multimode feature is not available or ADC Instance is Independent or Master, - or is not Slave ADC with dual regular conversions enabled. - Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } @@ -1284,16 +1318,26 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) } else { + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } +#else + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif } else { @@ -1321,7 +1365,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1375,10 +1419,13 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0U; - uint32_t tmp_Flag_End = 0U; - uint32_t tmp_cfgr = 0U; - ADC_TypeDef *tmpADC_Master; + uint32_t tickstart; + uint32_t tmp_Flag_End; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1397,10 +1444,14 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ - if(ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Check ADC DMA mode in independant mode */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) + /* Check ADC DMA mode in independent mode on ADC group regular */ + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; @@ -1412,8 +1463,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti } else { - /* Check ADC DMA mode in multimode */ - if(ADC_MULTIMODE_DMA_ENABLED(hadc)) + /* Check ADC DMA mode in multimode on ADC group regular */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; @@ -1423,18 +1474,30 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tmp_Flag_End = (ADC_FLAG_EOC); } } +#else + /* Check ADC DMA mode */ + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } +#endif } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) + while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1452,8 +1515,9 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) + if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) { /* Check whether end of sequence is reached */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) @@ -1461,8 +1525,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -1471,17 +1535,26 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { /* Retrieve handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* Retrieve Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } +#else + /* Retrieve handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) @@ -1493,7 +1566,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } @@ -1525,7 +1598,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1535,12 +1608,12 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy tickstart = HAL_GetTick(); /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + while(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1570,9 +1643,10 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* which one triggered and on which ADCx, test ADC state of analog watchdog */ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ /* For example: */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ @@ -1669,14 +1743,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_TypeDef *tmpADC_Master; + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); @@ -1694,17 +1771,21 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#endif /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); @@ -1756,12 +1837,15 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if(ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Multimode feature is not available or ADC Instance is Independent or Master, - or is not Slave ADC with dual regular conversions enabled. - Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); @@ -1788,13 +1872,12 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } else { - /* hadc is the handle of a Slave ADC with dual regular conversions - enabled. Therefore, ADC_CR_ADSTART is NOT set */ + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, Slave injected interruptions are enabled nevertheless (for same reason as above) */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ @@ -1814,6 +1897,33 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } } } +#else + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + + /* Enable as well injected interruptions in case + HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This + allows to start regular and injected conversions when JAUTO is + set with a single call to HAL_ADC_Start_IT() */ + switch(hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif } else { @@ -1840,7 +1950,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1893,20 +2003,28 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - /* Ensure that dual regular conversions are not enabled or unavailable. */ +#if defined(ADC_MULTIMODE_SUPPORT) + /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ - if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) + if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) +#endif { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); @@ -1921,16 +2039,20 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#endif /* Check if a conversion is on going on ADC group injected */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); @@ -1973,7 +2095,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ @@ -1987,13 +2109,16 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Process unlocked */ __HAL_UNLOCK(hadc); } + } +#if defined(ADC_MULTIMODE_SUPPORT) else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); } +#endif } else { @@ -2019,7 +2144,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2038,28 +2163,31 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) + if(hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ - /* in memory a potential failing status. */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { - ADC_Disable(hadc); + (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ @@ -2118,11 +2246,16 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { - uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; uint32_t tmp_ier = hadc->Instance->IER; - uint32_t tmp_cfgr = 0x0; - ADC_TypeDef *tmpADC_Master; + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2132,7 +2265,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); @@ -2154,7 +2287,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) { /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); @@ -2163,22 +2296,30 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { /* check CONT bit directly in handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* else need to check Master ADC CONT bit */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* Carry on if continuous mode is disabled */ if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) @@ -2188,7 +2329,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ @@ -2197,10 +2338,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -2240,37 +2381,48 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) { /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { - tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) { /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -2278,11 +2430,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); @@ -2290,7 +2442,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -2383,34 +2535,35 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - overrun_error = 1; + overrun_error = 1UL; } else { /* Check DMA configuration */ - if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET) +#if defined(ADC_MULTIMODE_SUPPORT) + if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) { - /* Multimode not set or feature not available or ADC independent */ - if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) + /* Multimode (when feature is available) is enabled, + Common Control Register MDMA bits must be checked. */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { - overrun_error = 1; + overrun_error = 1UL; } } else +#endif { - /* Multimode (when feature is available) is enabled, - Common Control Register MDMA bits must be checked. */ - if (ADC_MULTIMODE_DMA_ENABLED(hadc)) + /* Multimode not set or feature not available or ADC independent */ + if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) { - overrun_error = 1; + overrun_error = 1UL; } } } - if (overrun_error == 1) + if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); @@ -2505,7 +2658,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" @@ -2563,7 +2716,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; + uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2595,11 +2751,11 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { #if !defined (USE_FULL_ASSERT) - /* Correspondance for compatibility with legacy definition of */ - /* sequencer ranks in direct number format. This correspondance can */ + /* Correspondence for compatibility with legacy definition of */ + /* sequencer ranks in direct number format. This correspondence can */ /* be done only on ranks 1 to 5 due to literal values. */ /* Note: Sequencer ranks in direct number format are no more used */ /* and are detected by activating USE_FULL_ASSERT feature. */ @@ -2612,7 +2768,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break; case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break; /* case 1U */ - default: sConfig->Rank = ADC_REGULAR_RANK_1; + default: sConfig->Rank = ADC_REGULAR_RANK_1; break; } } #endif @@ -2625,7 +2781,11 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { #if defined(ADC_SMPR1_SMPPLUS) /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ @@ -2688,7 +2848,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); @@ -2697,7 +2857,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1UL) & 0x1FUL), sConfig->SamplingTime); } } @@ -2707,51 +2868,49 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { - /* Configuration of common ADC parameters (continuation) */ - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } } } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) + else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } + else + { + /* nothing to do */ + } } } @@ -2792,8 +2951,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted = 0U; - uint32_t tmpAWDLowThresholdShifted = 0U; + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2807,11 +2968,23 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG { assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); } - - /* Verify if threshold is within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); - + + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + } + /* Process locked */ __HAL_LOCK(hadc); @@ -2820,7 +2993,11 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* Analog watchdog configuration */ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) @@ -2899,11 +3076,11 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* several channels by successive calls of this function. */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; @@ -3015,8 +3192,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ @@ -3066,17 +3243,24 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) { - uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0; - uint32_t tickstart = 0; - uint32_t Conversion_Timeout_CPU_cycles = 0; - + uint32_t tickstart; + uint32_t Conversion_Timeout_CPU_cycles = 0UL; + uint32_t conversion_group_reassigned = ConversionGroup; + uint32_t tmp_ADC_CR_ADSTART_JADSTART; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - + /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ( (tmp_adc_is_conversion_on_going_regular != 0UL) + || (tmp_adc_is_conversion_on_going_injected != 0UL) + ) { /* Particular case of continuous auto-injection mode combined with */ /* auto-delay mode. */ @@ -3084,17 +3268,18 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ - if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) - && (hadc->Init.ContinuousConvMode==ENABLE) - && (hadc->Init.LowPowerAutoWait==ENABLE)) + if ( ((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) + && (hadc->Init.ContinuousConvMode == ENABLE) + && (hadc->Init.LowPowerAutoWait == ENABLE) + ) { /* Use stop of regular group */ - ConversionGroup = ADC_REGULAR_GROUP; + conversion_group_reassigned = ADC_REGULAR_GROUP; /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) + while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { - if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4)) + if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -3111,32 +3296,36 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } - /* Stop potential conversion on going on regular group */ - if (ConversionGroup != ADC_INJECTED_GROUP) + /* Stop potential conversion on going on ADC group regular */ + if (conversion_group_reassigned != ADC_INJECTED_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && - HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { - /* Stop conversions on regular group */ - LL_ADC_REG_StopConversion(hadc->Instance); + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } } } - /* Stop potential conversion on going on injected group */ - if (ConversionGroup != ADC_REGULAR_GROUP) + /* Stop potential conversion on going on ADC group injected */ + if (conversion_group_reassigned != ADC_REGULAR_GROUP) { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && - HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { - /* Stop conversions on injected group */ - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP); - } + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group injected conversion */ + LL_ADC_INJ_StopConversion(hadc->Instance); + } + } } /* Selection of start and stop bits with respect to the regular or injected group */ - switch(ConversionGroup) + switch(conversion_group_reassigned) { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); @@ -3151,11 +3340,9 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio } /* Wait for conversion effectively stopped */ - - tickstart = HAL_GetTick(); - while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET) + while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { @@ -3186,17 +3373,16 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tickstart; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ - if (ADC_ENABLING_CONDITIONS(hadc) == RESET) + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -3210,20 +3396,10 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) - { - wait_loop_index--; - } - /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) + while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), ADEN bit is reset by the @@ -3233,7 +3409,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ - if(LL_ADC_IsEnabled(hadc->Instance) == 0) + if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_Enable(hadc->Instance); } @@ -3264,15 +3440,18 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ - if (ADC_IS_ENABLE(hadc) != RESET) + if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) { /* Check if conditions to disable the ADC are fulfilled */ - if (ADC_DISABLING_CONDITIONS(hadc) != RESET) + if((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); @@ -3288,12 +3467,12 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) return HAL_ERROR; } - + /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) + while((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { @@ -3323,7 +3502,7 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update state machine on conversion status if not in error state */ - if(HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))) + if((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); @@ -3332,17 +3511,17 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ - if(HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) + if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3353,11 +3532,11 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3373,7 +3552,7 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } else /* DMA and-or internal error occurred */ { - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) { /* Call HAL ADC Error Callback function */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) @@ -3402,7 +3581,7 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvHalfCpltCallback(hadc); + hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c index f1baf9b8da..830351536a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c @@ -76,10 +76,10 @@ * @{ */ -#define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ - ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime - once the ADC is enabled */ +#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ + ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime + once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: maximum ratio between ADC */ @@ -88,8 +88,8 @@ /* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */ /* Calibration time max = 116 / fADC (refer to datasheet) */ /* = 296 960 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (296960U) /*!< ADC calibration time-out value (unit: CPU cycles) */ - +#define ADC_CALIBRATION_TIMEOUT (296960UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ + /** * @} */ @@ -144,8 +144,8 @@ */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t WaitLoopIndex = 0; + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -176,10 +176,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); /* Wait for calibration completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) + while(LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { - WaitLoopIndex++; - if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT) + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, @@ -228,14 +228,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the selected ADC calibration value */ - if (SingleDiff == ADC_DIFFERENTIAL_ENDED) - { - return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); - } - else - { - return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S); - } + return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); } /** @@ -251,29 +244,29 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - assert_param(IS_ADC_CALFACT(CalibrationFactor)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ - if ( (ADC_IS_ENABLE(hadc) != RESET) && - (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) ) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* Set the selected ADC calibration value */ - if (SingleDiff == ADC_DIFFERENTIAL_ENDED) - { - MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor)); - } - else - { - MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor); - } + LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); } else { @@ -306,18 +299,21 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error @@ -325,13 +321,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) - && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } - /* Process locked */ __HAL_LOCK(hadc); @@ -343,10 +341,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { @@ -361,13 +359,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#endif /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ @@ -385,28 +387,37 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* if ADC is slave, */ - /* - ADC is enabled only (conversion is not started). */ + /* - ADC is enabled only (conversion is not started), */ /* - if multimode only concerns regular conversion, ADC is enabled */ /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ - - /* Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - set ADSTART only if JAUTO is cleared */ - if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; + LL_ADC_INJ_StartConversion(hadc->Instance); } } else { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - ADSTART is not set */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#else + if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); } +#endif + } else { @@ -437,7 +448,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -452,7 +463,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) { - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); @@ -492,10 +503,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0U; - uint32_t tmp_Flag_End = 0U; - uint32_t tmp_cfgr = 0U; - ADC_TypeDef *tmpADC_Master; + uint32_t tickstart; + uint32_t tmp_Flag_End; + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -511,15 +527,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait until End of Conversion or Sequence flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) + while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -532,18 +548,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } } + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == SET) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); @@ -551,10 +578,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) { /* Check whether end of sequence is reached */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) @@ -565,12 +592,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + if((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -585,7 +612,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } @@ -613,12 +640,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } @@ -631,8 +662,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) - && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; @@ -648,7 +682,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); @@ -666,14 +700,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - +#endif + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); @@ -685,7 +723,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ - if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) + if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } @@ -716,23 +754,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ - - /* Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - set ADSTART only if JAUTO is cleared */ - if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; + LL_ADC_INJ_StartConversion(hadc->Instance); } } else { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - ADSTART is not set */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#else + if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); } +#endif + } else { @@ -766,7 +813,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -785,7 +832,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); @@ -833,7 +880,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; ADC_Common_TypeDef *tmpADC_Common; @@ -843,7 +890,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } @@ -913,7 +960,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ @@ -948,9 +995,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; + uint32_t tmphadcSlave_conversion_on_going; + HAL_StatusTypeDef tmphadcSlave_disable_status; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -982,11 +1031,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); - while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || - ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + while( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) { if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { @@ -998,6 +1049,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) return HAL_ERROR; } + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1021,17 +1074,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - /* Check if ADC are effectively disabled */ - if ((ADC_Disable(hadc) == HAL_OK) && - (ADC_Disable(&tmphadcSlave) == HAL_OK) ) + tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); + if ((ADC_Disable(hadc) == HAL_OK) && + (tmphadcSlave_disable_status == HAL_OK) ) { tmp_hal_status = HAL_OK; } } else { - ADC_Disable(hadc); - ADC_Disable(&tmphadcSlave); + /* In case of error, attempt to disable ADC master and slave without status assert */ + (void) ADC_Disable(hadc); + (void) ADC_Disable(&tmphadcSlave); } /* Set ADC state (ADC master) */ @@ -1054,7 +1108,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) { - ADC_Common_TypeDef *tmpADC_Common; + const ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -1101,7 +1155,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { - uint32_t tmp_jdr = 0; + uint32_t tmp_jdr; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1218,7 +1272,7 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1236,7 +1290,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); @@ -1276,7 +1330,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1298,7 +1352,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable ADC peripheral if no injected conversions are on-going */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ @@ -1336,7 +1390,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1351,7 +1405,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ + /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ @@ -1359,30 +1413,30 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ - /* memory a potential failing status. */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - { + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { - ADC_Disable(hadc); + (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ @@ -1396,7 +1450,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) } else { - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } @@ -1423,9 +1477,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; + uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -1460,11 +1515,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); - while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || - ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + while( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) { if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { @@ -1476,6 +1533,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) return HAL_ERROR; } + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1500,12 +1559,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); if (tmp_hal_status == HAL_OK) { - if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET) + if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) { tmp_hal_status = ADC_Disable(&tmphadcSlave); } @@ -1594,7 +1653,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; - uint32_t wait_loop_index = 0U; + uint32_t tmp_config_internal_channel; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + __IO uint32_t wait_loop_index = 0; uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; @@ -1774,21 +1836,23 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* enable (context decremented, up to 2 contexts queued) */ /* - Injected discontinuous mode: can be enabled only if auto-injected */ /* mode is disabled. */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) { - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode) ); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) ); + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) ); } } @@ -1800,7 +1864,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* external triggers are disabled. */ /* - Channel sampling time */ /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ @@ -1923,16 +1992,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); /* Configuration of differential mode */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL), sConfigInjected->InjectedSamplingTime); } } @@ -1942,47 +2012,49 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) { - if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } } } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) + else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) + else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } + else + { + /* nothing to do */ + } } /* Process unlocked */ @@ -2011,9 +2083,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSlave; + uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -2045,20 +2118,21 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ - if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) ) + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + && (tmphadcSlave_conversion_on_going == 0UL) ) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - /* If multimode is selected, configure all multimode paramaters. */ + /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if(multimode->Mode != ADC_MODE_INDEPENDENT) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, multimode->DMAAccessMode | - ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests)); + ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ @@ -2070,8 +2144,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | @@ -2088,8 +2161,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); } @@ -2124,20 +2196,34 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) { - /* Parameter can be set only if no conversion is on-going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - return HAL_OK; + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** @@ -2151,16 +2237,30 @@ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) { - /* Parameter can be set only if no conversion is on-going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - return HAL_OK; + LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** @@ -2168,22 +2268,29 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. * @note To enable again the voltage regulator, the user is expected to - * resort to HAL_ADC_Init() API. + * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) { - /* ADVREGEN can be written only when the ADC is disabled */ - if (ADC_IS_ENABLE(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { - CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); - return HAL_OK; + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** @@ -2194,7 +2301,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal - * calibration is lost. + * calibration is lost. * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously @@ -2204,16 +2311,23 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) { - /* DEEPPWD can be written only when the ADC is disabled */ - if (ADC_IS_ENABLE(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - return HAL_OK; + LL_ADC_EnableDeepPowerDown(hadc->Instance); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c index 62cbea9361..f3a9e93c1b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c @@ -18,7 +18,10 @@ [..] The STM32L4xx device family integrates two analog comparators instances: - COMP1, COMP2. + COMP1, COMP2 except for the STM32L412xx/STM32L422xx products that embed only + one: COMP1. + In the rest of the file, all comments related to a pair of comparators are not + applicable to STM32L412xx or STM32L422xx. (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). @@ -146,32 +149,33 @@ ****************************************************************************** Table 1. COMP inputs and output for STM32L4xx devices - +---------------------------------------------------------+ - | | | COMP1 | COMP2 | - |----------------|----------------|-----------|-----------| - | | IO1 | PC5 | PB4 | - | Input plus | IO2 | PB2 | PB6 | - | | IO3 (3) | PA1 | PA3 | - |----------------|----------------|-----------------------| - | | 1/4 VrefInt | Available | Available | - | | 1/2 VrefInt | Available | Available | - | | 3/4 VrefInt | Available | Available | - | Input minus | VrefInt | Available | Available | - | | DAC1 channel 1 | Available | Available | - | | DAC1 channel 2 | Available | Available | - | | IO1 | PB1 | PB3 | - | | IO2 | PC4 | PB7 | - | | IO3 (3) | PA0 | PA2 | - | | IO4 (3) | PA4 | PA4 | - | | IO5 (3) | PA5 | PA5 | - +---------------------------------------------------------+ - | Output | | PB0 (1) | PB5 (1) | - | | | PB10 (1) | PB11 (1) | - | | | TIM (2) | TIM (2) | - +---------------------------------------------------------+ + +-----------------------------------------------------------------+ + | | | COMP1 | COMP2 (4) | + |----------------|----------------|---------------|---------------+ + | | IO1 | PC5 | PB4 | + | Input plus | IO2 | PB2 | PB6 | + | | IO3 (3) | PA1 | PA3 | + |----------------|----------------|---------------|---------------+ + | | 1/4 VrefInt | Available | Available | + | | 1/2 VrefInt | Available | Available | + | | 3/4 VrefInt | Available | Available | + | Input minus | VrefInt | Available | Available | + | | DAC1 channel 1 | Available | Available (4) | + | | DAC1 channel 2 | Available | Available (4) | + | | IO1 | PB1 | PB3 | + | | IO2 | PC4 | PB7 | + | | IO3 (3) | PA0 | PA2 | + | | IO4 (3) | PA4 | PA4 | + | | IO5 (3) | PA5 | PA5 | + +----------------|----------------|---------------|---------------+ + | Output | | PB0 (1) | PB5 (1) | + | | | PB10 (1) | PB11 (1) | + | | | TIM (2) | TIM (2) | + +-----------------------------------------------------------------+ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances. (3) Only STM32L43x/L44x + (4) Not applicable to STM32L412x/L422x ****************************************************************************** * @attention @@ -230,15 +234,15 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US (80U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART_SCALER"). */ /* Unit: us */ -#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200U) /*!< Delay for COMP voltage scaler stabilization time */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */ -#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /** * @} @@ -276,14 +280,18 @@ */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { - uint32_t tmp_csr = 0U; - uint32_t exti_line = 0U; - uint32_t comp_voltage_scaler_not_initialized = 0U; - __IO uint32_t wait_loop_index = 0U; + uint32_t tmp_csr; + uint32_t exti_line; + uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ + __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -298,7 +306,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); +#if defined(COMP2) assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); +#endif if(hcomp->State == HAL_COMP_STATE_RESET) { @@ -337,7 +347,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Memorize voltage scaler state before initialization */ - comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0); + comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); /* Set COMP parameters */ tmp_csr = ( hcomp->Init.NonInvertingInput @@ -351,12 +361,21 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Set parameters in COMP register */ /* Note: Update all bits except read-only, lock and enable bits */ #if defined (COMP_CSR_INMESEL) +#if defined (COMP_CSR_WINMODE) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, tmp_csr ); +#else + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | + COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, + tmp_csr + ); +#endif #else MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | @@ -366,6 +385,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) ); #endif +#if defined(COMP2) /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ @@ -378,17 +398,19 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); } +#endif /* COMP2 */ /* Delay for COMP scaler bridge voltage stabilization */ - /* Apply the delay if voltage scaler bridge is enabled for the first time */ - if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0U) && - (comp_voltage_scaler_not_initialized != 0U) ) + /* Apply the delay if voltage scaler bridge is required and not already enabled */ + if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && + (comp_voltage_scaler_initialized == 0UL) ) { /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2U))); - while(wait_loop_index != 0U) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } @@ -398,10 +420,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Manage EXTI settings */ - if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET) + if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { /* Configure EXTI rising edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { LL_EXTI_EnableRisingTrig_0_31(exti_line); } @@ -411,7 +433,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI falling edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { LL_EXTI_EnableFallingTrig_0_31(exti_line); } @@ -424,7 +446,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) LL_EXTI_ClearFlag_0_31(exti_line); /* Configure EXTI event mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { LL_EXTI_EnableEvent_0_31(exti_line); } @@ -434,7 +456,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) } /* Configure EXTI interrupt mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { LL_EXTI_EnableIT_0_31(exti_line); } @@ -476,7 +498,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -486,7 +512,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set COMP_CSR register to reset value */ - WRITE_REG(hcomp->Instance->CSR, 0x00000000U); + WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) if (hcomp->MspDeInitCallback == NULL) @@ -727,11 +753,15 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { - __IO uint32_t wait_loop_index = 0U; + __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -750,10 +780,11 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Delay for COMP startup time */ /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U))); - while(wait_loop_index != 0U) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } @@ -777,7 +808,11 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -786,8 +821,9 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - if((hcomp->State == HAL_COMP_STATE_BUSY) || - (hcomp->State == HAL_COMP_STATE_READY) ) + /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ + /* (all states except HAL_COMP_STATE_RESET and except locked status. */ + if(hcomp->State != HAL_COMP_STATE_RESET) { /* Disable the selected comparator */ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -815,8 +851,9 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP EXTI flag */ - if(LL_EXTI_IsActiveFlag_0_31(exti_line) != RESET) + if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { +#if defined(COMP2) /* Check whether comparator is in independent or window mode */ if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET) { @@ -830,6 +867,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else +#endif /* COMP2 */ { /* Clear COMP EXTI line pending bit */ LL_EXTI_ClearFlag_0_31(exti_line); @@ -875,7 +913,11 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -885,7 +927,18 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set HAL COMP handle state */ - hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK)); + switch(hcomp->State) + { + case HAL_COMP_STATE_RESET: + hcomp->State = HAL_COMP_STATE_RESET_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: /* HAL_COMP_STATE_BUSY */ + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + } } if(status == HAL_OK) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c index 7d7289c373..819158cdce 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c @@ -305,9 +305,6 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ - /* Process locked */ - __HAL_LOCK(hcrc); - /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; @@ -327,7 +324,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; @@ -336,9 +333,6 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - /* Return the CRC computed value */ return temp; } @@ -363,9 +357,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ - /* Process locked */ - __HAL_LOCK(hcrc); - /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; @@ -391,7 +382,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: @@ -401,9 +392,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - /* Return the CRC computed value */ return temp; } @@ -469,30 +457,30 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ for (i = 0U; i < (BufferLength / 4U); i++) { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ - ((uint32_t)pBuffer[4U * i + 1U] << 16U) | \ - ((uint32_t)pBuffer[4U * i + 2U] << 8U) | \ - (uint32_t)pBuffer[4U * i + 3U]; + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) { - if (BufferLength % 4U == 1U) + if ((BufferLength % 4U) == 1U) { - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if (BufferLength % 4U == 2U) + if ((BufferLength % 4U) == 2U) { - data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if (BufferLength % 4U == 3U) + if ((BufferLength % 4U) == 3U) { - data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i + 2U]; + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } } @@ -518,11 +506,11 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 * a correct type handling by the IP */ for (i = 0U; i < (BufferLength / 2U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[2U * i + 1U]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; } if ((BufferLength % 2U) != 0U) { - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = pBuffer[2U * i]; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c index 88ad1de311..1ecef9cb6a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c @@ -117,7 +117,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << msb)) == 0U)) + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) { } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c index ff83ce4d7c..3747e05752 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c @@ -1432,26 +1432,43 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /* Check if computation complete interrupt is enabled and if the computation complete flag is raised */ - if((__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) { + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + { #if defined(AES_CR_NPBLB) - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) #else - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) #endif - { - /* To ensure proper suspension requests management, CCF flag - is reset in CRYP_AES_Auth_IT() according to the current - phase under handling */ - CRYP_AES_Auth_IT(hcryp); - } - else - { - /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - CRYP_AES_IT(hcryp); + { + /* To ensure proper suspension requests management, CCF flag + is reset in CRYP_AES_Auth_IT() according to the current + phase under handling */ + if (CRYP_AES_Auth_IT(hcryp) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + if (CRYP_AES_IT(hcryp) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } } } } @@ -1519,9 +1536,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) { - uint32_t keyaddr = 0x0; + uint32_t keyaddr; - if ((uint32_t)(hcryp->Init.pKey == NULL)) + if (hcryp->Init.pKey == NULL) { return HAL_ERROR; } @@ -1532,21 +1549,21 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; } hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); return HAL_OK; @@ -1560,7 +1577,7 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) { - uint32_t ivaddr = 0x0; + uint32_t ivaddr; #if !defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) @@ -1581,11 +1598,11 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) ivaddr = (uint32_t)(hcryp->Init.pInitVect); hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } return HAL_OK; @@ -1603,7 +1620,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t inputaddr = 0; + uint32_t inputaddr; uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; if(hcryp->State == HAL_CRYP_STATE_BUSY) @@ -1612,14 +1629,14 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { /* Read the last available output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; + hcryp->CrypOutCount -= 16U; } else @@ -1628,27 +1645,27 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); - outputaddr+=4; + outputaddr+=4U; } *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); } /* In case of ciphering or deciphering, check if all output text has been retrieved; In case of key derivation, stop right there */ - if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) + if ((hcryp->CrypOutCount == 0U) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) { /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); @@ -1690,15 +1707,15 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; /* Write the next input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); return HAL_OK; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c index 5fb87be580..9a85f160ac 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c @@ -83,8 +83,8 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout); static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAError(DMA_HandleTypeDef *hdma); @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -261,7 +261,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, */ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; + uint32_t inputaddr; if(hcryp->State == HAL_CRYP_STATE_READY) { @@ -275,7 +275,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -321,14 +321,14 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; /* Write the first input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } @@ -366,8 +366,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD */ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; + uint32_t inputaddr; + uint32_t outputaddr; if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -447,23 +447,27 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInput */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout) { - uint32_t index = 0; - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; - uint32_t tagaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint64_t payloadlength = 0; + uint32_t index ; + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t tagaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint64_t payloadlength ; uint32_t difflength = 0; uint32_t addhoc_process = 0; if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) || - ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0))) + if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) || + ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0U))) { return HAL_ERROR; } @@ -474,7 +478,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput #endif { /* In case of CMAC or CCM (when applicable) header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } @@ -482,9 +486,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - if (((pInputData == NULL) && (Size != 0)) || \ - ((pInputData != NULL) && (Size == 0)) || \ - ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))) + if (((pInputData == NULL) && (Size != 0U)) || \ + ((pInputData != NULL) && (Size == 0U)) || \ + ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL))) { return HAL_ERROR; } @@ -502,6 +506,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } #endif } + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } /* Process Locked */ @@ -555,21 +564,22 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* in case of CMAC, enter B0 block in header phase, before the header itself. */ /* If Size = 0 (possible case of resumption after CMAC header phase suspension), skip these steps and go directly to header buffer feeding to the HW */ - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0)) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0U)) { + uint64_t index_test; inputaddr = (uint32_t)pInputData; - for( ; (index < Size); index += 16) + for(index=0U ; (index < Size); index += 16U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -582,7 +592,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size)) + index_test = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_test < Size)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -595,7 +606,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the total number of bytes (B blocks + header) that remain to be processed at this point */ - hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16); + hcryp->CrypInCount = (uint32_t) (hcryp->Init.HeaderSize + Size - index_test); /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -610,22 +621,23 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput inputaddr = (uint32_t)hcryp->Init.Header; /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; - if ((hcryp->Init.HeaderSize % 16) != 0) + headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ; + if ((hcryp->Init.HeaderSize % 16U) != 0U) { difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); } - for(index=0; index < headerlength; index += 16) + for(index=0U ; index < headerlength; index += 16U) { + uint64_t index_temp; /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -638,7 +650,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength)) + index_temp = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_temp < headerlength)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -650,7 +663,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the total number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16); + hcryp->CrypInCount = (uint32_t) (hcryp->Init.HeaderSize - index_temp); /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -660,7 +673,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } /* Case header length is not a multiple of 16 bytes */ - if (difflength != 0) + if (difflength != 0U) { hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); @@ -688,9 +701,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Enter payload */ /* Specific handling to manage payload last block size less than 128 bits */ - if ((Size % 16) != 0) + if ((Size % 16U) != 0U) { - payloadlength = (Size/16) * 16; + payloadlength = (Size/16U) * 16U; difflength = (uint32_t) (Size - payloadlength); addhoc_process = 1; } @@ -700,17 +713,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } /* Feed payload */ - for( ; index < payloadlength; index += 16) + for(index=0U ; index < payloadlength; index += 16U) { + uint64_t index_temp; /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { @@ -725,17 +739,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Retrieve output data: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength)) + index_temp = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_temp < payloadlength)) { /* no flag waiting under IRQ handling */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) @@ -759,7 +774,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = Size - (index+16); + hcryp->CrypInCount = (uint32_t) (Size - index_temp); /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -771,7 +786,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Additional processing to manage GCM(/CCM) encryption and decryption cases when payload last block size less than 128 bits */ - if (addhoc_process == 1) + if (addhoc_process == 1U) { hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; @@ -786,7 +801,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + else { tagaddr = (uint32_t)pOutputData; @@ -805,30 +820,30 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* input length in bits */ #if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(headerlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(inputlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -837,6 +852,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } #else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); @@ -851,13 +871,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } #endif @@ -870,11 +895,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Read the Auth TAG in the Data Out register */ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; @@ -885,15 +910,6 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -943,27 +959,33 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint32_t index = 0; + uint32_t inputaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint32_t index ; uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask[4][3]; + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) || - ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0))) + if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) || + ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0U))) { return HAL_ERROR; } @@ -974,7 +996,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn #endif { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } @@ -982,7 +1004,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) + if ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL)) { return HAL_ERROR; } @@ -1000,6 +1022,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn } #endif } + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } /* Process Locked */ @@ -1044,21 +1071,21 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn However, in case of resumption after suspension, if all the B blocks have been entered (in that case, Size = 0), only the remainder of the non-processed header bytes are entered. */ - if (Size != 0) + if (Size != 0U) { - hcryp->CrypInCount = Size + hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)(Size + hcryp->Init.HeaderSize); hcryp->pCrypInBuffPtr = pInputData; } else { - hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)hcryp->Init.HeaderSize; hcryp->pCrypInBuffPtr = hcryp->Init.Header; } } else { /* Get the header addresses and sizes */ - hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)hcryp->Init.HeaderSize; hcryp->pCrypInBuffPtr = hcryp->Init.Header; } @@ -1081,7 +1108,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn __HAL_CRYP_ENABLE(hcryp); /* Increment/decrement instance pointer/counter */ - if (hcryp->CrypInCount == 0) + if (hcryp->CrypInCount == 0U) { /* Case of no header */ hcryp->State = HAL_CRYP_STATE_READY; @@ -1089,17 +1116,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; return HAL_OK; } - else if (hcryp->CrypInCount < 16) + else if (hcryp->CrypInCount < 16U) { hcryp->CrypInCount = 0; addhoc_process = 1; difflength = (uint32_t) (hcryp->Init.HeaderSize); - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; } else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; } @@ -1120,35 +1147,35 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* Enter header first block to initiate the process in the Data Input register */ - if (addhoc_process == 0) + if (addhoc_process == 0U) { /* Header has size equal or larger than 128 bits */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } else { /* Header has size less than 128 bits */ /* Enter complete words when possible */ - for( ; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; } @@ -1161,10 +1188,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; + hcryp->CrypInCount = (uint32_t)Size; hcryp->pCrypInBuffPtr = pInputData; hcryp->pCrypOutBuffPtr = pOutputData; - hcryp->CrypOutCount = Size; + hcryp->CrypOutCount = (uint32_t)Size; inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; @@ -1189,7 +1216,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn } /* Specific handling to manage payload size less than 128 bits */ - if (Size < 16) + if (Size < 16U) { difflength = (uint32_t) (Size); #if defined(AES_CR_NPBLB) @@ -1197,14 +1224,14 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) { /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); } } #else @@ -1222,22 +1249,22 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, to have a complete block of 128 bits */ - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; /* Insert the last block (which size is inferior to 128 bits) padded with zeroes to have a complete block of 128 bits */ - for(index=0; index < (difflength/4); index ++) + for(index=0U; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* If required, manage input data size not multiple of 32 bits */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; } @@ -1246,23 +1273,23 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn { /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; /* Enter payload first block to initiate the process in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + else { hcryp->pCrypOutBuffPtr = pOutputData; @@ -1281,32 +1308,32 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* Input length in bits */ + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* Input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ #if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)((headerlength)>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)((inputlength)>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)((headerlength)>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)((inputlength)>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1315,6 +1342,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } #else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); @@ -1329,23 +1361,20 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } #endif } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - return HAL_ERROR; - } return HAL_OK; } @@ -1389,20 +1418,24 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; - uint32_t tagaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint64_t payloadlength = 0; + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t tagaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint64_t payloadlength ; if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) + { + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) + if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) { return HAL_ERROR; } @@ -1410,7 +1443,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } @@ -1418,7 +1451,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI #else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { - if ((pInputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1427,7 +1460,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) + if ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL)) { return HAL_ERROR; } @@ -1445,6 +1478,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } #endif } + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } /* Process Locked */ @@ -1502,11 +1540,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { inputaddr = (uint32_t)pInputData; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) @@ -1533,10 +1571,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } inputaddr = (uint32_t)hcryp->Init.Header; - if ((hcryp->Init.HeaderSize % 16) != 0) + if ((hcryp->Init.HeaderSize % 16U) != 0U) { - if (hcryp->Init.HeaderSize < 16) + if (hcryp->Init.HeaderSize < 16U) { hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); @@ -1554,7 +1592,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ; /* Store the ending transfer point */ hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength; hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */ @@ -1562,14 +1600,14 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /* Set the input and output addresses and start DMA transfer */ /* (incomplete DMA transfer, will be wrapped up after completion of the first one (initiated here) with data padding */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, headerlength, 0); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)headerlength, 0); } } else { hcryp->CrypInCount = 0; /* Set the input address and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)hcryp->Init.HeaderSize, 0); } } /*============================================*/ @@ -1612,11 +1650,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /* Specific handling to manage payload size less than 128 bits */ - if ((Size % 16) != 0) + if ((Size % 16U) != 0U) { inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - if (Size < 16) + if (Size < 16U) { /* Block is now entered in polling mode, no actual gain in resorting to DMA */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; @@ -1638,17 +1676,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } else { - payloadlength = (Size/16) * 16; + payloadlength = (Size/16U) * 16U; /* Store the ending transfer points */ - hcryp->pCrypInBuffPtr = pInputData + payloadlength; - hcryp->pCrypOutBuffPtr = pOutputData + payloadlength; + hcryp->pCrypInBuffPtr = pInputData; + hcryp->pCrypInBuffPtr += payloadlength; + hcryp->pCrypOutBuffPtr = pOutputData; + hcryp->pCrypOutBuffPtr += payloadlength; hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */ /* Set the input and output addresses and start DMA transfer */ /* (incomplete DMA transfer, will be wrapped up with data padding after completion of the one initiated here) */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)payloadlength, outputaddr); } } else @@ -1658,13 +1698,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI outputaddr = (uint32_t)pOutputData; /* Set the input and output addresses and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)Size, outputaddr); } } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + else { /* If coming from header phase (GMAC or CMAC case when applicable), wait for CCF flag to be raised */ @@ -1696,31 +1736,31 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ #if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(headerlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(inputlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1729,6 +1769,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } #else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); @@ -1745,13 +1790,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } #endif /* No DMA transfer is required at that point therefore, the software @@ -1765,11 +1815,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /* Read the Auth TAG in the IN FIFO */ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; /* Clear CCF Flag */ @@ -1782,15 +1832,6 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI __HAL_CRYP_DISABLE(hcryp); } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -1841,11 +1882,11 @@ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) uint32_t outputaddr = (uint32_t)Output; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0); } @@ -1865,11 +1906,11 @@ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) uint32_t ivaddr = (uint32_t)Input; hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } @@ -1910,19 +1951,19 @@ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output } *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); } @@ -1940,19 +1981,19 @@ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input uint32_t ivaddr = (uint32_t)Input; hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); } @@ -1974,21 +2015,21 @@ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, ui if (KeySize == CRYP_KEYSIZE_256B) { *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4); - keyaddr+=4; + keyaddr+=4U; } *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); } @@ -2009,21 +2050,21 @@ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, ui if (KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; } hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } @@ -2039,7 +2080,7 @@ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, ui */ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { - *(uint32_t*)(Output) = hcryp->Instance->CR; + *(uint32_t*)(void *)(Output) = hcryp->Instance->CR; /* Derogation MisraC2012 R.11.5 */ } /** @@ -2053,7 +2094,7 @@ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) */ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) { - hcryp->Instance->CR = *(uint32_t*)(Input); + hcryp->Instance->CR = *(uint32_t*)(void *)(Input); /* Derogation MisraC2012 R.11.5 */ /* At the same time, set handle state back to READY to be able to resume the AES calculations without the processing APIs returning HAL_BUSY when called. */ hcryp->State = HAL_CRYP_STATE_READY; @@ -2100,9 +2141,8 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) */ static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) { - uint32_t difflength = 0; - - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + uint32_t difflength; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2110,7 +2150,7 @@ static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - if (hcryp->CrypInCount != 0) + if (hcryp->CrypInCount != 0U) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; @@ -2145,8 +2185,8 @@ static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) { - uint32_t difflength = 0; - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + uint32_t difflength; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); @@ -2155,7 +2195,7 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Initiate additional transfer to wrap-up data feeding to the IP */ - if (hcryp->CrypInCount != 0) + if (hcryp->CrypInCount != 0U) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; @@ -2185,7 +2225,7 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; @@ -2211,19 +2251,21 @@ static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t inputaddr = 0x0; - uint32_t outputaddr = 0x0; - uint32_t index = 0x0; + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t index ; uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask[4][3] ; uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; uint32_t intermediate_data[4] = {0}; + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ + if(hcryp->State == HAL_CRYP_STATE_BUSY) { /*===========================*/ @@ -2257,7 +2299,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { /* Check if all input header data have been entered */ - if (hcryp->CrypInCount == 0) + if (hcryp->CrypInCount == 0U) { /* Clear Computation Complete Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2308,17 +2350,17 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Increment/decrement instance pointer/counter */ - if (hcryp->CrypInCount < 16) + if (hcryp->CrypInCount < 16U) { difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; addhoc_process = 1; - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; } else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; } #if defined(AES_CR_NPBLB) @@ -2337,34 +2379,34 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) } /* Write the Input block in the Data Input register */ - if (addhoc_process == 0) + if (addhoc_process == 0U) { hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } else { /* Header remainder has size less than 128 bits */ /* Enter complete words when possible */ - for( ; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; } @@ -2385,38 +2427,37 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) when GCM (or CCM when applicable) encryption or decryption is selected. Check here if the last block output data are read */ #if defined(AES_CR_NPBLB) - if ((hcryp->CrypOutCount < 16) && \ - (hcryp->CrypOutCount > 0)) + if ((hcryp->CrypOutCount < 16U) && \ + (hcryp->CrypOutCount > 0U)) #else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \ - (hcryp->CrypOutCount < 16) && \ - (hcryp->CrypOutCount > 0)) + (hcryp->CrypOutCount < 16U) && \ + (hcryp->CrypOutCount > 0U)) #endif { - addhoc_process = 1; difflength = hcryp->CrypOutCount; - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ /* Retrieve intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { intermediate_data[index] = hcryp->Instance->DOUTR; } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; + outputaddr+=4U; } /* Next, retrieve partial output word if applicable; at the same time, start masking intermediate data with a mask of zeros of same size than the padding applied to the last block of payload */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + intermediate_data[difflength/4U] &= mask[mask_index][difflengthmod4-1U]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U]; } #if !defined(AES_CR_NPBLB) @@ -2430,15 +2471,15 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { - intermediate_data[(difflength+3)/4+index] = 0; + intermediate_data[((difflength+3U)/4U)+index] = 0; } /* Insert intermediate data to trigger an additional DOUTR reading round */ /* Clear Computation Complete Flag before entering new block */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { hcryp->Instance->DINR = intermediate_data[index]; } @@ -2470,28 +2511,28 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) } else { - if (hcryp->CrypOutCount != 0) + if (hcryp->CrypOutCount != 0U) { /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ /* Retrieve the last block available from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; /* Increment/decrement instance pointer/counter */ hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; + hcryp->CrypOutCount -= 16U; } #if !defined(AES_CR_NPBLB) else { /* Software work-around: additional DOUTR reading round to discard the data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { intermediate_data[index] = hcryp->Instance->DOUTR; } @@ -2500,7 +2541,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) } /* Check if all output text has been retrieved */ - if (hcryp->CrypOutCount == 0) + if (hcryp->CrypOutCount == 0U) { /* Clear Computation Complete Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2552,24 +2593,26 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Usual input data feeding case */ - if (hcryp->CrypInCount < 16) + if (hcryp->CrypInCount < 16U) { difflength = (uint32_t) (hcryp->CrypInCount); - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; hcryp->CrypInCount = 0; #if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) - { - /* Set NPBLB field in writing the number of padding bytes - for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); - } + { + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) + { + /* Set NPBLB field in writing the number of padding bytes + for the last block of payload */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); + } + } #else /* Software workaround applied to GCM encryption only */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) @@ -2581,19 +2624,19 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /* Insert the last block (which size is inferior to 128 bits) padded with zeroes to have a complete block of 128 bits */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* If required, manage input data size not multiple of 32 bits */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; } @@ -2602,15 +2645,15 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } @@ -2632,11 +2675,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /* Retrieve the last expected data from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2696,7 +2739,7 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t /* Set the DMA error callback */ hcryp->hdmain->XferErrorCallback = CRYP_Authentication_DMAError; - if (outputaddr != 0) + if (outputaddr != 0U) { /* Set the output CRYP DMA transfer complete callback */ hcryp->hdmaout->XferCpltCallback = CRYP_Authentication_DMAOutCplt; @@ -2708,16 +2751,30 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t __HAL_CRYP_ENABLE(hcryp); /* Enable the DMA input stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable the DMA input request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - if (outputaddr != 0) + if (outputaddr != 0U) { /* Enable the DMA output stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable the DMA output request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); @@ -2738,22 +2795,22 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { - uint32_t index = 0; + uint32_t index; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; - for(index=0; (index < Ilength); index += 16) + for(index=0U ; (index < Ilength); index += 16U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; /* Wait for CCF flag to be raised */ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -2768,17 +2825,17 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /* Read the Output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength)) + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Ilength)) { /* Reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -2787,7 +2844,7 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = Ilength - (index+16); + hcryp->CrypInCount = Ilength - (index+16U); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; @@ -2833,21 +2890,21 @@ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); - outputaddr+=4; + outputaddr+=4U; } *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); @@ -2877,10 +2934,24 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; /* Enable the DMA input stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable the DMA output stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable In and Out DMA requests */ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); @@ -2897,9 +2968,9 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin * @param Timeout: Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2925,9 +2996,9 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T * @param Timeout: Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2954,7 +3025,7 @@ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uin */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2974,7 +3045,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); @@ -3003,7 +3074,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; @@ -3027,31 +3098,33 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) */ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling) { - uint32_t index = 0; - uint32_t difflengthmod4 = difflength%4; + uint32_t index; + uint32_t difflengthmod4 = difflength%4U; uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask[4][3]; uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; uint32_t intermediate_data[4] = {0}; + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ + #if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) { /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); } } #else @@ -3066,25 +3139,25 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /* Wrap-up entering header or payload data */ /* Enter complete words when possible */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; } - if (polling == CRYP_POLLING_ON) + if (polling == (uint32_t)CRYP_POLLING_ON) { if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) { @@ -3106,25 +3179,25 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ { /* Retrieve intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { intermediate_data[index] = hcryp->Instance->DOUTR; } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; + outputaddr+=4U; } /* Next, retrieve partial output word if applicable; at the same time, start masking intermediate data with a mask of zeros of same size than the padding applied to the last block of payload */ - if (difflengthmod4 != 0) + if (difflengthmod4 != 0U) { - intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; + intermediate_data[difflength/4U] &= mask[mask_index][difflengthmod4-1U]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U]; } @@ -3141,12 +3214,12 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { - intermediate_data[(difflength+3)/4+index] = 0; + intermediate_data[((difflength+3U)/4U)+index] = 0; } /* Insert intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { hcryp->Instance->DINR = intermediate_data[index]; } @@ -3162,7 +3235,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /* Read data to discard */ /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { intermediate_data[index] = hcryp->Instance->DOUTR; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c index ece455a744..e2e51adf8f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c @@ -47,7 +47,6 @@ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) (#) Software using DAC_TRIGGER_SOFTWARE - *** DAC Buffer mode feature *** =============================== [..] @@ -317,7 +316,6 @@ ****************************************************************************** */ - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -325,21 +323,23 @@ * @{ */ +#ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC1) + /** @defgroup DAC DAC * @brief DAC driver modules * @{ */ -#ifdef HAL_DAC_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup DAC_Private_Constants DAC Private Constants * @{ */ -#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1 ms */ -#define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */ +#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */ +#define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */ + /** * @} */ @@ -381,7 +381,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -413,10 +413,6 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) { hdac->MspInitCallback = HAL_DAC_MspInit; } - if(hdac->MspDeInitCallback == NULL) - { - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ @@ -446,7 +442,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) /** * @brief Deinitialize the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -471,7 +467,6 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) } /* DeInit the low level hardware */ hdac->MspDeInitCallback(hdac); - #else /* DeInit the low level hardware */ HAL_DAC_MspDeInit(hdac); @@ -492,7 +487,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -508,7 +503,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /** * @brief DeInitialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -546,9 +541,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported) @@ -595,7 +590,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) if(Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ - if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); @@ -604,7 +599,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) else { /* Check if software trigger enabled */ - if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); @@ -634,9 +629,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -660,14 +655,14 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -676,7 +671,8 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + HAL_StatusTypeDef status; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -724,16 +720,23 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); /* Process Unlocked */ __HAL_UNLOCK(hdac); - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } /* Return function status */ - return HAL_OK; + return status; } #endif /* STM32L451xx STM32L452xx STM32L462xx */ @@ -749,9 +752,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -760,7 +763,8 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + HAL_StatusTypeDef status; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -846,7 +850,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { @@ -854,17 +858,24 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ __HAL_UNLOCK(hdac); - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } /* Return function status */ - return HAL_OK; + return status; } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ @@ -872,9 +883,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -882,13 +893,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); @@ -950,7 +961,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) * @brief Handles DAC interrupt request * This function uses the interruption of DMA * underrun. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -978,7 +989,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ @@ -998,7 +1009,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - /* Disable the selected DAC channel1 DMA request */ + /* Disable the selected DAC channel2 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Error callback */ @@ -1006,7 +1017,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ @@ -1016,18 +1027,18 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -1058,7 +1069,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** * @brief Conversion complete callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1074,7 +1085,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1090,7 +1101,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1106,7 +1117,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1141,9 +1152,9 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -1180,10 +1191,15 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @note By calling this function, the high frequency interface mode (HFSEL bits) + * will be set. This parameter scope is the DAC instance. As the function + * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig + * must be the same at each call. + * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect). + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present) @@ -1191,10 +1207,10 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; - uint32_t tickstart = 0; + uint32_t tmpreg1, tmpreg2; + uint32_t tickstart = 0U; #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hclkfreq = 0; + uint32_t hclkfreq; #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /* Check the DAC parameters */ @@ -1233,8 +1249,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Get timeout */ tickstart = HAL_GetTick(); - /* SHSR1 can be written when BWST1 equals RESET */ - while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) + /* SHSR1 can be written when BWST1 is cleared */ + while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) @@ -1254,9 +1270,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf #if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) else /* Channel 2 */ { - /* SHSR2 can be written when BWST2 equals RESET */ + /* SHSR2 can be written when BWST2 is cleared */ - while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET) + while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) @@ -1276,9 +1292,9 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf #endif /* STM32L451xx STM32L452xx STM32L462xx */ /* HoldTime */ - MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<DAC_SampleAndHoldConfig.DAC_HoldTime)<Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ - MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<DAC_SampleAndHoldConfig.DAC_RefreshTime)<Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) @@ -1287,11 +1303,11 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ - tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } @@ -1300,27 +1316,27 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; - /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ - tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); + /* Clear DAC_MCR_MODEx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); /* Calculate MCR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ - CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); + CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ - tmpreg2 = (sConfig->DAC_Trigger); + tmpreg2 = sConfig->DAC_Trigger; /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) { @@ -1354,7 +1370,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -1366,12 +1382,71 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf return HAL_OK; } +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC handle state + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +{ + /* Return DAC handle state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback * To be used instead of the weak (surcharged) predefined callback * @param hdac DAC handle - * @param CallbackID ID of the callback to be registered + * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID @@ -1479,7 +1554,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal * @brief Unregister a User DAC Callback * DAC Callback is redirected to the weak (surcharged) predefined callback * @param hdac DAC handle - * @param CallbackID ID of the callback to be unregistered + * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID @@ -1587,51 +1662,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DAC state. - (+) Check the DAC Errors. - -@endverbatim - * @{ - */ - -/** - * @brief return the DAC handle state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL state - */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) -{ - /* Return DAC handle state */ - return hdac->State; -} - - -/** - * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval DAC Error Code - */ -uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) -{ - return hdac->ErrorCode; -} - /** * @} */ @@ -1646,50 +1676,49 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh1(hdac); #else HAL_DAC_ConvCpltCallbackCh1(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - hdac->State= HAL_DAC_STATE_READY; + hdac->State = HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh1(hdac); #else HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; @@ -1698,22 +1727,23 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) hdac->ErrorCallbackCh1(hdac); #else HAL_DAC_ErrorCallbackCh1(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - hdac->State= HAL_DAC_STATE_READY; + hdac->State = HAL_DAC_STATE_READY; } /** * @} */ -#endif /* HAL_DAC_MODULE_ENABLED */ - - /** * @} */ +#endif /* DAC1 */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c index 79c8e2a405..55100ceb55 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c @@ -63,13 +63,15 @@ * @{ */ +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(DAC1) + /** @defgroup DACEx DACEx * @brief DAC Extended HAL module driver * @{ */ -#ifdef HAL_DAC_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -102,12 +104,13 @@ /** * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -136,7 +139,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -150,12 +153,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -184,7 +188,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -202,22 +206,22 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { - uint32_t data = 0, tmp = 0; + uint32_t data, tmp; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); @@ -227,11 +231,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t)hdac->Instance; @@ -246,7 +250,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /** * @brief Conversion complete callback in non-blocking mode for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -262,7 +266,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -278,7 +282,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -294,7 +298,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -313,10 +317,10 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief Run the self calibration of one DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC channel configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC channel configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -329,19 +333,23 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t tmp = 0; - uint32_t trimmingvalue = 0; + __IO uint32_t tmp; + uint32_t trimmingvalue; uint32_t delta; /* store/restore channel configuration structure purpose */ - uint32_t oldmodeconfiguration = 0; + uint32_t oldmodeconfiguration; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Check the DAC handle allocation */ /* Check if DAC running */ - if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY)) + if (hdac == NULL) + { + status = HAL_ERROR; + } + else if (hdac->State == HAL_DAC_STATE_BUSY) { status = HAL_ERROR; } @@ -351,13 +359,13 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC __HAL_LOCK(hdac); /* Store configuration */ - oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel)); + oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL))); /* Disable the selected DAC channel */ - CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel)); + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); /* Set mode in MCR for calibration */ - MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0); + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); /* Set DAC Channel1 DHR register to the middle value */ tmp = (uint32_t)hdac->Instance; @@ -379,26 +387,26 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); #endif /* STM32L451xx STM32L452xx STM32L462xx */ - *(__IO uint32_t *) tmp = 0x0800; + *(__IO uint32_t *) tmp = 0x0800U; /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ - SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel)); + SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16; - delta = 8; - while (delta != 0) + trimmingvalue = 16U; + delta = 8U; + while (delta != 0U) { /* Set candidate trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ HAL_Delay(1); - if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */ trimmingvalue -= delta; @@ -408,35 +416,35 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ trimmingvalue += delta; } - delta >>= 1; + delta >>= 1U; } /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ /* Set candidate trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); + HAL_Delay(1U); - if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { /* OPAMP_CSR_OUTCAL is actually one value more */ trimmingvalue++; /* Set right trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } /* Disable the selected DAC channel calibration */ /* i.e. clear DAC_CR_CENx bit */ - CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel)); + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); sConfig->DAC_TrimmingValue = trimmingvalue; sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; /* Restore configuration */ - MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration); + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); /* Process unlocked */ __HAL_UNLOCK(hdac); @@ -447,14 +455,14 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC /** * @brief Set the trimming mode and trimming value (user trimming mode applied). - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure updated with new DAC trimming value. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure updated with new DAC trimming value. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param NewTrimmingValue: DAC new trimming value + * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ @@ -477,7 +485,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe __HAL_LOCK(hdac); /* Set new trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); /* Update trimming mode */ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; @@ -491,8 +499,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /** * @brief Return the DAC trimming value. - * @param hdac : DAC handle - * @param Channel: The selected DAC channel. + * @param hdac DAC handle + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -502,23 +510,11 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) { - uint32_t trimmingvalue = 0; - - /* Check the DAC handle allocation */ - /* And not in Reset state */ - if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET)) - { - return HAL_ERROR; - } - else - { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(Channel)); /* Retrieve trimming */ - trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel); - } - return trimmingvalue; + return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); } /** @@ -537,7 +533,6 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. (+) Set the specified data holding register value for DAC channel. @endverbatim @@ -546,17 +541,17 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) /** * @brief Return the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp |= hdac->Instance->DOR1; - tmp |= hdac->Instance->DOR2 << 16; + tmp |= hdac->Instance->DOR2 << 16U; /* Returns the DAC channel data output register value */ return tmp; @@ -586,7 +581,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -598,32 +593,31 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) hdac->ConvCpltCallbackCh2(hdac); #else HAL_DACEx_ConvCpltCallbackCh2(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State= HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh2(hdac); #else HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -638,7 +632,8 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) hdac->ErrorCallbackCh2(hdac); #else HAL_DACEx_ErrorCallbackCh2(hdac); -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + hdac->State= HAL_DAC_STATE_READY; } @@ -649,12 +644,14 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#endif /* HAL_DAC_MODULE_ENABLED */ - /** * @} */ +#endif /* DAC1 */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c index c4c1734b24..327c672f4c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c @@ -202,17 +202,13 @@ * @} */ -#define NPRIME 16 +#define NPRIME 16U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -uint32_t PrimeArray[NPRIME] = { 1, 2, 3, 5, - 7, 11, 13, 17, - 19, 23, 29, 31, - 37, 41, 43, 47}; /* Private function prototypes -----------------------------------------------*/ /** @addtogroup DCMI_Private_Functions DCMI Private Functions * @{ @@ -486,7 +482,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { - uint32_t circular_copy_length = 0; + uint32_t circular_copy_length; /* Check capture parameter */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); @@ -509,7 +505,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Set the dma abort callback */ hdcmi->DMA_Handle->XferAbortCallback = NULL; - if(Length <= 0xFFFF) + if(Length <= 0xFFFFU) { hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */ @@ -543,7 +539,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo circular_copy_length = DCMI_TransferSize(Length); /* Check if issue in intermediate length computation */ - if (circular_copy_length == 0) + if (circular_copy_length == 0U) { /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; @@ -555,9 +551,9 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo } /* Store the number of half - intermediate buffer copies needed */ - hdcmi->XferCount = 2 * ((Length / circular_copy_length) - 1); + hdcmi->XferCount = 2U * ((Length / circular_copy_length) - 1U); /* Store the half-buffer copy length */ - hdcmi->HalfCopyLength = circular_copy_length / 2; + hdcmi->HalfCopyLength = circular_copy_length / 2U; /* DCMI DR samples in circular mode will be copied at the end of the final buffer. @@ -566,7 +562,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo hdcmi->pCircularBuffer = pData; /* Update pCircularBuffer in "moving" at the end of the final buffer, don't forger to convert in bytes to compute exact address */ - hdcmi->pCircularBuffer += 4 * (((Length / circular_copy_length) - 1) * circular_copy_length); + hdcmi->pCircularBuffer += 4U * (((Length / circular_copy_length) - 1U) * circular_copy_length); /* Initiate the circular DMA transfer from DCMI IP to final buffer end */ if ( HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)hdcmi->pCircularBuffer, circular_copy_length) != HAL_OK) @@ -602,7 +598,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) { - uint32_t tickstart = 0; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -618,7 +614,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) tickstart = HAL_GetTick(); /* Check if the DCMI capture is effectively disabled */ - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) { @@ -631,7 +627,10 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) } /* Disable the DMA */ - HAL_DMA_Abort(hdcmi->DMA_Handle); + if (HAL_DMA_Abort(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } /* Disable DCMI IP */ __HAL_DCMI_DISABLE(hdcmi); @@ -654,7 +653,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) */ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Process locked */ __HAL_LOCK(hdcmi); @@ -671,7 +670,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) tickstart = HAL_GetTick(); /* Check if the DCMI capture is effectively disabled */ - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) { @@ -733,7 +732,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) uint32_t misflags = READ_REG(hdcmi->Instance->MISR); /* Synchronization error interrupt management *******************************/ - if ((misflags & DCMI_MIS_ERR_MIS) != RESET) + if ((misflags & DCMI_MIS_ERR_MIS) != 0x0U) { /* Clear the Synchronization error flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); @@ -743,7 +742,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) } /* Overflow interrupt management ********************************************/ - if ((misflags & DCMI_MIS_OVR_MIS) != RESET) + if ((misflags & DCMI_MIS_OVR_MIS) != 0x0U) { /* Clear the Overflow flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); @@ -761,11 +760,14 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); + if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } } /* Line Interrupt management ************************************************/ - if ((misflags & DCMI_MIS_LINE_MIS) != RESET) + if ((misflags & DCMI_MIS_LINE_MIS) != 0x0U) { /* Clear the Line interrupt flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); @@ -780,7 +782,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) } /* VSYNC interrupt management ***********************************************/ - if ((misflags & DCMI_MIS_VSYNC_MIS) != RESET) + if ((misflags & DCMI_MIS_VSYNC_MIS) != 0x0U) { /* Clear the VSYNC flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); @@ -795,7 +797,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) } /* End of Frame interrupt management ****************************************/ - if ((misflags & DCMI_MIS_FRAME_MIS) != RESET) + if ((misflags & DCMI_MIS_FRAME_MIS) != 0x0U) { /* Disable the Line interrupt when using snapshot mode */ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) @@ -1080,7 +1082,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) * @brief DCMI Callback registering * @param hdcmi dcmi handle * @param CallbackID dcmi Callback ID - * @param pCallback pointer to dcmi Callback function + * @param hdcmi pointer to dcmi Callback function * @retval status */ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback) @@ -1261,14 +1263,15 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM */ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { - uint32_t loop_length = 0; /* transfer length */ - uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; + uint32_t loop_length; /* transfer length */ + uint32_t * tmpBuffer_Dest; + uint32_t * tmpBuffer_Orig; + uint32_t temp; DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if(hdcmi->XferCount != 0) + if(hdcmi->XferCount != 0U) { /* Manage second half buffer copy in case of big transfer */ @@ -1280,13 +1283,15 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) /* Point at DCMI circular buffer mid-location */ tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; - tmpBuffer_Orig += hdcmi->HalfCopyLength; + temp = (uint32_t) (tmpBuffer_Orig); + temp += hdcmi->HalfCopyLength; + tmpBuffer_Orig = (uint32_t *) temp; /* copy half the buffer size */ loop_length = hdcmi->HalfCopyLength; /* Save next entry to write at next half DMA transfer interruption */ - hdcmi->pBuffPtr += (uint32_t) loop_length*4; + hdcmi->pBuffPtr += (uint32_t) loop_length*4U; hdcmi->XferSize -= hdcmi->HalfCopyLength; /* Data copy from work buffer to final destination buffer */ @@ -1314,10 +1319,10 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) else { /* if End of frame IT is disabled */ - if((hdcmi->Instance->IER & DCMI_IT_FRAME) == RESET) + if((hdcmi->Instance->IER & DCMI_IT_FRAME) == 0x0U) { /* If End of Frame flag is set */ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET) + if(__HAL_DCMI_GET_FLAG(hdcmi, (uint32_t)DCMI_FLAG_FRAMERI) != 0x0UL) { /* Clear the End of Frame flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); @@ -1359,13 +1364,13 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) */ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) { - uint32_t loop_length = 0; /* transfer length */ - uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; + uint32_t loop_length; /* transfer length */ + uint32_t * tmpBuffer_Dest; + uint32_t * tmpBuffer_Orig; DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if(hdcmi->XferCount != 0) + if(hdcmi->XferCount != 0U) { /* Manage first half buffer copy in case of big transfer */ @@ -1382,7 +1387,7 @@ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) loop_length = hdcmi->HalfCopyLength; /* Save next entry to write at next DMA transfer interruption */ - hdcmi->pBuffPtr += (uint32_t) loop_length*4; + hdcmi->pBuffPtr += (uint32_t) loop_length*4U; hdcmi->XferSize -= hdcmi->HalfCopyLength; /* Data copy from work buffer to final destination buffer */ @@ -1453,6 +1458,10 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) uint32_t temp = InputSize; uint32_t aPrime[NPRIME] = {0}; uint32_t output = 2; /* Want a result which is an even number */ + uint32_t PrimeArray[NPRIME] = { 1UL, 2UL, 3UL, 5UL, + 7UL, 11UL, 13UL, 17UL, + 19UL, 23UL, 29UL, 31UL, + 37UL, 41UL, 43UL, 47UL}; /* Develop InputSize in product of prime numbers */ @@ -1463,7 +1472,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) { break; } - while ((temp % PrimeArray[j]) == 0) + while ((temp % PrimeArray[j]) == 0U) { aPrime[j]++; temp /= PrimeArray[j]; @@ -1472,16 +1481,16 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) } /* Search for the biggest even divisor less or equal to 0xFFFE = 65534 */ - aPrime[1] -= 1; /* output is initialized to 2, so don't count dividor 2 twice */ + aPrime[1] -= 1U; /* output is initialized to 2, so don't count dividor 2 twice */ /* The algorithm below yields a sub-optimal solution but in an acceptable time. */ - j = NPRIME-1; - while ((j > 0) && (output <= 0xFFFE)) + j = NPRIME-1U; + while ((j > 0U) && (output <= 0xFFFEU)) { - while (aPrime[j] >0) + while (aPrime[j] > 0U) { - if (output * PrimeArray[j] > 0xFFFE) + if ((output * PrimeArray[j]) > 0xFFFEU) { break; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c index 1179234ee6..7c8d9d97f5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c @@ -241,7 +241,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Reset Request generator parameters if any */ - if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - + hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; @@ -1115,9 +1115,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t #if defined(DMAMUX1) /** - * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) @@ -1145,7 +1145,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) /** * @brief Updates the DMA handle with the DMAMUX request generator params * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Channel. * @retval None */ @@ -1160,7 +1160,6 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); - } #endif /* DMAMUX1 */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c index 586d786124..2e9433536a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c @@ -133,8 +133,8 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy MODIFY_REG( hdma->DMAmuxChannel->CCR, \ (~DMAMUX_CxCR_DMAREQ_ID) , \ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ - pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ - (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); /* Process UnLocked */ __HAL_UNLOCK(hdma); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c new file mode 100644 index 0000000000..f22844aa69 --- /dev/null +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c @@ -0,0 +1,659 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between MCU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between MCU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending register address */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c index 415fd0a36d..2ce9e3996d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c @@ -135,24 +135,24 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) /* Check Firewall configuration addresses and lengths when segment is protected */ /* Code segment */ - if (fw_init->CodeSegmentLength != 0) + if (fw_init->CodeSegmentLength != 0U) { assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); /* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */ - if (fw_init->NonVDataSegmentLength < 0x100) + if (fw_init->NonVDataSegmentLength < 0x100U) { return HAL_ERROR; } } /* Non volatile data segment */ - if (fw_init->NonVDataSegmentLength != 0) + if (fw_init->NonVDataSegmentLength != 0U) { assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); } /* Volatile data segment */ - if (fw_init->VDataSegmentLength != 0) + if (fw_init->VDataSegmentLength != 0U) { assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c index 4947e050ae..47c39948d0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c @@ -382,7 +382,7 @@ void HAL_FLASH_IRQHandler(void) } else { - /* Nothing to do */ + HAL_FLASH_OperationErrorCallback(0U); } /*Stop the procedure ongoing*/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c index 01826406ff..b027cec1f0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c @@ -952,8 +952,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_mask |= FLASH_OPTR_SRAM2_RST; } -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ + defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((UserType & OB_USER_nSWBOOT0) != 0U) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c index dc41e5133e..849b40cabc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c @@ -74,7 +74,7 @@ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). @@ -129,6 +129,12 @@ * @brief GPIO HAL module driver * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ #ifdef HAL_GPIO_MODULE_ENABLED @@ -137,28 +143,21 @@ /** @defgroup GPIO_Private_Defines GPIO Private Defines * @{ */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define ANALOG_MODE ((uint32_t)0x00000008) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) - -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_MODE (0x00000003u) +#define ANALOG_MODE (0x00000008u) +#define EXTI_MODE (0x10000000u) +#define GPIO_MODE_IT (0x00010000u) +#define GPIO_MODE_EVT (0x00020000u) +#define RISING_EDGE (0x00100000u) +#define FALLING_EDGE (0x00200000u) +#define GPIO_OUTPUT_TYPE (0x00000010u) + +#define GPIO_NUMBER (16u) /** * @} */ - -/* Private macros ------------------------------------------------------------*/ + /* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -/** - * @} - */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -167,7 +166,7 @@ * @{ */ -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -188,9 +187,9 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -199,12 +198,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) + while (((GPIO_Init->Pin) >> position) != 0x00u) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); + iocurrent = (GPIO_Init->Pin) & (1uL << position); - if(iocurrent) + if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ @@ -213,18 +212,18 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - + /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ @@ -235,14 +234,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); GPIOx->OTYPER = temp; } @@ -262,8 +261,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ @@ -273,14 +272,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; + temp = SYSCFG->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + SYSCFG->EXTICR[position >> 2u] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { temp |= iocurrent; @@ -288,7 +287,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->IMR1 = temp; temp = EXTI->EMR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { temp |= iocurrent; @@ -297,7 +296,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { temp |= iocurrent; @@ -305,7 +304,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->RTSR1 = temp; temp = EXTI->FTSR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { temp |= iocurrent; @@ -313,7 +312,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->FTSR1 = temp; } } - + position++; } } @@ -322,70 +321,68 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) + while ((GPIO_Pin >> position) != 0x00u) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1U << position); + iocurrent = (GPIO_Pin) & (1uL << position); - if (iocurrent) + if (iocurrent != 0x00u) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2)); + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - /* Deactivate the Control bit of Analog mode for the current IO */ GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position); - #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + + tmp = SYSCFG->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (4u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~((uint32_t)iocurrent); - EXTI->EMR1 &= ~((uint32_t)iocurrent); + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~((uint32_t)iocurrent); - EXTI->FTSR1 &= ~((uint32_t)iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); } } - + position++; } } @@ -394,7 +391,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim @@ -410,7 +407,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @brief Read the specified input port pin. * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -420,7 +417,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) { bitstatus = GPIO_PIN_SET; } @@ -438,10 +435,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -465,8 +462,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the pin to be toggled. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -483,8 +480,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bits to be locked. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -507,7 +504,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Read LCKK bit*/ tmp = GPIOx->LCKR; - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; } @@ -519,13 +516,13 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c index f2e95930af..2b67912e35 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c @@ -66,14 +66,12 @@ well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). - (+++) HMAC processing (requires to resort to extended functions): after initialization, the key and the first input buffer are entered in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and @@ -184,19 +182,19 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_HASH_MODULE_ENABLED - -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (HASH) /** @defgroup HASH HASH * @brief HASH HAL module driver. * @{ */ +#ifdef HAL_HASH_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup HASH_Private_Constants HASH Private Constants @@ -206,8 +204,8 @@ /** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status * @{ */ -#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */ -#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register */ +#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */ +#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */ /** * @} */ @@ -215,7 +213,7 @@ /** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers * @{ */ -#define HASH_NUMBER_OF_CSR_REGISTERS 54 /*!< Number of Context Swap Registers */ +#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */ /** * @} */ @@ -223,7 +221,7 @@ /** @defgroup HASH_TimeOut_Value HASH TimeOut Value * @{ */ -#define HASH_TIMEOUTVALUE 1000 /*!< Time-out value */ +#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */ /** * @} */ @@ -231,7 +229,7 @@ /** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit * @{ */ -#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */ +#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */ /** * @} */ @@ -353,9 +351,10 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Set phase to READY */ hhash->Phase = HAL_HASH_PHASE_READY; - /* Set the data type and reset MDMAT bit */ - MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType); - + /* Set the data type bit */ + MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); + /* Reset MDMAT bit */ +__HAL_HASH_RESET_MDMAT(); /* Reset HASH handle status */ hhash->Status = HAL_OK; @@ -907,13 +906,11 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) [..] When resorting to DMA mode to enter the data in the IP, user must resort to HAL_HASH_xxx_Start_DMA() then read the resulting digest with HAL_HASH_xxx_Finish(). - [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally retrieved thanks to HAL_HASH_xxx_Finish(). - @endverbatim * @{ */ @@ -1251,26 +1248,26 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i = 0; + uint32_t i; /* Prevent unused argument(s) compilation warning */ UNUSED(hhash); /* Save IMR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI); - mem_ptr+=4; + mem_ptr+=4U; /* Save STR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW); - mem_ptr+=4; + mem_ptr+=4U; /* Save CR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT); - mem_ptr+=4; + mem_ptr+=4U; /* By default, save all CSRs registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) { *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr); - mem_ptr+=4; - csr_ptr+=4; + mem_ptr+=4U; + csr_ptr+=4U; } } @@ -1291,31 +1288,31 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i = 0; + uint32_t i; /* Prevent unused argument(s) compilation warning */ UNUSED(hhash); /* Restore IMR register content */ WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; + mem_ptr+=4U; /* Restore STR register content */ WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; + mem_ptr+=4U; /* Restore CR register content */ WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; + mem_ptr+=4U; /* Reset the HASH processor before restoring the Context Swap Registers (CSR) */ __HAL_HASH_INIT(); /* By default, restore all CSR registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) { WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; - csr_ptr+=4; + mem_ptr+=4U; + csr_ptr+=4U; } } @@ -1347,9 +1344,9 @@ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) */ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { - uint32_t tmp_remaining_DMATransferSize_inWords = 0x0; - uint32_t tmp_initial_DMATransferSize_inWords = 0x0; - uint32_t tmp_words_already_pushed = 0x0; + uint32_t tmp_remaining_DMATransferSize_inWords; + uint32_t tmp_initial_DMATransferSize_inWords; + uint32_t tmp_words_already_pushed; if (hhash->State == HAL_HASH_STATE_READY) { @@ -1359,7 +1356,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { /* Make sure there is enough time to suspend the processing */ - tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR; if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) { /* No suspension attempted since almost to the end of the transferred data. */ @@ -1385,7 +1382,16 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) } /* Disable DMA channel */ - HAL_DMA_Abort(hhash->hdmain); + /* + Note that the Abort function will + - clear the transfer error flags + - unlock + - set the State + */ + if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) + { + return HAL_ERROR; + } /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); @@ -1402,9 +1408,9 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* At this point, DMA interface is disabled and no transfer is on-going */ /* Retrieve from the DMA handle how many words remain to be written */ - tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR; - if (tmp_remaining_DMATransferSize_inWords == 0) + if (tmp_remaining_DMATransferSize_inWords == 0U) { /* All the DMA transfer is actually done. Suspension occurred at the very end of the transfer. Either the digest computation is about to start (HASH case) @@ -1421,23 +1427,23 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { /* Compute how many words were supposed to be transferred by DMA */ - tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ? (hhash->HashInCount+3)/4: hhash->HashInCount/4); + tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U)); /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported by HASH IP, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before the start of DMA transfer (multi-buffer processing case) */ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; - if ((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16 != HASH_NBW_PUSHED()) + if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED()) { tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ - hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; + hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; /* And store in HashInCount the remaining size to transfer (in bytes) */ - hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords; + hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords; } @@ -1482,118 +1488,130 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) { HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t inputaddr = 0x0; - uint32_t buffersize = 0x0; - + uint32_t inputaddr; + uint32_t buffersize; + HAL_StatusTypeDef status ; + if (hhash->State != HAL_HASH_STATE_SUSPENDED) { - - /* Disable the DMA transfer */ - CLEAR_BIT(HASH->CR, HASH_CR_DMAE); - - if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET) - { - /* If no HMAC processing, input data transfer is now over */ - - /* Change the HASH state to ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - } - else - { - /* HMAC processing: depending on the current HMAC step and whether or - not multi-buffer processing is on-going, the next step is initiated - and MDMAT bit is set. */ - - - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) - { - /* This is the end of HMAC processing */ - + + /* Disable the DMA transfer */ + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); + + if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U) + { + /* If no HMAC processing, input data transfer is now over */ + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back - (note that the last DMA transfer was that of the key - for the outer HASH operation). */ + + /* Call Input data transfer complete call back */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) hhash->InCpltCallback(hhash); #else HAL_HASH_InCpltCallback(hhash); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - return; + } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) - { - inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ - buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ - - /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ - hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ - - hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ - - /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ - if (hhash->DigestCalculationDisable != RESET) - { - /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, - no digest calculation will be triggered at the end of the input buffer feeding to the IP */ - __HAL_HASH_SET_MDMAT(); - } - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) + else { - if (hhash->DigestCalculationDisable != RESET) + /* HMAC processing: depending on the current HMAC step and whether or + not multi-buffer processing is on-going, the next step is initiated + and MDMAT bit is set. */ + + + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) { - /* No automatic move to Step 3 as a new message buffer will be fed to the IP - (case of multi-buffer HMAC processing): - DCAL must not be set. - Phase remains in Step 2, MDMAT remains set at this point. - Change the HASH state to ready and call Input data transfer complete call back. */ + /* This is the end of HMAC processing */ + + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; + + /* Call Input data transfer complete call back + (note that the last DMA transfer was that of the key + for the outer HASH operation). */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) hhash->InCpltCallback(hhash); #else HAL_HASH_InCpltCallback(hhash); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - return ; + + return; } - else + else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { - /* Digest calculation is not disabled (case of single buffer input or last buffer - of multi-buffer HMAC processing) */ - inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ - buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ + inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ + buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ + /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ - - hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ + hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ + hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ + + hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ + /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ + if (hhash->DigestCalculationDisable != RESET) + { + /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, + no digest calculation will be triggered at the end of the input buffer feeding to the IP */ + __HAL_HASH_SET_MDMAT(); + } } - } + else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/ + { + if (hhash->DigestCalculationDisable != RESET) + { + /* No automatic move to Step 3 as a new message buffer will be fed to the IP + (case of multi-buffer HMAC processing): + DCAL must not be set. + Phase remains in Step 2, MDMAT remains set at this point. + Change the HASH state to ready and call Input data transfer complete call back. */ + hhash->State = HAL_HASH_STATE_READY; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return ; + } + else + { + /* Digest calculation is not disabled (case of single buffer input or last buffer + of multi-buffer HMAC processing) */ + inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ + buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ + /* In case of suspension request, save the new starting parameters */ + hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ + + hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ + } + } + /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(buffersize); - /* Set the HASH DMA transfert completion call back */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4)); + + /* Enable the DMA In DMA Stream */ + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize%4U)!=0U) ? ((buffersize+3U)/4U):(buffersize/4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); + + /* Return function status */ + if (status != HAL_OK) + { + /* Update DAC state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; + } + else + { + /* Change DAC state */ + hhash->State = HAL_HASH_STATE_READY; + } } } @@ -1646,15 +1664,15 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; - for(buffercounter = 0; buffercounter < Size; buffercounter+=4) + for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; + inputaddr+=4U; /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size)) { /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free in the input buffer */ @@ -1670,14 +1688,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter + 4); + hhash->HashInCount = Size - (buffercounter + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4); + hhash->HashKeyCount = Size - (buffercounter + 4U); } else { @@ -1714,54 +1732,54 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /* Read the message digest */ case 16: /* MD5 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); break; case 20: /* SHA1 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); break; case 28: /* SHA224 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); break; case 32: /* SHA256 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); break; default: @@ -1791,7 +1809,7 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1813,7 +1831,7 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1846,7 +1864,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (hhash->State == HAL_HASH_STATE_BUSY) { /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ - if(hhash->HashITCounter == 0) + if(hhash->HashITCounter == 0U) { /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); @@ -1855,18 +1873,18 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - else if (hhash->HashITCounter == 1) + else if (hhash->HashITCounter == 1U) { /* This is the first call to HASH_IT, the first input data are about to be entered in the IP. A specific processing is carried out at this point to start-up the processing. */ - hhash->HashITCounter = 2; + hhash->HashITCounter = 2U; } else { /* Cruise speed reached, HashITCounter remains equal to 3 until the end of the HASH processing or the end of the current step for HMAC processing. */ - hhash->HashITCounter = 3; + hhash->HashITCounter = 3U; } /* If digest is ready */ @@ -1895,7 +1913,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (hhash->HashInCount != 0)) + if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) { /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); @@ -1955,6 +1973,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } + else + { + /* Nothing to do */ + } } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/ @@ -1982,34 +2004,33 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; /* If there are more than 64 bytes remaining to be entered */ - if(hhash->HashInCount > 64) + if(hhash->HashInCount > 64U) { inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Write the Input block in the Data IN register (16 32-bit words, or 64 bytes are entered) */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) + for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U) { HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; + inputaddr+=4U; } /* If this is the start of input data entering, an additional word must be entered to start up the HASH processing */ - if(hhash->HashITCounter == 2) + if(hhash->HashITCounter == 2U) { HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; - if(hhash->HashInCount >= 68) + if(hhash->HashInCount >= 68U) { /* There are still data waiting to be entered in the IP. Decrement buffer counter and set pointer to the proper memory location for the next data entering round. */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; + hhash->HashInCount -= 68U; + hhash->pHashInBuffPtr+= 68U; } else { /* All the input buffer has been fed to the HW. */ - hhash->HashInCount = 0; + hhash->HashInCount = 0U; } } else @@ -2017,8 +2038,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /* 64 bytes have been entered and there are still some remaining: Decrement buffer counter and set pointer to the proper memory location for the next data entering round.*/ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; + hhash->HashInCount -= 64U; + hhash->pHashInBuffPtr+= 64U; } } else @@ -2034,10 +2055,10 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI); /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < (inputcounter+3)/4; buffercounter++) + for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++) { HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4; + inputaddr+=4U; } /* Start the Digest calculation */ __HAL_HASH_START_DIGEST(); @@ -2083,7 +2104,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); + if (hhash->Status != HAL_OK) { return hhash->Status; } @@ -2124,7 +2146,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount); + if (hhash->Status != HAL_OK) { return hhash->Status; } @@ -2170,7 +2193,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); + if (hhash->Status != HAL_OK) { return hhash->Status; } @@ -2224,112 +2248,115 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */ + uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* Initiate HASH processing in case of start or resumption */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Check if initialization phase has not been already performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - } - else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) - { - /* if the IP has already been initialized, two cases are possible */ - - /* Process resumption time ... */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Check if initialization phase has not been already performed */ + if(hhash->Phase == HAL_HASH_PHASE_READY) { - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(Size); + + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) + { + /* if the IP has already been initialized, two cases are possible */ + + /* Process resumption time ... */ + if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; - Size_tmp = hhash->HashInCount; + pInBuffer_tmp = hhash->pHashInBuffPtr; + Size_tmp = hhash->HashInCount; + } + /* ... or multi-buffer HASH processing end */ + else + { + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; + Size_tmp = Size; + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(Size); + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; } - /* ... or multi-buffer HASH processing end */ else { - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; - Size_tmp = Size; - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); + /* Phase error */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_ERROR; } - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - } - else - { - /* Phase error */ - hhash->State = HAL_HASH_STATE_READY; - + + + /* Write input buffer in Data register */ + hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); + if (hhash->Status != HAL_OK) + { + return hhash->Status; + } + + /* If the process has not been suspended, carry on to digest calculation */ + if (hhash->State != HAL_HASH_STATE_SUSPENDED) + { + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + + /* Wait for DCIS flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read the message digest */ + HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + } + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_ERROR; - } - - - /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) - { - return hhash->Status; - } - - /* If the process has not been suspended, carry on to digest calculation */ - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - + return HAL_OK; + } else { @@ -2354,17 +2381,17 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */ - + uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* Make sure the input buffer size (in bytes) is a multiple of 4 */ assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size)); - /* Initiate HASH processing in case of start or resumption */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0)) + if ((pInBuffer == NULL) || (Size == 0U)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2409,7 +2436,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, } /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); + if (hhash->Status != HAL_OK) { return hhash->Status; } @@ -2450,12 +2478,13 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, */ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) { + HAL_HASH_StateTypeDef State_tmp = hhash->State; /* If State is ready or suspended, start or resume IT-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2530,17 +2559,20 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; - uint32_t inputSize = 0x0; + uint32_t inputSize; + HAL_StatusTypeDef status ; + HAL_HASH_StateTypeDef State_tmp = hhash->State; +#if defined (HASH_CR_MDMAT) /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - - /* If State is ready or suspended, start or resume DMA-based HASH processing */ - if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +#endif /* MDMA defined*/ + /* If State is ready or suspended, start or resume polling-based HASH processing */ +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ( (pInBuffer == NULL ) || (Size == 0) || + if ( (pInBuffer == NULL ) || (Size == 0U) || /* Check phase coherency. Phase must be either READY (fresh start) or PROCESS (multi-buffer HASH management) */ @@ -2607,22 +2639,32 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); - + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize%4U)!=0U) ? ((inputSize+3U)/4U):(inputSize/4U))); + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; + if (status != HAL_OK) + { + /* Update HASH state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; + } + else + { + /* Change HASH state */ + hhash->State = HAL_HASH_STATE_READY; + } + + return status; } else { return HAL_BUSY; - } - + } } /** @@ -2693,12 +2735,13 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui */ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - - /* If State is ready or suspended, start or resume polling-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { + HAL_HASH_StateTypeDef State_tmp = hhash->State; + + /* If State is ready or suspended, start or resume polling-based HASH processing */ +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2714,7 +2757,7 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } @@ -2762,11 +2805,13 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint */ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) { + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* If State is ready or suspended, start or resume IT-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2785,7 +2830,7 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } @@ -2868,17 +2913,17 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; - uint32_t inputSize = 0x0; - + uint32_t inputSize; + HAL_StatusTypeDef status ; + HAL_HASH_StateTypeDef State_tmp = hhash->State; /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); - /* If State is ready or suspended, start or resume DMA-based HASH processing */ - if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) - { +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { /* Check input parameters */ - if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) || + if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) || /* Check phase coherency. Phase must be either READY (fresh start) or one of HMAC PROCESS steps (multi-buffer HASH management) */ @@ -2900,10 +2945,9 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. At the same time, ensure MDMAT bit is cleared. */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } @@ -2911,7 +2955,6 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, { MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } - /* Store input aparameters in handle fields to manage steps transition or possible HMAC suspension/resumption */ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ @@ -2950,7 +2993,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, if (hhash->DigestCalculationDisable == RESET) { /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ - __HAL_HASH_RESET_MDMAT(); + __HAL_HASH_RESET_MDMAT(); __HAL_HASH_SET_NBVALIDBITS(inputSize); } } @@ -2987,15 +3030,26 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+3U)/4U):(inputSize/4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; + if (status != HAL_OK) + { + /* Update HASH state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; + } + else + { + /* Change HASH state */ + hhash->State = HAL_HASH_STATE_READY; + } + /* Return function status */ + return status; } else { @@ -3006,16 +3060,16 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ +#endif /* HAL_HASH_MODULE_ENABLED */ + /** * @} */ - +#endif /* HASH*/ /** * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ -#endif /* HAL_HASH_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c index 9a49ff1de3..3842e07929 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c @@ -95,28 +95,28 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (HASH) /** @defgroup HASHEx HASHEx * @brief HASH HAL extended module driver. * @{ */ - +#ifdef HAL_HASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (HASH_CR_MDMAT) /** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions * @{ */ - /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode * @brief HASH extended processing functions using polling mode. * @@ -599,6 +599,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t (++) HAL_HMACEx_SHA1_Step1_2_DMA() (++) HAL_HMACEx_SHA1_Step2_DMA() (++) HAL_HMACEx_SHA1_Step2_3_DMA() + (+) SHA256 (++) HAL_HMACEx_SHA224_Step1_2_DMA() (++) HAL_HMACEx_SHA224_Step2_DMA() @@ -912,21 +913,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ - +#endif /* MDMA defined*/ /** * @} */ +#endif /* HAL_HASH_MODULE_ENABLED */ /** * @} */ - +#endif /* HASH*/ /** * @} */ -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ -#endif /* HAL_HASH_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c index 5b205dabdb..e648e26700 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c @@ -73,15 +73,15 @@ * @{ */ +#ifdef HAL_HCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + /** @defgroup HCD HCD * @brief HCD HAL module driver * @{ */ -#ifdef HAL_HCD_MODULE_ENABLED - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c index 830eacd17d..0dd646d8c1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c @@ -356,14 +356,14 @@ #define SlaveAddr_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ @@ -382,10 +382,6 @@ */ /* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ? \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) - /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -491,7 +487,6 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Check the I2C handle allocation */ if (hi2c == NULL) { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -601,7 +596,6 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* Check the I2C handle allocation */ if (hi2c == NULL) { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -1110,12 +1104,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1126,7 +1120,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA return HAL_ERROR; } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; @@ -1141,12 +1139,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -1220,12 +1218,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1237,7 +1235,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; @@ -1252,12 +1254,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -1372,7 +1374,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } @@ -1491,7 +1497,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } @@ -1499,7 +1509,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } @@ -1586,7 +1600,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1655,7 +1669,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1788,7 +1802,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1857,7 +1871,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1896,7 +1910,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1931,7 +1945,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -2000,7 +2014,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2039,7 +2053,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2071,7 +2085,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -2174,7 +2188,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -2326,12 +2340,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } do @@ -2343,7 +2357,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; @@ -2358,12 +2376,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } @@ -2458,12 +2476,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } do @@ -2475,7 +2493,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; @@ -2490,12 +2512,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -2596,7 +2618,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2687,7 +2709,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2724,7 +2746,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { uint32_t tickstart; uint32_t xfermode; - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2812,7 +2834,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2868,7 +2890,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { uint32_t tickstart; uint32_t xfermode; - uint32_t dmaxferstatus; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2954,7 +2976,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3009,7 +3031,10 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { uint32_t tickstart; - __IO uint32_t I2C_Trials = 0U; + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -3032,7 +3057,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) { if (Timeout != HAL_MAX_DELAY) { @@ -3050,6 +3079,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_ERROR; } } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); } /* Check if the NACKF flag has not been set */ @@ -3088,7 +3120,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) + if (I2C_Trials == Trials) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3102,6 +3134,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } + + /* Increment Trials */ + I2C_Trials++; } while (I2C_Trials < Trials); @@ -3171,7 +3206,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3188,7 +3223,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3222,6 +3257,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3255,7 +3291,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3286,7 +3322,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -3303,23 +3339,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c return HAL_ERROR; } - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { @@ -3328,7 +3381,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3399,7 +3452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3416,7 +3469,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, } /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3450,6 +3503,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3483,7 +3537,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(hi2c->XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3514,7 +3568,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { @@ -3531,23 +3585,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, return HAL_ERROR; } - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { @@ -3556,7 +3627,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3593,7 +3664,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -3615,10 +3686,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmarx); + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } } } @@ -3672,10 +3756,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, */ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + HAL_StatusTypeDef dmaxferstatus; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -3696,22 +3782,52 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmarx); + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } } } else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } } } + else + { + /* Nothing to do */ + } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; @@ -3740,8 +3856,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3755,7 +3888,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3805,7 +3938,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -3826,11 +3959,24 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } } } @@ -3884,10 +4030,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + HAL_StatusTypeDef dmaxferstatus; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { @@ -3908,22 +4056,52 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmatx); + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } } } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - HAL_DMA_Abort_IT(hi2c->hdmarx); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } } } + else + { + /* Nothing to do */ + } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; @@ -3952,8 +4130,25 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3967,7 +4162,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4138,9 +4333,10 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4149,7 +4345,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4158,7 +4354,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4166,10 +4362,13 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); } + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { - I2C_ITError(hi2c, hi2c->ErrorCode); + I2C_ITError(hi2c, tmperror); } } @@ -4416,7 +4615,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4429,41 +4628,49 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -4483,7 +4690,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4514,7 +4721,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -4536,10 +4743,12 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint32_t tmpoptions = hi2c->XferOptions; + /* Process locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4547,13 +4756,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4579,30 +4787,40 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } } } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); } } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -4611,13 +4829,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint if (hi2c->XferCount > 0U) { /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; } else { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -4631,7 +4853,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -4659,7 +4881,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4675,7 +4897,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -4683,7 +4905,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui if (hi2c->XferCount != 0U) { /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -4705,7 +4927,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -4736,7 +4958,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4762,7 +4984,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -4788,27 +5010,47 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + /* Process locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) { - if (((hi2c->hdmarx != NULL) || (hi2c->hdmatx != NULL)) && (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)) + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + + if (treatdmanack == 1U) { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4834,6 +5076,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } } } else @@ -4842,11 +5090,11 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -4876,7 +5124,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) @@ -4929,7 +5177,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) @@ -4985,7 +5233,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -5180,6 +5428,8 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { + uint32_t tmperror; + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -5191,7 +5441,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if ((ITFlags & I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5206,8 +5456,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); @@ -5280,6 +5533,10 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } + else + { + /* Nothing to do */ + } } /** @@ -5290,6 +5547,8 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -5309,20 +5568,33 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { - if ((hi2c->hdmarx != NULL) || (hi2c->hdmatx != NULL)) + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + if (hi2c->hdmarx != NULL) { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); } } + else + { + /* Do nothing */ + } /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; if ((hi2c->XferSize > 0U)) { @@ -5416,10 +5688,13 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; if ((hi2c->XferSize > 0U)) { @@ -5456,6 +5731,8 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -5465,9 +5742,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -5593,7 +5870,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -5641,9 +5918,10 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -5667,7 +5945,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -5715,10 +5993,11 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; - if ((I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -5741,7 +6020,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5758,10 +6037,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ hi2c->hdmatx->XferAbortCallback = NULL; @@ -6131,7 +6407,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; @@ -6143,7 +6419,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c index 41fc911a97..c039aff753 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c @@ -257,17 +257,6 @@ */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup IRDA_Private_Variables IRDA Private Variables - * @{ - */ -#if defined(USART_PRESC_PRESCALER) -static const uint16_t IRDAPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -#else -#endif -/** - * @} - */ - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions * @{ @@ -290,9 +279,9 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} */ @@ -822,13 +811,14 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be sent. - * @param Timeout Specify timeout value. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; - uint32_t tickstart = 0U; + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -849,6 +839,19 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->TxXferSize = Size; hirda->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + while (hirda->TxXferCount > 0U) { hirda->TxXferCount--; @@ -857,15 +860,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u { return HAL_TIMEOUT; } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t *) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2U; + hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; } else { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; } } @@ -894,14 +897,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @param Timeout Specify timeout value. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint16_t uhMask; - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check that a Rx process is not already ongoing */ if (hirda->RxState == HAL_IRDA_STATE_READY) @@ -928,6 +932,18 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui IRDA_MASK_COMPUTATION(hirda); uhMask = hirda->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + /* Check data remaining to be received */ while (hirda->RxXferCount > 0U) { @@ -937,15 +953,15 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui { return HAL_TIMEOUT; } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t *) pData ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData += 2U; + *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask); + pdata16bits++; } else { - *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; } } @@ -1103,19 +1119,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->hdmatx->XferAbortCallback = NULL; /* Enable the IRDA transmit DMA channel */ - HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size); + if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); - /* Clear the TC flag in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->gState to ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1165,22 +1195,36 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size); + if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->RxState to ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1200,21 +1244,25 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - /* Disable the IRDA DMA Tx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the IRDA DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } } - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - /* Disable the IRDA DMA Rx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Disable the IRDA DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } } /* Process Unlocked */ @@ -1274,33 +1322,61 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) the stream and the corresponding call back is executed. */ /* Stop IRDA DMA Tx request if ongoing */ - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel */ - if (hirda->hdmatx != NULL) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { - HAL_DMA_Abort(hirda->hdmatx); - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel */ + if (hirda->hdmatx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } - IRDA_EndTxTransfer(hirda); + IRDA_EndTxTransfer(hirda); + } } /* Stop IRDA DMA Rx request if ongoing */ - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if (hirda->hdmarx != NULL) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { - HAL_DMA_Abort(hirda->hdmarx); - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } + } - IRDA_EndRxTransfer(hirda); + IRDA_EndRxTransfer(hirda); + } } return HAL_OK; @@ -1341,7 +1417,19 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmatx); + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } } } @@ -1357,7 +1445,19 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmarx); + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } } } @@ -1412,7 +1512,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmatx); + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } } } @@ -1460,7 +1572,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmarx); + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; + } + } } } @@ -1798,13 +1922,13 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) + if (errorflags == 0U) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) #else - if (((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { IRDA_Receive_IT(hirda); @@ -1814,16 +1938,16 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* If some errors occur */ cr3its = READ_REG(hirda->Instance->CR3); - if ((errorflags != RESET) - && (((cr3its & USART_CR3_EIE) != RESET) + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) #if defined(USART_CR1_FIFOEN) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) #else - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) #endif { /* IRDA parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); @@ -1831,7 +1955,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); @@ -1839,7 +1963,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); @@ -1847,11 +1971,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != RESET) && + if (((isrflags & USART_ISR_ORE) != 0U) && #if defined(USART_CR1_FIFOEN) - (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) #else - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) #endif { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); @@ -1864,9 +1988,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) #else - if (((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { IRDA_Receive_IT(hirda); @@ -1874,8 +1998,8 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ - if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || + ((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != 0U)) { /* Blocking error : transfer is aborted Set the IRDA state ready to be able to start again the process, @@ -1943,9 +2067,9 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)) #else - if (((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U)) #endif { IRDA_Transmit_IT(hirda); @@ -1953,7 +2077,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { IRDA_EndTransmit_IT(hirda); return; @@ -2121,9 +2245,9 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1 = 0x00U, temp2 = 0x00U; - temp1 = hirda->gState; - temp2 = hirda->RxState; + uint32_t temp1, temp2; + temp1 = (uint32_t)hirda->gState; + temp2 = (uint32_t)hirda->RxState; return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } @@ -2180,9 +2304,12 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000U; - IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; + uint32_t tmpreg; + IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; +#if defined(USART_PRESC_PRESCALER) + const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +#endif /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -2252,12 +2379,11 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) break; case IRDA_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate)); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate)); #endif break; - case IRDA_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2284,7 +2410,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -2341,7 +2467,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) @@ -2526,19 +2652,23 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* Stop IRDA DMA Tx request if ongoing */ - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) - && (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - hirda->TxXferCount = 0U; - IRDA_EndTxTransfer(hirda); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } } /* Stop IRDA DMA Rx request if ongoing */ - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - && (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - hirda->RxXferCount = 0U; - IRDA_EndRxTransfer(hirda); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } } hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; @@ -2731,9 +2861,9 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) * interruptions have been enabled by HAL_IRDA_Transmit_IT(). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { uint16_t *tmp; @@ -2751,30 +2881,23 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /* Enable the IRDA Transmit Complete Interrupt */ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; } else { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t *) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); hirda->pTxBuffPtr += 2U; } else { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU); + hirda->pTxBuffPtr++; } hirda->TxXferCount--; - - return HAL_OK; } } - else - { - return HAL_BUSY; - } } /** @@ -2806,9 +2929,9 @@ static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) * interruptions have been enabled by HAL_IRDA_Receive_IT() * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { uint16_t *tmp; uint16_t uhMask = hirda->Mask; @@ -2820,16 +2943,18 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t *) hirda->pRxBuffPtr ; + tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */ *tmp = (uint16_t)(uhdata & uhMask); hirda->pRxBuffPtr += 2U; } else { - *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + hirda->pRxBuffPtr++; } - if (--hirda->RxXferCount == 0U) + hirda->RxXferCount--; + if (hirda->RxXferCount == 0U) { /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ #if defined(USART_CR1_FIFOEN) @@ -2851,18 +2976,12 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /* Call legacy weak Rx complete callback */ HAL_IRDA_RxCpltCallback(hirda); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - - return HAL_OK; } - - return HAL_OK; } else { /* Clear RXNE interrupt flag */ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - - return HAL_BUSY; } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c index eb2cb4db4c..2cf5b4a5bb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c @@ -197,8 +197,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); - /* Wait for register to be updated */ - while(hiwdg->Instance->SR != RESET) + /* Wait for register to be updated */ + while (hiwdg->Instance->SR != 0x00u) { if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c index bac17d5edb..d88f78fbcc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c @@ -249,6 +249,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); +#if defined(LPTIM_RCR_REP) + assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter)); +#endif + if(hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -473,6 +477,14 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -547,6 +559,14 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -556,6 +576,14 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -601,6 +629,14 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -642,6 +678,14 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -713,6 +757,14 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -722,6 +774,14 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -767,6 +827,14 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -805,6 +873,14 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -879,6 +955,14 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -888,6 +972,14 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -933,6 +1025,14 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -1302,6 +1402,14 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1366,13 +1474,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ + #if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ @@ -1404,6 +1528,14 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -1614,6 +1746,43 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } + +#if defined(LPTIM_RCR_REP) + /* Repetition counter underflowed (or contains zero) and the LPTIM counter + overflowed */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET) + { + /* Clear update event flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE); + + /* Update event Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Successful APB bus write to repetition counter register */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET) + { + /* Clear successful APB bus write to repetition counter flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Successful APB bus write to repetition counter Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->RepCounterWriteCallback(hlptim); +#else + HAL_LPTIM_RepCounterWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } +#endif } /** @@ -1721,6 +1890,38 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) */ } +#if defined(LPTIM_RCR_REP) +/** + * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode. + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventCallback could be implemented in the user file + */ +} + +/** + * @brief Successful APB bus write to repetition counter register callback in non-blocking mode. + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file + */ +} +#endif /* LPTIM_RCR_REP */ + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User LPTIM callback to be used instead of the weak predefined callback @@ -1793,6 +1994,16 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, hlptim->DirectionDownCallback = pCallback; break; +#if defined(LPTIM_RCR_REP) + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = pCallback; + break; + + case HAL_LPTIM_REPETITION_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = pCallback; + break; +#endif /* LPTIM_RCR_REP */ + default : /* Return error status */ status = HAL_ERROR; @@ -1894,6 +2105,16 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak One Pulse Msp Init Callback */ break; +#if defined(LPTIM_RCR_REP) + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Legacy weak Update Event Callback */ + break; + + case HAL_LPTIM_REPETITION_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Legacy weak Repetition counter successful write Callback */ + break; +#endif /* LPTIM_RCR_REP */ + default : /* Return error status */ status = HAL_ERROR; @@ -1990,7 +2211,11 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ +#if defined(LPTIM_RCR_REP) + lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Update Event Callback */ + lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Repetition counter successful write Callback */ +#endif /* LPTIM_RCR_REP */ } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c index e2faf39655..d3e2806a22 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c @@ -3,8 +3,8 @@ * @file stm32l4xx_hal_opamp.c * @author MCD Application Team * @brief OPAMP HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the operational amplifier(s) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the operational amplifier(s) peripheral: * + OPAMP configuration * + OPAMP calibration * Thanks to @@ -12,16 +12,16 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ================================================================================ ##### OPAMP Peripheral Features ##### ================================================================================ - + [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2 - - (#) The OPAMP(s) provide(s) several exclusive running modes. - (++) 1 OPAMP: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx + + (#) The OPAMP(s) provide(s) several exclusive running modes. + (++) 1 OPAMP: STM32L412xx STM32L422xx STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx (++) 2 OPAMP: STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx (#) The OPAMP(s) provide(s) several exclusive running modes. @@ -35,47 +35,47 @@ (#) Each OPAMP(s) can be configured in normal and low power mode. - (#) The OPAMP(s) provide(s) calibration capabilities. + (#) The OPAMP(s) provide(s) calibration capabilities. (++) Calibration aims at correcting some offset for running mode. - (++) The OPAMP uses either factory calibration settings OR user defined + (++) The OPAMP uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). - (++) The user defined settings can be figured out using self calibration + (++) The user defined settings can be figured out using self calibration handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll (++) HAL_OPAMP_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode - (+++) Updates the init structure with trimming values with fresh calibration - results. - The user may store the calibration results for larger - (ex monitoring the trimming as a function of temperature + (+++) Updates the init structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature for instance) (+++) HAL_OPAMPEx_SelfCalibrateAll runs calibration of all OPAMPs in parallel to save search time. - - (#) Running mode: Standalone mode + + (#) Running mode: Standalone mode (++) Gain is set externally (gain depends on external loads). (++) Follower mode also possible externally by connecting the inverting input to the output. - + (#) Running mode: Follower mode (++) No Inverting Input is connected. - - (#) Running mode: Programmable Gain Amplifier (PGA) mode + + (#) Running mode: Programmable Gain Amplifier (PGA) mode (Resistor feedback output) (++) The OPAMP(s) output(s) can be internally connected to resistor feedback output. (++) OPAMP gain is either 2, 4, 8 or 16. - - (#) The OPAMPs inverting input can be selected according to the Reference Manual + + (#) The OPAMPs inverting input can be selected according to the Reference Manual "OPAMP function description" chapter. - - (#) The OPAMPs non inverting input can be selected according to the Reference Manual + + (#) The OPAMPs non inverting input can be selected according to the Reference Manual "OPAMP function description" chapter. - - + + ##### How to use this driver ##### ================================================================================ - [..] + [..] *** Power supply range *** ============================================ @@ -97,51 +97,51 @@ ============================================ [..] To run the OPAMP calibration self calibration: - (#) Start calibration using HAL_OPAMP_SelfCalibrate. + (#) Start calibration using HAL_OPAMP_SelfCalibrate. Store the calibration results. *** Running mode *** ============================================ - + [..] To use the OPAMP, perform the following steps: - + (#) Fill in the HAL_OPAMP_MspInit() to (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE() - (++) Configure the OPAMP input AND output in analog mode using + (++) Configure the OPAMP input AND output in analog mode using HAL_GPIO_Init() to map the OPAMP output to the GPIO pin. - + (#) Registrate Callbacks (++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback, it allows to register following callbacks: - (+++) MspInitCallback : OPAMP MspInit. + (+++) MspInitCallback : OPAMP MspInit. (+++) MspDeInitCallback : OPAMP MspFeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: - (+++) MspInitCallback : OPAMP MspInit. + (+++) MspInitCallback : OPAMP MspInit. (+++) MspDeInitCallback : OPAMP MspdeInit. (+++) All Callbacks (#) Configure the OPAMP using HAL_OPAMP_Init() function: (++) Select the mode (++) Select the inverting input - (++) Select the non-inverting input + (++) Select the non-inverting input (++) If PGA mode is enabled, Select if inverting input is connected. (++) Select either factory or user defined trimming mode. (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values (typically values set by HAL_OPAMP_SelfCalibrate function). - + (#) Enable the OPAMP using HAL_OPAMP_Start() function. - + (#) Disable the OPAMP using HAL_OPAMP_Stop() function. - + (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function. - Caution: On STM32L4, HAL OPAMP lock is software lock only (not + Caution: On STM32L4, HAL OPAMP lock is software lock only (not hardware lock as on some other STM32 devices) (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function. @@ -154,9 +154,9 @@ (#) Configure the OPAMP using HAL_OPAMP_Init() function: (++) As in configure case, select first the parameters you wish to modify. - - (#) Change from low power mode to normal power mode (& vice versa) requires - first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). + + (#) Change from low power mode to normal power mode (& vice versa) requires + first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode alone. @@ -164,7 +164,7 @@ ****************************************************************************** Table 1. OPAMPs inverting/non-inverting inputs for the STM32L4 devices: - +------------------------------------------------------------------------| + +------------------------------------------------------------------------| | | | OPAMP1 | OPAMP2 | |-----------------|---------|----------------------|---------------------| | Inverting Input | VM_SEL | | | @@ -179,11 +179,11 @@ +------------------------------------------------------------------------| (1): NA in follower mode. (2): Available on some package only (ex. BGA132). - - + + Table 2. OPAMPs outputs for the STM32L4 devices: - +------------------------------------------------------------------------- + +------------------------------------------------------------------------- | | | OPAMP1 | OPAMP2 | |-----------------|--------|-----------------------|---------------------| | Output | VOUT | PA3 | PB0 | @@ -219,12 +219,12 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -243,7 +243,7 @@ * @{ */ -/* CSR register reset value */ +/* CSR register reset value */ #define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000) #define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE \ @@ -263,7 +263,7 @@ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -273,14 +273,14 @@ * @{ */ -/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== - + @endverbatim * @{ */ @@ -294,14 +294,21 @@ * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - uint32_t updateotrlpotr = 0; + uint32_t updateotrlpotr; /* Check the OPAMP handle allocation and lock status */ /* Init not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + return HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + { + return HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { return HAL_ERROR; } @@ -309,39 +316,39 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* Set OPAMP parameters */ assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); - + if(hopamp->State == HAL_OPAMP_STATE_RESET) - { + { #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) if(hopamp->MspInitCallback == NULL) { hopamp->MspInitCallback = HAL_OPAMP_MspInit; - } + } #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ } - + if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput)); } - if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) + if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput)); } - + if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) { assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain)); } - - assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); + + assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER) { if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) @@ -355,7 +362,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower)); } } - + if(hopamp->State == HAL_OPAMP_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -363,15 +370,15 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) } #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) - hopamp->MspInitCallback(hopamp); -#else + hopamp->MspInitCallback(hopamp); +#else /* Call MSP init function */ HAL_OPAMP_MspInit(hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Set operating mode */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON); - + if (hopamp->Init.Mode == OPAMP_PGA_MODE) { MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \ @@ -382,7 +389,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.NonInvertingInput | \ hopamp->Init.UserTrimming); } - + if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) { /* In Follower mode InvertingInput is Not Applicable */ @@ -390,9 +397,9 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.PowerMode | \ hopamp->Init.Mode | \ hopamp->Init.NonInvertingInput | \ - hopamp->Init.UserTrimming); - } - + hopamp->Init.UserTrimming); + } + if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE) { MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \ @@ -401,8 +408,8 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.InvertingInput | \ hopamp->Init.NonInvertingInput | \ hopamp->Init.UserTrimming); - } - + } + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { /* Set power mode and associated calibration parameters */ @@ -413,7 +420,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) /* transistors differential pair high (PMOS) and low (NMOS) for */ /* normal mode. */ updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \ - | (hopamp->Init.TrimmingValueN)); + | (hopamp->Init.TrimmingValueN)); MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); } else @@ -422,16 +429,16 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) /* transistors differential pair high (PMOS) and low (NMOS) for */ /* low power mode. */ updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \ - | (hopamp->Init.TrimmingValueNLowPower)); - MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); + | (hopamp->Init.TrimmingValueNLowPower)); + MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); } - } + } /* Configure the power supply range */ /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */ /* bit OPAMP1_CSR_OPARANGE is used for both OPAMPs */ MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, hopamp->Init.PowerSupplyRange); - + /* Update the OPAMP state*/ if (hopamp->State == HAL_OPAMP_STATE_RESET) { @@ -453,10 +460,14 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* DeInit not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { status = HAL_ERROR; } @@ -466,11 +477,11 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); /* Set OPAMP_CSR register to reset value */ - /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */ - /* OPAMP shall be disabled first separately */ + /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */ + /* OPAMP shall be disabled first separately */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE); - + #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) if(hopamp->MspDeInitCallback == NULL) { @@ -483,8 +494,8 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) HAL_OPAMP_MspDeInit(hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Update the OPAMP state*/ - hopamp->State = HAL_OPAMP_STATE_RESET; - + hopamp->State = HAL_OPAMP_STATE_RESET; + /* Process unlocked */ __HAL_UNLOCK(hopamp); } @@ -526,13 +537,13 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp) */ -/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to manage the OPAMP start, stop and calibration actions. @@ -548,12 +559,16 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp) */ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { status = HAL_ERROR; } @@ -561,21 +576,21 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Enable the selected opamp */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - /* Update the OPAMP state*/ + /* Update the OPAMP state*/ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */ - hopamp->State = HAL_OPAMP_STATE_BUSY; + hopamp->State = HAL_OPAMP_STATE_BUSY; } else { status = HAL_ERROR; } - + } return status; } @@ -586,14 +601,21 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ /* Check if OPAMP calibration ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { status = HAL_ERROR; } @@ -605,9 +627,9 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) if(hopamp->State == HAL_OPAMP_STATE_BUSY) { /* Disable the selected opamp */ - CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Update the OPAMP state*/ + CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Update the OPAMP state*/ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/ hopamp->State = HAL_OPAMP_STATE_READY; } @@ -633,20 +655,24 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) */ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - - uint32_t trimmingvaluen = 0; - uint32_t trimmingvaluep = 0; + + uint32_t trimmingvaluen; + uint32_t trimmingvaluep; uint32_t delta; uint32_t opampmode; - + __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { status = HAL_ERROR; } @@ -663,13 +689,13 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ /* the calibration is not working in PGA mode */ opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE); - - /* Use of standalone mode */ - MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + + /* Use of standalone mode */ + MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); /* user trimming values are used for offset calibration */ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM); - + /* Select trimming settings depending on power mode */ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { @@ -679,34 +705,34 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) { tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR; } - + /* Enable calibration */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON); - + /* 1st calibration - N */ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL); - + /* Enable the selected opamp */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Init trimming counter */ + + /* Init trimming counter */ /* Medium value */ - trimmingvaluen = 16; - delta = 8; - - while (delta != 0) + trimmingvaluen = 16U; + delta = 8U; + + while (delta != 0U) { /* Set candidate trimming */ /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ HAL_Delay(OPAMP_TRIMMING_DELAY); - if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ trimmingvaluen -= delta; } @@ -715,22 +741,22 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* OPAMP_CSR_CALOUT is LOW try lower trimming */ trimmingvaluen += delta; } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; } /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ /* Set candidate trimming */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ HAL_Delay(OPAMP_TRIMMING_DELAY); - - if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) - { + + if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { /* Trimming value is actually one value more */ trimmingvaluen++; /* Set right trimming */ @@ -739,25 +765,25 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* 2nd calibration - P */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Init trimming counter */ + + /* Init trimming counter */ /* Medium value */ - trimmingvaluep = 16; - delta = 8; - - while (delta != 0) + trimmingvaluep = 16U; + delta = 8U; + + while (delta != 0U) { /* Set candidate trimming */ /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ trimmingvaluep += delta; } @@ -766,38 +792,38 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* OPAMP_CSR_CALOUT is LOW try lower trimming */ trimmingvaluep -= delta; } - + /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; + delta >>= 1U; } - + /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ /* Set candidate trimming */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) + + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { /* Trimming value is actually one value more */ trimmingvaluep++; MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_OPAMPxEN); - + /* Disable calibration & set normal mode (operating mode) */ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON); - + /* Self calibration is successful */ /* Store calibration(user trimming) results in init structure. */ - /* Set user trimming mode */ + /* Set user trimming mode */ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; /* Affect calibration parameters depending on mode normal/low power */ @@ -815,15 +841,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* Write calibration result P */ hopamp->Init.TrimmingValuePLowPower = trimmingvaluep; } - + /* Restore OPAMP mode after calibration */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode); } else { - /* OPAMP can not be calibrated from this mode */ + /* OPAMP can not be calibrated from this mode */ status = HAL_ERROR; - } + } } return status; } @@ -832,15 +858,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) * @} */ -/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the OPAMP data + This subsection provides a set of functions allowing to control the OPAMP data transfers. @@ -851,8 +877,8 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /** * @brief Lock the selected OPAMP configuration. - * @note On STM32L4, HAL OPAMP lock is software lock only (in - * contrast of hardware lock available on some other STM32 + * @note On STM32L4, HAL OPAMP lock is software lock only (in + * contrast of hardware lock available on some other STM32 * devices). * @param hopamp: OPAMP handle * @retval HAL status @@ -863,44 +889,43 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - /* OPAMP can be locked when enabled and running in normal mode */ + /* OPAMP can be locked when enabled and running in normal mode */ /* It is meaningless otherwise */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_READY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - + if(hopamp == NULL) { status = HAL_ERROR; } - - else + else if(hopamp->State == HAL_OPAMP_STATE_BUSY) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* OPAMP state changed to locked */ hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; } - return status; + else + { + status = HAL_ERROR; + } + return status; } /** * @brief Return the OPAMP factory trimming value. - * @note On STM32L4 OPAMP, user can retrieve factory trimming if + * @note On STM32L4 OPAMP, user can retrieve factory trimming if * OPAMP has never been set to user trimming before. - * Therefore, this function must be called when OPAMP init - * parameter "UserTrimming" is set to trimming factory, - * and before OPAMP calibration (function + * Therefore, this function must be called when OPAMP init + * parameter "UserTrimming" is set to trimming factory, + * and before OPAMP calibration (function * "HAL_OPAMP_SelfCalibrate()"). - * Otherwise, factory trimming value cannot be retrieved and + * Otherwise, factory trimming value cannot be retrieved and * error status is returned. * @param hopamp : OPAMP handle * @param trimmingoffset : Trimming offset (P or N) * This parameter must be a value of @ref OPAMP_FactoryTrimming - * @note Calibration parameter retrieved is corresponding to the mode - * specified in OPAMP init structure (mode normal or low-power). - * To retrieve calibration parameters for both modes, repeat this + * @note Calibration parameter retrieved is corresponding to the mode + * specified in OPAMP init structure (mode normal or low-power). + * To retrieve calibration parameters for both modes, repeat this * function after OPAMP init structure accordingly updated. * @retval Trimming value (P or N): range: 0->31 * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available @@ -911,25 +936,25 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - + /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_BUSY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) { return OPAMP_FACTORYTRIMMING_DUMMY; } - else + + /* Check the OPAMP handle allocation */ + /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ + if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); - + /* Check the trimming mode */ - if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != RESET) + if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != 0U) { /* This function must called when OPAMP init parameter "UserTrimming" */ /* is set to trimming factory, and before OPAMP calibration (function */ @@ -948,8 +973,8 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop else { tmp_opamp_reg_trimming = &OPAMP->LPOTR; - } - + } + /* Get factory trimming */ if (trimmingoffset == OPAMP_FACTORYTRIMMING_P) { @@ -962,7 +987,11 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN; } } - } + } + else + { + return OPAMP_FACTORYTRIMMING_DUMMY; + } return trimmingvalue; } @@ -971,13 +1000,13 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ -/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -1012,12 +1041,12 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) /** * @brief Register a User OPAMP Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (surcharged) predefined callback * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID - * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID + * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID + * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID * @param pCallback : pointer to the Callback function * @retval status */ @@ -1032,7 +1061,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O /* Process locked */ __HAL_LOCK(hopamp); - + if(hopamp->State == HAL_OPAMP_STATE_READY) { switch (CallbackID) @@ -1078,7 +1107,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O /** * @brief Unregister a User OPAMP Callback - * OPAMP Callback is redirected to the weak (surcharged) predefined callback + * OPAMP Callback is redirected to the weak (surcharged) predefined callback * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1094,11 +1123,11 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL /* Process locked */ __HAL_LOCK(hopamp); - + if(hopamp->State == HAL_OPAMP_STATE_READY) { switch (CallbackID) - { + { case HAL_OPAMP_MSP_INIT_CB_ID : hopamp->MspInitCallback = HAL_OPAMP_MspInit; break; @@ -1148,11 +1177,11 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL /** * @} */ - + /** * @} - */ - + */ + #endif /* HAL_OPAMP_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c index 6ed9472edb..40651c206a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c @@ -8,7 +8,7 @@ * peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * @verbatim ****************************************************************************** * @attention @@ -77,7 +77,7 @@ ##### Extended IO operation functions ##### =============================================================================== [..] - (+) OPAMP Self calibration. + (+) OPAMP Self calibration. @endverbatim * @{ @@ -85,17 +85,17 @@ /* 2 OPAMPS available */ /* 2 OPAMPS can be calibrated in parallel */ -/* Not available on STM32L43x/STM32L44x where only one OPAMP available */ +/* Not available on STM32L41x/STM32L42x/STM32L43x/STM32L44x where only one OPAMP available */ /** * @brief Run the self calibration of the 2 OPAMPs in parallel. - * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * @note Trimming values (PMOS & NMOS) are updated and user trimming is * enabled is calibration is successful. * @note Calibration is performed in the mode specified in OPAMP init * structure (mode normal or low-power). To perform calibration for * both modes, repeat this function twice after OPAMP init structure * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P + * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P * and N transistors: 10 steps with 1 ms for each step). * @param hopamp1 handle * @param hopamp2 handle @@ -106,280 +106,279 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { HAL_StatusTypeDef status = HAL_OK; - uint32_t trimmingvaluen1 = 0; - uint32_t trimmingvaluep1 = 0; - uint32_t trimmingvaluen2 = 0; - uint32_t trimmingvaluep2 = 0; + uint32_t trimmingvaluen1; + uint32_t trimmingvaluep1; + uint32_t trimmingvaluen2; + uint32_t trimmingvaluep2; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - __IO uint32_t* tmp_opamp1_reg_trimming; + __IO uint32_t* tmp_opamp1_reg_trimming; __IO uint32_t* tmp_opamp2_reg_trimming; uint32_t delta; uint32_t opampmode1; uint32_t opampmode2; - - if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \ - (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED)) + + if((hopamp1 == NULL) || (hopamp2 == NULL)) + { + status = HAL_ERROR; + } + /* Check if OPAMP in calibration mode and calibration not yet enable */ + else if(hopamp1->State != HAL_OPAMP_STATE_READY) + { + status = HAL_ERROR; + } + else if(hopamp2->State != HAL_OPAMP_STATE_READY) { status = HAL_ERROR; } else { - /* Check if OPAMP in calibration mode and calibration not yet enable */ - if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY)) + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); + + assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); + assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); + + /* Save OPAMP mode as in */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* the calibration is not working in PGA mode */ + opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE); + opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE); + + /* Use of standalone mode */ + MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + + /* user trimming values are used for offset calibration */ + SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); + SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); + + /* Select trimming settings depending on power mode */ + if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); - - assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); - assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); - - /* Save OPAMP mode as in */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ - /* the calibration is not working in PGA mode */ - opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE); - opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE); - - /* Use of standalone mode */ - MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); - MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); - - /* user trimming values are used for offset calibration */ - SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); - SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); - - /* Select trimming settings depending on power mode */ - if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp1_reg_trimming = &OPAMP1->OTR; - } - else - { - tmp_opamp1_reg_trimming = &OPAMP1->LPOTR; - } - - if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp2_reg_trimming = &OPAMP2->OTR; - } - else - { - tmp_opamp2_reg_trimming = &OPAMP2->LPOTR; - } - - /* Enable calibration */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); - - /* 1st calibration - N */ - CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Enable the selected opamp */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Init trimming counter */ - /* Medium value */ - trimmingvaluen1 = 16; - trimmingvaluen2 = 16; - delta = 8; - - while (delta != 0) - { - /* Set candidate trimming */ - /* OPAMP_POWERMODE_NORMAL */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ - /* Offset trim time: during calibration, minimum time needed between */ - /* two steps to have 1 mV accuracy */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluen1 -= delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try higher trimming */ - trimmingvaluen1 += delta; - } - - if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluen2 -= delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try higher trimming */ - trimmingvaluen2 += delta; - } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - } + tmp_opamp1_reg_trimming = &OPAMP1->OTR; + } + else + { + tmp_opamp1_reg_trimming = &OPAMP1->LPOTR; + } + + if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp2_reg_trimming = &OPAMP2->OTR; + } + else + { + tmp_opamp2_reg_trimming = &OPAMP2->LPOTR; + } + + /* Enable calibration */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); + + /* 1st calibration - N */ + CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); + + /* Enable the selected opamp */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Init trimming counter */ + /* Medium value */ + trimmingvaluen1 = 16U; + trimmingvaluen2 = 16U; + delta = 8U; - /* Still need to check if right calibration is current value or one step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ + while (delta != 0U) + { /* Set candidate trimming */ + /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ HAL_Delay(OPAMP_TRIMMING_DELAY); - - if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) + + if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { - /* Trimming value is actually one value more */ - trimmingvaluen1++; - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluen1 -= delta; } - - if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) + else { - /* Trimming value is actually one value more */ - trimmingvaluen2++; - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + /* OPAMP_CSR_CALOUT is LOW try higher trimming */ + trimmingvaluen1 += delta; } - - /* 2nd calibration - P */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Init trimming counter */ - /* Medium value */ - trimmingvaluep1 = 16; - trimmingvaluep2 = 16; - delta = 8; - - while (delta != 0) + + if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { - /* Set candidate trimming */ - /* OPAMP_POWERMODE_NORMAL */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ - trimmingvaluep1 += delta; - } - else - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluep1 -= delta; - } - - if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ - trimmingvaluep2 += delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try lower trimming */ - trimmingvaluep2 -= delta; - } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluen2 -= delta; } - - /* Still need to check if right calibration is current value or one step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + else + { + /* OPAMP_CSR_CALOUT is LOW try higher trimming */ + trimmingvaluen2 += delta; + } + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluen1++; + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + } + + if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluen2++; + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + } + + /* 2nd calibration - P */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); + + /* Init trimming counter */ + /* Medium value */ + trimmingvaluep1 = 16U; + trimmingvaluep2 = 16U; + delta = 8U; + + while (delta != 0U) + { /* Set candidate trimming */ + /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* Trimming value is actually one value more */ - trimmingvaluep1++; - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* Trimming value is actually one value more */ - trimmingvaluep2++; - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<Instance->CSR, OPAMP_CSR_OPAMPxEN); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Disable calibration & set normal mode (operating mode) */ - CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); - - /* Self calibration is successful */ - /* Store calibration (user trimming) results in init structure. */ - - /* Set user trimming mode */ - hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; - hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; - - /* Affect calibration parameters depending on mode normal/low power */ - if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + + if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueN = trimmingvaluen1; - /* Write calibration result P */ - hopamp1->Init.TrimmingValueP = trimmingvaluep1; + /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ + trimmingvaluep1 += delta; } else { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1; - /* Write calibration result P */ - hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1; + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluep1 -= delta; } - - if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + + if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueN = trimmingvaluen2; - /* Write calibration result P */ - hopamp2->Init.TrimmingValueP = trimmingvaluep2; + /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ + trimmingvaluep2 += delta; } else { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2; - /* Write calibration result P */ - hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2; + /* OPAMP_CSR_CALOUT is LOW try lower trimming */ + trimmingvaluep2 -= delta; } + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluep1++; + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluep2++; + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<Instance->CSR, OPAMP_CSR_OPAMPxEN); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Disable calibration & set normal mode (operating mode) */ + CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_READY; - hopamp2->State = HAL_OPAMP_STATE_READY; + /* Self calibration is successful */ + /* Store calibration (user trimming) results in init structure. */ - /* Restore OPAMP mode after calibration */ - MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1); - MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2); + /* Set user trimming mode */ + hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; + hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; + + /* Affect calibration parameters depending on mode normal/low power */ + if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueN = trimmingvaluen1; + /* Write calibration result P */ + hopamp1->Init.TrimmingValueP = trimmingvaluep1; } else { - /* At least one OPAMP can not be calibrated */ - status = HAL_ERROR; - } + /* Write calibration result N */ + hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1; + /* Write calibration result P */ + hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1; + } + + if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueN = trimmingvaluen2; + /* Write calibration result P */ + hopamp2->Init.TrimmingValueP = trimmingvaluep2; + } + else + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2; + /* Write calibration result P */ + hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2; + } + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_READY; + hopamp2->State = HAL_OPAMP_STATE_READY; + + /* Restore OPAMP mode after calibration */ + MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1); + MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2); } return status; } @@ -390,15 +389,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #endif -/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] - (+) OPAMP unlock. + (+) OPAMP unlock. @endverbatim * @{ @@ -416,23 +415,26 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) - || (hopamp->State == HAL_OPAMP_STATE_READY) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) - || (hopamp->State == HAL_OPAMP_STATE_BUSY)) - + if(hopamp == NULL) { status = HAL_ERROR; } - else + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* OPAMP state changed to locked */ hopamp->State = HAL_OPAMP_STATE_BUSY; } - return status; + else + { + status = HAL_ERROR; + } + + return status; } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c index 5a082932ff..1e15d9f31e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_ospi.c * @author MCD Application Team * @brief OSPI HAL module driver. - This file provides firmware functions to manage the following + This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration @@ -14,7 +14,7 @@ + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration - + @verbatim =============================================================================== ##### How to use this driver ##### @@ -30,28 +30,28 @@ (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt or DMA mode is used, enable and configure OctoSPI global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure + (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the fifo threshold, the dual-quad mode, the memory type, the - device size, the CS high time, the free running clock, the clock mode, - the wrap size, the clock prescaler, the sample shifting, the hold delay + (#) Configure the fifo threshold, the dual-quad mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay and the CS boundary using the HAL_OSPI_Init() function. - (#) When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + (#) When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() function. *** Indirect functional mode *** ================================ [..] - (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() + (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() or HAL_OSPI_Command_IT() functions : - (++) Instruction phase : the mode used and if present the size, the instruction + (++) Instruction phase : the mode used and if present the size, the instruction opcode and the DTR mode. - (++) Address phase : the mode used and if present the size, the address + (++) Address phase : the mode used and if present the size, the address value and the DTR mode. - (++) Alternate-bytes phase : the mode used and if present the size, the + (++) Alternate-bytes phase : the mode used and if present the size, the alternate bytes values and the DTR mode. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used and if present the number of bytes and the DTR mode. @@ -59,36 +59,36 @@ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) Flash identifier : in dual-quad mode, indicates which flash is concerned (++) Operation type : always common configuration - (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() + (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() function : - (++) Address space : indicate if the access will be done in register or memory + (++) Address space : indicate if the access will be done in register or memory (++) Address size (++) Number of data (++) Data strobe (DQS) mode : the activation (or not) of this mode - (#) If no data is required for the command (only for regular mode, not for + (#) If no data is required for the command (only for regular mode, not for Hyperbus mode), it is sent directly to the memory : (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or + (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or HAL_OSPI_Transmit_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or + (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or HAL_OSPI_Receive_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== [..] (#) Configure the command sequence by the same way than the indirect mode - (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() + (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() or HAL_OSPI_AutoPolling_IT() functions : (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), the polling interval and the automatic stop activation. @@ -100,29 +100,29 @@ *** Memory-mapped functional mode *** ===================================== [..] - (#) Configure the command sequence by the same way than the indirect mode except + (#) Configure the command sequence by the same way than the indirect mode except for the operation type in regular mode : - (++) Operation type equals to read configuration : the command configuration + (++) Operation type equals to read configuration : the command configuration applies to read access in memory-mapped mode - (++) Operation type equals to write configuration : the command configuration + (++) Operation type equals to write configuration : the command configuration applies to write access in memory-mapped mode - (++) Both read and write configuration should be performed before activating + (++) Both read and write configuration should be performed before activating memory-mapped mode - (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() + (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() functions : (++) The timeout activation and the timeout period. - (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on + (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** ================================================= [..] (#) HAL_OSPI_GetError() function gives the error raised during the last operation. - (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer + (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when + (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when the transfer complete bit is set. *** Control functions *** @@ -131,7 +131,7 @@ (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI IP. - (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold *** IO manager configuration functions *** ========================================== @@ -180,7 +180,7 @@ By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init + reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -190,18 +190,18 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit + using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit or @ref HAL_OSPI_Init function. When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available + not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @endverbatim ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -225,7 +225,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -243,7 +243,7 @@ */ #ifdef HAL_OSPI_MODULE_ENABLED - + /** @cond 0 */ @@ -258,8 +258,9 @@ #define OSPI_CFG_STATE_MASK 0x00000004U #define OSPI_BUSY_STATE_MASK 0x00000008U -#define OSPI_NB_INSTANCE 2 -#define OSPI_IOM_NB_PORTS 2 +#define OSPI_NB_INSTANCE 2U +#define OSPI_IOM_NB_PORTS 2U +#define OSPI_IOM_PORT_MASK 0x1U /* Private macro -------------------------------------------------------------*/ #define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ @@ -272,7 +273,7 @@ /* Private function prototypes -----------------------------------------------*/ static void OSPI_DMACplt (DMA_HandleTypeDef *hdma); static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma); -static void OSPI_DMAError (DMA_HandleTypeDef *hdma); +static void OSPI_DMAError (DMA_HandleTypeDef *hdma); static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); @@ -287,8 +288,8 @@ static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSP * @{ */ -/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -335,14 +336,14 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle)); assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); - + /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Check if the state is the reset state */ if (hospi->State == HAL_OSPI_STATE_RESET) { -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */ hospi->ErrorCallback = HAL_OSPI_ErrorCallback; hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; @@ -366,11 +367,11 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) /* Initialization of the low level hardware */ HAL_OSPI_MspInit(hospi); #endif - + /* Configure the default timeout for the OSPI memory access */ status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); } - + if (status == HAL_OK) { /* Configure memory type, device size, chip select high time, free running clock, clock mode */ @@ -378,34 +379,34 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | hospi->Init.ClockMode)); - + /* Configure wrap size */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); - + /* Configure chip select boundary */ hospi->Instance->DCR3 = (hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos); /* Configure FIFO threshold */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); - + /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Configure clock prescaler */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); - + /* Configure Dual Quad mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); - + /* Configure sample shifting and delay hold quarter cycle */ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); - + /* Enable OctoSPI */ __HAL_OSPI_ENABLE(hospi); - + /* Initialize the OSPI state */ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { @@ -418,7 +419,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) } } } - + /* Return function status */ return status; } @@ -435,11 +436,11 @@ __weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) /* NOTE : This function should not be modified, when the callback is needed, the HAL_OSPI_MspInit can be implemented in the user file - */ + */ } /** - * @brief De-Initialize the OSPI peripheral. + * @brief De-Initialize the OSPI peripheral. * @param hospi : OSPI handle * @retval HAL status */ @@ -457,8 +458,8 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) { /* Disable OctoSPI */ __HAL_OSPI_DISABLE(hospi); - -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) + +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) if(hospi->MspDeInitCallback == NULL) { hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; @@ -470,7 +471,7 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) /* De-initialize the low-level hardware */ HAL_OSPI_MspDeInit(hospi); #endif - + /* Reset the driver state */ hospi->State = HAL_OSPI_STATE_RESET; } @@ -490,15 +491,15 @@ __weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) /* NOTE : This function should not be modified, when the callback is needed, the HAL_OSPI_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief OSPI Transmit/Receive functions +/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief OSPI Transmit/Receive functions * @verbatim =============================================================================== @@ -529,7 +530,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) uint32_t flag = hospi->Instance->SR; uint32_t itsource = hospi->Instance->CR; uint32_t currentstate = hospi->State; - + /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U)) { @@ -560,7 +561,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) } /* Fifo threshold callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->FifoThresholdCallback(hospi); #else HAL_OSPI_FifoThresholdCallback(hospi); @@ -590,7 +591,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* RX complete callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->RxCpltCallback(hospi); #else HAL_OSPI_RxCpltCallback(hospi); @@ -615,16 +616,16 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) if (currentstate == HAL_OSPI_STATE_BUSY_TX) { /* TX complete callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->TxCpltCallback(hospi); -#else +#else HAL_OSPI_TxCpltCallback(hospi); #endif } else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) { /* Command complete callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->CmdCpltCallback(hospi); #else HAL_OSPI_CmdCpltCallback(hospi); @@ -636,7 +637,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Abort called by the user */ /* Abort complete callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); @@ -646,7 +647,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Abort due to an error (eg : DMA error) */ /* Error callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); @@ -664,19 +665,19 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_SM; - + /* Check if automatic poll mode stop is activated */ if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U) { /* Disable the interrupts */ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } - + /* Status match callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->StatusMatchCallback(hospi); #else HAL_OSPI_StatusMatchCallback(hospi); @@ -690,25 +691,25 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) /* Disable all interrupts */ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); - + /* Set error code */ hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; - + /* Check if the DMA is enabled */ if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) { /* Update state */ hospi->State = HAL_OSPI_STATE_READY; - + /* Error callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); @@ -719,9 +720,9 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Update state */ hospi->State = HAL_OSPI_STATE_READY; - + /* Error callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); @@ -733,9 +734,9 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TO; - + /* Timeout callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->TimeOutCallback(hospi); #else HAL_OSPI_TimeOutCallback(hospi); @@ -748,7 +749,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) } /** - * @brief Set the command configuration. + * @brief Set the command configuration. * @param hospi : OSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration @@ -762,7 +763,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp /* Check the parameters of the command structure */ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); @@ -774,7 +775,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); } - + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) { @@ -802,21 +803,21 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Check the state of the driver */ state = hospi->State; - if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((state == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || + if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Configure the registers */ status = OSPI_ConfigCmd(hospi, cmd); @@ -824,7 +825,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp { if (cmd->DataMode == HAL_OSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so wait until TC flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); @@ -833,7 +834,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp else { /* Update the state */ - if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) { hospi->State = HAL_OSPI_STATE_CMD_CFG; } @@ -874,7 +875,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp } /** - * @brief Set the command configuration in interrupt mode. + * @brief Set the command configuration in interrupt mode. * @param hospi : OSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes @@ -884,10 +885,10 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters of the command structure */ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); @@ -899,7 +900,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); } - + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) { @@ -924,19 +925,19 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Check the state of the driver */ if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) && (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -964,7 +965,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd } /** - * @brief Configure the Hyperbus parameters. + * @brief Configure the Hyperbus parameters. * @param hospi : OSPI handle * @param cfg : Structure containing the Hyperbus configuration * @param Timeout : Timeout duration @@ -988,14 +989,14 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure Hyperbus configuration Latency register */ - WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | + WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | cfg->WriteZeroLatency | cfg->LatencyMode)); - + /* Update the state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1005,13 +1006,13 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } /** - * @brief Set the Hyperbus command configuration. + * @brief Set the Hyperbus command configuration. * @param hospi : OSPI handle * @param cmd : Structure containing the Hyperbus command * @param Timeout : Timeout duration @@ -1033,7 +1034,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Re-initialize the value of the functional mode */ @@ -1041,14 +1042,14 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC /* Configure the address space in the DCR1 register */ MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); - + /* Configure the CCR and WCCR registers with the address size and the following configuration : - DQS signal enabled (used as RWDS) - DTR mode enabled on address and data - address and data on 8 lines */ - WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | + WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2)); - WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | + WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); /* Configure the DLR register with the number of data */ @@ -1056,7 +1057,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC /* Configure the AR register with the address value */ WRITE_REG(hospi->Instance->AR, cmd->Address); - + /* Update the state */ hospi->State = HAL_OSPI_STATE_CMD_CFG; } @@ -1066,13 +1067,13 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } /** - * @brief Transmit an amount of data in blocking mode. + * @brief Transmit an amount of data in blocking mode. * @param hospi : OSPI handle * @param pData : pointer to data buffer * @param Timeout : Timeout duration @@ -1100,15 +1101,15 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + do { /* Wait till fifo threshold flag is set to send data */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout); - + if (status != HAL_OK) { break; @@ -1118,17 +1119,17 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u hospi->pBuffPtr++; hospi->XferCount--; } while (hospi->XferCount > 0U); - + if (status == HAL_OK) { /* Wait till transfer complete flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1160,7 +1161,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui __IO uint32_t *data_reg = &hospi->Instance->DR; uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; - + /* Check the data pointer allocation */ if (pData == NULL) { @@ -1176,10 +1177,10 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Trig the transfer by re-writing address or instruction register */ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { @@ -1196,12 +1197,12 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui WRITE_REG(hospi->Instance->IR, ir_reg); } } - + do { /* Wait till fifo threshold or transfer complete flags are set to read received data */ status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout); - + if (status != HAL_OK) { break; @@ -1216,12 +1217,12 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui { /* Wait till transfer complete flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1246,7 +1247,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Check the data pointer allocation */ @@ -1264,7 +1265,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1316,10 +1317,10 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -1358,13 +1359,13 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) } /** - * @brief Send an amount of data in non-blocking mode with DMA. + * @brief Send an amount of data in non-blocking mode with DMA. * @param hospi : OSPI handle * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ @@ -1393,7 +1394,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat { if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1407,7 +1408,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat { if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1426,7 +1427,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat { hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1438,16 +1439,16 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat /* Set the DMA transfer complete callback */ hospi->hdma->XferCpltCallback = OSPI_DMACplt; - + /* Set the DMA Half transfer complete callback */ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - + /* Set the DMA error callback */ hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hospi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); @@ -1481,13 +1482,13 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } /** - * @brief Receive an amount of data in non-blocking mode with DMA. + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hospi : OSPI handle * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ @@ -1518,7 +1519,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData { if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1532,7 +1533,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData { if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1551,10 +1552,10 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData { hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -1563,16 +1564,16 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData /* Set the DMA transfer complete callback */ hospi->hdma->XferCpltCallback = OSPI_DMACplt; - + /* Set the DMA Half transfer complete callback */ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - + /* Set the DMA error callback */ hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hospi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); @@ -1623,7 +1624,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } /** - * @brief Configure the OSPI Automatic Polling Mode in blocking mode. + * @brief Configure the OSPI Automatic Polling Mode in blocking mode. * @param hospi : OSPI handle * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration @@ -1652,14 +1653,14 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure registers */ WRITE_REG (hospi->Instance->PSMAR, cfg->Match); WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); WRITE_REG (hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); /* Trig the transfer by re-writing address or instruction register */ @@ -1677,16 +1678,16 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli { WRITE_REG(hospi->Instance->IR, ir_reg); } - } - + } + /* Wait till status match flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear status match flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1699,11 +1700,11 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli } /* Return function status */ - return status; + return status; } /** - * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. + * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. * @param hospi : OSPI handle * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode @@ -1731,14 +1732,14 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Configure registers */ WRITE_REG (hospi->Instance->PSMAR, cfg->Match); WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); WRITE_REG (hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); /* Clear flags related to interrupt */ @@ -1746,7 +1747,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo /* Update state */ hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING; - + /* Enable the status match and transfer error interrupts */ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); @@ -1775,11 +1776,11 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo } /* Return function status */ - return status; + return status; } /** - * @brief Configure the Memory Mapped mode. + * @brief Configure the Memory Mapped mode. * @param hospi : OSPI handle * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode @@ -1798,16 +1799,16 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Update state */ hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED; - + if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - + /* Configure register */ WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod); @@ -1819,7 +1820,7 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa } /* Configure CR register with functional mode as memory-mapped */ - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); } } @@ -1830,7 +1831,7 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa } /* Return function status */ - return status; + return status; } /** @@ -1920,7 +1921,7 @@ __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi) /* NOTE: This function should not be modified, when the callback is needed, the HAL_OSPI_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1950,7 +1951,7 @@ __weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi) /* NOTE: This function should not be modified, when the callback is needed, the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** @@ -1983,10 +1984,10 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) */ } -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /** * @brief Register a User OSPI Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (surcharged) predefined callback * @param hospi : OSPI handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: @@ -2000,8 +2001,8 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID - * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID - * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID * @param pCallback : pointer to the Callback function * @retval status */ @@ -2058,7 +2059,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI break; default : /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; @@ -2076,7 +2077,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI break; default : /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; @@ -2085,7 +2086,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI else { /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } @@ -2095,7 +2096,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI /** * @brief Unregister a User OSPI Callback - * OSPI Callback is redirected to the weak (surcharged) predefined callback + * OSPI Callback is redirected to the weak (surcharged) predefined callback * @param hospi : OSPI handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -2109,8 +2110,8 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID - * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID - * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID) @@ -2159,7 +2160,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS break; default : /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; @@ -2177,7 +2178,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS break; default : /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; @@ -2186,7 +2187,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS else { /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } @@ -2199,16 +2200,16 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS * @} */ -/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief OSPI control and State functions +/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief OSPI control and State functions * @verbatim =============================================================================== ##### Peripheral Control and State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. + (+) Check in run-time the state of the driver. (+) Check the error code set during last operation. (+) Abort any operation. (+) Manage the Fifo threshold. @@ -2238,7 +2239,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ status = HAL_DMA_Abort(hospi->hdma); if (status != HAL_OK) @@ -2246,23 +2247,23 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) hospi->ErrorCode = HAL_OSPI_ERROR_DMA; } } - + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) { /* Perform an abort of the OctoSPI */ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - + /* Wait until the transfer complete flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Wait until the busy flag is reset to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Update state */ @@ -2305,13 +2306,13 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) /* Update state */ hospi->State = HAL_OSPI_STATE_ABORT; - + /* Check if the DMA is enabled */ if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) @@ -2320,7 +2321,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* Abort callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); @@ -2333,10 +2334,10 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Enable the transfer complete interrupts */ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); - + /* Perform an abort of the OctoSPI */ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); } @@ -2346,7 +2347,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* Abort callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); @@ -2378,17 +2379,17 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t { /* Synchronize initialization structure with the new fifo threshold value */ hospi->Init.FifoThreshold = Threshold; - + /* Configure new fifo threshold */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos)); - + } else { status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } @@ -2438,13 +2439,13 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) * @} */ -/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function - * @brief OSPI IO Manager configuration function +/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief OSPI IO Manager configuration function * @verbatim =============================================================================== ##### IO Manager configuration function ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : (+) Configure the IO manager. @@ -2454,7 +2455,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) */ /** - * @brief Configure the OctoSPI IO manager. + * @brief Configure the OctoSPI IO manager. * @param hospi : OSPI handle * @param cfg : Configuration of the IO Manager for the instance * @param Timeout : Timeout duration @@ -2463,8 +2464,8 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; - uint32_t instance = 0U; - uint8_t index = 0U, ospi_enabled = 0U, other_instance = 0U; + uint32_t instance; + uint8_t index, ospi_enabled = 0U, other_instance; OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; /* Prevent unused argument(s) compilation warning */ @@ -2476,7 +2477,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * assert_param(IS_OSPIM_PORT(cfg->NCSPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); - + if (hospi->Instance == OCTOSPI1) { instance = 0U; @@ -2497,69 +2498,70 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; } } - + if (status == HAL_OK) { /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ - if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0) + if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U) { CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); ospi_enabled |= 0x1U; } - if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0) + if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U) { CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); ospi_enabled |= 0x2U; } - + /***************** Deactivation of previous configuration *****************/ - if (IOM_cfg[instance].ClkPort != 0) + if (IOM_cfg[instance].ClkPort != 0U) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xFU)-1U)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xFU)-1U)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); } - + /********************* Deactivation of other instance *********************/ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xFU)-1U)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xFU)-1U)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); } - + /******************** Activation of new configuration *********************/ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); - + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xFU)-1U)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1U)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1U)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1U)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } - + /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ if ((ospi_enabled & 0x1U) != 0U) { @@ -2583,18 +2585,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * @cond 0 */ /** - * @brief DMA OSPI process complete callback. + * @brief DMA OSPI process complete callback. * @param hdma : DMA handle * @retval None */ -static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) +static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) { OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; - + /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -2603,7 +2605,7 @@ static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA OSPI process half complete callback. + * @brief DMA OSPI process half complete callback. * @param hdma : DMA handle * @retval None */ @@ -2611,10 +2613,10 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) { OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = (hospi->XferCount >> 1); - + if (hospi->State == HAL_OSPI_STATE_BUSY_RX) { -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->RxHalfCpltCallback(hospi); #else HAL_OSPI_RxHalfCpltCallback(hospi); @@ -2622,7 +2624,7 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) } else { -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->TxHalfCpltCallback(hospi); #else HAL_OSPI_TxHalfCpltCallback(hospi); @@ -2635,7 +2637,7 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void OSPI_DMAError(DMA_HandleTypeDef *hdma) +static void OSPI_DMAError(DMA_HandleTypeDef *hdma) { OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; @@ -2643,18 +2645,18 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Abort the OctoSPI */ if (HAL_OSPI_Abort_IT(hospi) != HAL_OK) { /* Disable the interrupts */ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; /* Error callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); @@ -2667,7 +2669,7 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; @@ -2680,10 +2682,10 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Enable the transfer complete interrupts */ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); - + /* Perform an abort of the OctoSPI */ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); } @@ -2693,7 +2695,7 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) hospi->State = HAL_OSPI_STATE_READY; /* Abort callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); @@ -2705,9 +2707,9 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /* DMA abort called due to a transfer error interrupt */ /* Update state */ hospi->State = HAL_OSPI_STATE_READY; - + /* Error callback */ -#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); @@ -2724,10 +2726,10 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) * @param Tickstart : Tick start value * @retval HAL status */ -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { - /* Wait until flag is in expected state */ + /* Wait until flag is in expected state */ while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) { /* Check for the Timeout */ @@ -2737,7 +2739,7 @@ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hosp { hospi->State = HAL_OSPI_STATE_ERROR; hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - + return HAL_ERROR; } } @@ -2758,13 +2760,13 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Re-initialize the value of the functional mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); - + /* Configure the flash ID */ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); } - + if (cmd->OperationType != HAL_OSPI_OPTYPE_WRITE_CFG) { ccr_reg = &(hospi->Instance->CCR); @@ -2787,13 +2789,13 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC { /* Configure the ABR register with alternate bytes value */ *abr_reg = cmd->AlternateBytes; - + /* Configure the CCR register with alternate bytes communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE), (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)); } - /* Configure the TCR register with the number of dummy cycles */ + /* Configure the TCR register with the number of dummy cycles */ MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles); if (cmd->DataMode != HAL_OSPI_DATA_NONE) @@ -2804,7 +2806,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC hospi->Instance->DLR = (cmd->NbData - 1U); } } - + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) { if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) @@ -2812,7 +2814,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->DataMode != HAL_OSPI_DATA_NONE) { /* ---- Command with instruction, address and data ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | @@ -2824,7 +2826,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC else { /* ---- Command with instruction and address ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), @@ -2832,7 +2834,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) { MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); @@ -2841,7 +2843,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the IR register with the instruction value */ *ir_reg = cmd->Instruction; - + /* Configure the AR register with the address value */ hospi->Instance->AR = cmd->Address; } @@ -2850,7 +2852,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->DataMode != HAL_OSPI_DATA_NONE) { /* ---- Command with instruction and data ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), @@ -2866,7 +2868,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize)); /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) { MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); @@ -2875,7 +2877,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the IR register with the instruction value */ *ir_reg = cmd->Instruction; - + } } else @@ -2925,9 +2927,9 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { HAL_StatusTypeDef status = HAL_OK; - uint32_t reg = 0U, value = 0U; - uint32_t index = 0U; - + uint32_t reg, value = 0U; + uint32_t index; + if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) { /* Invalid parameter -> error returned */ @@ -2936,13 +2938,13 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * else { /* Initialize the structure */ - cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0U; - - if (instance_nb == 1U) - { - value = 0U; - } - else if (instance_nb == 2U) + cfg->ClkPort = 0U; + cfg->DQSPort = 0U; + cfg->NCSPort = 0U; + cfg->IOLowPort = 0U; + cfg->IOHighPort = 0U; + + if (instance_nb == 2U) { value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c index 0d31714d00..f6560814c4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c @@ -1081,6 +1081,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } else { + if ((USBx_OUTEP(0U)->DOEPINT & (1U << 5)) != 0U) + { + CLEAR_OUT_EP_INTR(epnum, (1U << 5)); + } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c index fe1caadad0..30c18bb9b3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c @@ -53,19 +53,19 @@ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Defines PWR Private Defines * @{ */ - + /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ -#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ -#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ +#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ /** * @} */ @@ -73,7 +73,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -83,7 +83,7 @@ * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -107,30 +107,30 @@ void HAL_PWR_DeInit(void) } /** - * @brief Enable access to the backup domain + * @brief Enable access to the backup domain * (RTC registers, RTC backup data registers). - * @note After reset, the backup domain is protected against + * @note After reset, the backup domain is protected against * possible unwanted write accesses. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. * In order to set or modify the RTC clock, the backup domain access must be - * disabled. + * disabled. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the - * back-up domain. + * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { - SET_BIT(PWR->CR1, PWR_CR1_DBP); + SET_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @brief Disable access to the backup domain - * (RTC registers, RTC backup data registers). + * (RTC registers, RTC backup data registers). * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); } @@ -150,7 +150,7 @@ void HAL_PWR_DisableBkUpAccess(void) =============================================================================== ##### Peripheral Control functions ##### =============================================================================== - + [..] *** PVD configuration *** ========================= @@ -163,17 +163,17 @@ void HAL_PWR_DisableBkUpAccess(void) line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. - - + + *** WakeUp pin configuration *** ================================ [..] - (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. - The polarity of these pins can be set to configure event detection on high + (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. + The polarity of these pins can be set to configure event detection on high level (rising edge) or low level (falling edge). - + *** Low Power modes configuration *** ===================================== [..] @@ -183,8 +183,8 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. - (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. - (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. + (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. + (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. @@ -193,8 +193,8 @@ void HAL_PWR_DisableBkUpAccess(void) ========================== [..] (+) Entry: (from main run mode) - (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. - + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. + (+) Exit: (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency be increased above 2 MHz. @@ -203,90 +203,90 @@ void HAL_PWR_DisableBkUpAccess(void) *** Sleep mode / Low-power sleep mode *** ========================================= [..] - (+) Entry: + (+) Entry: The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API - in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. - (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). - In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. + In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - + (+) WFI Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) or any wake-up event. - + (+) WFE Exit: - (++) Any wake-up event such as an EXTI line configured in event mode. - - [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, - the MCU is in Low-power Run mode. + (++) Any wake-up event such as an EXTI line configured in event mode. + + [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. *** Stop 0, Stop 1 and Stop 2 modes *** =============================== [..] - (+) Entry: + (+) Entry: The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). - (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. + (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON (++) PWR_LOWPOWERREGULATOR_ON (+) Exit (interrupt or event-triggered, specified when entering STOP mode): (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction - + (+) WFI Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt mode. - (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts - when programmed in wakeup mode. - (+) WFE Exit: + (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts + when programmed in wakeup mode. + (+) WFE Exit: (++) Any EXTI Line (Internal or External) configured in Event mode. - - [..] + + [..] When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode - depending on the LPR bit setting. - When exiting Stop 2 mode, the MCU is in Run mode. + depending on the LPR bit setting. + When exiting Stop 2 mode, the MCU is in Run mode. *** Standby mode *** ==================== [..] - The Standby mode offers two options: + The Standby mode offers two options: (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). - SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers - and Standby circuitry. + SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers + and Standby circuitry. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). - SRAM and register contents are lost except for the RTC registers, RTC backup registers + SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry. - (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. - SRAM1 and register contents are lost except for registers in the Backup domain and - Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - to set RRS bit. - + (++) Entry: + (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. + SRAM1 and register contents are lost except for registers in the Backup domain and + Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API + to set RRS bit. + (++) Exit: - (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - + [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. - + *** Shutdown mode *** ====================== [..] - In Shutdown mode, + In Shutdown mode, voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. SRAM and registers contents are lost except for backup domain registers. - (+) Entry: + (+) Entry: The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. - + (+) Exit: - (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin. - + [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. @@ -298,7 +298,7 @@ void HAL_PWR_DisableBkUpAccess(void) an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes - + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. @@ -318,7 +318,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). - * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD + * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD * configuration information. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -333,11 +333,11 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Set PLS bits according to PVDLevel value */ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -345,24 +345,24 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } - + return HAL_OK; } @@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) */ void HAL_PWR_EnablePVD(void) { - SET_BIT(PWR->CR2, PWR_CR2_PVDE); + SET_BIT(PWR->CR2, PWR_CR2_PVDE); } /** @@ -382,7 +382,7 @@ void HAL_PWR_EnablePVD(void) */ void HAL_PWR_DisablePVD(void) { - CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); } @@ -391,46 +391,46 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity + * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * + * * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: - * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) { - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - + MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + /* Enable wake-up pin */ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); - + } /** * @brief Disable the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); } @@ -440,22 +440,22 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) - * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet - * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set - * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet + * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set + * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWR_EnterSLEEPMode() API. - * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in - * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. + * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWR_EnterSLEEPMode() API. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in + * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction - * @note When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) @@ -470,8 +470,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) /* If in low-power run mode at this point, exit it */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { - HAL_PWREx_DisableLowPowerRunMode(); - } + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + { + return ; + } + } /* Regulator now in main mode. */ } else @@ -480,13 +483,13 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) { - HAL_PWREx_EnableLowPowerRunMode(); - } - } - + HAL_PWREx_EnableLowPowerRunMode(); + } + } + /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - + /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { @@ -508,18 +511,18 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @brief Enter Stop mode * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running * on devices where only "Stop mode" is mentioned with main or low power regulator ON. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. - * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). + * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note When the voltage regulator operates in low power mode (Stop 1), an additional * startup delay is incurred when waking up. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption @@ -527,7 +530,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. @@ -538,7 +541,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); - + if(Regulator == PWR_LOWPOWERREGULATOR_ON) { HAL_PWREx_EnterSTOP1Mode(STOPEntry); @@ -551,20 +554,20 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /** * @brief Enter Standby mode. - * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched + * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched * off. The voltage regulator is disabled, except when SRAM2 content is preserved - * in which case the regulator is in low-power mode. - * SRAM1 and register contents are lost except for registers in the Backup domain and - * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - * to set RRS bit. - * The BOR is available. + * in which case the regulator is in low-power mode. + * SRAM1 and register contents are lost except for registers in the Backup domain and + * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API + * to set RRS bit. + * The BOR is available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the * same. * These states are effective in Standby mode only if APC bit is set through - * HAL_PWREx_EnablePullUpPullDownConfig() API. + * HAL_PWREx_EnablePullUpPullDownConfig() API. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) @@ -586,11 +589,11 @@ void HAL_PWR_EnterSTANDBYMode(void) /** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -601,9 +604,9 @@ void HAL_PWR_EnableSleepOnExit(void) /** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) @@ -615,8 +618,8 @@ void HAL_PWR_DisableSleepOnExit(void) /** - * @brief Enable CORTEX M4 SEVONPEND bit. - * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enable CORTEX M4 SEVONPEND bit. + * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -628,9 +631,9 @@ void HAL_PWR_EnableSEVOnPend(void) /** - * @brief Disable CORTEX M4 SEVONPEND bit. - * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disable CORTEX M4 SEVONPEND bit. + * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c index 819eba0b4d..c7ddab0e5b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c @@ -7,7 +7,7 @@ * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -55,7 +55,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ @@ -72,10 +72,10 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ - + /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask * @{ - */ + */ #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ @@ -83,16 +83,16 @@ /** * @} */ - + /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ - */ -#define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ + */ +#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ /** * @} */ - - + + /** * @} @@ -104,7 +104,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - + /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ @@ -121,13 +121,13 @@ @endverbatim * @{ */ - + /** * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) - */ + */ uint32_t HAL_PWREx_GetVoltageRange(void) { #if defined(PWR_CR5_R1MODE) @@ -146,10 +146,10 @@ uint32_t HAL_PWREx_GetVoltageRange(void) } #else return (PWR->CR1 & PWR_CR1_VOS); -#endif +#endif } - + /** * @brief Configure the main internal regulator output voltage. @@ -158,28 +158,28 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * This parameter can be one of the following values: @if STM32L4S9xx * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, - * typical output voltage at 1.2 V, - * system frequency up to 120 MHz. + * typical output voltage at 1.2 V, + * system frequency up to 120 MHz. @endif * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, + * typical output voltage at 1.2 V, * system frequency up to 80 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, + * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For - * some devices, the system frequency can be increased up to 120 MHz. + * some devices, the system frequency can be increased up to 120 MHz. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within - * 50 microseconds, HAL_TIMEOUT status is reported. + * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { - uint32_t wait_loop_index = 0; + uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); @@ -191,21 +191,21 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - + /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; - } - } + } + } /* If current range is range 1 normal or boost mode */ else { @@ -220,36 +220,36 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - + /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; - } - } + } + } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - } + } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); /* No need to wait for VOSF to be cleared for this transition */ - /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ + /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } - + #else /* If Set Range 1 */ @@ -259,10 +259,10 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } @@ -281,47 +281,47 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No need to wait for VOSF to be cleared for this transition */ } } -#endif - +#endif + return HAL_OK; -} +} /** * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. + * When VDD is present, charge the external battery on VBAT thru an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor * @retval None */ void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) { assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); - + /* Specify resistor selection */ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); - + /* Enable battery charging */ SET_BIT(PWR->CR4, PWR_CR4_VBE); } /** - * @brief Disable battery charging. + * @brief Disable battery charging. * @retval None */ void HAL_PWREx_DisableBatteryCharging(void) { - CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); -} + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} #if defined(PWR_CR2_USV) /** - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @retval None */ void HAL_PWREx_EnableVddUSB(void) @@ -331,7 +331,7 @@ void HAL_PWREx_EnableVddUSB(void) /** - * @brief Disable VDDUSB supply. + * @brief Disable VDDUSB supply. * @retval None */ void HAL_PWREx_DisableVddUSB(void) @@ -342,8 +342,8 @@ void HAL_PWREx_DisableVddUSB(void) #if defined(PWR_CR2_IOSV) /** - * @brief Enable VDDIO2 supply. - * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + * @brief Enable VDDIO2 supply. + * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. * @retval None */ void HAL_PWREx_EnableVddIO2(void) @@ -353,7 +353,7 @@ void HAL_PWREx_EnableVddIO2(void) /** - * @brief Disable VDDIO2 supply. + * @brief Disable VDDIO2 supply. * @retval None */ void HAL_PWREx_DisableVddIO2(void) @@ -364,7 +364,7 @@ void HAL_PWREx_DisableVddIO2(void) /** - * @brief Enable Internal Wake-up Line. + * @brief Enable Internal Wake-up Line. * @retval None */ void HAL_PWREx_EnableInternalWakeUpLine(void) @@ -374,7 +374,7 @@ void HAL_PWREx_EnableInternalWakeUpLine(void) /** - * @brief Disable Internal Wake-up Line. + * @brief Disable Internal Wake-up Line. * @retval None */ void HAL_PWREx_DisableInternalWakeUpLine(void) @@ -386,27 +386,29 @@ void HAL_PWREx_DisableInternalWakeUpLine(void) /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in - * pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PDy bit of PWR_PDCRx register is cleared unless it is reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); @@ -452,9 +454,9 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); #if defined (STM32L496xx) || defined (STM32L4A6xx) CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif +#endif break; #if defined(GPIOI) case PWR_GPIO_I: @@ -463,10 +465,11 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } @@ -474,22 +477,24 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O * in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -521,7 +526,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber CLEAR_BIT(PWR->PUCRG, GPIONumber); break; #endif - case PWR_GPIO_H: + case PWR_GPIO_H: CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); break; #if defined(GPIOI) @@ -530,40 +535,43 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in - * pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PUy bit of PWR_PUCRx register is cleared unless it is reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -605,9 +613,9 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe case PWR_GPIO_H: #if defined (STM32L496xx) || defined (STM32L4A6xx) SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif +#endif CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); break; #if defined(GPIOI) @@ -617,33 +625,36 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -651,7 +662,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb break; case PWR_GPIO_B: CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; + break; case PWR_GPIO_C: CLEAR_BIT(PWR->PDCRC, GPIONumber); break; @@ -665,7 +676,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb CLEAR_BIT(PWR->PDCRE, GPIONumber); break; #endif -#if defined(GPIOF) +#if defined(GPIOF) case PWR_GPIO_F: CLEAR_BIT(PWR->PDCRF, GPIONumber); break; @@ -678,32 +689,33 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb case PWR_GPIO_H: #if defined (STM32L496xx) || defined (STM32L4A6xx) CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; +#endif + break; #if defined(GPIOI) case PWR_GPIO_I: CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding - * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there - * is no conflict when setting PUy or PDy bit. + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there + * is no conflict when setting PUy or PDy bit. * @retval None */ void HAL_PWREx_EnablePullUpPullDownConfig(void) @@ -714,8 +726,8 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void) /** * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. * @retval None */ void HAL_PWREx_DisablePullUpPullDownConfig(void) @@ -727,8 +739,8 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void) /** * @brief Enable SRAM2 content retention in Standby mode. - * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in - * Standby mode and its content is kept. + * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in + * Standby mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM2ContentRetention(void) @@ -739,8 +751,8 @@ void HAL_PWREx_EnableSRAM2ContentRetention(void) /** * @brief Disable SRAM2 content retention in Standby mode. - * @note When RRS bit is reset, SRAM2 is powered off in Standby mode - * and its content is lost. + * @note When RRS bit is reset, SRAM2 is powered off in Standby mode + * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM2ContentRetention(void) @@ -749,11 +761,61 @@ void HAL_PWREx_DisableSRAM2ContentRetention(void) } +#if defined(PWR_CR3_EN_ULP) +/** + * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes. + * @note All the other modes are not affected by this bit. + * @retval None + */ +void HAL_PWREx_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EN_ULP); +} + + +/** + * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes. + * @note All the other modes are not affected by this bit + * @retval None + */ +void HAL_PWREx_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EN_ULP); +} +#endif /* PWR_CR3_EN_ULP */ + + +#if defined(PWR_CR4_EXT_SMPS_ON) +/** + * @brief Enable the CFLDO working @ 0.95V. + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @retval None + */ +void HAL_PWREx_EnableExtSMPS_0V95(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Disable the CFLDO working @ 0.95V + * @note Before SMPS is switched off, the regulated voltage of the + * internal CFLDO shall be set to 1.00V. + * 1.00V. is also default operating Range 2 voltage. + * @retval None + */ +void HAL_PWREx_DisableExtSMPS_0V95(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} +#endif /* PWR_CR4_EXT_SMPS_ON */ + + #if defined(PWR_CR1_RRSTP) /** * @brief Enable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in - * Stop 2 mode and its content is kept. + * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in + * Stop 2 mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM3ContentRetention(void) @@ -764,8 +826,8 @@ void HAL_PWREx_EnableSRAM3ContentRetention(void) /** * @brief Disable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode - * and its content is lost. + * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode + * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM3ContentRetention(void) @@ -776,7 +838,7 @@ void HAL_PWREx_DisableSRAM3ContentRetention(void) #if defined(PWR_CR3_DSIPDEN) /** - * @brief Enable pull-down activation on DSI pins. + * @brief Enable pull-down activation on DSI pins. * @retval None */ void HAL_PWREx_EnableDSIPinsPDActivation(void) @@ -786,7 +848,7 @@ void HAL_PWREx_EnableDSIPinsPDActivation(void) /** - * @brief Disable pull-down activation on DSI pins. + * @brief Disable pull-down activation on DSI pins. * @retval None */ void HAL_PWREx_DisableDSIPinsPDActivation(void) @@ -802,7 +864,7 @@ void HAL_PWREx_DisableDSIPinsPDActivation(void) */ void HAL_PWREx_EnablePVM1(void) { - SET_BIT(PWR->CR2, PWR_PVM_1); + SET_BIT(PWR->CR2, PWR_PVM_1); } /** @@ -811,7 +873,7 @@ void HAL_PWREx_EnablePVM1(void) */ void HAL_PWREx_DisablePVM1(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_1); + CLEAR_BIT(PWR->CR2, PWR_PVM_1); } #endif /* PWR_CR2_PVME1 */ @@ -823,7 +885,7 @@ void HAL_PWREx_DisablePVM1(void) */ void HAL_PWREx_EnablePVM2(void) { - SET_BIT(PWR->CR2, PWR_PVM_2); + SET_BIT(PWR->CR2, PWR_PVM_2); } /** @@ -832,7 +894,7 @@ void HAL_PWREx_EnablePVM2(void) */ void HAL_PWREx_DisablePVM2(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_2); + CLEAR_BIT(PWR->CR2, PWR_PVM_2); } #endif /* PWR_CR2_PVME2 */ @@ -843,7 +905,7 @@ void HAL_PWREx_DisablePVM2(void) */ void HAL_PWREx_EnablePVM3(void) { - SET_BIT(PWR->CR2, PWR_PVM_3); + SET_BIT(PWR->CR2, PWR_PVM_3); } /** @@ -852,7 +914,7 @@ void HAL_PWREx_EnablePVM3(void) */ void HAL_PWREx_DisablePVM3(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_3); + CLEAR_BIT(PWR->CR2, PWR_PVM_3); } @@ -862,7 +924,7 @@ void HAL_PWREx_DisablePVM3(void) */ void HAL_PWREx_EnablePVM4(void) { - SET_BIT(PWR->CR2, PWR_PVM_4); + SET_BIT(PWR->CR2, PWR_PVM_4); } /** @@ -871,7 +933,7 @@ void HAL_PWREx_EnablePVM4(void) */ void HAL_PWREx_DisablePVM4(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_4); + CLEAR_BIT(PWR->CR2, PWR_PVM_4); } @@ -881,8 +943,8 @@ void HAL_PWREx_DisablePVM4(void) * @brief Configure the Peripheral Voltage Monitoring (PVM). * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. - * @note The API configures a single PVM according to the information contained - * in the input structure. To configure several PVMs, the API must be singly + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -890,7 +952,9 @@ void HAL_PWREx_DisablePVM4(void) * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); @@ -901,12 +965,12 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_IT(); - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -914,32 +978,32 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM1_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } - break; -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) + break; +#endif /* PWR_CR2_PVME1 */ + +#if defined(PWR_CR2_PVME2) case PWR_PVM_2: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM2_EXTI_DISABLE_IT(); - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -947,31 +1011,31 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM2_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); } break; -#endif /* PWR_CR2_PVME2 */ - +#endif /* PWR_CR2_PVME2 */ + case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM3_EXTI_DISABLE_IT(); - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -979,30 +1043,30 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM3_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); } break; - + case PWR_PVM_4: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM4_EXTI_DISABLE_IT(); - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -1010,71 +1074,70 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM4_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); } - break; - + break; + default: - return HAL_ERROR; - - } + status = HAL_ERROR; + break; + } - - return HAL_OK; + return status; } /** * @brief Enter Low-power Run mode - * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. - * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. + * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Set Regulator parameter */ - SET_BIT(PWR->CR1, PWR_CR1_LPR); + SET_BIT(PWR->CR1, PWR_CR1_LPR); } /** * @brief Exit Low-power Run mode. - * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that - * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode * returns HAL_TIMEOUT status). The system clock frequency can then be - * increased above 2 MHz. + * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { - uint32_t wait_loop_index = 0; - + uint32_t wait_loop_index; + /* Clear LPR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) { wait_loop_index--; } @@ -1082,7 +1145,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -1091,16 +1154,16 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) * @brief Enter Stop 0 mode. * @note In Stop 0 mode, main and low voltage regulators are ON. * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note By keeping the internal regulator ON during Stop 0 mode, the consumption * is higher although the startup time is reduced. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. @@ -1113,7 +1176,7 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Stop 0 mode with Main Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); @@ -1143,16 +1206,16 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: @@ -1164,7 +1227,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Stop 1 mode with Low-Power Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); @@ -1194,18 +1257,18 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) * @brief Enter Stop 2 mode. * @note In Stop 2 mode, only low power voltage regulator is ON. * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability - * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after - * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only + * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability + * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after + * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only * to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. + * The BOR is available. * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. - * Otherwise, Stop 1 mode is entered. + * Otherwise, Stop 1 mode is entered. * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction @@ -1246,20 +1309,20 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) /** - * @brief Enter Shutdown mode. - * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched - * off. The voltage regulator is disabled and Vcore domain is powered off. + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. - * The BOR is not available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * @retval None */ void HAL_PWREx_EnterSHUTDOWNMode(void) { - + /* Set Shutdown mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); - + /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); @@ -1276,13 +1339,13 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) /** * @brief This function handles the PWR PVD/PVMx interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). + * @note This API should be called under the PVD_PVM_IRQHandler(). * @retval None */ void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); @@ -1291,42 +1354,42 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } /* Next, successively check PVMx exti flags */ -#if defined(PWR_CR2_PVME1) - if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) +#if defined(PWR_CR2_PVME1) + if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM1 interrupt user callback */ HAL_PWREx_PVM1Callback(); - + /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) - if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) +#if defined(PWR_CR2_PVME2) + if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM2 interrupt user callback */ HAL_PWREx_PVM2Callback(); - + /* Clear PVM2 exti pending bit */ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); } -#endif /* PWR_CR2_PVME2 */ - if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) +#endif /* PWR_CR2_PVME2 */ + if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM3 interrupt user callback */ HAL_PWREx_PVM3Callback(); - + /* Clear PVM3 exti pending bit */ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); } - if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) + if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM4 interrupt user callback */ HAL_PWREx_PVM4Callback(); - + /* Clear PVM4 exti pending bit */ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); - } + } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c index 6a7ef5fa8a..712ebdae34 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c @@ -2033,7 +2033,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback * @param hqspi : QSPI handle - * @param CallbackID : ID of the callback to be registered + * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2050,7 +2050,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -2066,7 +2066,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI if(hqspi->State == HAL_QSPI_STATE_READY) { - switch (CallbackID) + switch (CallbackId) { case HAL_QSPI_ERROR_CB_ID : hqspi->ErrorCallback = pCallback; @@ -2114,7 +2114,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI } else if (hqspi->State == HAL_QSPI_STATE_RESET) { - switch (CallbackID) + switch (CallbackId) { case HAL_QSPI_MSP_INIT_CB_ID : hqspi->MspInitCallback = pCallback; @@ -2147,7 +2147,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback * @param hqspi : QSPI handle - * @param CallbackID : ID of the callback to be unregistered + * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2163,7 +2163,7 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; @@ -2172,7 +2172,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS if(hqspi->State == HAL_QSPI_STATE_READY) { - switch (CallbackID) + switch (CallbackId) { case HAL_QSPI_ERROR_CB_ID : hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; @@ -2220,7 +2220,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS } else if (hqspi->State == HAL_QSPI_STATE_RESET) { - switch (CallbackID) + switch (CallbackId) { case HAL_QSPI_MSP_INIT_CB_ID : hqspi->MspInitCallback = HAL_QSPI_MspInit; @@ -2585,21 +2585,8 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort the QSPI */ - if (HAL_QSPI_Abort_IT(hqspi) != HAL_OK) - { - /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + (void)HAL_QSPI_Abort_IT(hqspi); - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->ErrorCallback(hqspi); -#else - HAL_QSPI_ErrorCallback(hqspi); -#endif - } } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c index 91ca75f688..cce985cbb6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c @@ -87,7 +87,11 @@ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#if defined(RCC_CSR_LSIPREDIV) +#define LSI_TIMEOUT_VALUE 17U /* 17 ms (16 ms starting time + 1) */ +#else #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_CSR_LSIPREDIV */ #define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ @@ -172,7 +176,7 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); (++) The Third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. - (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: + (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to two independent output clocks: (++) The first output is used to generate SAR ADC2 clock. (++) The second output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. @@ -275,7 +279,7 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); @@ -285,7 +289,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -326,10 +330,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); -#else +#elif defined(RCC_PLLSAI1_SUPPORT) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); +#else + + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON); + #endif /* RCC_PLLSAI2_SUPPORT */ /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ @@ -340,10 +348,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) -#else +#elif defined(RCC_PLLSAI1_SUPPORT) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) +#else + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + #endif { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) @@ -356,10 +368,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); +#if defined(RCC_PLLSAI1_SUPPORT) + /* Reset PLLSAI1CFGR register */ CLEAR_REG(RCC->PLLSAI1CFGR); SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2CFGR register */ @@ -400,6 +416,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_oscsource; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) @@ -410,6 +428,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) { @@ -418,10 +439,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - /* When the MSI is used as system clock it will not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) + /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_CFGR_SWS_MSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) { - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) { return HAL_ERROR; } @@ -461,10 +483,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); + status = HAL_InitTick (TICK_INT_PRIORITY); + if(status != HAL_OK) + { + return status; + } } } else @@ -479,7 +505,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -501,7 +527,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -518,10 +544,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + if((sysclk_source == RCC_CFGR_SWS_HSE) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_HSE))) { - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } @@ -538,7 +564,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSE is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { @@ -552,7 +578,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { @@ -570,11 +596,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + if((sysclk_source == RCC_CFGR_SWS_HSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; } @@ -597,7 +623,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { @@ -617,7 +643,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { @@ -636,6 +662,45 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { +#if defined(RCC_CSR_LSIPREDIV) + uint32_t csr_temp = RCC->CSR; + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV)) + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + { + /* If LSIRDY is set while LSION is not enabled, + LSIPREDIV can't be updated */ + return HAL_ERROR; + } + + /* Turn off LSI before changing RCC_CSR_LSIPREDIV */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + { + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv); + } +#endif /* RCC_CSR_LSIPREDIV */ + /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); @@ -643,7 +708,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { @@ -660,7 +725,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { @@ -703,7 +768,32 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Set the new LSE configuration -----------------------------------------*/ +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U) + { + /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS)); + + if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U) + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + else + { + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + } +#else __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); +#endif /* RCC_BDCR_LSESYSDIS */ /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) @@ -712,7 +802,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { @@ -726,13 +816,18 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } + +#if defined(RCC_BDCR_LSESYSDIS) + /* By default, stop disabling LSE propagation */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +#endif /* RCC_BDCR_LSESYSDIS */ } /* Restore clock configuration if changed */ @@ -758,7 +853,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { @@ -775,7 +870,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI48 is disabled */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { @@ -792,7 +887,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if(sysclk_source != RCC_CFGR_SWS_PLL) { if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { @@ -800,7 +895,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); +#if defined(RCC_PLLP_SUPPORT) assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); +#endif /* RCC_PLLP_SUPPORT */ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); @@ -811,7 +908,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -823,7 +920,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLN, +#if defined(RCC_PLLP_SUPPORT) RCC_OscInitStruct->PLL.PLLP, +#endif RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); @@ -837,7 +936,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -851,27 +950,33 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PLL_DISABLE(); /* Disable all PLL outputs to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) +#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY) + if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } +#elif defined(RCC_PLLSAI1_SUPPORT) + if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + { + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); + } +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); +#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */ #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); -#else +#elif defined(RCC_PLLSAI1_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); +#else + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK); #endif /* RCC_PLLSAI2_SUPPORT */ /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -942,9 +1047,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { uint32_t tickstart; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t pllfreq = 0; uint32_t hpre = RCC_SYSCLK_DIV1; #endif + HAL_StatusTypeDef status; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) @@ -983,23 +1088,31 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { return HAL_ERROR; } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ - pllfreq = RCC_GetSysClockFreqFromPLLSource(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ - if((pllfreq > 80000000U) && - (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) - || - ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) + if(RCC_GetSysClockFreqFromPLLSource() > 80000000U) { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; + if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + { + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) + { + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + else + { + /* nothing to do */ + } } #endif } @@ -1009,7 +1122,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { return HAL_ERROR; } @@ -1018,7 +1131,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) { /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { return HAL_ERROR; } @@ -1027,18 +1140,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui else { /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { return HAL_ERROR; } } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ - pllfreq = HAL_RCC_GetSysClockFreq(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ - if(pllfreq > 80000000U) + if(HAL_RCC_GetSysClockFreq() > 80000000U) { + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } @@ -1106,12 +1217,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); + status = HAL_InitTick (TICK_INT_PRIORITY); - return HAL_OK; + return status; } /** @@ -1225,16 +1336,20 @@ void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_ */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; + uint32_t msirange = 0U, sysclockfreq = 0U; + uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */ + uint32_t sysclk_source, pll_oscsource; - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + + if((sysclk_source == RCC_CFGR_SWS_MSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) { /* MSI or PLL with MSI source used as system clock source */ /* Get SYSCLK source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) { /* MSISRANGE from RCC_CSR applies */ msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } @@ -1245,24 +1360,28 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) + if(sysclk_source == RCC_CFGR_SWS_MSI) { /* MSI used as system clock source */ sysclockfreq = msirange; } } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + else if(sysclk_source == RCC_CFGR_SWS_HSI) { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + else if(sysclk_source == RCC_CFGR_SWS_HSE) { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } + else + { + /* unexpected case: sysclockfreq at 0 */ + } - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) + if(sysclk_source == RCC_CFGR_SWS_PLL) { /* PLL used as system clock source */ @@ -1316,7 +1435,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); } /** @@ -1328,7 +1447,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); } /** @@ -1341,7 +1460,7 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); + assert_param(RCC_OscInitStruct != (void *)NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ #if defined(RCC_HSI48_SUPPORT) @@ -1394,11 +1513,29 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get the LSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY; + } + else +#endif /* RCC_BDCR_LSESYSDIS */ + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } } else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY; + } + else +#endif /* RCC_BDCR_LSESYSDIS */ + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } } else { @@ -1414,6 +1551,18 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } +#if defined(RCC_CSR_LSIPREDIV) + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV) + { + RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128; + } + else + { + RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1; + } +#endif /* RCC_CSR_LSIPREDIV */ #if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ @@ -1443,10 +1592,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; #else - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; } @@ -1455,6 +1605,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7; } #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLP_SUPPORT */ } /** @@ -1468,8 +1619,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; @@ -1554,7 +1705,7 @@ __weak void HAL_RCC_CSSCallback(void) */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { - uint32_t vos = 0; + uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ if(__HAL_RCC_PWR_IS_CLK_ENABLED()) @@ -1645,13 +1796,13 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; + uint32_t msirange = 0U; + uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) { /* Get MSI range source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) { /* MSISRANGE from RCC_CSR applies */ msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c index 7896c12fc5..52fd2334d0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c @@ -79,14 +79,23 @@ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + +static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency); + +#endif /* SAI1 */ /** * @} */ @@ -148,7 +157,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) @if STM32L486xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif @@ -202,14 +211,15 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tmpregister = 0; - uint32_t tickstart = 0U; + uint32_t tmpregister, tickstart; /* no init needed */ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ HAL_StatusTypeDef status = HAL_OK; /* Final status */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); +#if defined(SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) { @@ -268,6 +278,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#endif /* SAI1 */ + #if defined(SAI2) /*-------------------------- SAI2 clock source configuration ---------------------*/ @@ -330,7 +342,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; @@ -342,7 +354,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { @@ -374,7 +386,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { @@ -557,6 +569,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } else { +#if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ @@ -568,6 +581,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ } } @@ -604,6 +618,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } + else + { + /* nothing to do */ + } } #endif /* SDMMC1 */ @@ -619,6 +637,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } +#if defined(RCC_PLLSAI1_SUPPORT) else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ @@ -630,9 +649,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ + else + { + /* nothing to do */ + } } /*-------------------------- ADC clock source configuration ----------------------*/ +#if !defined(STM32L412xx) && !defined(STM32L422xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ @@ -641,6 +666,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); +#if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -652,6 +678,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) @@ -670,6 +697,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ } +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) @@ -727,7 +755,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -815,7 +843,15 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ -#if defined(STM32L431xx) +#if defined(STM32L412xx) || defined(STM32L422xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC ; + +#elif defined(STM32L431xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ @@ -905,6 +941,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #endif /* STM32L431xx */ +#if defined(RCC_PLLSAI1_SUPPORT) + /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; @@ -918,6 +956,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ @@ -982,8 +1022,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the LPTIM2 clock source ---------------------------------------------*/ PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +#if defined(SAI1) /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#endif /* SAI1 */ #if defined(SAI2) /* Get the SAI2 clock source -----------------------------------------------*/ @@ -1006,8 +1048,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if !defined(STM32L412xx) && !defined(STM32L422xx) /* Get the ADC clock source ------------------------------------------------*/ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) /* Get the SWPMI1 clock source ---------------------------------------------*/ @@ -1072,7 +1116,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) @if STM32L486xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif @@ -1124,8 +1168,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t frequency = 0U; - uint32_t srcclk = 0U; - uint32_t pllvco = 0U, plln = 0U, pllp = 0U; + uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */ +#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) + uint32_t pllp; /* no init needed */ +#endif /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); @@ -1135,34 +1181,43 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the current RTC source */ srcclk = __HAL_RCC_GET_RTC_SOURCE(); - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + switch(srcclk) { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; + case RCC_RTCCLKSOURCE_LSE: + /* Check if LSE is ready */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + case RCC_RTCCLKSOURCE_LSI: + /* Check if LSI is ready */ + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { + frequency = LSI_VALUE; + } + break; + case RCC_RTCCLKSOURCE_HSE_DIV32: + /* Check if HSE is ready */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE / 32U; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } } else { /* Other external peripheral clock source than RTC */ + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); /* Compute PLL clock input */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ + switch(pll_oscsource) { + case RCC_PLLSOURCE_MSI: /* MSI ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) { /*MSI frequency range in HZ*/ @@ -1172,9 +1227,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ - { + break; + case RCC_PLLSOURCE_HSI: /* HSI ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { pllvco = HSI_VALUE; @@ -1183,9 +1237,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ - { + break; + case RCC_PLLSOURCE_HSE: /* HSE ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { pllvco = HSE_VALUE; @@ -1194,141 +1247,123 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else /* No source */ - { + break; + default: + /* No source */ pllvco = 0U; + break; } switch(PeriphClk) { -#if defined(SAI2) +#if defined(SAI1) case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); + break; - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); +#endif - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - else /* RCC_PERIPHCLK_SAI2 */ - { - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); +#if defined(SAI2) - if(srcclk == RCC_SAI2CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI2_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } + case RCC_PERIPHCLK_SAI2: + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco); + break; -#else +#endif - case RCC_PERIPHCLK_SAI1: +#if defined(USB_OTG_FS) || defined(USB) - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); + case RCC_PERIPHCLK_USB: - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } +#endif /* USB_OTG_FS || USB */ -#endif /* SAI2 */ + case RCC_PERIPHCLK_RNG: + +#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) + + case RCC_PERIPHCLK_SDMMC1: - if(frequency == 0U) +#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ { -#if defined(SAI2) - if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); + + switch(srcclk) { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) + case RCC_CCIPR_CLK48SEL: /* MSI ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_CCIPR_CLK48SEL_1: /* PLL ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } - frequency = (pllvco * plln) / pllp; } - } - else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) + break; +#if defined(RCC_PLLSAI1_SUPPORT) + case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) { + if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); #else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } + /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); } - frequency = (pllvco * plln) / pllp; } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + break; +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_HSI48_SUPPORT) + case 0U: + if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ { - frequency = HSI_VALUE; + frequency = HSI48_VALUE; } - } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + break; +#endif /* RCC_HSI48_SUPPORT */ + default: + /* No clock source, frequency default init at 0 */ + break; + } /* switch(srcclk) */ + break; + } -#else - if(srcclk == RCC_SAI1CLKSOURCE_PLL) +#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) + + case RCC_PERIPHCLK_SDMMC1: + + if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) { /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif if(pllp == 0U) { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { pllp = 17U; } @@ -1337,256 +1372,286 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - frequency = (pllvco * plln) / pllp; } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + } + } + else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ + { + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); + + switch(srcclk) + { + case RCC_CCIPR_CLK48SEL: /* MSI ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; } - else + break; + case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - /* No clock source */ - frequency = 0U; + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } } - } - else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) + break; + case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) + if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); + /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); } - - frequency = (pllvco * plln) / pllp; } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + break; + case 0U: + if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ + { + frequency = HSI48_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } /* switch(srcclk) */ + } + break; + +#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ + + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + switch(srcclk) + { + case RCC_USART1CLKSOURCE_PCLK2: + frequency = HAL_RCC_GetPCLK2Freq(); + break; + case RCC_USART1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - /* HSI automatically selected as clock source if PLLs not enabled */ frequency = HSI_VALUE; } - else + break; + case RCC_USART1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) { - /* No clock source */ - frequency = 0U; + frequency = LSE_VALUE; } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } -#endif /* SAI2 */ -#if defined(RCC_PLLSAI2_SUPPORT) + break; + } + + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); - else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) + switch(srcclk) { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) + case RCC_USART2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_USART2CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; + frequency = HSI_VALUE; + } + break; + case RCC_USART2CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } -#endif /* RCC_PLLSAI2_SUPPORT */ - - else - { - /* No clock source */ - frequency = 0U; - } + break; } - break; - -#if defined(USB_OTG_FS) || defined(USB) - - case RCC_PERIPHCLK_USB: - -#endif /* USB_OTG_FS || USB */ - - case RCC_PERIPHCLK_RNG: -#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) - - case RCC_PERIPHCLK_SDMMC1: - -#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ - - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); +#if defined(USART3) - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ + case RCC_PERIPHCLK_USART3: { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + switch(srcclk) { - frequency = 0U; + case RCC_USART3CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_USART3CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART3CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_USART3CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } + + break; } -#if defined(RCC_HSI48_SUPPORT) - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } -#else - else /* No clock source */ - { - frequency = 0U; - } -#endif /* RCC_HSI48_SUPPORT */ - break; -#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) +#endif /* USART3 */ - case RCC_PERIPHCLK_SDMMC1: +#if defined(UART4) - if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ + case RCC_PERIPHCLK_UART4: { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); + + switch(srcclk) { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) + case RCC_UART4CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_UART4CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_UART4CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } + frequency = HSI_VALUE; } - frequency = (pllvco * plln) / pllp; - } - else - { - frequency = 0U; + break; + case RCC_UART4CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } + + break; } - else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ + +#endif /* UART4 */ + +#if defined(UART5) + + case RCC_PERIPHCLK_UART5: { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ + switch(srcclk) { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + case RCC_UART5CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_UART5CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_UART5CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + frequency = HSI_VALUE; } - else + break; + case RCC_UART5CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) { - frequency = 0U; + frequency = LSE_VALUE; } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ + + break; + } + +#endif /* UART5 */ + + case RCC_PERIPHCLK_LPUART1: + { + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + switch(srcclk) { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + case RCC_LPUART1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPUART1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_LPUART1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + frequency = HSI_VALUE; } - else + break; + case RCC_LPUART1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) { - frequency = 0U; + frequency = LSE_VALUE; } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ + + break; + } + + case RCC_PERIPHCLK_ADC: + { + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch(srcclk) { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + case RCC_ADCCLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; +#if defined(RCC_PLLSAI1_SUPPORT) + case RCC_ADCCLKSOURCE_PLLSAI1: + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U) { #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ @@ -1596,512 +1661,349 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ + /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); } - else + break; +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) + case RCC_ADCCLKSOURCE_PLLSAI2: + if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U) { - frequency = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); } + break; +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ + default: + /* No clock source, frequency default init at 0 */ + break; } - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } - } - break; - -#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ - - case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - if(srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ - else - { - frequency = 0U; - } - break; - case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - if(srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } - break; - -#if defined(USART3) - - case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - if(srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } - break; - -#endif /* USART3 */ - -#if defined(UART4) - - case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); - - if(srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } - break; - -#endif /* UART4 */ - -#if defined(UART5) - - case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); - - if(srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; + break; } - break; - -#endif /* UART5 */ - case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(DFSDM1_Filter0) - if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPUART1 */ - else + case RCC_PERIPHCLK_DFSDM1: { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_ADC: - - srcclk = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the current DFSDM1 source */ + srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) + if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); + frequency = HAL_RCC_GetPCLK2Freq(); } - } -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) + else { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#else - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); + frequency = HAL_RCC_GetSysClockFreq(); } - } -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - /* Clock not enabled for ADC */ - else - { - frequency = 0U; - } - break; -#if defined(DFSDM1_Filter0) - - case RCC_PERIPHCLK_DFSDM1: - /* Get the current DFSDM1 source */ - srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - - if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else - { - frequency = HAL_RCC_GetSysClockFreq(); + break; } - break; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) case RCC_PERIPHCLK_DFSDM1AUDIO: - /* Get the current DFSDM1 audio source */ - srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - - if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) - { - frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { - frequency = HSI_VALUE; - } - /* Clock not enabled for DFSDM1 audio source */ - else - { - frequency = 0U; + /* Get the current DFSDM1 audio source */ + srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + + switch(srcclk) + { + case RCC_DFSDM1AUDIOCLKSOURCE_SAI1: + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); + break; + case RCC_DFSDM1AUDIOCLKSOURCE_MSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_DFSDM1AUDIOCLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C1 */ - else { - frequency = 0U; + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + switch(srcclk) + { + case RCC_I2C1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #if defined(I2C2) case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - - if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C2 */ - else { - frequency = 0U; + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + switch(srcclk) + { + case RCC_I2C2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C2CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #endif /* I2C2 */ case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - - if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C3 */ - else - { - frequency = 0U; + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + switch(srcclk) + { + case RCC_I2C3CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C3CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C3CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #if defined(I2C4) case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - - if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C4 */ - else { - frequency = 0U; - } - break; - -#endif /* I2C4 */ + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - - if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ - else - { - frequency = 0U; + switch(srcclk) + { + case RCC_I2C4CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C4CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C4CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; - case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); +#endif /* I2C4 */ - if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + case RCC_PERIPHCLK_LPTIM1: { - frequency = LSE_VALUE; + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + switch(srcclk) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPTIM1CLKSOURCE_LSI: + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { + frequency = LSI_VALUE; + } + break; + case RCC_LPTIM1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_LPTIM1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - /* Clock not enabled for LPTIM2 */ - else + + case RCC_PERIPHCLK_LPTIM2: { - frequency = 0U; + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + switch(srcclk) + { + case RCC_LPTIM2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPTIM2CLKSOURCE_LSI: + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { + frequency = LSI_VALUE; + } + break; + case RCC_LPTIM2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_LPTIM2CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #if defined(SWPMI1) case RCC_PERIPHCLK_SWPMI1: - /* Get the current SWPMI1 source */ - srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - - if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for SWPMI1 */ - else { - frequency = 0U; + /* Get the current SWPMI1 source */ + srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); + + switch(srcclk) + { + case RCC_SWPMI1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_SWPMI1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #endif /* SWPMI1 */ #if defined(OCTOSPI1) || defined(OCTOSPI2) case RCC_PERIPHCLK_OSPI: - /* Get the current OctoSPI clock source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if(srcclk == RCC_OSPICLKSOURCE_PLL) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else + /* Get the current OctoSPI clock source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + + switch(srcclk) { - frequency = 0U; + case RCC_OSPICLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_OSPICLKSOURCE_MSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_OSPICLKSOURCE_PLL: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } + + break; } - /* Clock not enabled for OctoSPI */ - else - { - frequency = 0U; - } - break; #endif /* OCTOSPI1 || OCTOSPI2 */ @@ -2132,6 +2034,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + /** * @brief Enable PLLSAI1. * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -2140,7 +2044,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ @@ -2159,7 +2063,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2189,7 +2093,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2208,7 +2112,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Disable the PLLSAI1 */ @@ -2218,7 +2122,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2231,19 +2135,23 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) + if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U) + { + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); + } +#else + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } +#endif /* RCC_PLLSAI2_SUPPORT */ return status; } +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -2254,7 +2162,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ @@ -2275,7 +2183,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2313,7 +2221,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2332,7 +2240,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Disable the PLLSAI2 */ @@ -2342,7 +2250,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2359,10 +2267,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - ) + if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } @@ -2663,7 +2568,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { - uint32_t value = 0; + uint32_t value; /* no init needed */ /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); @@ -2690,7 +2595,8 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise + according to RCC_CRS_HSI48CalibrationValue value */ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); /* START AUTOMATIC SYNCHRONIZATION*/ @@ -2716,7 +2622,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) { /* Check the parameter */ - assert_param(pSynchroInfo != NULL); + assert_param(pSynchroInfo != (void *)NULL); /* Get the reload value */ pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); @@ -2749,7 +2655,7 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; + uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2759,7 +2665,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } @@ -2837,7 +2743,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) uint32_t itsources = READ_REG(CRS->CR); /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) { /* Clear CRS SYNC event OK flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); @@ -2846,7 +2752,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncOkCallback(); } /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) { /* Clear CRS SYNCWARN flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); @@ -2855,7 +2761,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncWarnCallback(); } /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) { /* frequency error counter reached a zero value */ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); @@ -2866,17 +2772,17 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Check CRS Error flags */ else { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) { crserror |= RCC_CRS_SYNCERR; } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) { crserror |= RCC_CRS_SYNCMISS; } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) { crserror |= RCC_CRS_TRIMOVF; } @@ -2956,6 +2862,8 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + /** * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -2968,7 +2876,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) */ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ @@ -3012,9 +2920,12 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } break; case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) { - status = HAL_ERROR; + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + { + status = HAL_ERROR; + } } break; default: @@ -3043,7 +2954,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -3134,7 +3045,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -3154,6 +3065,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u return status; } +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -3168,7 +3081,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u */ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ @@ -3212,9 +3125,12 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } break; case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) { - status = HAL_ERROR; + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + { + status = HAL_ERROR; + } } break; default: @@ -3243,7 +3159,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -3336,7 +3252,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -3358,6 +3274,238 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + +static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency) +{ + uint32_t frequency = 0U; + uint32_t srcclk = 0U; + uint32_t pllvco, plln; /* no init needed */ +#if defined(RCC_PLLP_SUPPORT) + uint32_t pllp = 0U; +#endif /* RCC_PLLP_SUPPORT */ + + /* Handle SAIs */ + if(PeriphClk == RCC_PERIPHCLK_SAI1) + { + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); + if(srcclk == RCC_SAI1CLKSOURCE_PIN) + { + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + } + /* Else, PLL clock output to check below */ + } +#if defined(SAI2) + else + { + if(PeriphClk == RCC_PERIPHCLK_SAI2) + { + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); + if(srcclk == RCC_SAI2CLKSOURCE_PIN) + { + frequency = EXTERNAL_SAI2_CLOCK_VALUE; + } + /* Else, PLL clock output to check below */ + } + } +#endif /* SAI2 */ + + if(frequency == 0U) + { + pllvco = InputFrequency; + +#if defined(SAI2) + if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) + { + if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } + else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ + { + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#else + if(srcclk == RCC_SAI1CLKSOURCE_PLL) + { + if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + /* HSI automatically selected as clock source if PLLs not enabled */ + frequency = HSI_VALUE; + } + else + { + /* No clock source, frequency default init at 0 */ + } + } + else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) + { + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + /* HSI automatically selected as clock source if PLLs not enabled */ + frequency = HSI_VALUE; + } + else + { + /* No clock source, frequency default init at 0 */ + } + } +#endif /* SAI2 */ + +#if defined(RCC_PLLSAI2_SUPPORT) + + else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) + { + if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U) + { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } + +#endif /* RCC_PLLSAI2_SUPPORT */ + + else + { + /* No clock source, frequency default init at 0 */ + } + } + + + return frequency; +} + +#endif /* SAI1 */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c index e3c0973532..0ef90ec281 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c @@ -5,41 +5,46 @@ * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization + * + Initialization/de-initialization functions * + Calendar (Time and Date) configuration * + Alarms (Alarm A and Alarm B) configuration * + WakeUp Timer configuration * + TimeStamp configuration * + Tampers configuration - * + Backup Data Registers configuration - * + RTC Tamper and TimeStamp Pins Selection + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection * + Interrupts and flags management - * + * @verbatim - =============================================================================== + =============================================================================== ##### RTC Operating Condition ##### =============================================================================== [..] The real-time clock (RTC) and the RTC backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC + To retain the content of the RTC backup registers and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. ##### Backup Domain Reset ##### =============================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. + to their reset values. A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the + (#) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). (#) VDD or VBAT power on, if both supplies have previously been powered off. (#) Tamper detection event resets all data backup registers. ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for @@ -49,43 +54,47 @@ ##### How to use RTC Driver ##### =================================================================== [..] - (#) Enable the RTC domain access (see description in the section above). - (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the HAL_RTC_Init() function. *** Time and Date configuration *** =================================== - [..] - (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() and HAL_RTC_SetDate() functions. - (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. *** Alarm configuration *** =========================== [..] - (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. - (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. ##### RTC and low power modes ##### - =================================================================== + ================================================================== [..] The MCU can be woken up from a low power mode by an RTC alternate function. [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and + These RTC alternate functions can wake up the system from the Stop and Standby low power modes. [..] The system can also wake up from low power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source is LSE or LSI. *** Callback registration *** ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. @@ -141,7 +150,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** * @attention * @@ -169,7 +177,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -179,7 +187,8 @@ * @{ */ -/** @defgroup RTC RTC + +/** @addtogroup RTC * @brief RTC HAL module driver * @{ */ @@ -193,38 +202,38 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions +/** @addtogroup RTC_Exported_Functions * @{ */ -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This section provide functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the + (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter + (#) To configure the RTC Calendar, user application should enter initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is + and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar + (#) To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim @@ -232,241 +241,291 @@ */ /** - * @brief Initialize the RTC according to the specified parameters - * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status = HAL_ERROR; + /* Check the RTC peripheral state */ - if(hrtc == NULL) + if(hrtc != NULL) { - return HAL_ERROR; - } + status = HAL_OK; + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); +#if defined(STM32L412xx) || defined(STM32L422xx) + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); +#endif - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ #if defined(RTC_TAMPER1_SUPPORT) - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ #endif /* RTC_TAMPER1_SUPPORT */ - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ #if defined(RTC_TAMPER3_SUPPORT) - hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ #endif /* RTC_TAMPER3_SUPPORT */ - if(hrtc->MspInitCallback == NULL) - { - hrtc->MspInitCallback = HAL_RTC_MspInit; - } - /* Init the low level hardware */ - hrtc->MspInitCallback(hrtc); + if(hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); - if(hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } } - } -#else - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); +#else /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP ip offset from RTC one */ + hrtc->TampOffset = (TAMP_BASE - RTC_BASE); +#endif /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + hrtc->State = HAL_RTC_STATE_BUSY; - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + status = HAL_ERROR; + } + else { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); +#else + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL); +#endif + /* Set RTC_CR register */ + hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + + /* Exit Initialization mode */ +#if defined(STM32L412xx) || defined(STM32L422xx) + CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); +#else + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); +#endif + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) { +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); + hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#else + hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); + hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#endif + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; } } - - hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; } + + return status; } /** * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle * @note This function doesn't reset the RTC Backup Data registers. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + /* Check the RTC peripheral state */ + if(hrtc != NULL) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + status = HAL_OK; - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= RTC_CR_WUCKSEL; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; - tickstart = HAL_GetTick(); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_TIMEOUT; - } + status = HAL_ERROR; } + else + { + /* Reset TR, DR and CR registers */ + hrtc->Instance->TR = 0x00000000U; + hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + /* Reset All CR bits except CR[2:0] */ + hrtc->Instance->CR &= RTC_CR_WUCKSEL; - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; + tickstart = HAL_GetTick(); - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; + /* Wait till WUTWF flag is set and if Time out is reached exit */ +#if defined(STM32L412xx) || defined(STM32L422xx) + while(((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) +#else + while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) +#endif + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; + status = HAL_TIMEOUT; + } + } - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + if(status == HAL_OK) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Reset all RTC CR register bits */ + hrtc->Instance->CR &= 0x00000000U; + + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMASSR = 0x00000000U; + hrtc->Instance->ALRMBSSR = 0x00000000U; + +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Exit initialization mode */ + CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); +#else + /* Reset ISR register and exit initialization mode */ + hrtc->Instance->ISR = 0x00000000U; - hrtc->State = HAL_RTC_STATE_ERROR; + /* Reset Tamper configuration register */ + hrtc->Instance->TAMPCR = 0x00000000U; - return HAL_ERROR; + /* Reset Option register */ + hrtc->Instance->OR = 0x00000000U; +#endif + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + status = HAL_ERROR; + } + } } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->MspDeInitCallback == NULL) + if(status == HAL_OK) { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Reset TAMP registers */ + ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset))->CR1 = 0xFFFF0000U; + ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset))->CR2 = 0x00000000U; +#endif - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); #else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); + hrtc->State = HAL_RTC_STATE_RESET; - return HAL_OK; + /* Release Lock */ + __HAL_UNLOCK(hrtc); + } + } + + return status; } #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -687,7 +746,7 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca /** * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) @@ -702,7 +761,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) @@ -712,21 +771,21 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTC_MspDeInit could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions +/** @addtogroup RTC_Exported_Functions_Group2 * @brief RTC Time and Date functions * @verbatim =============================================================================== ##### RTC Time and Date functions ##### =============================================================================== - + [..] This section provides functions allowing to configure Time and Date features @endverbatim @@ -735,69 +794,28 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -810,27 +828,72 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_ERROR; } else { + if(Format == RTC_FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos ) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + { + tmpreg = RTC_Bcd2ToByte(sTime->Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); +#if defined(STM32L412xx) || defined(STM32L422xx) + CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); +#else + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); +#endif /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) { @@ -839,7 +902,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_ERROR; @@ -848,10 +911,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - + hrtc->State = HAL_RTC_STATE_READY; - __HAL_UNLOCK(hrtc); + __HAL_UNLOCK(hrtc); return HAL_OK; } @@ -859,28 +922,28 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds * value in second fraction ratio with time unit following generic formula: * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -890,15 +953,15 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Get SecondFraction structure field from the corresponding register field*/ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - + /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -914,17 +977,17 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -947,23 +1010,21 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); } else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); - - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); } /* Disable the write protection for RTC registers */ @@ -978,7 +1039,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /* Set RTC state*/ hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_ERROR; @@ -989,19 +1050,23 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); +#if defined(STM32L412xx) || defined(STM32L422xx) + CLEAR_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); +#else + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); +#endif /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) { /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_ERROR; @@ -1013,7 +1078,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_READY ; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; @@ -1022,20 +1087,20 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1044,10 +1109,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -1064,14 +1129,14 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions +/** @addtogroup RTC_Exported_Functions_Group3 * @brief RTC Alarm functions * -@verbatim +@verbatim =============================================================================== ##### RTC Alarm functions ##### - =============================================================================== - + =============================================================================== + [..] This section provides functions allowing to configure Alarm feature @endverbatim @@ -1079,18 +1144,18 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1107,14 +1172,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if(Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -1128,18 +1193,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay ) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); assert_param(IS_RTC_HOUR12(tmpreg)); @@ -1147,7 +1211,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -1165,13 +1229,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + ((uint32_t)sAlarm->AlarmMask)); } /* Configure the Alarm A or Alarm B Sub Second registers */ @@ -1185,22 +1249,23 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA { /* Disable the Alarm A interrupt */ __HAL_RTC_ALARMA_DISABLE(hrtc); - + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); tickstart = HAL_GetTick(); /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; @@ -1217,13 +1282,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA { /* Disable the Alarm B interrupt */ __HAL_RTC_ALARMB_DISABLE(hrtc); - + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); tickstart = HAL_GetTick(); /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1260,21 +1326,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1284,21 +1350,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; if(Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -1312,31 +1378,32 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat << RTC_ALRMAR_PM_Pos)) | \ + ((uint32_t)(RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos)) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); assert_param(IS_RTC_HOUR12(tmpreg)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } + } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); @@ -1347,13 +1414,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + ((uint32_t)sAlarm->AlarmMask)); } /* Configure the Alarm A or Alarm B Sub Second registers */ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); @@ -1366,20 +1434,20 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { /* Disable the Alarm A interrupt */ __HAL_RTC_ALARMA_DISABLE(hrtc); - + /* Clear flag alarm A */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); tickstart = HAL_GetTick(); /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1400,13 +1468,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { /* Disable the Alarm B interrupt */ __HAL_RTC_ALARMB_DISABLE(hrtc); - + /* Clear flag alarm B */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); tickstart = HAL_GetTick(); /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1433,13 +1501,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* RTC Alarm Interrupt Configuration: EXTI configuration */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1449,8 +1516,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB @@ -1458,7 +1525,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); @@ -1482,7 +1549,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar tickstart = HAL_GetTick(); /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1509,7 +1576,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar tickstart = HAL_GetTick(); /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1533,26 +1600,26 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return HAL_OK; } /** * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1565,6 +1632,16 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } else { @@ -1572,18 +1649,17 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - /* Fill the structure with the read parameters */ - /* ALRMAR/ALRMBR registers have same mapping) */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } if(Format == RTC_FORMAT_BIN) { @@ -1598,7 +1674,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1606,38 +1682,72 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /* Clear the EXTI's line Flag for RTC Alarm */ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - /* As alarms are sharing the same EXTI line, exit when no more pending Alarm event */ - while(((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) || - ((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET))) +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Get interrupt status */ + uint32_t tmp = hrtc->Instance->MISR; + + if ((tmp & RTC_MISR_ALRAMF) != 0u) { - /* Get the AlarmA interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) + /* Clear the AlarmA interrupt pending bit */ + hrtc->Instance->SCR = RTC_SCR_CALRAF; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); + #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTC_AlarmAEventCallback(hrtc); + #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0u) + { + /* Clear the AlarmB interrupt pending bit */ + hrtc->Instance->SCR = RTC_SCR_CALRBF; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif + } + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + /* Get the AlarmA interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) + { + /* Get the pending status of the AlarmA Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { /* Clear the AlarmA interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - /* AlarmA callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmAEventCallback(hrtc); #else HAL_RTC_AlarmAEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif } + } - /* Get the AlarmB interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)) + /* Get the AlarmB interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) + { + /* Get the pending status of the AlarmB Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { /* Clear the AlarmB interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - /* AlarmB callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmBEventCallback(hrtc); #else HAL_RTCEx_AlarmBEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif } } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1645,7 +1755,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1660,20 +1770,20 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1694,8 +1804,8 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @} */ -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -1712,28 +1822,36 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the + * @note The RTC Resynchronization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar + * @note To read the calendar through the shadow registers after Calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Clear RSF flag */ +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; +#else hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; +#endif tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + while((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) +#else + while((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) +#endif { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1748,13 +1866,13 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Get RTC state @@ -1764,7 +1882,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Return the RTC handle state. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) @@ -1776,34 +1894,51 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) /** * @} */ - + /** * @} */ -/** @defgroup RTC_Private_Functions RTC Private functions +/** @addtogroup RTC_Private_Functions * @{ */ /** * @brief Enter the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + if((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + while((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1811,6 +1946,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) } } } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ return HAL_OK; } @@ -1818,32 +1954,33 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { - uint32_t bcdhigh = 0; + uint32_t bcdhigh = 0U; + uint8_t temp = Value; - while(Value >= 10) + while(temp >= 10U) { bcdhigh++; - Value -= 10; + temp -= 10U; } - return ((uint8_t)(bcdhigh << 4) | Value); + return ((uint8_t)(bcdhigh << 4U) | temp); } /** * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) { - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint8_t tmp; + tmp = ((Value & 0xF0U) >> 4U) * 10U; + return (tmp + (Value & 0x0FU)); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c index 3eb3933ba6..ae3620dbc4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_rtc_ex.c * @author MCD Application Team * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: * + RTC Time Stamp functions - * + RTC Tamper functions + * + RTC Tamper functions * + RTC Wake-up functions * + Extended Control functions - * + Extended RTC features functions + * + Extended RTC features functions * @verbatim ============================================================================== @@ -22,31 +22,31 @@ *** RTC Wakeup configuration *** ================================ - [..] + [..] (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode + function. You can also configure the RTC Wakeup timer with interrupt mode using the HAL_RTCEx_SetWakeUpTimer_IT() function. (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. - + *** Outputs configuration *** ============================= [..] The RTC has 2 different outputs: (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B and WaKeUp signals. - To output the selected RTC signal, use the HAL_RTC_Init() function. + To output the selected RTC signal, use the HAL_RTC_Init() function. (+) RTC_CALIB: this output is 512Hz signal or 1Hz. To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. - (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on + (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on the RTC_OR register. (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is - automatically configured in output alternate function. + automatically configured in output alternate function. *** Smooth digital Calibration configuration *** ================================================ [..] (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() function. *** TimeStamp configuration *** @@ -66,24 +66,32 @@ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() function. - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, NoErase, MaskFlag, precharge or discharge and - Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper - with interrupt mode using HAL_RTCEx_SetTamper_IT() function. - (+) The default configuration of the Tamper erases the backup registers. To avoid - erase, enable the NoErase field on the RTC_TAMPCR register. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the RTC_TAMPCR register. + (+) STM32L412xx and STM32L422xx only : With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) STM32L412xx and STM32L422xx only : If you don't intend to have tamper using RTC clock, you can bypass its initialization + by setting ClockEnable inti field to RTC_CLOCK_DISABLE. + (+) STM32L412xx and STM32L422xx only : Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + (+) STM32L412xx and STM32L422xx only : Before calling these functions you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. @endverbatim ****************************************************************************** @@ -113,7 +121,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -123,7 +131,7 @@ * @{ */ -/** @defgroup RTCEx RTCEx +/** @addtogroup RTCEx * @brief RTC Extended HAL module driver * @{ */ @@ -132,6 +140,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(STM32L412xx) || defined(STM32L422xx) +#else #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) #define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ @@ -157,26 +167,27 @@ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) #endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions +/** @addtogroup RTCEx_Exported_Functions * @{ */ -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions * @verbatim =============================================================================== ##### RTC TimeStamp and Tamper functions ##### =============================================================================== - - [..] This section provide functions allowing to configure TimeStamp feature + + [..] This section provides functions allowing to configure TimeStamp feature @endverbatim * @{ @@ -185,15 +196,15 @@ /** * @brief Set TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * The RTC TimeStamp Pin is per default PC13, but for reasons of @@ -202,7 +213,7 @@ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -219,7 +230,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg|= TimeStampEdge; + tmpreg |= TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -233,9 +244,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; @@ -243,16 +254,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * The RTC TimeStamp Pin is per default PC13, but for reasons of @@ -261,7 +272,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -270,7 +281,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Prevent unused argument(s) compilation warning if no assert_param check */ UNUSED(RTC_TimeStampPin); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -293,7 +304,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* RTC timestamp Interrupt Configuration: EXTI configuration */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ @@ -309,12 +319,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Process Locked */ __HAL_LOCK(hrtc); @@ -347,8 +357,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Set Internal TimeStamp. * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) @@ -370,7 +379,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; @@ -378,8 +387,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Deactivate Internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) @@ -408,18 +416,18 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0, tmpdate = 0; + uint32_t tmptime, tmpdate; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -429,17 +437,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -463,231 +471,323 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe } /** - * @brief Set Tamper. - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status + * @brief Handle TimeStamp interrupt request. + * @param hrtc RTC handle + * @retval None */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; +#if defined(STM32L412xx) || defined(STM32L422xx) - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); - hrtc->State = HAL_RTC_STATE_BUSY; + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + if((hrtc->Instance->MISR & RTC_MISR_TSMF) != 0u) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif + /* Not immediatly clear flags because the content of RTC_TSTR and RTC_TSDR arecleared when TSF bit is reset.*/ + hrtc->Instance->SCR = RTC_SCR_CTSF; } - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; + /* Get interrupt status */ + uint32_t tmp = tamp->MISR; + + /* Immediatly clear flags */ + tamp->SCR = tmp; + #if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ + /* Check Tamper1 status */ + if((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif } +#endif /* RTC_TAMPER1_SUPPORT */ - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + /* Check Tamper2 status */ + if((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif } - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); +#if defined(RTC_TAMPER3_SUPPORT) + /* Check Tamper3 status */ + if((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif + } - hrtc->Instance->TAMPCR |= tmpreg; +#endif /* RTC_TAMPER3_SUPPORT */ + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; } -/** - * @brief Set Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ - hrtc->State = HAL_RTC_STATE_BUSY; +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + /* Get the TimeStamp interrupt source enable status and pending flag status */ + if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + /* TIMESTAMP callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->TimeStampEventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + + /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } -#endif /* RTC_TAMPER3_SUPPORT */ } - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; #if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + /* Get the Tamper1 interrupt source enable status and pending flag status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + /* Clear the Tamper1 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + + /* Tamper1 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } + } #endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + + /* Get the Tamper2 interrupt source enable status and pending flag status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + /* Clear the Tamper2 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + + /* Tamper2 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper2EventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } + } + #if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + /* Get the Tamper3 interrupts source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + /* Clear the Tamper3 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + + /* Tamper3 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper3EventCallback(hrtc); +#else + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* RTC_TAMPER3_SUPPORT */ } +#endif /* RTC_TAMPER3_SUPPORT */ - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); +/** + * @brief TimeStamp callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ } /** - * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. - * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. + * @brief Handle TimeStamp polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - assert_param(IS_RTC_TAMPER(Tamper)); + uint32_t tickstart = HAL_GetTick(); - /* Process Locked */ - __HAL_LOCK(hrtc); + while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) + { + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) + { + /* Clear the TIMESTAMP OverRun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - hrtc->State = HAL_RTC_STATE_BUSY; + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); + return HAL_ERROR; + } -#if defined(RTC_TAMPER1_SUPPORT) - if ((Tamper & RTC_TAMPER_1) != 0) - { - /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } } -#endif /* RTC_TAMPER1_SUPPORT */ - if ((Tamper & RTC_TAMPER_2) != 0) + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Set wake up timer. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } } -#if defined(RTC_TAMPER3_SUPPORT) - if ((Tamper & RTC_TAMPER_3) != 0) + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - /* Disable the Tamper3 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */ + { + uint32_t CR_tmp = hrtc->Instance->CR; + CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL; + CR_tmp |= (uint32_t)WakeUpClock; + hrtc->Instance->CR = CR_tmp; } -#endif /* RTC_TAMPER3_SUPPORT */ + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; @@ -698,184 +798,270 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T } /** - * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle - * @retval None + * @brief Set wake up timer with interrupt. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - Only available for STM32L412xx and STM32L422xx + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningfull in case of Low power mode to avoid any RTC software execution after Wake Up. + * That's why when WakeUpAutoClr is set, EXTI is configured as EVENT instead of Interrupt to avoid useless IRQ handler execution. + * @retval HAL status */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr) +#else +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +#endif +{ + uint32_t tickstart; - /* As Tampers and TimeStamp are sharing the same EXTI line, exit when no more pending event */ - while( - ((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) -#if defined(RTC_TAMPER1_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) -#endif /* RTC_TAMPER1_SUPPORT */ - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) -#if defined(RTC_TAMPER3_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) -#endif /* RTC_TAMPER3_SUPPORT */ - ) + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); +#if defined(STM32L412xx) || defined(STM32L422xx) + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); +#endif + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { - - /* Get the TimeStamp interrupt source enable status and pending flag status */ - if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) - { - /* TIMESTAMP callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->TimeStampEventCallback(hrtc); -#else - HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } + tickstart = HAL_GetTick(); -#if defined(RTC_TAMPER1_SUPPORT) - /* Get the Tamper1 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) - { - /* Clear the Tamper1 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Tamper1 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper1EventCallback(hrtc); -#else - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } } -#endif /* RTC_TAMPER1_SUPPORT */ - - /* Get the Tamper2 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) + } + /* Disable the Wake-Up timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Clear flag Wake-Up */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { - /* Clear the Tamper2 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Tamper2 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper2EventCallback(hrtc); -#else - HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; } + } -#if defined(RTC_TAMPER3_SUPPORT) - /* Get the Tamper3 interrupts source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) - { - /* Clear the Tamper3 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Tamper3 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper3EventCallback(hrtc); +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Configure the Wakeup Timer counter and auto clear value */ + hrtc->Instance->WUTR = (uint32_t) (WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos)); #else - HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } -#endif /* RTC_TAMPER3_SUPPORT */ - +/* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; +#endif + + /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */ + { + uint32_t CR_tmp = hrtc->Instance->CR; + CR_tmp &= (uint32_t)~RTC_CR_WUCKSEL; + CR_tmp |= (uint32_t)WakeUpClock; + hrtc->Instance->CR = CR_tmp; } - - /* Change RTC state */ + +#if defined(STM32L412xx) || defined(STM32L422xx) + /* In case of WUT autoclr, the IRQ handler should not be called */ + if (WakeUpAutoClr != 0u) + { + /* RTC WakeUpTimer EXTI Configuration: Event configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); + } + else + { + /* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + } +#else /* defined(STM32L412xx) || defined(STM32L422xx) */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); +#endif /* defined(STM32L412xx) || defined(STM32L422xx) */ + + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } /** - * @brief TimeStamp callback. - * @param hrtc: RTC handle - * @retval None + * @brief Deactivate wake up timer counter. + * @param hrtc RTC handle + * @retval HAL status */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); + uint32_t tickstart; - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } -#if defined(RTC_TAMPER1_SUPPORT) /** - * @brief Tamper 1 callback. - * @param hrtc: RTC handle - * @retval None + * @brief Get wake up timer counter. + * @param hrtc RTC handle + * @retval Counter value */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ + /* Get the counter value */ + return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); } -#endif /* RTC_TAMPER1_SUPPORT */ /** - * @brief Tamper 2 callback. - * @param hrtc: RTC handle + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc RTC handle * @retval None */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ + +#if defined(STM32L412xx) || defined(STM32L422xx) + if((hrtc->Instance->MISR & RTC_MISR_WUTMF) != 0u) + { + /* Immediately clear flags */ + hrtc->Instance->SCR = RTC_SCR_CWUTF; +#else + /* Get the pending status of the WAKEUPTIMER Interrupt */ + if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) + { + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); +#endif + + /* WAKEUPTIMER callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call WakeUpTimerEvent registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; } -#if defined(RTC_TAMPER3_SUPPORT) /** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle + * @brief Wake Up Timer callback. + * @param hrtc RTC handle * @retval None */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file */ } -#endif /* RTC_TAMPER3_SUPPORT */ + /** - * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @brief Handle Wake Up Timer Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -883,146 +1069,191 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 } } + /* Clear the WAKEUPTIMER Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - + return HAL_OK; } -#if defined(RTC_TAMPER1_SUPPORT) /** - * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status + * @} */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER1_SUPPORT */ +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) STM32L412xx and STM32L422xx only : Set Low Power calibration parameter. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + /** - * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @brief Set the Smooth calibration parameters. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue must be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { - uint32_t tickstart = HAL_GetTick(); + uint32_t tickstart; - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ +#if defined(STM32L412xx) || defined(STM32L422xx) + if((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) +#else + if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) +#endif { - if(Timeout != HAL_MAX_DELAY) + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ +#if defined(STM32L412xx) || defined(STM32L422xx) + while((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) +#else + while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) +#endif { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_TIMEOUT; } } } - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + /* Configure the Smooth calibration settings */ + MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_OK; } -#if defined(RTC_TAMPER3_SUPPORT) +#if defined(STM32L412xx) || defined(STM32L422xx) /** - * @brief Handle Tamper 3 Polling. + * @brief Select the low power Calibration mode. * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param LowPowerCalib: Low power Calibration mode. + * This parameter can be can be one of the following values : + * @arg RTC_LPCAL_SET: Low power mode. + * @arg RTC_LPCAL_RESET: High consumption mode. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib) { - uint32_t tickstart = HAL_GetTick(); + /* Check the parameters */ + assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib)); - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + hrtc->State = HAL_RTC_STATE_BUSY; - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - return HAL_OK; -} -#endif /* RTC_TAMPER3_SUPPORT */ + /* Configure the Smooth calibration settings */ + MODIFY_REG(hrtc->Instance->CALR, RTC_CALR_LPCAL, LowPowerCalib); -/** - * @} - */ + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; - [..] This section provide functions allowing to configure Wake-up feature + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); -@endverbatim - * @{ - */ + return HAL_OK; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** - * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1030,13 +1261,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + /* Wait until the shift is completed*/ +#if defined(STM32L412xx) || defined(STM32L422xx) + while((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U) +#else + while((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) +#endif { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { @@ -1045,50 +1277,96 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; } } - } - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + /* Check if the reference clock detection is disabled */ + if((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - tickstart = HAL_GetTick(); + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_ERROR; } - } - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + return HAL_OK; +} - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear flags before config */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)CalibOutput; + + __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1098,21 +1376,42 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } /** - * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} - /* Process Locked */ +/** + * @brief Enable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1120,77 +1419,90 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) { - tickstart = HAL_GetTick(); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - return HAL_TIMEOUT; - } - } + /* Exit Initialization mode */ +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; +#else + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; +#endif } - /* Disable the Wake-Up timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Clear flag Wake-Up */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - tickstart = HAL_GetTick(); + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_OK; +} - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); - return HAL_TIMEOUT; - } - } + hrtc->State = HAL_RTC_STATE_BUSY; - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + /* Exit Initialization mode */ +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; +#else + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; +#endif + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1199,15 +1511,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } /** - * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle + * @brief Enable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle * @retval HAL status */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; - - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1215,33 +1527,13 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } + /* Set the BYPSHAD bit */ + hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1251,85 +1543,96 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief Get wake up timer counter. - * @param hrtc: RTC handle - * @retval Counter value + * @brief Disable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) { - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} + /* Process Locked */ + __HAL_LOCK(hrtc); -/** - * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) - { - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + hrtc->State = HAL_RTC_STATE_BUSY; - /* WAKEUPTIMER callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->WakeUpTimerEventCallback(hrtc); -#else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } /** - * @brief Wake Up Timer callback. - * @param hrtc: RTC handle + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alarm B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc RTC handle * @retval None */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file */ } /** - * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @brief Handle Alarm B Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; } } } - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - + /* Clear the Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1340,283 +1643,359 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ - -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Coarse calibration parameters. - (+) Deactivate the Coarse calibration parameters - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. @endverbatim * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) /** - * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmp = 0; + uint32_t tmpreg; + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + /* Configuration register 2 */ + tmpreg = tamp->CR2; + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} + /* Configure the tamper trigger bit */ + if((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } -/** - * @brief Read data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; + /* Configure the tamper flags masking bit */ + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); + /* Configure the tamper backup registers erasure bit */ + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + tamp->CR2 = tmpreg; - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} + /* Configure filtering parameters */ + tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \ + (sTamper->PrechargeDuration) | (sTamper->TamperPullUp); + + /* Configure Timestamp saving on tamper detection */ + if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection)) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS); + hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection)); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Enable selected tamper */ + tamp->CR1 |= (sTamper->Tamper); + return HAL_OK; +} +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** - * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmoothCalibMinusPulsesValue must be equal to 0. + * @brief Set Tamper. + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tickstart = 0; + uint32_t tmpreg; /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Configure the tamper trigger */ + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { - tickstart = HAL_GetTick(); + sTamper->NoErase = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined(RTC_TAMPER3_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_1) != 0) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined(RTC_TAMPER3_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; } +#endif /* RTC_TAMPER3_SUPPORT */ } - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->Instance->TAMPCR |= tmpreg; + + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + +#if defined(STM32L412xx) || defined(STM32L422xx) /** - * @brief Configure the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. + * @brief Set Tamper with interrupt. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tickstart = 0; + uint32_t tmpreg; + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - return HAL_TIMEOUT; - } - } + /* Copy configuration register into temporary variable */ + tmpreg = tamp->CR2; - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + /* Clear the bits that are going to be configured and leave the others unchanged */ + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } - hrtc->State = HAL_RTC_STATE_ERROR; + /* Configure the tamper flags masking bit */ + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Configure the tamper backup registers erasure bit */ + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + tamp->CR2 = tmpreg; - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Configure filtering parameters */ + tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \ + (sTamper->PrechargeDuration) | (sTamper->TamperPullUp); - return HAL_ERROR; - } + /* Configure Timestamp saving on tamper detection */ + if((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection)) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS); + hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection)); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Configure RTC Tamper Interrupt: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE(); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + /* Enable interrupt on selected tamper */ + tamp->IER |= sTamper->Tamper; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enable selected tamper */ + tamp->CR1 |= sTamper->Tamper; return HAL_OK; } +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @brief Set Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { + uint32_t tmpreg = 0; + /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Configure the tamper trigger */ + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined(RTC_TAMPER3_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined(RTC_TAMPER3_SUPPORT) + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); + + hrtc->Instance->TAMPCR |= tmpreg; + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1624,77 +2003,83 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 return HAL_OK; } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#if defined(STM32L412xx) || defined(STM32L422xx) /** - * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + /* Disable the selected Tamper pin */ + tamp->CR1 &= ~Tamper; - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear tamper mask/noerase/trigger configuration */ + tamp->CR2 &= ~((Tamper << 24) | (Tamper << 16) | Tamper); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + /* Clear tamper interrupt mode configuration */ + tamp->IER &= ~Tamper; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Clear tamper interrupt and event flags (WO register) */ + tamp->SCR = Tamper; return HAL_OK; } - +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** - * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { + assert_param(IS_RTC_TAMPER(Tamper)); + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Disable the selected Tamper pin */ + hrtc->Instance->TAMPCR &= ~Tamper; - return HAL_ERROR; +#if defined(RTC_TAMPER1_SUPPORT) + if ((Tamper & RTC_TAMPER_1) != 0U) + { + /* Disable the Tamper1 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); } - else +#endif /* RTC_TAMPER1_SUPPORT */ + if ((Tamper & RTC_TAMPER_2) != 0U) { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + /* Disable the Tamper2 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); } +#if defined(RTC_TAMPER3_SUPPORT) + if ((Tamper & RTC_TAMPER_3) != 0U) + { + /* Disable the Tamper3 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); + } +#endif /* RTC_TAMPER3_SUPPORT */ - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1702,185 +2087,252 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) return HAL_OK; } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#if defined(RTC_TAMPER1_SUPPORT) /** - * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle + * @brief Handle Tamper 1 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; + uint32_t tickstart = HAL_GetTick(); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + return HAL_OK; +} +#endif /* RTC_TAMPER1_SUPPORT */ - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; +/** + * @brief Handle Tamper 2 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - return HAL_OK; } +#if defined(RTC_TAMPER3_SUPPORT) /** - * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. + * @brief Handle Tamper 3 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + uint32_t tickstart = HAL_GetTick(); - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - return HAL_OK; } +#endif /* RTC_TAMPER3_SUPPORT */ + + +#if defined(RTC_TAMPER1_SUPPORT) /** - * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} +#endif /* RTC_TAMPER1_SUPPORT */ - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); +#if defined(RTC_TAMPER3_SUPPORT) +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); - return HAL_OK; + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ } +#endif /* RTC_TAMPER3_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alarm B callback - (+) RTC Poll for Alarm B request - +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register @endverbatim * @{ */ + /** - * @brief Alarm B callback. - * @param hrtc: RTC handle + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to + * specify the register. + * @param Data Data to be written in the specified Backup data register. * @retval None */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); + uint32_t __IO tmp; +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(tamp->BKP0R); +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; } + /** - * @brief Handle Alarm B Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status + * @brief Read data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to + * specify the register. + * @retval Read value */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + tmp = (uint32_t)&(tamp->BKP0R); +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); - return HAL_OK; + tmp = (uint32_t)&(hrtc->Instance->BKP0R); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); } + /** * @} */ @@ -1890,6 +2342,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ #endif /* HAL_RTC_MODULE_ENABLED */ + /** * @} */ @@ -1899,3 +2352,4 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c index b7c037cc39..50210864a4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c @@ -227,13 +227,14 @@ * @{ */ +#ifdef HAL_SAI_MODULE_ENABLED +#if !defined(STM32L412xx) && !defined(STM32L422xx) + /** @defgroup SAI SAI * @brief SAI HAL module driver * @{ */ -#ifdef HAL_SAI_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ @@ -251,7 +252,6 @@ typedef enum /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_FIFO_SIZE 8 #define SAI_DEFAULT_TIMEOUT 4U #define SAI_LONG_TIMEOUT 1000U /** @@ -602,6 +602,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } + /* Check the SAI Block master clock divider parameter */ + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) @@ -1098,10 +1100,8 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint hsai->Instance->CLRFR = 0xFFFFFFFFU; /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - /* Nothing to do because state update, unlock and error return will be performed later */ - } + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1211,10 +1211,8 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 hsai->Instance->CLRFR = 0xFFFFFFFFU; /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - /* Nothing to do because state update, unlock and error return will be performed later */ - } + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1873,10 +1871,8 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) else { /* Abort SAI */ - if (HAL_SAI_Abort(hsai) != HAL_OK) - { - /* Nothing to do because HAL_SAI_ErrorCallback will be called later */ - } + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); /* Set error callback */ #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) @@ -1930,10 +1926,8 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) else { /* Abort SAI */ - if (HAL_SAI_Abort(hsai) != HAL_OK) - { - /* Nothing to do because HAL_SAI_ErrorCallback will be called later */ - } + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); /* Set error callback */ #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) @@ -2757,10 +2751,8 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - /* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */ - } + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); /* Set the SAI state ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; @@ -2796,10 +2788,8 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) { /* Disable SAI peripheral */ - if (SAI_Disable(hsai) != HAL_OK) - { - /* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */ - } + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -2822,11 +2812,13 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) * @} */ -#endif /* HAL_SAI_MODULE_ENABLED */ /** * @} */ +#endif /* !STM32L412xx && !STM32L422xx */ +#endif /* HAL_SAI_MODULE_ENABLED */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c index 882323e6eb..13ed45d1c5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c @@ -54,9 +54,15 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines + * @{ + */ #define SAI_PDM_DELAY_MASK 0x77U #define SAI_PDM_DELAY_OFFSET 8U #define SAI_PDM_RIGHT_DELAY_OFFSET 4U +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c index d8b6f47531..4f16587bde 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c @@ -245,17 +245,7 @@ */ /* Private macros ------------------------------------------------------------*/ -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup SMARTCARD_Private_Variables SMARTCARD Private Variables - * @{ - */ -static const uint16_t SMARTCARDPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - +/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions * @{ @@ -841,11 +831,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint8_t *ptmpdata = pData; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if ((pData == NULL) || (Size == 0U)) + if ((ptmpdata == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -880,7 +871,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui { return HAL_TIMEOUT; } - hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); + ptmpdata++; } if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) { @@ -926,11 +918,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint8_t *ptmpdata = pData; /* Check that a Rx process is not already ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if ((pData == NULL) || (Size == 0U)) + if ((ptmpdata == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -956,7 +949,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin { return HAL_TIMEOUT; } - *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + ptmpdata++; } /* At end of Rx process, restore hsmartcard->RxState to Ready */ @@ -1151,6 +1145,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef status; + /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -1190,22 +1186,38 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size); + status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size); - /* Clear the TC flag in the ICR register */ - CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); + if(status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - /* Enable the UART Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + /* Enable the UART Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - return HAL_OK; + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1225,6 +1237,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef status; + /* Check that a Rx process is not already ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { @@ -1252,22 +1266,38 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size); + status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + if(status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - /* Enable the SMARTCARD Parity Error Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - return HAL_OK; + /* Restore hsmartcard->State to ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1311,7 +1341,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmatx); + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } } } @@ -1327,7 +1369,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmarx); + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } } } @@ -1391,7 +1445,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmatx); + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } } } @@ -1451,7 +1517,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmarx); + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_TIMEOUT; + } + } } } @@ -1828,16 +1906,16 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == RESET) + if (errorflags == 0U) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { if (hsmartcard->RxISR != NULL) @@ -1850,17 +1928,17 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if ((errorflags != RESET) - && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)))) + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) #else - if ((errorflags != RESET) - && (((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) #endif { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); @@ -1868,7 +1946,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); @@ -1876,7 +1954,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); @@ -1885,14 +1963,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_ORE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) #else - if (((isrflags & USART_ISR_ORE) != RESET) - && (((cr1its & USART_CR1_RXNEIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) #endif { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); @@ -1901,7 +1979,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); @@ -1913,12 +1991,12 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { if (hsmartcard->RxISR != NULL) @@ -1933,7 +2011,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) - any error occurs in DMA mode reception */ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)) + || ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, @@ -1985,7 +2063,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) - Frame error in Transmission */ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != 0U)) { /* Blocking error : transfer is aborted Set the SMARTCARD state ready to be able to start again the process, @@ -2052,7 +2130,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* End if some error occurs */ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ - if (((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) + if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) { hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; __HAL_UNLOCK(hsmartcard); @@ -2071,12 +2149,12 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET))) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) #endif { if (hsmartcard->TxISR != NULL) @@ -2087,16 +2165,18 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if ((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) - && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) + if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - SMARTCARD_EndTransmit_IT(hsmartcard); - return; + if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } } #if defined(USART_CR1_FIFOEN) /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ @@ -2109,7 +2189,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ @@ -2252,8 +2332,8 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar { /* Return SMARTCARD handle state */ uint32_t temp1, temp2; - temp1 = hsmartcard->gState; - temp2 = hsmartcard->RxState; + temp1 = (uint32_t)hsmartcard->gState; + temp2 = (uint32_t)hsmartcard->RxState; return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } @@ -2313,8 +2393,11 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t tmpreg; - SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; + SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; +#if defined(USART_PRESC_PRESCALER) + const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +#endif /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -2395,35 +2478,35 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif break; case SMARTCARD_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif break; case SMARTCARD_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif break; case SMARTCARD_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif break; case SMARTCARD_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #endif @@ -2711,19 +2794,23 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); /* Stop SMARTCARD DMA Tx request if ongoing */ - if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - hsmartcard->TxXferCount = 0U; - SMARTCARD_EndTxTransfer(hsmartcard); + if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->TxXferCount = 0U; + SMARTCARD_EndTxTransfer(hsmartcard); + } } /* Stop SMARTCARD DMA Rx request if ongoing */ - if ((hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - && (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - hsmartcard->RxXferCount = 0U; - SMARTCARD_EndRxTransfer(hsmartcard); + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->RxXferCount = 0U; + SMARTCARD_EndRxTransfer(hsmartcard); + } } hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; @@ -2937,7 +3024,8 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) } else { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; hsmartcard->TxXferCount--; } } @@ -2955,7 +3043,7 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) */ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) { - uint8_t nb_tx_data; + uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) @@ -2970,11 +3058,16 @@ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } - else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; hsmartcard->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } @@ -3037,9 +3130,11 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; - if (--hsmartcard->RxXferCount == 0U) + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) { #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); @@ -3090,16 +3185,19 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) */ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) { - uint8_t nb_rx_data; + uint16_t nb_rx_data; + uint16_t rxdatacount; /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; - if (--hsmartcard->RxXferCount == 0U) + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) { CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); @@ -3132,7 +3230,8 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((hsmartcard->RxXferCount != 0U)) && (hsmartcard->RxXferCount < hsmartcard->NbRxDataToProcess)) + rxdatacount = hsmartcard->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c index 31130df502..4d5a2479ea 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c @@ -283,7 +283,7 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartc */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); @@ -324,7 +324,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmart */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); @@ -370,7 +370,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmar */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); @@ -419,7 +419,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hs */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); @@ -480,8 +480,9 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { @@ -492,10 +493,10 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = (tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = (rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; + rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c index 2230912086..04206d8f87 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c @@ -199,7 +199,7 @@ /** @defgroup SMBUS_Private_Define SMBUS Private Constants * @{ */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ #define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ #define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ #define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ @@ -223,8 +223,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); @@ -354,7 +354,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if (hsmbus->Init.OwnAddress1 != 0U) + if (hsmbus->Init.OwnAddress1 != 0UL) { if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { @@ -533,7 +533,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint */ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) { - uint32_t tmpreg = 0U; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -929,6 +929,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -964,15 +966,19 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + + /* Store current volatile XferOptions, misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -981,12 +987,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1022,6 +1028,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint */ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1058,15 +1066,19 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + + /* Store current volatile XferOptions, Misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1075,7 +1087,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } @@ -1131,7 +1143,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1176,7 +1188,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - if ((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0UL)) { hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; return HAL_ERROR; @@ -1217,16 +1229,16 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1270,7 +1282,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - if ((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0UL)) { hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; return HAL_ERROR; @@ -1305,13 +1317,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if (((SMBUS_GET_PEC_MODE(hsmbus) != RESET) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) + if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else { - SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); } /* Clear ADDR flag after prepare the transfer parameters */ @@ -1425,7 +1437,10 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t { uint32_t tickstart; - __IO uint32_t SMBUS_Trials = 0U; + __IO uint32_t SMBUS_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; if (hsmbus->State == HAL_SMBUS_STATE_READY) { @@ -1448,11 +1463,15 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1465,6 +1484,9 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t return HAL_ERROR; } } + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); } /* Check if the NACKF flag has not been set */ @@ -1503,7 +1525,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t } /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials++ == Trials) + if (SMBUS_Trials == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; @@ -1517,6 +1539,9 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } + + /* Increment Trials */ + SMBUS_Trials++; } while (SMBUS_Trials < Trials); @@ -1553,20 +1578,21 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ - uint32_t tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); + uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR); + uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - (void)SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { - (void)SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); } else { @@ -1575,17 +1601,17 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { - (void)SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { - (void)SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); } else { @@ -1594,12 +1620,11 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - (void)SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } } } @@ -1789,16 +1814,17 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1817,7 +1843,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_ErrorCallback(hsmbus); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) { /* Check and treat errors if errors occurs during STOP process */ SMBUS_ITErrorHandler(hsmbus); @@ -1857,10 +1883,13 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = hsmbus->Instance->RXDR; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; if ((hsmbus->XferSize > 0U)) { @@ -1896,21 +1925,31 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Nothing to do */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = hsmbus->Instance->RXDR; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ hsmbus->XferSize--; hsmbus->XferCount--; } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ - hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ hsmbus->XferSize--; hsmbus->XferCount--; } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET) { if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) { @@ -1924,17 +1963,17 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) + else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) @@ -1984,7 +2023,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Nothing to do */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET) { if (hsmbus->XferCount == 0U) { @@ -2059,9 +2098,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2069,7 +2109,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Locked */ __HAL_LOCK(hsmbus); - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ @@ -2112,7 +2152,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); @@ -2131,12 +2171,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = hsmbus->Instance->RXDR; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + hsmbus->XferSize--; hsmbus->XferCount--; @@ -2146,7 +2190,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else if (hsmbus->XferCount == 0U) { @@ -2170,7 +2214,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -2182,16 +2226,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2204,7 +2248,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Nothing to do */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -2213,7 +2257,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ - hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + hsmbus->XferCount--; hsmbus->XferSize--; } @@ -2243,7 +2291,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -2251,7 +2299,10 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = hsmbus->Instance->RXDR; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; if ((hsmbus->XferSize > 0U)) { @@ -2278,7 +2329,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear ADDR flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); - hsmbus->XferOptions = 0U; + hsmbus->XferOptions = 0; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -2308,7 +2359,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) */ static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0U; + uint32_t tmpisr = 0UL; if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { @@ -2348,9 +2399,10 @@ static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequ */ static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0U; + uint32_t tmpisr = 0UL; + uint32_t tmpstate = hsmbus->State; - if ((hsmbus->State == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) + if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -2358,48 +2410,48 @@ static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptReq if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { - /* Disable TC, STOP, NACK, TXI interrupt */ + /* Disable TC, STOP, NACK and TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { - /* Disable STOPI, NACKI */ + /* Disable STOP and NACK interrupt */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { - /* Disable TC, STOP, NACK, RXI interrupt */ + /* Disable TC, STOP, NACK and RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { - /* Disable STOPI, NACKI */ + /* Disable STOP and NACK interrupt */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { - /* Enable ADDR, STOP interrupt */ + /* Disable ADDR, STOP and NACK interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -2421,9 +2473,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + uint32_t tmpstate; + uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -2432,7 +2486,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -2441,7 +2495,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -2450,7 +2504,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -2459,7 +2513,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -2468,7 +2522,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -2476,14 +2530,20 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } + /* Store current volatile hsmbus->State, misra rule */ + tmperror = hsmbus->ErrorCode; + /* Call the Error Callback in case of Error detected */ - if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF)) { /* Do not Reset the HAL state in case of ALERT error */ - if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) { - if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + /* Store current volatile hsmbus->State, misra rule */ + tmpstate = hsmbus->State; + + if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) { /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ /* keep HAL_SMBUS_STATE_LISTEN if set */ @@ -2515,12 +2575,12 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == Status) + while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -2567,7 +2627,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c index f33d1c318a..900949372a 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c @@ -250,7 +250,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma); static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart); @@ -804,8 +804,9 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -815,6 +816,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); + initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { @@ -866,10 +868,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } /* Transmit data in 16 Bit mode */ @@ -878,14 +880,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -896,18 +898,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; hspi->TxXferCount--; } } @@ -919,20 +922,21 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -983,10 +987,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1073,14 +1074,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { /* read the received data */ - (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; - pData += sizeof(uint8_t); + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -1096,14 +1097,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - *((uint16_t *)pData) = hspi->Instance->DR; - pData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -1130,12 +1131,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Receive last data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - *((uint16_t *)pData) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; } /* Receive last data in 8 Bit mode */ else { - (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; } /* Wait the CRC data */ @@ -1149,28 +1150,25 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Read CRC to Flush DR and RXNE flag */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -1215,14 +1213,19 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp = 0U, tmp1 = 0U; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; #if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; + uint32_t spi_cr1; + uint32_t spi_cr2; #endif /* USE_SPI_CRC */ - uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ - uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1233,11 +1236,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ - if (!((tmp == HAL_SPI_STATE_READY) || \ - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -1277,7 +1287,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1298,19 +1308,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; @@ -1320,7 +1330,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } @@ -1330,15 +1340,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Check RXNE flag */ - if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { - *((uint16_t *)pRxData) = hspi->Instance->DR; - pRxData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } - if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; goto error; @@ -1348,34 +1358,36 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } /* Next Data is a reception (Rx). Tx not allowed */ @@ -1386,7 +1398,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } @@ -1396,12 +1408,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Wait until RXNE flag is reset */ - if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { if (hspi->RxXferCount > 1U) { - *((uint16_t *)pRxData) = hspi->Instance->DR; - pRxData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount -= 2U; if (hspi->RxXferCount <= 1U) { @@ -1411,13 +1423,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } else { - (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; hspi->RxXferCount--; } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } - if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -1440,15 +1453,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1459,9 +1470,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD errorcode = HAL_TIMEOUT; goto error; } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -1688,8 +1698,9 @@ error : */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmp = 0U, tmp1 = 0U; - HAL_StatusTypeDef errorcode = HAL_OK; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1697,11 +1708,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Process locked */ __HAL_LOCK(hspi); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; - if (!((tmp == HAL_SPI_STATE_READY) || \ - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -1758,7 +1770,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p #endif /* USE_SPI_CRC */ /* Check if packing mode is enabled and if there is more than 2 data to receive */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) { /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1876,7 +1888,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, } /* Enable the Tx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -2010,7 +2030,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -2044,7 +2072,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmp = 0U, tmp1 = 0U; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ @@ -2057,10 +2086,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Process locked */ __HAL_LOCK(hspi); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; - if (!((tmp == HAL_SPI_STATE_READY) || - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -2166,7 +2197,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); @@ -2179,7 +2218,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -2229,11 +2276,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -2246,11 +2294,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -2261,7 +2310,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ - if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmatx != NULL) @@ -2385,11 +2434,12 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -2402,11 +2452,12 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -2448,7 +2499,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ - if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel */ if (hspi->hdmatx != NULL) @@ -2602,6 +2653,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { + HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated @@ -2611,18 +2663,26 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /* Abort the SPI DMA tx Stream/Channel */ if (hspi->hdmatx != NULL) { - HAL_DMA_Abort(hspi->hdmatx); + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Abort the SPI DMA rx Stream/Channel */ if (hspi->hdmarx != NULL) { - HAL_DMA_Abort(hspi->hdmarx); + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Disable the SPI DMA Tx & Rx requests */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; - return HAL_OK; + return errorcode; } /** @@ -2637,25 +2697,25 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) uint32_t itflag = hspi->Instance->SR; /* SPI in mode Receiver ----------------------------------------------------*/ - if (((itflag & SPI_FLAG_OVR) == RESET) && - ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } /* SPI in mode Transmitter -------------------------------------------------*/ - if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } /* SPI in Error Treatment --------------------------------------------------*/ - if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) { /* SPI Overrun error interrupt occurred ----------------------------------*/ - if ((itflag & SPI_FLAG_OVR) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) { if (hspi->State != HAL_SPI_STATE_BUSY_TX) { @@ -2670,14 +2730,14 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /* SPI Mode Fault error interrupt occurred -------------------------------*/ - if ((itflag & SPI_FLAG_MODF) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); __HAL_SPI_CLEAR_MODFFLAG(hspi); } /* SPI Frame error interrupt occurred ------------------------------------*/ - if ((itflag & SPI_FLAG_FRE) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); __HAL_SPI_CLEAR_FREFLAG(hspi); @@ -2700,7 +2760,10 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - HAL_DMA_Abort_IT(hspi->hdmarx); + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } } /* Abort the SPI DMA Tx channel */ if (hspi->hdmatx != NULL) @@ -2708,7 +2771,10 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - HAL_DMA_Abort_IT(hspi->hdmatx); + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } } } else @@ -2919,8 +2985,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); @@ -2976,11 +3042,8 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -2996,7 +3059,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3004,26 +3067,23 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* Read CRC */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -3077,11 +3137,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; -#if (USE_SPI_CRC != 0U) - __IO int16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3104,9 +3162,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } else { @@ -3116,9 +3172,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + READ_REG(hspi->Instance->DR); } } #endif /* USE_SPI_CRC */ @@ -3172,7 +3226,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3190,7 +3244,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3208,7 +3262,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3226,7 +3280,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3249,7 +3303,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3271,7 +3325,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ hspi->hdmatx->XferAbortCallback = NULL; @@ -3337,7 +3391,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3417,7 +3471,8 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in 8 Bit mode */ else { - *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount--; } @@ -3452,13 +3507,8 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Regsiter */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3494,7 +3544,8 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3564,14 +3615,8 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Receive data in 16 Bit mode */ - __IO uint16_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = hspi->Instance->DR; - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC to flush Data Regsiter */ + READ_REG(hspi->Instance->DR); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3626,13 +3671,8 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Register */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3651,7 +3691,8 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount--; #if (USE_SPI_CRC != 0U) @@ -3684,13 +3725,8 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = hspi->Instance->DR; - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3740,7 +3776,8 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; if (hspi->TxXferCount == 0U) @@ -3792,14 +3829,14 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) * @param Tickstart tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3847,20 +3884,17 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { - __IO uint8_t tmpreg; - while ((hspi->Instance->SR & Fifo) != State) { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Register */ + READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); } if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3973,7 +4007,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); @@ -4107,7 +4141,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -4169,11 +4203,12 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /* Check RXNEIE is disabled */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); @@ -4210,11 +4245,12 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) /* Check TXEIE is disabled */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c index 8ec6570b0f..578f081fcb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c @@ -55,7 +55,7 @@ /** @defgroup SPIEx_Private_Constants SPIEx Private Constants * @{ */ -#define SPI_FIFO_SIZE 4 +#define SPI_FIFO_SIZE 4UL /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c index 46e304b145..a6c49cb5e1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c @@ -61,7 +61,7 @@ (+) Receive an amount of data in non-blocking mode using HAL_SWPMI_Receive_IT() (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback() - (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can + (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_SWPMI_ErrorCallback() *** DMA mode IO operation *** @@ -104,7 +104,7 @@ The compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows + Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows to register the following callbacks: (+) RxCpltCallback : SWPMI receive complete. (+) RxHalfCpltCallback : SWPMI receive half complete. @@ -218,11 +218,11 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void SWPMI_DMAError(DMA_HandleTypeDef *hdma); static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout); /* Exported functions --------------------------------------------------------*/ @@ -254,7 +254,7 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the SWPMI handle allocation */ if(hswpmi == NULL) @@ -311,8 +311,8 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Insure 300 µs wait to insure SWPMI_IO output not higher than 1.8V */ /* Wait loop initialization and execution */ /* Note: Variable divided by 4 to compensate partially CPU processing cycles. */ - wait_loop_index = (300 * (SystemCoreClock / (1000000 * 4))) + 150; - while(wait_loop_index != 0) + wait_loop_index = (300U * (SystemCoreClock / (1000000U * 4U))) + 150U; + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -663,8 +663,11 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; + uint32_t *ptmp_data; + uint32_t tmp_size; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -673,10 +676,11 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Check if a non-blocking receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -694,27 +698,30 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX; } + ptmp_data = pData; + tmp_size = Size; do { /* Wait the TXE to write data */ if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE)) { - hswpmi->Instance->TDR = (*pData++); - Size--; + hswpmi->Instance->TDR = *ptmp_data; + ptmp_data++; + tmp_size--; } else { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(Size != 0); + } while(tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) @@ -767,8 +774,11 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; + uint32_t *ptmp_data; + uint32_t tmp_size; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -777,10 +787,11 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Check if a non-blocking transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -795,27 +806,30 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX; } + ptmp_data = pData; + tmp_size = Size; do { /* Wait the RXNE to read data */ if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE)) { - (*pData++) = hswpmi->Instance->RDR; - Size--; + *ptmp_data = hswpmi->Instance->RDR; + ptmp_data++; + tmp_size--; } else { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(Size != 0); + } while(tmp_size != 0U); if(status == HAL_OK) { @@ -863,8 +877,9 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -873,7 +888,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -882,7 +898,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -928,8 +944,9 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -938,7 +955,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -947,7 +965,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -989,8 +1007,9 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -999,7 +1018,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -1008,7 +1028,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -1030,17 +1050,27 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; /* Enable the SWPMI transmit DMA channel */ - HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size); + if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + { + hswpmi->State = tmp_state; /* Back to previous state */ + hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hswpmi); + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); - /* Enable the SWPMI transmit underrun error */ - __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE); + /* Enable the SWPMI transmit underrun error */ + __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE); - /* Enable the DMA transfer for transmit request by setting the TXDMA bit - in the SWPMI CR register */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); + /* Enable the DMA transfer for transmit request by setting the TXDMA bit + in the SWPMI CR register */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); + } } else { @@ -1064,8 +1094,9 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -1074,7 +1105,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -1082,7 +1114,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -1104,17 +1136,27 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size); + if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + { + hswpmi->State = tmp_state; /* Back to previous state */ + hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hswpmi); + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); - /* Enable the SWPMI receive CRC Error and receive overrun interrupts */ - __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE); + /* Enable the SWPMI receive CRC Error and receive overrun interrupts */ + __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE); - /* Enable the DMA transfer for the receiver request by setting the RXDMA bit - in the SWPMI CR register */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); + /* Enable the DMA transfer for the receiver request by setting the RXDMA bit + in the SWPMI CR register */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); + } } else { @@ -1131,10 +1173,12 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /** * @brief Stop all DMA transfers. * @param hswpmi SWPMI handle - * @retval HAL_OK + * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hswpmi); @@ -1144,12 +1188,20 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) /* Abort the SWPMI DMA tx channel */ if(hswpmi->hdmatx != NULL) { - HAL_DMA_Abort(hswpmi->hdmatx); + if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK) + { + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; + } } /* Abort the SWPMI DMA rx channel */ if(hswpmi->hdmarx != NULL) { - HAL_DMA_Abort(hswpmi->hdmarx); + if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK) + { + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; + } } /* Disable SWPMI interface */ @@ -1160,7 +1212,7 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) /* Process Unlocked */ __HAL_UNLOCK(hswpmi); - return HAL_OK; + return status; } @@ -1250,7 +1302,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) uint32_t errcode = HAL_SWPMI_ERROR_NONE; /* SWPMI CRC error interrupt occurred --------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U)) { /* Disable Receive CRC interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE); @@ -1261,7 +1313,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Over-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U)) { /* Disable Receive overrun interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE); @@ -1272,7 +1324,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Under-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U)) { /* Disable Transmit under run interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE); @@ -1287,7 +1339,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) { hswpmi->ErrorCode |= errcode; - if((errcode & HAL_SWPMI_ERROR_UDR) != RESET) + if((errcode & HAL_SWPMI_ERROR_UDR) != 0U) { /* Check TXDMA transfer to abort */ if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA)) @@ -1380,31 +1432,31 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI in mode Receiver ---------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U)) { SWPMI_Receive_IT(hswpmi); } /* SWPMI in mode Transmitter ------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U)) { SWPMI_Transmit_IT(hswpmi); } /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/ - if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U)) { SWPMI_EndTransmit_IT(hswpmi); } /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/ - if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U)) { SWPMI_EndReceive_IT(hswpmi); } /* Both Transmission and reception complete ---------------------------------*/ - if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET)) + if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U)) { SWPMI_EndTransmitReceive_IT(hswpmi); } @@ -1544,40 +1596,38 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) * @brief Transmit an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT() * @param hswpmi SWPMI handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) { - HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State; - if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)) + if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { - if(hswpmi->TxXferCount == 0) + if(hswpmi->TxXferCount == 0U) { /* Disable the SWPMI TXE and Underrun Interrupts */ CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE)); } else { - hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++); + hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr; + hswpmi->pTxBuffPtr++; hswpmi->TxXferCount--; } } else { - status = HAL_BUSY; + /* nothing to do */ } - - return status; } /** * @brief Wraps up transmission in non-blocking mode. * @param hswpmi SWPMI handle - * @retval HAL status - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Transmit buffer empty Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF); @@ -1599,25 +1649,25 @@ static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) #else HAL_SWPMI_TxCpltCallback(hswpmi); #endif - - return HAL_OK; } /** * @brief Receive an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT() * @param hswpmi SWPMI handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) { - HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State; - if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)) + if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { - *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR); + *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR); + hswpmi->pRxBuffPtr++; - if(--hswpmi->RxXferCount == 0) + --hswpmi->RxXferCount; + if(hswpmi->RxXferCount == 0U) { /* Wait for RXBFF flag to update state */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) @@ -1629,19 +1679,16 @@ static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) } else { - status = HAL_BUSY; + /* nothing to do */ } - - return status; } /** * @brief Wraps up reception in non-blocking mode. * @param hswpmi SWPMI handle - * @retval HAL status - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Receive buffer full Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF); @@ -1657,17 +1704,14 @@ static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) { hswpmi->State = HAL_SWPMI_STATE_READY; } - - return HAL_OK; } /** * @brief Wraps up transmission and reception in non-blocking mode. * @param hswpmi SWPMI handle - * @retval HAL status - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Transmission Complete Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF); @@ -1683,8 +1727,10 @@ static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi { hswpmi->State = HAL_SWPMI_STATE_READY; } - - return HAL_OK; + else + { + /* nothing to do */ + } } /** @@ -1695,12 +1741,12 @@ static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t tickstart = 0; + uint32_t tickstart; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hswpmi->TxXferCount = 0; + hswpmi->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by setting the TXDMA bit in the SWPMI CR register */ @@ -1714,7 +1760,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { /* Timeout occurred */ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; - + #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) hswpmi->ErrorCallback(hswpmi); #else @@ -1779,9 +1825,9 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hswpmi->RxXferCount = 0; + hswpmi->RxXferCount = 0U; /* Disable the DMA transfer for the receiver request by setting the RXDMA bit in the SWPMI CR register */ @@ -1830,8 +1876,8 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update handle */ - hswpmi->RxXferCount = 0; - hswpmi->TxXferCount = 0; + hswpmi->RxXferCount = 0U; + hswpmi->TxXferCount = 0U; hswpmi->State= HAL_SWPMI_STATE_READY; hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; @@ -1852,8 +1898,8 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update handle */ - hswpmi->RxXferCount = 0; - hswpmi->TxXferCount = 0; + hswpmi->RxXferCount = 0U; + hswpmi->TxXferCount = 0U; hswpmi->State= HAL_SWPMI_STATE_READY; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) @@ -1879,16 +1925,13 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - /* Set the SWPMI state ready to be able to start again the process */ - hswpmi->State = HAL_SWPMI_STATE_READY; + /* Set the SWPMI state ready to be able to start again the process */ + hswpmi->State = HAL_SWPMI_STATE_READY; - status = HAL_TIMEOUT; - break; - } + status = HAL_TIMEOUT; + break; } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c index f9aaf91fcc..310bf4d0d5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c @@ -2550,6 +2550,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -3364,7 +3367,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, case TIM_CHANNEL_3: { /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c index 5c26d23357..2f9ce3d8d9 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c @@ -1845,6 +1845,21 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. + * + @if STM32L422xx + * For TIM1, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * + * field2 can have the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * + @endif @if STM32L486xx * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): * @@ -1908,6 +1923,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output @endif + @if STM32L422xx + * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): + * + * field1 can have the following values: + * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 + * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF + * + * field2 can have the following values: + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * + * field3 can have the following values: + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * + @endif @if STM32L443xx * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): * @@ -1967,7 +1999,34 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant * @endif - * For TIM15, the parameter is a combination of 3 fields (field1 | field2): + @if STM32L422xx + * For TIM15, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE + * + * field2 can have the following values: + * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection + * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + * + @endif + @if STM32L443xx + * For TIM15, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE + * + * field2 can have the following values: + * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection + * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + * + @endif + @if STM32L486xx + * For TIM15, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO @@ -1979,6 +2038,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * + @endif @if STM32L486xx * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI @@ -1986,6 +2046,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt * @endif + @if STM32L422xx + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt + * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) + * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source) + * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO + * + @endif @if STM32L443xx * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c index b1b72651ac..7eef3a24e6 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc) htsc->Init.AcquisitionMode); /* Spread spectrum */ - if (htsc->Init.SpreadSpectrum == ENABLE) + if ((FunctionalState)htsc->Init.SpreadSpectrum == ENABLE) { htsc->Instance->CR |= TSC_CR_SSE; } @@ -692,7 +692,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc) __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA); /* Enable max count error interrupt (optional) */ - if (htsc->Init.MaxCountInterrupt == ENABLE) + if ((FunctionalState)htsc->Init.MaxCountInterrupt == ENABLE) { __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE); } @@ -928,7 +928,7 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, uint32_t choice) /* Process locked */ __HAL_LOCK(htsc); - if (choice == ENABLE) + if ((FunctionalState)choice == ENABLE) { __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); } @@ -1102,14 +1102,14 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc) */ static uint32_t TSC_extract_groups(uint32_t iomask) { - uint32_t groups = 0U; + uint32_t groups = 0UL; uint32_t idx; - for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++) + for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++) { - if ((iomask & (0x0FU << (idx * 4U))) != RESET) + if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL ) { - groups |= (1U << idx); + groups |= (1UL << idx); } } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c index cb6ac32997..825af70256 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c @@ -242,7 +242,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); */ /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -685,7 +685,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions + * @brief USART Transmit and Receive functions * @verbatim =============================================================================== @@ -697,32 +697,34 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ [..] The USART supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). + [..] + (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (++) HAL_USART_Transmit()in simplex mode + (++) HAL_USART_Transmit() in simplex mode (++) HAL_USART_Receive() in full duplex receive only (++) HAL_USART_TransmitReceive() in full duplex mode (#) Non-Blocking mode API's with Interrupt are : - (++) HAL_USART_Transmit_IT()in simplex mode + (++) HAL_USART_Transmit_IT() in simplex mode (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT()in full duplex mode + (++) HAL_USART_TransmitReceive_IT() in full duplex mode (++) HAL_USART_IRQHandler() (#) No-Blocking mode API's with DMA are : - (++) HAL_USART_Transmit_DMA()in simplex mode + (++) HAL_USART_Transmit_DMA() in simplex mode (++) HAL_USART_Receive_DMA() in full duplex receive only (++) HAL_USART_TransmitReceive_DMA() in full duplex mode (++) HAL_USART_DMAPause() @@ -738,22 +740,22 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ (++) HAL_USART_TxRxCpltCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_USART_Abort() - (+) HAL_USART_Abort_IT() + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: - (+) HAL_USART_AbortCpltCallback() + (++) HAL_USART_AbortCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -769,8 +771,9 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; - uint32_t tickstart = 0U; + uint8_t *ptxdata8bits; + uint16_t *ptxdata16bits; + uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) { @@ -791,6 +794,18 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->TxXferSize = Size; husart->TxXferCount = Size; + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + /* Check the remaining data to be sent */ while (husart->TxXferCount > 0U) { @@ -798,15 +813,15 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa { return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t *) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pTxData += 2U; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; } husart->TxXferCount--; @@ -850,9 +865,10 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; uint16_t uhMask; - uint32_t tickstart = 0U; + uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) { @@ -877,6 +893,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + /* as long as data have to be received */ while (husart->RxXferCount > 0U) { @@ -901,15 +929,15 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (prxdata8bits == NULL) { - tmp = (uint16_t *) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData += 2U; + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + prxdata8bits++; } husart->RxXferCount--; @@ -950,9 +978,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint8_t *ptxdata8bits; + uint16_t *ptxdata16bits; uint16_t uhMask; - uint32_t tickstart = 0U; + uint16_t rxdatacount; + uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) { @@ -979,8 +1011,24 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + #if defined(USART_CR2_SLVEN) - if ((husart->SlaveMode == USART_SLAVEMODE_ENABLE) || (husart->TxXferCount == 0x01U)) + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) #else if (husart->TxXferCount == 0x01U) #endif @@ -990,22 +1038,24 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t *) pTxData; - husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2U; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)uhMask); + ptxdata8bits++; } husart->TxXferCount--; } /* Check the remain data to be sent */ - while ((husart->TxXferCount > 0U) || (husart->RxXferCount > 0U)) + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) { if (husart->TxXferCount > 0U) { @@ -1014,15 +1064,15 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t *) pTxData; - husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2U; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)uhMask); + ptxdata8bits++; } husart->TxXferCount--; @@ -1036,19 +1086,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (prxdata8bits == NULL) { - tmp = (uint16_t *) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData += 2U; + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + prxdata8bits++; } husart->RxXferCount--; } + rxdatacount = husart->RxXferCount; } /* At end of TxRx process, restore husart->State to Ready */ @@ -1147,7 +1198,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData pointer to data buffer. @@ -1157,7 +1208,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { #if defined(USART_CR1_FIFOEN) - uint8_t nb_dummy_data; + uint16_t nb_dummy_data; #endif if (husart->State == HAL_USART_STATE_READY) @@ -1373,6 +1424,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { + HAL_StatusTypeDef status = HAL_OK; uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) @@ -1392,30 +1444,49 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* Set the USART DMA transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + if(status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - return HAL_OK; + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1435,7 +1506,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp; + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; /* Check that a Rx process is not already ongoing */ if (husart->State == HAL_USART_STATE_READY) @@ -1456,52 +1528,82 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; - /* Enable the USART receive DMA channel */ - tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + } #if defined(USART_CR2_SLVEN) - if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #endif { /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ /* Set the USART DMA Tx Complete and Error callback to Null */ - husart->hdmatx->XferErrorCallback = NULL; - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } } - /* Process Unlocked */ - __HAL_UNLOCK(husart); + if(status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - return HAL_OK; + return HAL_OK; + } + else + { + if(husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1520,6 +1622,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR */ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + HAL_StatusTypeDef status = HAL_OK; uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) @@ -1540,53 +1643,82 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - /* Set the USART DMA Tx transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - /* Set the USART DMA Tx transfer error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; - /* Enable the USART receive DMA channel */ - tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + /* Enable the USART receive DMA channel */ + tmp = (uint32_t *)&pRxData; + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Enable the USART transmit DMA channel */ + if(status == HAL_OK) + { + tmp = (uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } + } + if(status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; + } + else + { + if(husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } - return HAL_OK; + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1601,17 +1733,19 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Process Locked */ __HAL_LOCK(husart); - if ((husart->State == HAL_USART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { @@ -1628,6 +1762,10 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1642,16 +1780,18 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Process Locked */ __HAL_LOCK(husart); - if (husart->State == HAL_USART_STATE_BUSY_TX) + if (state == HAL_USART_STATE_BUSY_TX) { /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); @@ -1666,6 +1806,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1694,12 +1838,36 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) /* Abort the USART DMA tx channel */ if (husart->hdmatx != NULL) { - HAL_DMA_Abort(husart->hdmatx); + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } } /* Abort the USART DMA rx channel */ if (husart->hdmarx != NULL) { - HAL_DMA_Abort(husart->hdmarx); + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } } USART_EndTransfer(husart); @@ -1743,7 +1911,19 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) No call back execution at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(husart->hdmatx); + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } } } @@ -1759,7 +1939,19 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) No call back execution at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(husart->hdmarx); + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } } } @@ -1948,6 +2140,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t cr3its = READ_REG(husart->Instance->CR3); uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ #if defined(USART_CR2_SLVEN) @@ -1955,16 +2148,16 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) #else errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); #endif - if (errorflags == RESET) + if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { if (husart->RxISR != NULL) @@ -1977,17 +2170,17 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if ((errorflags != RESET) - && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) #else - if ((errorflags != RESET) - && (((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) #endif { /* USART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); @@ -1995,7 +2188,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); @@ -2003,7 +2196,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); @@ -2012,13 +2205,13 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_ORE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) #else - if (((isrflags & USART_ISR_ORE) != RESET) - && (((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) #endif { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); @@ -2028,7 +2221,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) #if defined(USART_CR2_SLVEN) /* USART SPI slave underrun error interrupt occurred -------------------------*/ - if (((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { /* Ignore SPI slave underrun errors when reception is going on */ if (husart->State == HAL_USART_STATE_BUSY_RX) @@ -2049,12 +2242,12 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) #endif { if (husart->RxISR != NULL) @@ -2064,13 +2257,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) { /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Interrupts, and disable DMA requests, if ongoing */ + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); /* Disable the USART DMA Rx request if enabled */ @@ -2082,18 +2276,21 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) if (husart->hdmatx != NULL) { /* Set the USART Tx DMA Abort callback to NULL : no callback - executed at end of DMA abort procedure */ + executed at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; /* Abort DMA TX */ - HAL_DMA_Abort_IT(husart->hdmatx); + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + /* Nothing to do */ + } } /* Abort the USART DMA Rx channel */ if (husart->hdmarx != NULL) { /* Set the USART Rx DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; /* Abort DMA RX */ @@ -2130,7 +2327,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Error Callback */ husart->ErrorCallback(husart); @@ -2148,12 +2345,12 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET))) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else - if (((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) #endif { if (husart->TxISR != NULL) @@ -2164,7 +2361,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { USART_EndTransmit_IT(husart); return; @@ -2172,7 +2369,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) #if defined(USART_CR1_FIFOEN) /* USART TX Fifo Empty occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ @@ -2185,7 +2382,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART RX Fifo Full occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ @@ -2480,10 +2677,10 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ + in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ + clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); if (husart->State == HAL_USART_STATE_BUSY_RX) @@ -2712,7 +2909,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { husart->State = HAL_USART_STATE_READY; @@ -2733,10 +2930,10 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0U; - USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000; + uint16_t brrtemp; uint32_t usartdiv = 0x00000000; /* Check the parameters */ @@ -2768,7 +2965,6 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = 0U; tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); @@ -2823,7 +3019,6 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); #endif break; - case USART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2861,7 +3056,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2911,9 +3106,11 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) */ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { if (husart->TxXferCount == 0U) { @@ -2925,7 +3122,8 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) } else { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; husart->TxXferCount--; } } @@ -2943,10 +3141,11 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; uint16_t *tmp; - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { if (husart->TxXferCount == 0U) { @@ -2959,7 +3158,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) else { tmp = (uint16_t *) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; } @@ -2979,10 +3178,12 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) */ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint8_t nb_tx_data; + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { @@ -2998,9 +3199,14 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; husart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } @@ -3017,12 +3223,13 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; uint16_t *tmp; - uint8_t nb_tx_data; + uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { @@ -3039,10 +3246,14 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { tmp = (uint16_t *) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } @@ -3095,6 +3306,10 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + else + { + /* Nothing to do */ + } } @@ -3109,14 +3324,18 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) */ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; uint16_t uhMask = husart->Mask; - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; - if (--husart->RxXferCount == 0U) + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) @@ -3131,7 +3350,10 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - if (husart->State == HAL_USART_STATE_BUSY_RX) + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -3153,8 +3375,8 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) HAL_USART_RxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0U) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -3167,17 +3389,25 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + else + { + /* Nothing to do */ + } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) + else if (state == HAL_USART_STATE_BUSY_RX) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } @@ -3192,17 +3422,20 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; uint16_t *tmp; uint16_t uhMask = husart->Mask; - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); husart->pRxBuffPtr += 2U; + husart->RxXferCount--; - if (--husart->RxXferCount == 0U) + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) @@ -3217,7 +3450,10 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - if (husart->State == HAL_USART_STATE_BUSY_RX) + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -3239,8 +3475,8 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) HAL_USART_RxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0U) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -3253,17 +3489,25 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + else + { + /* Nothing to do */ + } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) + else if (state == HAL_USART_STATE_BUSY_RX) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } @@ -3279,20 +3523,25 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) */ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; uint16_t uhMask = husart->Mask; - uint8_t nb_rx_data; + uint16_t nb_rx_data; /* Check that a Rx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; - if (--husart->RxXferCount == 0U) + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -3303,7 +3552,10 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - if (husart->State == HAL_USART_STATE_BUSY_RX) + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -3316,6 +3568,7 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Rx Complete Callback */ @@ -3325,11 +3578,12 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) HAL_USART_RxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0U) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Tx Rx Complete Callback */ @@ -3339,17 +3593,25 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + else + { + /* Nothing to do */ + } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) + else if (state == HAL_USART_STATE_BUSY_RX) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } @@ -3357,7 +3619,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); @@ -3369,12 +3632,12 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); #if defined(USART_CR2_SLVEN) - if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX)) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ @@ -3400,13 +3663,16 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; uint16_t *tmp; uint16_t uhMask = husart->Mask; - uint8_t nb_rx_data; + uint16_t nb_rx_data; /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { @@ -3415,8 +3681,9 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); husart->pRxBuffPtr += 2U; + husart->RxXferCount--; - if (--husart->RxXferCount == 0U) + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -3427,7 +3694,10 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Clear RxISR function pointer */ husart->RxISR = NULL; - if (husart->State == HAL_USART_STATE_BUSY_RX) + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -3440,6 +3710,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Rx Complete Callback */ @@ -3449,11 +3720,12 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) HAL_USART_RxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0U) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /* Call registered Tx Rx Complete Callback */ @@ -3463,17 +3735,25 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + else + { + /* Nothing to do */ + } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) + else if (state == HAL_USART_STATE_BUSY_RX) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } @@ -3481,7 +3761,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); @@ -3493,12 +3774,12 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); #if defined(USART_CR2_SLVEN) - if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - if ((husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX)) #endif { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c index dbcf6567ec..c3aa4f7259 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c @@ -98,8 +98,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); * @{ */ -/** @defgroup USARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended USART Transmit/Receive functions +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions * @verbatim =============================================================================== @@ -151,9 +151,9 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) * @} */ -/** @defgroup USARTEx_Exported_Functions_Group3 Peripheral Control functions +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -190,7 +190,7 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); @@ -238,7 +238,7 @@ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); @@ -286,7 +286,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); @@ -326,7 +326,7 @@ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NS */ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); @@ -367,7 +367,7 @@ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); @@ -413,7 +413,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); @@ -462,7 +462,7 @@ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, ui */ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); @@ -523,8 +523,9 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { @@ -535,10 +536,10 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - husart->NbTxDataToProcess = (tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = (rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c index 3ad5ed650d..e9ec2cfcde 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c @@ -41,7 +41,7 @@ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) + #define assert_param(expr) ((void)0UL) #endif /** @addtogroup STM32L4xx_LL_Driver @@ -80,9 +80,9 @@ /* with highest ratio CPU clock frequency vs HSI clock frequency: */ /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */ /* Unit: CPU cycles. */ -#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) -#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) -#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) /** * @} @@ -374,7 +374,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 serie, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) + if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -471,13 +471,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; - __IO uint32_t timeout_cpu_cycles = 0U; + __IO uint32_t timeout_cpu_cycles = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1U) + if(LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ @@ -485,9 +485,9 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) + if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) + if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } @@ -499,9 +499,9 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); /* Stop potential ADC conversion on going on ADC group injected. */ - if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U) + if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U) + if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } @@ -510,10 +510,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) - | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U) + | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0U) + if(timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; @@ -530,10 +530,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; - while (LL_ADC_IsDisableOngoing(ADCx) == 1U) + while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0U) + if(timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; @@ -546,7 +546,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) ) - == 0U) + == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ @@ -561,7 +561,8 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 - | LL_ADC_IT_AWD3 ) + | LL_ADC_IT_AWD3 + ) ); /* Reset register ISR */ @@ -576,7 +577,8 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 - | LL_ADC_FLAG_AWD3 ) + | LL_ADC_FLAG_AWD3 + ) ); /* Reset register CR */ @@ -751,7 +753,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if(LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ @@ -843,7 +845,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if(LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -974,7 +976,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if(LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c index a6ef78cfbe..431d8f79c7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c @@ -131,10 +131,11 @@ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) +#if defined(COMP2) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ ? ( \ - (1U) \ + (1UL) \ ) \ : \ (((__COMP_INSTANCE__) == COMP1) \ @@ -151,7 +152,34 @@ ) \ ) \ ) - +#else +#if defined(TIM3) +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1UL) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) \ + ) +#else +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1UL) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + ) \ + ) +#endif /* TIM3 */ +#endif /* COMP2 */ /** * @} */ @@ -188,9 +216,9 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) /* Note: Hardware constraint (refer to description of this function): */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if(LL_COMP_IsLocked(COMPx) == 0UL) { - LL_COMP_WriteReg(COMPx, CSR, 0x00000000U); + LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL); } else @@ -231,7 +259,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if(LL_COMP_IsLocked(COMPx) == 0UL) { /* Configuration of comparator instance : */ /* - PowerMode */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c index 9de1dd6968..2d6b9e9ed8 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c @@ -64,13 +64,13 @@ */ #if defined(DAC_CHANNEL2_SUPPORT) -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ +#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #else -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ +#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ ) @@ -86,8 +86,8 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) @@ -110,8 +110,9 @@ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ - ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ + ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ @@ -122,8 +123,10 @@ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ @@ -134,7 +137,8 @@ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ @@ -180,26 +184,37 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); - + /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); - + /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); - + return SUCCESS; } /** - * @brief Initialize some features of DAC instance. + * @brief Initialize some features of DAC channel. + * @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel. + * Leaving it ready to be enabled and output: + * a level by calling one of + * @ref LL_DAC_ConvertData12RightAligned + * @ref LL_DAC_ConvertData12LeftAligned + * @ref LL_DAC_ConvertData8RightAligned + * or one of the supported autogenerated wave. + * @note This function allows configuration of: + * - Output mode + * - Trigger + * - Wave generation * @note The setting of these parameters by function @ref LL_DAC_Init() * is conditioned to DAC state: - * DAC instance must be disabled. + * DAC channel must be disabled. * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure @@ -210,10 +225,10 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); - assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); + assert_param(IS_LL_DAC_CHANNEL(DAC_Channel)); assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection)); @@ -221,9 +236,9 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, DAC_InitStruct->WaveAutoGenerationConfig)); } - + /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) @@ -260,7 +275,7 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } - + MODIFY_REG(DACx->MCR, ( DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0 diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c index 6ceb3ee639..b345ddecda 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

          © COPYRIGHT(c) 2016 STMicroelectronics

          + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -176,7 +176,7 @@ * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; ErrorStatus status = SUCCESS; @@ -230,7 +230,7 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) #if defined(DMAMUX1) /* Reset Request register field for DMAx Channel */ - LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQUEST_MEM2MEM); + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); #else /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); @@ -300,7 +300,7 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) * - SUCCESS: DMA registers are initialized * - ERROR: Not applicable */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) { /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); @@ -389,7 +389,7 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; DMA_InitStruct->NbData = 0x00000000U; #if defined(DMAMUX1) - DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQUEST_MEM2MEM; + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM; #else DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; #endif /* DMAMUX1 */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c index 57c6f1a46e..96f2747052 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c @@ -91,8 +91,7 @@ /** * @brief De-initialize the EXTI registers to their default reset values. * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable + * - 0x00: EXTI registers are de-initialized */ uint32_t LL_EXTI_DeInit(void) { @@ -126,19 +125,20 @@ uint32_t LL_EXTI_DeInit(void) /* Pending register 2 clear */ LL_EXTI_WriteReg(PR2, 0x00000078U); - return SUCCESS; + return 0x00u; } /** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable + * - 0x00: EXTI registers are initialized + * - any other calue : wrong configuration */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { - ErrorStatus status = SUCCESS; + uint32_t status = 0x00u; + /* Check the parameters */ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); @@ -173,7 +173,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; default: - status = ERROR; + status = 0x01u; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) @@ -197,7 +197,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; default: - status = ERROR; + status |= 0x02u; break; } } @@ -225,7 +225,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); break; default: - status = ERROR; + status |= 0x04u; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) @@ -265,6 +265,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); } + return status; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c index e83fb04c7d..6f69259ee5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c @@ -52,6 +52,11 @@ /** @addtogroup GPIO_LL * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -60,7 +65,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -193,7 +198,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -201,8 +206,8 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { - uint32_t pinpos = 0x00000000U; - uint32_t currentpin = 0x00000000U; + uint32_t pinpos; + uint32_t currentpin; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -215,12 +220,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru pinpos = POSITION_VAL(GPIO_InitStruct->Pin); /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) { /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); - if (currentpin) + if (currentpin != 0x00u) { /* Pin Mode configuration */ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); @@ -243,7 +248,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); /* Speed mode configuration */ - if (POSITION_VAL(currentpin) < 0x00000008U) + if (currentpin < LL_GPIO_PIN_8) { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); } @@ -270,7 +275,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c index 85c2079661..fe870838f7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c @@ -100,7 +100,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -160,7 +160,7 @@ uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c index d8b0a8484c..8ec215b87e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c @@ -105,16 +105,16 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) ErrorStatus result = SUCCESS; /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + if (LPTIMx == LPTIM1) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); - } + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); + } #if defined(LPTIM2) else if (LPTIMx == LPTIM2) - { + { LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); } @@ -123,7 +123,7 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) { result = ERROR; } - + return result; } @@ -155,8 +155,8 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct) { ErrorStatus result = SUCCESS; - - /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + + /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to 0). */ if (LL_LPTIM_IsEnabled(LPTIMx)) @@ -166,18 +166,18 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In else { /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); - + /* Set CKSEL bitfield according to ClockSource value */ /* Set PRESC bitfield according to Prescaler value */ /* Set WAVE bitfield according to Waveform value */ /* Set WAVEPOL bitfield according to Polarity value */ - MODIFY_REG(LPTIMx->CFGR, - (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), LPTIM_InitStruct->ClockSource | \ LPTIM_InitStruct->Prescaler | \ LPTIM_InitStruct->Waveform | \ @@ -204,7 +204,7 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In /** * @} */ - + #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c index e6b0e76423..48a892cef8 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c @@ -121,10 +121,10 @@ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx)); - + LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U); return status; @@ -153,7 +153,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode)); assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode)); assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting)); - + /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */ /* or PGA with external capacitors for filtering circuit. */ /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */ @@ -162,7 +162,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini { assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting)); } - + /* Configuration of OPAMP instance : */ /* - PowerMode */ /* - Functional mode */ @@ -199,7 +199,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini | LL_OPAMP_INPUT_INVERT_CONNECT_NO ); } - + return SUCCESS; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c index 6df00afc43..c2fe7c4b01 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c @@ -99,19 +99,20 @@ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) -#if defined(RCC_CCIPR_SAI2SEL) +#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) -#else +#elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) #endif /* RCC_CCIPR2_SDMMCSEL */ #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) - +#endif /* SDMMC1 */ #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) @@ -159,9 +160,11 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); uint32_t RCC_PLL_GetFreqDomain_SYS(void); uint32_t RCC_PLL_GetFreqDomain_SAI(void); uint32_t RCC_PLL_GetFreqDomain_48M(void); +#if defined(RCC_PLLSAI1_SUPPORT) uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); #if defined(LTDC) @@ -204,7 +207,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); */ ErrorStatus LL_RCC_DeInit(void) { - uint32_t vl_mask = 0U; + uint32_t vl_mask; /* Set MSION bit */ LL_RCC_MSI_Enable(); @@ -232,8 +235,10 @@ ErrorStatus LL_RCC_DeInit(void) CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); +#if defined(RCC_PLLSAI1_SUPPORT) /* Reset PLLSAI1ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON); +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2ON bit */ @@ -248,18 +253,25 @@ ErrorStatus LL_RCC_DeInit(void) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) { } -#else - /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ +#elif defined(RCC_PLLSAI1_SUPPORT) + /* Wait for PLLRDY and PLLSAI1RDY to be reset */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) { } +#else + /* Wait for PLLRDY bit to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + } #endif /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); +#if defined(RCC_PLLSAI1_SUPPORT) /* Reset PLLSAI1CFGR register */ LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos); +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2CFGR register */ @@ -274,10 +286,13 @@ ErrorStatus LL_RCC_DeInit(void) /* Clear all interrupt flags */ vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ - RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; + RCC_CICR_CSSC | RCC_CICR_LSECSSC; #if defined(RCC_HSI48_SUPPORT) vl_mask |= RCC_CICR_HSI48RDYC; #endif +#if defined(RCC_PLLSAI1_SUPPORT) + vl_mask |= RCC_CICR_PLLSAI1RDYC; +#endif #if defined(RCC_PLLSAI2_SUPPORT) vl_mask |= RCC_CICR_PLLSAI2RDYC; #endif @@ -369,23 +384,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ - default: usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) @@ -398,23 +415,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ - default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else @@ -430,23 +449,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ - default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_USART3SEL */ @@ -481,23 +502,25 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ - default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_UART4SEL */ @@ -513,23 +536,25 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ - default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_UART5SEL */ @@ -567,16 +592,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #if defined(RCC_CCIPR_I2C2SEL) @@ -590,16 +617,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /*RCC_CCIPR_I2C2SEL*/ @@ -615,16 +644,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #if defined(RCC_CCIPR2_I2C4SEL) @@ -640,16 +671,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } } @@ -682,23 +715,25 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) break; case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lpuart_frequency = HSI_VALUE; } break; case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lpuart_frequency = LSE_VALUE; } break; case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ - default: lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return lpuart_frequency; @@ -725,30 +760,32 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady()) + if (LL_RCC_LSI_IsReady() != 0U) { lptim_frequency = LSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ - default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else @@ -759,30 +796,32 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady()) + if (LL_RCC_LSI_IsReady() != 0U) { lptim_frequency = LSI_VALUE; } break; case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ - default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } } @@ -790,6 +829,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) return lptim_frequency; } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL) /** * @brief Return SAIx clock frequency * @param SAIxSource This parameter can be one of the following values: @@ -814,7 +854,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } @@ -822,7 +862,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) #if defined(RCC_PLLSAI2_SUPPORT) case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); } @@ -830,7 +870,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) #endif /* RCC_PLLSAI2_SUPPORT */ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sai_frequency = RCC_PLL_GetFreqDomain_SAI(); } @@ -846,30 +886,30 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) } else { -#if defined(RCC_CCIPR_SAI2SEL) +#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL) if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) { /* SAI2CLK clock frequency */ switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } break; - #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); } break; - #endif /* RCC_PLLSAI2_SUPPORT */ +#endif /* RCC_PLLSAI2_SUPPORT */ case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sai_frequency = RCC_PLL_GetFreqDomain_SAI(); } @@ -883,12 +923,14 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) break; } } -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */ } return sai_frequency; } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** * @brief Return SDMMCx kernel clock frequency @@ -913,7 +955,7 @@ uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) break; case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI(); } @@ -948,7 +990,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) { #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1) case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } @@ -956,7 +998,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #endif case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); } @@ -964,10 +1006,10 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI) case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -976,7 +1018,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #if defined(RCC_HSI48_SUPPORT) case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ - if (LL_RCC_HSI48_IsReady()) + if (LL_RCC_HSI48_IsReady() != 0U) { sdmmc_frequency = HSI48_VALUE; } @@ -991,6 +1033,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) return sdmmc_frequency; } +#endif /* SDMMC1 */ /** * @brief Return RNGx clock frequency @@ -1010,25 +1053,27 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) /* RNGCLK clock frequency */ switch (LL_RCC_GetRNGClockSource(RNGxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { rng_frequency = RCC_PLL_GetFreqDomain_48M(); } break; case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1037,7 +1082,7 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) #if defined(RCC_HSI48_SUPPORT) case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */ - if (LL_RCC_HSI48_IsReady()) + if (LL_RCC_HSI48_IsReady() != 0U) { rng_frequency = HSI48_VALUE; } @@ -1074,25 +1119,27 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) /* USBCLK clock frequency */ switch (LL_RCC_GetUSBClockSource(USBxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { usb_frequency = RCC_PLL_GetFreqDomain_48M(); } break; case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1100,7 +1147,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) #if defined(RCC_HSI48_SUPPORT) case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */ - if (LL_RCC_HSI48_IsReady()) + if (LL_RCC_HSI48_IsReady() != 0U) { usb_frequency = HSI48_VALUE; } @@ -1135,16 +1182,18 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) /* ADCCLK clock frequency */ switch (LL_RCC_GetADCClockSource(ADCxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2) case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC(); } @@ -1154,6 +1203,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ adc_frequency = RCC_GetSystemClockFreq(); break; + case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */ default: adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; @@ -1189,9 +1239,11 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource) break; case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */ - default: swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return swpmi_frequency; @@ -1220,9 +1272,11 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ - default: dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return dfsdm_frequency; @@ -1251,10 +1305,10 @@ uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1262,7 +1316,7 @@ uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */ default: - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { dfsdm_frequency = HSI_VALUE; } @@ -1294,7 +1348,7 @@ uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) switch (LL_RCC_GetDSIClockSource(DSIxSource)) { case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI(); } @@ -1325,7 +1379,7 @@ uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) /* Check parameter */ assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC(); } @@ -1357,17 +1411,17 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) break; case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } break; case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { octospi_frequency = RCC_PLL_GetFreqDomain_48M(); } @@ -1400,14 +1454,14 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) */ uint32_t RCC_GetSystemClockFreq(void) { - uint32_t frequency = 0U; + uint32_t frequency; /* Get SYSCLK source -------------------------------------------------------*/ switch (LL_RCC_GetSysClkSource()) { case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1426,7 +1480,7 @@ uint32_t RCC_GetSystemClockFreq(void) default: frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1474,7 +1528,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR @@ -1485,7 +1539,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1500,7 +1554,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1508,13 +1562,15 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); } + +#if defined(SAI1) /** * @brief Return PLL clock frequency used for SAI domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN SAI Domain clock = PLL_VCO / PLLP @@ -1525,7 +1581,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1540,7 +1596,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1548,6 +1604,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); } +#endif /* SAI1 */ /** * @brief Return PLL clock frequency used for 48 MHz domain @@ -1555,7 +1612,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) */ uint32_t RCC_PLL_GetFreqDomain_48M(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 48M Domain clock = PLL_VCO / PLLQ @@ -1566,7 +1623,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1581,7 +1638,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1596,7 +1653,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ /* DSICLK = PLLSAI2_VCO / PLLSAI2R */ @@ -1606,7 +1663,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1621,7 +1678,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1632,13 +1689,14 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) } #endif /* DSI */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Return PLLSAI1 clock frequency used for SAI domain * @retval PLLSAI1 clock frequency (in Hz) */ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1652,7 +1710,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1667,7 +1725,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1682,7 +1740,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) */ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1696,7 +1754,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1711,7 +1769,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1726,7 +1784,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) */ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1740,7 +1798,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1755,7 +1813,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1763,6 +1821,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR()); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -1771,7 +1830,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ @@ -1785,7 +1844,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1800,7 +1859,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1821,7 +1880,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */ @@ -1831,7 +1890,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1846,7 +1905,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1874,7 +1933,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1889,7 +1948,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c index 3e32d80451..35469732ed 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c @@ -176,17 +176,13 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) if (LL_RTC_EnterInitMode(RTCx) != ERROR) { /* Reset TR, DR and CR registers */ - LL_RTC_WriteReg(RTCx, TR, 0x00000000U); -#if defined(RTC_WAKEUP_SUPPORT) - LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + LL_RTC_WriteReg(RTCx, TR, 0x00000000U); + + LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); + LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); /* Reset All CR bits except CR[2:0] */ -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); -#else - LL_RTC_WriteReg(RTCx, CR, 0x00000000U); -#endif /* RTC_WAKEUP_SUPPORT */ + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); @@ -195,6 +191,8 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); +#if defined(STM32L412xx) || defined(STM32L422xx) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Reset ISR register and exit initialization mode */ LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); @@ -203,6 +201,7 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) /* Reset Option register */ LL_RTC_WriteReg(RTCx, OR, 0x00000000U); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Wait till the RTC RSF flag is set */ status = LL_RTC_WaitForSynchro(RTCx); @@ -398,7 +397,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) { - RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + RTC_DateStruct->Month = (uint8_t)((RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU); } if (RTC_Format == LL_RTC_FORMAT_BIN) { @@ -757,7 +756,7 @@ ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) { __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; + uint32_t tmp; /* Check the parameter */ assert_param(IS_RTC_ALL_INSTANCE(RTCx)); @@ -828,7 +827,7 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) { __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; + uint32_t tmp; /* Check the parameter */ assert_param(IS_RTC_ALL_INSTANCE(RTCx)); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c index 42c07e240b..c13a8a2014 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c @@ -61,7 +61,7 @@ * @{ */ -#define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63)) +#define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63U)) #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \ || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) @@ -96,13 +96,22 @@ */ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) { + ErrorStatus status = SUCCESS; + /* Check the parameter */ assert_param(IS_SWPMI_INSTANCE(SWPMIx)); - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1); + if (SWPMIx == SWPMI1) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1); + } + else + { + status = ERROR; + } - return SUCCESS; + return status; } /** @@ -128,7 +137,7 @@ ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_Ini assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass)); /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */ - if (LL_SWPMI_IsActivated(SWPMIx) == 0) + if (LL_SWPMI_IsActivated(SWPMIx) == 0U) { /* Configure the BRR register (Bitrate) */ LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c index c74e669125..ee454553f7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c @@ -132,7 +132,7 @@ || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ || ((__VALUE__) == LL_RCC_PLLM_DIV_8)) -#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ @@ -202,20 +202,22 @@ void LL_Init1msTick(uint32_t HCLKFrequency) void LL_mDelay(uint32_t Delay) { __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + uint32_t tmpDelay = Delay; + /* Add this code to indicate that local variable is not used */ ((void)tmp); /* Add a period to guaranty minimum wait */ - if(Delay < LL_MAX_DELAY) + if(tmpDelay < LL_MAX_DELAY) { - Delay++; + tmpDelay++; } - while (Delay) + while (tmpDelay != 0U) { if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) { - Delay--; + tmpDelay--; } } } @@ -234,7 +236,7 @@ void LL_mDelay(uint32_t Delay) [..] System, AHB and APB buses clocks configuration - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others. @endverbatim @internal @@ -315,16 +317,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U, msi_range = 0U; + uint32_t pllfreq, msi_range; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) { /* Get the current MSI range */ - if(LL_RCC_MSI_IsEnabledRangeSelect()) + if(LL_RCC_MSI_IsEnabledRangeSelect() != 0U) { msi_range = LL_RCC_MSI_GetRange(); switch (msi_range) @@ -440,10 +442,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; + ErrorStatus status; + uint32_t pllfreq; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check if one of the PLL is enabled */ @@ -521,10 +523,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; + ErrorStatus status; + uint32_t pllfreq; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check the parameters */ @@ -746,7 +748,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) { - uint32_t pllfreq = 0U; + uint32_t pllfreq; /* Check the parameters */ assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); @@ -755,7 +757,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL /* Check different PLL parameters according to RM */ /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */ - pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1)); + pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U)); assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/ @@ -763,7 +765,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); /* - PLLR: ensure that max frequency at 120000000 Hz is reached */ - pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2); + pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U); assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); return pllfreq; @@ -786,12 +788,14 @@ static ErrorStatus UTILS_PLL_IsBusy(void) status = ERROR; } +#if defined(RCC_PLLSAI1_SUPPORT) /* Check if PLLSAI1 is busy*/ if(LL_RCC_PLLSAI1_IsReady() != 0U) { /* PLLSAI1 configuration cannot be modified */ status = ERROR; } +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Check if PLLSAI2 is busy*/ @@ -817,7 +821,7 @@ static ErrorStatus UTILS_PLL_IsBusy(void) static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; - uint32_t hclk_frequency = 0U; + uint32_t hclk_frequency; assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); @@ -856,7 +860,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); } - + /* Decreasing the number of wait states because of lower CPU frequency */ if(SystemCoreClock > hclk_frequency) { diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index adc62a657b..d91c2be1cf 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.6 * STM32L0: 1.8.2 * STM32L1: 1.3.1 - * STM32L4: 1.8.3 + * STM32L4: 1.9.0 Release notes of each STM32YYxx HAL Drivers available here: From 58eefa89c98ed33b0c950ae759c4c39cb3d2854a Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 15:46:44 +0200 Subject: [PATCH 054/109] Add new stm32 HAL wrapper file Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c diff --git a/cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c b/cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c new file mode 100644 index 0000000000..08379813f9 --- /dev/null +++ b/cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c @@ -0,0 +1,3 @@ +#ifdef STM32L4xx +#include "stm32l4xx_hal_exti.c" +#endif From 0772231b4683d57e527cc199cef3ee5f6048a20b Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 15:49:55 +0200 Subject: [PATCH 055/109] Update STM32L4xx CMSIS to v1.5.0 Included in STM32CubeL4 FW V1.13.0 Signed-off-by: Frederic.Pillon --- .../Device/ST/STM32L4xx/Include/stm32l412xx.h | 10907 +++++++++++++++ .../Device/ST/STM32L4xx/Include/stm32l422xx.h | 11135 ++++++++++++++++ .../Device/ST/STM32L4xx/Include/stm32l431xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l432xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l433xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l442xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l443xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l451xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l452xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l462xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l471xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l475xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l476xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l485xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l486xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l496xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l4a6xx.h | 11 +- .../Device/ST/STM32L4xx/Include/stm32l4r5xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4r7xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4r9xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4s5xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4s7xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4s9xx.h | 9 +- .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 15 +- .../Device/ST/STM32L4xx/Release_Notes.html | 347 +- .../Templates/gcc/startup_stm32l412xx.s | 447 + .../Templates/gcc/startup_stm32l422xx.s | 450 + .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 28 files changed, 23288 insertions(+), 234 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l422xx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h new file mode 100644 index 0000000000..4cb4f5b003 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h @@ -0,0 +1,10907 @@ +/** + ****************************************************************************** + * @file stm32l412xx.h + * @author MCD Application Team + * @brief CMSIS STM32L412xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l412xx + * @{ + */ + +#ifndef __STM32L412xx_H +#define __STM32L412xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 Interrupt */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + USB_IRQn = 67, /*!< USB event Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + CRS_IRQn = 82 /*!< CRS global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ +} FLASH_TypeDef; + + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM repetition counter register, Address offset: 0x28 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[7];/*!< Reserved, Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48];/*!< Reserved, Address offset: 0x40 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 128 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(8 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */ +#define SRAM2_SIZE (0x00002000UL) /*!< SRAM2 size (8 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) + + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) + + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + + +/******************* Bit definition for DMA_CSELR register *******************/ +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ + +/******************* Bit definition for EXTI_IMR2 register ******************/ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM_Pos (0U) +#define EXTI_IMR2_IM_Msk (0x6BUL << EXTI_IMR2_IM_Pos) /*!< 0x0000006B */ +#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */ + +/******************* Bit definition for EXTI_EMR2 register ******************/ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */ +#define EXTI_EMR2_EM37_Pos (5U) +#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ +#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */ +#define EXTI_EMR2_EM38_Pos (6U) +#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ +#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */ +#define EXTI_EMR2_EM_Pos (0U) +#define EXTI_EMR2_EM_Msk (0x6BUL << EXTI_EMR2_EM_Pos) /*!< 0x0000006B */ +#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT35_Pos (3U) +#define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */ +#define EXTI_RTSR2_RT37_Pos (5U) +#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */ +#define EXTI_RTSR2_RT38_Pos (6U) +#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT35_Pos (3U) +#define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */ +#define EXTI_FTSR2_FT37_Pos (5U) +#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */ +#define EXTI_FTSR2_FT38_Pos (6U) +#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI35_Pos (3U) +#define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */ +#define EXTI_SWIER2_SWI37_Pos (5U) +#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */ +#define EXTI_SWIER2_SWI38_Pos (6U) +#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF35_Pos (3U) +#define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */ +#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */ +#define EXTI_PR2_PIF37_Pos (5U) +#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */ +#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */ +#define EXTI_PR2_PIF38_Pos (6U) +#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */ +#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk +#define FLASH_ACR_RUN_PD_Pos (13U) +#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk +#define FLASH_SR_PEMPTY_Pos (17U) +#define FLASH_SR_PEMPTY_Msk (0x1UL << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */ +#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk +#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */ +#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */ +#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + +/****************** Bits definition for FLASH_PCROP1SR register **********/ +#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U) +#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00003FFF */ +#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1ER register ***********/ +#define FLASH_PCROP1ER_PCROP1_END_Pos (0U) +#define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00003FFF */ +#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk +#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRPB1R register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODE0 +#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0 +#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1 +#define GPIO_MODER_MODER1 GPIO_MODER_MODE1 +#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0 +#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1 +#define GPIO_MODER_MODER2 GPIO_MODER_MODE2 +#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0 +#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1 +#define GPIO_MODER_MODER3 GPIO_MODER_MODE3 +#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0 +#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1 +#define GPIO_MODER_MODER4 GPIO_MODER_MODE4 +#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0 +#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1 +#define GPIO_MODER_MODER5 GPIO_MODER_MODE5 +#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0 +#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1 +#define GPIO_MODER_MODER6 GPIO_MODER_MODE6 +#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0 +#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1 +#define GPIO_MODER_MODER7 GPIO_MODER_MODE7 +#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0 +#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1 +#define GPIO_MODER_MODER8 GPIO_MODER_MODE8 +#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0 +#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1 +#define GPIO_MODER_MODER9 GPIO_MODER_MODE9 +#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0 +#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1 +#define GPIO_MODER_MODER10 GPIO_MODER_MODE10 +#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0 +#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1 +#define GPIO_MODER_MODER11 GPIO_MODER_MODE11 +#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0 +#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1 +#define GPIO_MODER_MODER12 GPIO_MODER_MODE12 +#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0 +#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1 +#define GPIO_MODER_MODER13 GPIO_MODER_MODE13 +#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0 +#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1 +#define GPIO_MODER_MODER14 GPIO_MODER_MODE14 +#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0 +#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1 +#define GPIO_MODER_MODER15 GPIO_MODER_MODE15 +#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0 +#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1 + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/* Legacy defines */ +#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 +#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 +#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 +#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 +#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 +#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 +#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 +#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 +#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 +#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 +#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 +#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 +#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 +#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 +#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 +#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 +#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 +#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 +#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 +#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 +#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 +#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 +#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 +#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 +#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 +#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 +#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 +#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 +#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 +#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 +#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 +#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 +#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 +#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 +#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 +#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 +#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 +#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 +#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 +#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 +#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 +#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 +#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 +#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 +#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 +#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 +#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 +#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/* Legacy defines */ +#define GPIO_IDR_IDR_0 GPIO_IDR_ID0 +#define GPIO_IDR_IDR_1 GPIO_IDR_ID1 +#define GPIO_IDR_IDR_2 GPIO_IDR_ID2 +#define GPIO_IDR_IDR_3 GPIO_IDR_ID3 +#define GPIO_IDR_IDR_4 GPIO_IDR_ID4 +#define GPIO_IDR_IDR_5 GPIO_IDR_ID5 +#define GPIO_IDR_IDR_6 GPIO_IDR_ID6 +#define GPIO_IDR_IDR_7 GPIO_IDR_ID7 +#define GPIO_IDR_IDR_8 GPIO_IDR_ID8 +#define GPIO_IDR_IDR_9 GPIO_IDR_ID9 +#define GPIO_IDR_IDR_10 GPIO_IDR_ID10 +#define GPIO_IDR_IDR_11 GPIO_IDR_ID11 +#define GPIO_IDR_IDR_12 GPIO_IDR_ID12 +#define GPIO_IDR_IDR_13 GPIO_IDR_ID13 +#define GPIO_IDR_IDR_14 GPIO_IDR_ID14 +#define GPIO_IDR_IDR_15 GPIO_IDR_ID15 + +/* Old GPIO_IDR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0 +#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1 +#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2 +#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3 +#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4 +#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5 +#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6 +#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7 +#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8 +#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9 +#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10 +#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11 +#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12 +#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13 +#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14 +#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15 + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/* Legacy defines */ +#define GPIO_ODR_ODR_0 GPIO_ODR_OD0 +#define GPIO_ODR_ODR_1 GPIO_ODR_OD1 +#define GPIO_ODR_ODR_2 GPIO_ODR_OD2 +#define GPIO_ODR_ODR_3 GPIO_ODR_OD3 +#define GPIO_ODR_ODR_4 GPIO_ODR_OD4 +#define GPIO_ODR_ODR_5 GPIO_ODR_OD5 +#define GPIO_ODR_ODR_6 GPIO_ODR_OD6 +#define GPIO_ODR_ODR_7 GPIO_ODR_OD7 +#define GPIO_ODR_ODR_8 GPIO_ODR_OD8 +#define GPIO_ODR_ODR_9 GPIO_ODR_OD9 +#define GPIO_ODR_ODR_10 GPIO_ODR_OD10 +#define GPIO_ODR_ODR_11 GPIO_ODR_OD11 +#define GPIO_ODR_ODR_12 GPIO_ODR_OD12 +#define GPIO_ODR_ODR_13 GPIO_ODR_OD13 +#define GPIO_ODR_ODR_14 GPIO_ODR_OD14 +#define GPIO_ODR_ODR_15 GPIO_ODR_OD15 + +/* Old GPIO_ODR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0 +#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1 +#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2 +#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3 +#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4 +#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5 +#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6 +#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7 +#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8 +#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9 +#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10 +#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11 +#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12 +#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13 +#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14 +#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15 + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/* Legacy defines */ +#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 +#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 +#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 +#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 +#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 +#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 +#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 +#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 +#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 +#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 +#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 +#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 +#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 +#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 +#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 +#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 +#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 +#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 +#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 +#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 +#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 +#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 +#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 +#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 +#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 +#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 +#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 +#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 +#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 +#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 +#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 +#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/* Legacy defines */ +#define GPIO_BRR_BR_0 GPIO_BRR_BR0 +#define GPIO_BRR_BR_1 GPIO_BRR_BR1 +#define GPIO_BRR_BR_2 GPIO_BRR_BR2 +#define GPIO_BRR_BR_3 GPIO_BRR_BR3 +#define GPIO_BRR_BR_4 GPIO_BRR_BR4 +#define GPIO_BRR_BR_5 GPIO_BRR_BR5 +#define GPIO_BRR_BR_6 GPIO_BRR_BR6 +#define GPIO_BRR_BR_7 GPIO_BRR_BR7 +#define GPIO_BRR_BR_8 GPIO_BRR_BR8 +#define GPIO_BRR_BR_9 GPIO_BRR_BR9 +#define GPIO_BRR_BR_10 GPIO_BRR_BR10 +#define GPIO_BRR_BR_11 GPIO_BRR_BR11 +#define GPIO_BRR_BR_12 GPIO_BRR_BR12 +#define GPIO_BRR_BR_13 GPIO_BRR_BR13 +#define GPIO_BRR_BR_14 GPIO_BRR_BR14 +#define GPIO_BRR_BR_15 GPIO_BRR_BR15 + + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!
          © COPYRIGHT(c) 2017 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l422xx + * @{ + */ + +#ifndef __STM32L422xx_H +#define __STM32L422xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 Interrupt */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + USB_IRQn = 67, /*!< USB event Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 79, /*!< AES global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + CRS_IRQn = 82 /*!< CRS global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ +} FLASH_TypeDef; + + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM repetition counter register, Address offset: 0x28 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[7];/*!< Reserved, Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48];/*!< Reserved, Address offset: 0x40 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 128 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 32 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(8 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */ +#define SRAM2_SIZE (0x00002000UL) /*!< SRAM2 size (8 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) + + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + + +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) + + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + + +/******************* Bit definition for DMA_CSELR register *******************/ +#define DMA_CSELR_C1S_Pos (0U) +#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ +#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ +#define DMA_CSELR_C2S_Pos (4U) +#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ +#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ +#define DMA_CSELR_C3S_Pos (8U) +#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ +#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ +#define DMA_CSELR_C4S_Pos (12U) +#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ +#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ +#define DMA_CSELR_C5S_Pos (16U) +#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ +#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ +#define DMA_CSELR_C6S_Pos (20U) +#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ +#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ +#define DMA_CSELR_C7S_Pos (24U) +#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ +#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM27_Pos (27U) +#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ +#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM20_Pos (20U) +#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM24_Pos (24U) +#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ +#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM27_Pos (27U) +#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ +#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR1_RT19_Pos (19U) +#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR1_RT20_Pos (20U) +#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR1_RT21_Pos (21U) +#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR1_FT19_Pos (19U) +#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR1_FT20_Pos (20U) +#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR1_FT21_Pos (21U) +#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER1_SWI19_Pos (19U) +#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER1_SWI20_Pos (20U) +#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER1_SWI21_Pos (21U) +#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ + +/******************* Bit definition for EXTI_PR1 register *******************/ +#define EXTI_PR1_PIF0_Pos (0U) +#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ +#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR1_PIF1_Pos (1U) +#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ +#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR1_PIF2_Pos (2U) +#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ +#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR1_PIF3_Pos (3U) +#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ +#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR1_PIF4_Pos (4U) +#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ +#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR1_PIF5_Pos (5U) +#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ +#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR1_PIF6_Pos (6U) +#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ +#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR1_PIF7_Pos (7U) +#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ +#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR1_PIF8_Pos (8U) +#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ +#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR1_PIF9_Pos (9U) +#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ +#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR1_PIF10_Pos (10U) +#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ +#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR1_PIF11_Pos (11U) +#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ +#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR1_PIF12_Pos (12U) +#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ +#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR1_PIF13_Pos (13U) +#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ +#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR1_PIF14_Pos (14U) +#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ +#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR1_PIF15_Pos (15U) +#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ +#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR1_PIF16_Pos (16U) +#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ +#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR1_PIF18_Pos (18U) +#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ +#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR1_PIF19_Pos (19U) +#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ +#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR1_PIF20_Pos (20U) +#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ +#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR1_PIF21_Pos (21U) +#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ +#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ + +/******************* Bit definition for EXTI_IMR2 register ******************/ +#define EXTI_IMR2_IM32_Pos (0U) +#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ +#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */ +#define EXTI_IMR2_IM33_Pos (1U) +#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ +#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */ +#define EXTI_IMR2_IM35_Pos (3U) +#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ +#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */ +#define EXTI_IMR2_IM37_Pos (5U) +#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ +#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ +#define EXTI_IMR2_IM38_Pos (6U) +#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ +#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */ +#define EXTI_IMR2_IM_Pos (0U) +#define EXTI_IMR2_IM_Msk (0x6BUL << EXTI_IMR2_IM_Pos) /*!< 0x0000006B */ +#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */ + +/******************* Bit definition for EXTI_EMR2 register ******************/ +#define EXTI_EMR2_EM32_Pos (0U) +#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ +#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */ +#define EXTI_EMR2_EM33_Pos (1U) +#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ +#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ +#define EXTI_EMR2_EM35_Pos (3U) +#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ +#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */ +#define EXTI_EMR2_EM37_Pos (5U) +#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ +#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */ +#define EXTI_EMR2_EM38_Pos (6U) +#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ +#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */ +#define EXTI_EMR2_EM_Pos (0U) +#define EXTI_EMR2_EM_Msk (0x6BUL << EXTI_EMR2_EM_Pos) /*!< 0x0000006B */ +#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */ + +/****************** Bit definition for EXTI_RTSR2 register ******************/ +#define EXTI_RTSR2_RT35_Pos (3U) +#define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */ +#define EXTI_RTSR2_RT37_Pos (5U) +#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */ +#define EXTI_RTSR2_RT38_Pos (6U) +#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */ + +/****************** Bit definition for EXTI_FTSR2 register ******************/ +#define EXTI_FTSR2_FT35_Pos (3U) +#define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */ +#define EXTI_FTSR2_FT37_Pos (5U) +#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */ +#define EXTI_FTSR2_FT38_Pos (6U) +#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */ + +/****************** Bit definition for EXTI_SWIER2 register *****************/ +#define EXTI_SWIER2_SWI35_Pos (3U) +#define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */ +#define EXTI_SWIER2_SWI37_Pos (5U) +#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */ +#define EXTI_SWIER2_SWI38_Pos (6U) +#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */ + +/******************* Bit definition for EXTI_PR2 register *******************/ +#define EXTI_PR2_PIF35_Pos (3U) +#define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */ +#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */ +#define EXTI_PR2_PIF37_Pos (5U) +#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */ +#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */ +#define EXTI_PR2_PIF38_Pos (6U) +#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */ +#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk +#define FLASH_ACR_RUN_PD_Pos (13U) +#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */ + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk +#define FLASH_SR_PEMPTY_Pos (17U) +#define FLASH_SR_PEMPTY_Msk (0x1UL << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */ +#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk +#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */ +#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */ +#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (14U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_nBOOT1_Pos (23U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + +/****************** Bits definition for FLASH_PCROP1SR register **********/ +#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U) +#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00003FFF */ +#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1ER register ***********/ +#define FLASH_PCROP1ER_PCROP1_END_Pos (0U) +#define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00003FFF */ +#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk +#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRPB1R register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODE0 +#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0 +#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1 +#define GPIO_MODER_MODER1 GPIO_MODER_MODE1 +#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0 +#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1 +#define GPIO_MODER_MODER2 GPIO_MODER_MODE2 +#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0 +#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1 +#define GPIO_MODER_MODER3 GPIO_MODER_MODE3 +#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0 +#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1 +#define GPIO_MODER_MODER4 GPIO_MODER_MODE4 +#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0 +#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1 +#define GPIO_MODER_MODER5 GPIO_MODER_MODE5 +#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0 +#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1 +#define GPIO_MODER_MODER6 GPIO_MODER_MODE6 +#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0 +#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1 +#define GPIO_MODER_MODER7 GPIO_MODER_MODE7 +#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0 +#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1 +#define GPIO_MODER_MODER8 GPIO_MODER_MODE8 +#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0 +#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1 +#define GPIO_MODER_MODER9 GPIO_MODER_MODE9 +#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0 +#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1 +#define GPIO_MODER_MODER10 GPIO_MODER_MODE10 +#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0 +#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1 +#define GPIO_MODER_MODER11 GPIO_MODER_MODE11 +#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0 +#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1 +#define GPIO_MODER_MODER12 GPIO_MODER_MODE12 +#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0 +#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1 +#define GPIO_MODER_MODER13 GPIO_MODER_MODE13 +#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0 +#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1 +#define GPIO_MODER_MODER14 GPIO_MODER_MODE14 +#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0 +#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1 +#define GPIO_MODER_MODER15 GPIO_MODER_MODE15 +#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0 +#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1 + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/* Legacy defines */ +#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 +#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 +#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 +#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 +#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 +#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 +#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 +#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 +#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 +#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 +#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 +#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 +#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 +#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 +#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 +#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 +#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 +#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 +#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 +#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 +#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 +#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 +#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 +#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 +#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 +#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 +#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 +#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 +#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 +#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 +#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 +#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 +#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 +#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 +#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 +#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 +#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 +#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 +#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 +#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 +#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 +#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 +#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 +#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 +#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 +#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 +#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 +#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/* Legacy defines */ +#define GPIO_IDR_IDR_0 GPIO_IDR_ID0 +#define GPIO_IDR_IDR_1 GPIO_IDR_ID1 +#define GPIO_IDR_IDR_2 GPIO_IDR_ID2 +#define GPIO_IDR_IDR_3 GPIO_IDR_ID3 +#define GPIO_IDR_IDR_4 GPIO_IDR_ID4 +#define GPIO_IDR_IDR_5 GPIO_IDR_ID5 +#define GPIO_IDR_IDR_6 GPIO_IDR_ID6 +#define GPIO_IDR_IDR_7 GPIO_IDR_ID7 +#define GPIO_IDR_IDR_8 GPIO_IDR_ID8 +#define GPIO_IDR_IDR_9 GPIO_IDR_ID9 +#define GPIO_IDR_IDR_10 GPIO_IDR_ID10 +#define GPIO_IDR_IDR_11 GPIO_IDR_ID11 +#define GPIO_IDR_IDR_12 GPIO_IDR_ID12 +#define GPIO_IDR_IDR_13 GPIO_IDR_ID13 +#define GPIO_IDR_IDR_14 GPIO_IDR_ID14 +#define GPIO_IDR_IDR_15 GPIO_IDR_ID15 + +/* Old GPIO_IDR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0 +#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1 +#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2 +#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3 +#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4 +#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5 +#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6 +#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7 +#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8 +#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9 +#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10 +#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11 +#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12 +#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13 +#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14 +#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15 + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/* Legacy defines */ +#define GPIO_ODR_ODR_0 GPIO_ODR_OD0 +#define GPIO_ODR_ODR_1 GPIO_ODR_OD1 +#define GPIO_ODR_ODR_2 GPIO_ODR_OD2 +#define GPIO_ODR_ODR_3 GPIO_ODR_OD3 +#define GPIO_ODR_ODR_4 GPIO_ODR_OD4 +#define GPIO_ODR_ODR_5 GPIO_ODR_OD5 +#define GPIO_ODR_ODR_6 GPIO_ODR_OD6 +#define GPIO_ODR_ODR_7 GPIO_ODR_OD7 +#define GPIO_ODR_ODR_8 GPIO_ODR_OD8 +#define GPIO_ODR_ODR_9 GPIO_ODR_OD9 +#define GPIO_ODR_ODR_10 GPIO_ODR_OD10 +#define GPIO_ODR_ODR_11 GPIO_ODR_OD11 +#define GPIO_ODR_ODR_12 GPIO_ODR_OD12 +#define GPIO_ODR_ODR_13 GPIO_ODR_OD13 +#define GPIO_ODR_ODR_14 GPIO_ODR_OD14 +#define GPIO_ODR_ODR_15 GPIO_ODR_OD15 + +/* Old GPIO_ODR register bits definition, maintained for legacy purpose */ +#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0 +#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1 +#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2 +#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3 +#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4 +#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5 +#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6 +#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7 +#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8 +#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9 +#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10 +#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11 +#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12 +#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13 +#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14 +#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15 + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/* Legacy defines */ +#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 +#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 +#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 +#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 +#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 +#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 +#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 +#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 +#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 +#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 +#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 +#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 +#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 +#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 +#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 +#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 +#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 +#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 +#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 +#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 +#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 +#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 +#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 +#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 +#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 +#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 +#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 +#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 +#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 +#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 +#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 +#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/* Legacy defines */ +#define GPIO_BRR_BR_0 GPIO_BRR_BR0 +#define GPIO_BRR_BR_1 GPIO_BRR_BR1 +#define GPIO_BRR_BR_2 GPIO_BRR_BR2 +#define GPIO_BRR_BR_3 GPIO_BRR_BR3 +#define GPIO_BRR_BR_4 GPIO_BRR_BR4 +#define GPIO_BRR_BR_5 GPIO_BRR_BR5 +#define GPIO_BRR_BR_6 GPIO_BRR_BR6 +#define GPIO_BRR_BR_7 GPIO_BRR_BR7 +#define GPIO_BRR_BR_8 GPIO_BRR_BR8 +#define GPIO_BRR_BR_9 GPIO_BRR_BR9 +#define GPIO_BRR_BR_10 GPIO_BRR_BR10 +#define GPIO_BRR_BR_11 GPIO_BRR_BR11 +#define GPIO_BRR_BR_12 GPIO_BRR_BR12 +#define GPIO_BRR_BR_13 GPIO_BRR_BR13 +#define GPIO_BRR_BR_14 GPIO_BRR_BR14 +#define GPIO_BRR_BR_15 GPIO_BRR_BR15 + + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! + - - + +Release Notes for STM32L4xx CMSIS - - -Release Notes for STM32L4xx CMSIS - - -
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          Release -Notes for STM32L4xx CMSIS

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          Copyright -2017 STMicroelectronics

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          - - - - - - -
          - -

          Update History

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          V1.4.3 / 30-April-2018

          Main Changes

          • all stm32l4XXxx.h device description files
            • Fix DFSDM_FLTICR_CLRSCDF definition
            • Cleanup USB Host & Device bit definitions
            • [MISRAC2012-Rule-10.6] Use 'UL' postfix for _Msk definitions and memory/peripheral base addresses
          • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
            • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions (V1.4.1 update was incorrect)
          • all stm32l4XXxx.h device description files except stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h
            • Add missing USART_CR3_UCESM bit definition

          V1.4.2 / 22-December-2017

          Main Changes

          • SPI_TypeDef cleanup of Reserved fields.

          V1.4.1 / 13-October-2017

          Main Changes

          • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
            • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions
          • stm32l4r5xx.h and stm32l4s5xx.h devices description files
            • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices

          V1.4.0 / 25-August-2017

          Main Changes

          • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
            • Add stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h device description files
            • Add startup files startup_stm32l4r5xx.s, startup_stm32l4r7xx.s,  startup_stm32l4r9xx.s,  startup_stm32l4s5xx.s,  startup_stm32l4s7xx.s and startup_stm32l4s9xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
            • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
          • stm32l4xx.h
            • Add the following device defines:
              • "#define STM32L4R5xx" for all STM32L4R5xx devices
              • "#define STM32L4R7xx" for all STM32L4R7xx devices
              • "#define STM32L4R9xx" for all STM32L4R9xx devices
              • "#define STM32L4S5xx" for all STM32L4S5xx devices
              • "#define STM32L4S7xx" for all STM32L4S7xx devices
              • "#define STM32L4S9xx" for all STM32L4S9xx devices
          • all adequate stm32l4XXxx.h device description files
            • PWR: Rename PWR_CR3_EIWF to PWR_CR3_EIWUL
            • TIM: Add missing TIM8 check in debug macro IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() devices
            • USB: Fix USB_EP0R...USB_EP7R definitions
          • system_stm32l4xx.c
            • Fix MISRA C 2004 rule 10.6 : a 'U' suffix shall be applied to all constants of 'unsigned' type

          V1.3.2 + + + +
          Back to Release page + +
          +

          License

          +This software component is licensed by ST under BSD 3-Clause +license, the "License"; You may not use this component except in +compliance with +the License. You may obtain a copy of the License at: +

          https://opensource.org/licenses/BSD-3-Clause

          +
          +
          +
          +
          +

          V1.5.0 / 27-July-2018

          +
          +
          +

          Main +Changes

          +
          • Add the support of STM32L412xx/STM32L422x devices
            • Add stm32l412xx.h and stm32l422xx.h device description files
            • Add startup files startup_stm32l412xx.s and startup_stm32l422xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
            • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
          • stm32l4xx.h
            • Add the following device defines:
              • "#define STM32L412xx" for all STM32L412xx devices
              • "#define STM32L422xx" for all STM32L422xx devices
          • stm32l4r5xx.h, stm32l4r7xx.h, +stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and +stm32l4s9xx.h description files
            • Update SDMMC mask register
            • Correct SDMMC DPSMACT and CPSMACT bits definition
          • All stm32l4XXxx.h device description files except stm32l4rXxx.h and stm32l4sXxx.h
            • Correct Misra C:2012 Rule10.3 warning in replacing 0xFFUL by 0xFFU when CRC IDR register is 8-bit long only
          • All iar/linker/stm32l4XXxx_flash.icf and iar/linker/stm32l4XXxx_sram.icf
            • Remove SRAM1 and SRAM2 (and SRAM3 for stm32l4rXxx_flash.icf, stm32l4sXxx_flash.icf, stm32l4rXxx_sram.icf and stm32l4sXxx_sram.icf) start and end addresses from ICF editor section
            • Define RAM section as covering whole SRAM1 plus SRAM2 (and SRAM3 when applicable) when the SRAM regions are contiguous
          +
          +
          +
          +

          +
          +

          -

          -
          +
          • First official release for STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx devices

          +
          +
          +
          +

          For complete +documentation on STM32 Microcontrollers, +visit: www.st.com/STM32

          +
          -

           

          \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s new file mode 100644 index 0000000000..e6280c2127 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l412xx.s @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file startup_stm32l412xx.s + * @author MCD Application Team + * @brief STM32L412xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_IRQHandler + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l422xx.s b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l422xx.s new file mode 100644 index 0000000000..c2808ee6dd --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l422xx.s @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file startup_stm32l412xx.s + * @author MCD Application Team + * @brief STM32L412xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_IRQHandler + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word 0 + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word TSC_IRQHandler + .word 0 + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index e1c7df313c..d824740f5d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.3 * STM32L0: 1.7.2 * STM32L1: 2.2.3 - * STM32L4: 1.4.3 + * STM32L4: 1.5.0 Release notes of each STM32YYxx CMSIS available here: From 9e12729400e358682a21ea7f3848a54e4b75551f Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 14 Sep 2018 15:50:55 +0200 Subject: [PATCH 056/109] Add new CMSIS startup file Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/stm32_def_build.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 1478742b7a..d131d85361 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -247,6 +247,10 @@ #define CMSIS_STARTUP_FILE "startup_stm32l162xdx.s" #elif defined(STM32L162xE) #define CMSIS_STARTUP_FILE "startup_stm32l162xe.s" +#elif defined(STM32L412xx) +#define CMSIS_STARTUP_FILE "startup_stm32l412xx.s" +#elif defined(STM32L422xx) +#define CMSIS_STARTUP_FILE "startup_stm32l422xx.s" #elif defined(STM32L431xx) #define CMSIS_STARTUP_FILE "startup_stm32l431xx.s" #elif defined(STM32L432xx) From 78c5d124f654aab93f27a5295e2cc85920fe9a38 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 19 Sep 2018 14:43:08 +0200 Subject: [PATCH 057/109] Remove GSM built-in library GSM shield is a retired product and official library is no more supported. Moreover, this port is based on uart emulation which is not maintained (and not functional) and will be replaced by an official SoftwareSerial port for this core. See #267. Signed-off-by: Frederic.Pillon --- libraries/GSM/README.adoc | 23 - .../examples/GsmWebClient/GsmWebClient.ino | 100 --- .../examples/GsmWebServer/GsmWebServer.ino | 113 ---- .../examples/MakeVoiceCall/MakeVoiceCall.ino | 105 --- .../GSM/examples/ReceiveSMS/ReceiveSMS.ino | 93 --- .../ReceiveVoiceCall/ReceiveVoiceCall.ino | 101 --- libraries/GSM/examples/SendSMS/SendSMS.ino | 101 --- .../Tools/BandManagement/BandManagement.ino | 115 ---- .../Tools/GsmScanNetworks/GsmScanNetworks.ino | 92 --- .../Tools/PinManagement/PinManagement.ino | 146 ----- .../GSM/examples/Tools/TestGPRS/TestGPRS.ino | 190 ------ .../examples/Tools/TestModem/TestModem.ino | 70 -- .../Tools/TestWebServer/TestWebServer.ino | 82 --- libraries/GSM/extras/License.txt | 142 ---- libraries/GSM/keywords.txt | 72 -- libraries/GSM/library.properties | 9 - libraries/GSM/src/DEFAULT.h | 24 - libraries/GSM/src/GSM.h | 80 --- libraries/GSM/src/GSM3CircularBuffer.cpp | 317 --------- libraries/GSM/src/GSM3CircularBuffer.h | 203 ------ libraries/GSM/src/GSM3IO.h | 59 -- .../GSM/src/GSM3MobileAccessProvider.cpp | 36 - libraries/GSM/src/GSM3MobileAccessProvider.h | 73 --- .../GSM/src/GSM3MobileCellManagement.cpp | 34 - libraries/GSM/src/GSM3MobileCellManagement.h | 53 -- .../GSM/src/GSM3MobileClientProvider.cpp | 36 - libraries/GSM/src/GSM3MobileClientProvider.h | 156 ----- libraries/GSM/src/GSM3MobileClientService.cpp | 260 -------- libraries/GSM/src/GSM3MobileClientService.h | 162 ----- .../GSM/src/GSM3MobileDataNetworkProvider.cpp | 36 - .../GSM/src/GSM3MobileDataNetworkProvider.h | 62 -- .../GSM/src/GSM3MobileMockupProvider.cpp | 194 ------ libraries/GSM/src/GSM3MobileMockupProvider.h | 255 -------- .../GSM/src/GSM3MobileNetworkProvider.cpp | 71 -- libraries/GSM/src/GSM3MobileNetworkProvider.h | 136 ---- .../GSM/src/GSM3MobileNetworkRegistry.cpp | 51 -- libraries/GSM/src/GSM3MobileNetworkRegistry.h | 63 -- libraries/GSM/src/GSM3MobileSMSProvider.cpp | 36 - libraries/GSM/src/GSM3MobileSMSProvider.h | 91 --- .../GSM/src/GSM3MobileServerProvider.cpp | 39 -- libraries/GSM/src/GSM3MobileServerProvider.h | 95 --- libraries/GSM/src/GSM3MobileServerService.cpp | 160 ----- libraries/GSM/src/GSM3MobileServerService.h | 124 ---- libraries/GSM/src/GSM3MobileVoiceProvider.cpp | 36 - libraries/GSM/src/GSM3MobileVoiceProvider.h | 88 --- libraries/GSM/src/GSM3SMSService.cpp | 126 ---- libraries/GSM/src/GSM3SMSService.h | 110 ---- libraries/GSM/src/GSM3ShieldV1.cpp | 97 --- libraries/GSM/src/GSM3ShieldV1.h | 137 ---- .../GSM/src/GSM3ShieldV1AccessProvider.cpp | 364 ---------- .../GSM/src/GSM3ShieldV1AccessProvider.h | 121 ---- .../GSM/src/GSM3ShieldV1BandManagement.cpp | 100 --- .../GSM/src/GSM3ShieldV1BandManagement.h | 96 --- .../GSM/src/GSM3ShieldV1BaseProvider.cpp | 59 -- libraries/GSM/src/GSM3ShieldV1BaseProvider.h | 73 --- .../GSM/src/GSM3ShieldV1CellManagement.cpp | 204 ------ .../GSM/src/GSM3ShieldV1CellManagement.h | 92 --- .../GSM/src/GSM3ShieldV1ClientProvider.cpp | 330 ---------- .../GSM/src/GSM3ShieldV1ClientProvider.h | 181 ----- .../src/GSM3ShieldV1DataNetworkProvider.cpp | 401 ------------ .../GSM/src/GSM3ShieldV1DataNetworkProvider.h | 140 ---- .../src/GSM3ShieldV1DirectModemProvider.cpp | 142 ---- .../GSM/src/GSM3ShieldV1DirectModemProvider.h | 118 ---- libraries/GSM/src/GSM3ShieldV1ModemCore.cpp | 231 ------- libraries/GSM/src/GSM3ShieldV1ModemCore.h | 253 ------- .../GSM/src/GSM3ShieldV1ModemVerification.cpp | 73 --- .../GSM/src/GSM3ShieldV1ModemVerification.h | 64 -- .../src/GSM3ShieldV1MultiClientProvider.cpp | 619 ------------------ .../GSM/src/GSM3ShieldV1MultiClientProvider.h | 202 ------ .../src/GSM3ShieldV1MultiServerProvider.cpp | 393 ----------- .../GSM/src/GSM3ShieldV1MultiServerProvider.h | 136 ---- .../GSM/src/GSM3ShieldV1PinManagement.cpp | 203 ------ libraries/GSM/src/GSM3ShieldV1PinManagement.h | 103 --- libraries/GSM/src/GSM3ShieldV1SMSProvider.cpp | 330 ---------- libraries/GSM/src/GSM3ShieldV1SMSProvider.h | 130 ---- .../GSM/src/GSM3ShieldV1ScanNetworks.cpp | 126 ---- libraries/GSM/src/GSM3ShieldV1ScanNetworks.h | 75 --- .../GSM/src/GSM3ShieldV1ServerProvider.cpp | 241 ------- .../GSM/src/GSM3ShieldV1ServerProvider.h | 126 ---- .../GSM/src/GSM3ShieldV1VoiceProvider.cpp | 269 -------- libraries/GSM/src/GSM3ShieldV1VoiceProvider.h | 153 ----- libraries/GSM/src/GSM3ShieldV2.cpp | 256 -------- libraries/GSM/src/GSM3ShieldV2.h | 90 --- libraries/GSM/src/GSM3SoftSerial.cpp | 228 ------- libraries/GSM/src/GSM3SoftSerial.h | 139 ---- libraries/GSM/src/GSM3VoiceCallService.cpp | 145 ---- libraries/GSM/src/GSM3VoiceCallService.h | 103 --- 87 files changed, 12163 deletions(-) delete mode 100644 libraries/GSM/README.adoc delete mode 100644 libraries/GSM/examples/GsmWebClient/GsmWebClient.ino delete mode 100644 libraries/GSM/examples/GsmWebServer/GsmWebServer.ino delete mode 100644 libraries/GSM/examples/MakeVoiceCall/MakeVoiceCall.ino delete mode 100644 libraries/GSM/examples/ReceiveSMS/ReceiveSMS.ino delete mode 100644 libraries/GSM/examples/ReceiveVoiceCall/ReceiveVoiceCall.ino delete mode 100644 libraries/GSM/examples/SendSMS/SendSMS.ino delete mode 100644 libraries/GSM/examples/Tools/BandManagement/BandManagement.ino delete mode 100644 libraries/GSM/examples/Tools/GsmScanNetworks/GsmScanNetworks.ino delete mode 100644 libraries/GSM/examples/Tools/PinManagement/PinManagement.ino delete mode 100644 libraries/GSM/examples/Tools/TestGPRS/TestGPRS.ino delete mode 100644 libraries/GSM/examples/Tools/TestModem/TestModem.ino delete mode 100644 libraries/GSM/examples/Tools/TestWebServer/TestWebServer.ino delete mode 100644 libraries/GSM/extras/License.txt delete mode 100644 libraries/GSM/keywords.txt delete mode 100644 libraries/GSM/library.properties delete mode 100644 libraries/GSM/src/DEFAULT.h delete mode 100644 libraries/GSM/src/GSM.h delete mode 100644 libraries/GSM/src/GSM3CircularBuffer.cpp delete mode 100644 libraries/GSM/src/GSM3CircularBuffer.h delete mode 100644 libraries/GSM/src/GSM3IO.h delete mode 100644 libraries/GSM/src/GSM3MobileAccessProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileAccessProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileCellManagement.cpp delete mode 100644 libraries/GSM/src/GSM3MobileCellManagement.h delete mode 100644 libraries/GSM/src/GSM3MobileClientProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileClientProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileClientService.cpp delete mode 100644 libraries/GSM/src/GSM3MobileClientService.h delete mode 100644 libraries/GSM/src/GSM3MobileDataNetworkProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileDataNetworkProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileMockupProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileMockupProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileNetworkProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileNetworkProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileNetworkRegistry.cpp delete mode 100644 libraries/GSM/src/GSM3MobileNetworkRegistry.h delete mode 100644 libraries/GSM/src/GSM3MobileSMSProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileSMSProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileServerProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileServerProvider.h delete mode 100644 libraries/GSM/src/GSM3MobileServerService.cpp delete mode 100644 libraries/GSM/src/GSM3MobileServerService.h delete mode 100644 libraries/GSM/src/GSM3MobileVoiceProvider.cpp delete mode 100644 libraries/GSM/src/GSM3MobileVoiceProvider.h delete mode 100644 libraries/GSM/src/GSM3SMSService.cpp delete mode 100644 libraries/GSM/src/GSM3SMSService.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1AccessProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1AccessProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1BandManagement.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1BandManagement.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1BaseProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1BaseProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1CellManagement.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1CellManagement.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1ClientProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1ClientProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1DirectModemProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1DirectModemProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1ModemCore.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1ModemCore.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1ModemVerification.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1ModemVerification.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1MultiClientProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1MultiClientProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1MultiServerProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1MultiServerProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1PinManagement.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1PinManagement.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1SMSProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1SMSProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1ScanNetworks.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1ScanNetworks.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1ServerProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1ServerProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV1VoiceProvider.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV1VoiceProvider.h delete mode 100644 libraries/GSM/src/GSM3ShieldV2.cpp delete mode 100644 libraries/GSM/src/GSM3ShieldV2.h delete mode 100644 libraries/GSM/src/GSM3SoftSerial.cpp delete mode 100644 libraries/GSM/src/GSM3SoftSerial.h delete mode 100644 libraries/GSM/src/GSM3VoiceCallService.cpp delete mode 100644 libraries/GSM/src/GSM3VoiceCallService.h diff --git a/libraries/GSM/README.adoc b/libraries/GSM/README.adoc deleted file mode 100644 index 876f0dcb79..0000000000 --- a/libraries/GSM/README.adoc +++ /dev/null @@ -1,23 +0,0 @@ -= GSM Library for Arduino = - -With the Arduino GSM Shield, this library enables an Arduino board to do most of the operations you can do with a GSM phone: place and receive voice calls, send and receive SMS, and connect to the internet over a GPRS network. - -For more information about this library please visit us at -http://www.arduino.cc/en/Reference/GSM - -== License == -Copyright (c) 2012 Telefónica Digital - PDI - Physical Internet Lab - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/libraries/GSM/examples/GsmWebClient/GsmWebClient.ino b/libraries/GSM/examples/GsmWebClient/GsmWebClient.ino deleted file mode 100644 index 3abc4136ff..0000000000 --- a/libraries/GSM/examples/GsmWebClient/GsmWebClient.ino +++ /dev/null @@ -1,100 +0,0 @@ -/* - Web client - - This sketch connects to a website through a GSM shield. Specifically, - this example downloads the URL "http://www.arduino.cc/asciilogo.txt" and - prints it to the Serial monitor. - - Circuit: - * GSM shield attached to an Arduino - * SIM card with a data plan - - created 8 Mar 2012 - by Tom Igoe - - http://www.arduino.cc/en/Tutorial/GSMExamplesWebClient - - */ - -// libraries -#include - -// PIN Number -#define PINNUMBER "" - -// APN data -#define GPRS_APN "GPRS_APN" // replace your GPRS APN -#define GPRS_LOGIN "login" // replace with your GPRS login -#define GPRS_PASSWORD "password" // replace with your GPRS password - -// initialize the library instance -GSMClient client; -GPRS gprs; -GSM gsmAccess; - -// URL, path & port (for example: arduino.cc) -char server[] = "arduino.cc"; -char path[] = "/asciilogo.txt"; -int port = 80; // port 80 is the default for HTTP - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - Serial.println("Starting Arduino web client."); - // connection state - boolean notConnected = true; - - // After starting the modem with GSM.begin() - // attach the shield to the GPRS network with the APN, login and password - while (notConnected) { - if ((gsmAccess.begin(PINNUMBER) == GSM_READY) & - (gprs.attachGPRS(GPRS_APN, GPRS_LOGIN, GPRS_PASSWORD) == GPRS_READY)) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("connecting..."); - - // if you get a connection, report back via serial: - if (client.connect(server, port)) { - Serial.println("connected"); - // Make a HTTP request: - client.print("GET "); - client.print(path); - client.println(" HTTP/1.1"); - client.print("Host: "); - client.println(server); - client.println("Connection: close"); - client.println(); - } else { - // if you didn't get a connection to the server: - Serial.println("connection failed"); - } -} - -void loop() { - // if there are incoming bytes available - // from the server, read them and print them: - if (client.available()) { - char c = client.read(); - Serial.print(c); - } - - // if the server's disconnected, stop the client: - if (!client.available() && !client.connected()) { - Serial.println(); - Serial.println("disconnecting."); - client.stop(); - - // do nothing forevermore: - for (;;) - ; - } -} diff --git a/libraries/GSM/examples/GsmWebServer/GsmWebServer.ino b/libraries/GSM/examples/GsmWebServer/GsmWebServer.ino deleted file mode 100644 index 74fb572a1d..0000000000 --- a/libraries/GSM/examples/GsmWebServer/GsmWebServer.ino +++ /dev/null @@ -1,113 +0,0 @@ -/* - GSM Web Server - - A simple web server that shows the value of the analog input pins. - using a GSM shield. - - Circuit: - * GSM shield attached - * Analog inputs attached to pins A0 through A5 (optional) - - created 8 Mar 2012 - by Tom Igoe - */ - -// libraries -#include - -// PIN Number -#define PINNUMBER "" - -// APN data -#define GPRS_APN "GPRS_APN" // replace your GPRS APN -#define GPRS_LOGIN "login" // replace with your GPRS login -#define GPRS_PASSWORD "password" // replace with your GPRS password - - -// initialize the library instance -GPRS gprs; -GSM gsmAccess; // include a 'true' parameter for debug enabled -GSMServer server(80); // port 80 (http default) - -// timeout -const unsigned long __TIMEOUT__ = 10 * 1000; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - // connection state - boolean notConnected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (notConnected) { - if ((gsmAccess.begin(PINNUMBER) == GSM_READY) & - (gprs.attachGPRS(GPRS_APN, GPRS_LOGIN, GPRS_PASSWORD) == GPRS_READY)) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("Connected to GPRS network"); - - // start server - server.begin(); - - //Get IP. - IPAddress LocalIP = gprs.getIPAddress(); - Serial.println("Server IP address="); - Serial.println(LocalIP); -} - -void loop() { - - - // listen for incoming clients - GSMClient client = server.available(); - - - - if (client) { - while (client.connected()) { - if (client.available()) { - Serial.println("Receiving request!"); - bool sendResponse = false; - while (char c = client.read()) { - if (c == '\n') { - sendResponse = true; - } - } - - // if you've gotten to the end of the line (received a newline - // character) - if (sendResponse) { - // send a standard http response header - client.println("HTTP/1.1 200 OK"); - client.println("Content-Type: text/html"); - client.println(); - client.println(""); - // output the value of each analog input pin - for (int analogChannel = 0; analogChannel < 6; analogChannel++) { - client.print("analog input "); - client.print(analogChannel); - client.print(" is "); - client.print(analogRead(analogChannel)); - client.println("
          "); - } - client.println(""); - //necessary delay - delay(1000); - client.stop(); - } - } - } - } -} - - diff --git a/libraries/GSM/examples/MakeVoiceCall/MakeVoiceCall.ino b/libraries/GSM/examples/MakeVoiceCall/MakeVoiceCall.ino deleted file mode 100644 index 5eaace0a77..0000000000 --- a/libraries/GSM/examples/MakeVoiceCall/MakeVoiceCall.ino +++ /dev/null @@ -1,105 +0,0 @@ -/* - Make Voice Call - - This sketch, for the Arduino GSM shield, puts a voice call to - a remote phone number that you enter through the serial monitor. - To make it work, open the serial monitor, and when you see the - READY message, type a phone number. Make sure the serial monitor - is set to send a just newline when you press return. - - Circuit: - * GSM shield - * Voice circuit. - With no voice circuit the call will send nor receive any sound - - - created Mar 2012 - by Javier Zorzano - - This example is in the public domain. - */ - -// libraries -#include - -// PIN Number -#define PINNUMBER "" - -// initialize the library instance -GSM gsmAccess; // include a 'true' parameter for debug enabled -GSMVoiceCall vcs; - -String remoteNumber = ""; // the number you will call -char charbuffer[20]; - -void setup() { - - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - Serial.println("Make Voice Call"); - - // connection state - boolean notConnected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (notConnected) { - if (gsmAccess.begin(PINNUMBER) == GSM_READY) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("GSM initialized."); - Serial.println("Enter phone number to call."); - -} - -void loop() { - - // add any incoming characters to the String: - while (Serial.available() > 0) { - char inChar = Serial.read(); - // if it's a newline, that means you should make the call: - if (inChar == '\n') { - // make sure the phone number is not too long: - if (remoteNumber.length() < 20) { - // let the user know you're calling: - Serial.print("Calling to : "); - Serial.println(remoteNumber); - Serial.println(); - - // Call the remote number - remoteNumber.toCharArray(charbuffer, 20); - - - // Check if the receiving end has picked up the call - if (vcs.voiceCall(charbuffer)) { - Serial.println("Call Established. Enter line to end"); - // Wait for some input from the line - while (Serial.read() != '\n' && (vcs.getvoiceCallStatus() == TALKING)); - // And hang up - vcs.hangCall(); - } - Serial.println("Call Finished"); - remoteNumber = ""; - Serial.println("Enter phone number to call."); - } else { - Serial.println("That's too long for a phone number. I'm forgetting it"); - remoteNumber = ""; - } - } else { - // add the latest character to the message to send: - if (inChar != '\r') { - remoteNumber += inChar; - } - } - } -} - diff --git a/libraries/GSM/examples/ReceiveSMS/ReceiveSMS.ino b/libraries/GSM/examples/ReceiveSMS/ReceiveSMS.ino deleted file mode 100644 index 09546e51e3..0000000000 --- a/libraries/GSM/examples/ReceiveSMS/ReceiveSMS.ino +++ /dev/null @@ -1,93 +0,0 @@ -/* - SMS receiver - - This sketch, for the Arduino GSM shield, waits for a SMS message - and displays it through the Serial port. - - Circuit: - * GSM shield attached to and Arduino - * SIM card that can receive SMS messages - - created 25 Feb 2012 - by Javier Zorzano / TD - - This example is in the public domain. - - http://www.arduino.cc/en/Tutorial/GSMExamplesReceiveSMS - -*/ - -// include the GSM library -#include - -// PIN Number for the SIM -#define PINNUMBER "" - -// initialize the library instances -GSM gsmAccess; -GSM_SMS sms; - -// Array to hold the number a SMS is retreived from -char senderNumber[20]; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - Serial.println("SMS Messages Receiver"); - - // connection state - boolean notConnected = true; - - // Start GSM connection - while (notConnected) { - if (gsmAccess.begin(PINNUMBER) == GSM_READY) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("GSM initialized"); - Serial.println("Waiting for messages"); -} - -void loop() { - char c; - - // If there are any SMSs available() - if (sms.available()) { - Serial.println("Message received from:"); - - // Get remote number - sms.remoteNumber(senderNumber, 20); - Serial.println(senderNumber); - - // An example of message disposal - // Any messages starting with # should be discarded - if (sms.peek() == '#') { - Serial.println("Discarded SMS"); - sms.flush(); - } - - // Read message bytes and print them - while (c = sms.read()) { - Serial.print(c); - } - - Serial.println("\nEND OF MESSAGE"); - - // Delete message from modem memory - sms.flush(); - Serial.println("MESSAGE DELETED"); - } - - delay(1000); - -} - - diff --git a/libraries/GSM/examples/ReceiveVoiceCall/ReceiveVoiceCall.ino b/libraries/GSM/examples/ReceiveVoiceCall/ReceiveVoiceCall.ino deleted file mode 100644 index 6ec09f7572..0000000000 --- a/libraries/GSM/examples/ReceiveVoiceCall/ReceiveVoiceCall.ino +++ /dev/null @@ -1,101 +0,0 @@ -/* - Receive Voice Call - - This sketch, for the Arduino GSM shield, receives voice calls, - displays the calling number, waits a few seconds then hangs up. - - Circuit: - * GSM shield - * Voice circuit. Refer to to the GSM shield getting started guide - at http://www.arduino.cc/en/Guide/ArduinoGSMShield#toc11 - * SIM card that can accept voice calls - - With no voice circuit the call will connect, but will not send or receive sound - - created Mar 2012 - by Javier Zorzano - - This example is in the public domain. - - http://www.arduino.cc/en/Tutorial/GSMExamplesReceiveVoiceCall - - */ - -// Include the GSM library -#include - -// PIN Number -#define PINNUMBER "" - -// initialize the library instance -GSM gsmAccess; -GSMVoiceCall vcs; - -// Array to hold the number for the incoming call -char numtel[20]; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - Serial.println("Receive Voice Call"); - - // connection state - boolean notConnected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (notConnected) { - if (gsmAccess.begin(PINNUMBER) == GSM_READY) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - // This makes sure the modem correctly reports incoming events - vcs.hangCall(); - - Serial.println("Waiting for a call"); -} - -void loop() { - // Check the status of the voice call - switch (vcs.getvoiceCallStatus()) { - case IDLE_CALL: // Nothing is happening - - break; - - case RECEIVINGCALL: // Yes! Someone is calling us - - Serial.println("RECEIVING CALL"); - - // Retrieve the calling number - vcs.retrieveCallingNumber(numtel, 20); - - // Print the calling number - Serial.print("Number:"); - Serial.println(numtel); - - // Answer the call, establish the call - vcs.answerCall(); - break; - - case TALKING: // In this case the call would be established - - Serial.println("TALKING. Press enter to hang up."); - while (Serial.read() != '\n') { - delay(100); - } - vcs.hangCall(); - Serial.println("Hanging up and waiting for the next call."); - break; - } - delay(1000); -} - - diff --git a/libraries/GSM/examples/SendSMS/SendSMS.ino b/libraries/GSM/examples/SendSMS/SendSMS.ino deleted file mode 100644 index e49156ed96..0000000000 --- a/libraries/GSM/examples/SendSMS/SendSMS.ino +++ /dev/null @@ -1,101 +0,0 @@ -/* - SMS sender - - This sketch, for the Arduino GSM shield,sends an SMS message - you enter in the serial monitor. Connect your Arduino with the - GSM shield and SIM card, open the serial monitor, and wait for - the "READY" message to appear in the monitor. Next, type a - message to send and press "return". Make sure the serial - monitor is set to send a newline when you press return. - - Circuit: - * GSM shield - * SIM card that can send SMS - - created 25 Feb 2012 - by Tom Igoe - - This example is in the public domain. - - http://www.arduino.cc/en/Tutorial/GSMExamplesSendSMS - - */ - -// Include the GSM library -#include - -#define PINNUMBER "" - -// initialize the library instance -GSM gsmAccess; -GSM_SMS sms; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for native USB port only - } - - Serial.println("SMS Messages Sender"); - - // connection state - boolean notConnected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (notConnected) { - if (gsmAccess.begin(PINNUMBER) == GSM_READY) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("GSM initialized"); -} - -void loop() { - - Serial.print("Enter a mobile number: "); - char remoteNum[20]; // telephone number to send sms - readSerial(remoteNum); - Serial.println(remoteNum); - - // sms text - Serial.print("Now, enter SMS content: "); - char txtMsg[200]; - readSerial(txtMsg); - Serial.println("SENDING"); - Serial.println(); - Serial.println("Message:"); - Serial.println(txtMsg); - - // send the message - sms.beginSMS(remoteNum); - sms.print(txtMsg); - sms.endSMS(); - Serial.println("\nCOMPLETE!\n"); -} - -/* - Read input serial - */ -int readSerial(char result[]) { - int i = 0; - while (1) { - while (Serial.available() > 0) { - char inChar = Serial.read(); - if (inChar == '\n') { - result[i] = '\0'; - Serial.flush(); - return 0; - } - if (inChar != '\r') { - result[i] = inChar; - i++; - } - } - } -} diff --git a/libraries/GSM/examples/Tools/BandManagement/BandManagement.ino b/libraries/GSM/examples/Tools/BandManagement/BandManagement.ino deleted file mode 100644 index 2ef088a7f1..0000000000 --- a/libraries/GSM/examples/Tools/BandManagement/BandManagement.ino +++ /dev/null @@ -1,115 +0,0 @@ -/* - Band Management - - This sketch, for the Arduino GSM shield, checks the band - currently configured in the modem and allows you to change - it. - - Please check http://www.worldtimezone.com/gsm.html - Usual configurations: - Europe, Africa, Middle East: E-GSM(900)+DCS(1800) - USA, Canada, South America: GSM(850)+PCS(1900) - Mexico: PCS(1900) - Brazil: GSM(850)+E-GSM(900)+DCS(1800)+PCS(1900) - - - Circuit: - * GSM shield - - created 12 June 2012 - by Javier Zorzano, Scott Fitzgerald - - This example is in the public domain. - */ - -// libraries -#include - -// initialize the library instance -GSMBand band; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } - - // Beginning the band manager restarts the modem - Serial.println("Restarting modem..."); - band.begin(); - Serial.println("Modem restarted."); - -}; - - -void loop() { - // Get current band - String bandName = band.getBand(); // Get and print band name - Serial.print("Current band:"); - Serial.println(bandName); - Serial.println("Want to change the band you’re on?"); - String newBandName; - newBandName = askUser(); - // Tell the user what we are about to do… - Serial.print("\nConfiguring band "); - Serial.println(newBandName); - // Change the band - boolean operationSuccess; - operationSuccess = band.setBand(newBandName); - // Tell the user if the operation was OK - if (operationSuccess) { - Serial.println("Success"); - } else { - Serial.println("Error while changing band"); - } - - if (operationSuccess) { - while (true); - } -} - -// This function offers the user different options -// through the Serial interface -// The user selects one -String askUser() { - String newBand; - Serial.println("Select band:"); - // Print the different options - Serial.println("1 : E-GSM(900)"); - Serial.println("2 : DCS(1800)"); - Serial.println("3 : PCS(1900)"); - Serial.println("4 : E-GSM(900)+DCS(1800) ex: Europe"); - Serial.println("5 : GSM(850)+PCS(1900) Ex: USA, South Am."); - Serial.println("6 : GSM(850)+E-GSM(900)+DCS(1800)+PCS(1900)"); - - // Empty the incoming buffer - while (Serial.available()) { - Serial.read(); - } - - // Wait for an answer, just look at the first character - while (!Serial.available()); - char c = Serial.read(); - if (c == '1') { - newBand = GSM_MODE_EGSM; - } else if (c == '2') { - newBand = GSM_MODE_DCS; - } else if (c == '3') { - newBand = GSM_MODE_PCS; - } else if (c == '4') { - newBand = GSM_MODE_EGSM_DCS; - } else if (c == '5') { - newBand = GSM_MODE_GSM850_PCS; - } else if (c == '6') { - newBand = GSM_MODE_GSM850_EGSM_DCS_PCS; - } else { - newBand = "GSM_MODE_UNDEFINED"; - } - return newBand; -} - - - - - diff --git a/libraries/GSM/examples/Tools/GsmScanNetworks/GsmScanNetworks.ino b/libraries/GSM/examples/Tools/GsmScanNetworks/GsmScanNetworks.ino deleted file mode 100644 index 233d11ae1d..0000000000 --- a/libraries/GSM/examples/Tools/GsmScanNetworks/GsmScanNetworks.ino +++ /dev/null @@ -1,92 +0,0 @@ -/* - - GSM Scan Networks - - This example prints out the IMEI number of the modem, - then checks to see if it's connected to a carrier. If so, - it prints the phone number associated with the card. - Then it scans for nearby networks and prints out their signal strengths. - - Circuit: - * GSM shield - * SIM card - - Created 8 Mar 2012 - by Tom Igoe, implemented by Javier Carazo - Modified 4 Feb 2013 - by Scott Fitzgerald - - http://www.arduino.cc/en/Tutorial/GSMToolsGsmScanNetworks - - This example code is part of the public domain - */ - -// libraries -#include - -// PIN Number -#define PINNUMBER "" - -// initialize the library instance -GSM gsmAccess; // include a 'true' parameter to enable debugging -GSMScanner scannerNetworks; -GSMModem modemTest; - -// Save data variables -String IMEI = ""; - -// serial monitor result messages -String errortext = "ERROR"; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } - - Serial.println("GSM networks scanner"); - scannerNetworks.begin(); - - // connection state - boolean notConnected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (notConnected) { - if (gsmAccess.begin(PINNUMBER) == GSM_READY) { - notConnected = false; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - // get modem parameters - // IMEI, modem unique identifier - Serial.print("Modem IMEI: "); - IMEI = modemTest.getIMEI(); - IMEI.replace("\n", ""); - if (IMEI != NULL) { - Serial.println(IMEI); - } -} - -void loop() { - // scan for existing networks, displays a list of networks - Serial.println("Scanning available networks. May take some seconds."); - Serial.println(scannerNetworks.readNetworks()); - - // currently connected carrier - Serial.print("Current carrier: "); - Serial.println(scannerNetworks.getCurrentCarrier()); - - // returns strength and ber - // signal strength in 0-31 scale. 31 means power > 51dBm - // BER is the Bit Error Rate. 0-7 scale. 99=not detectable - Serial.print("Signal Strength: "); - Serial.print(scannerNetworks.getSignalStrength()); - Serial.println(" [0-31]"); - -} - diff --git a/libraries/GSM/examples/Tools/PinManagement/PinManagement.ino b/libraries/GSM/examples/Tools/PinManagement/PinManagement.ino deleted file mode 100644 index 6dc37b33d6..0000000000 --- a/libraries/GSM/examples/Tools/PinManagement/PinManagement.ino +++ /dev/null @@ -1,146 +0,0 @@ -/* - - This example enables you to change or remove the PIN number of - a SIM card inserted into a GSM shield. - - Circuit: - * GSM shield - * SIM card - - Created 12 Jun 2012 - by David del Peral - - This example code is part of the public domain - - http://www.arduino.cc/en/Tutorial/GSMToolsPinManagement - - */ - -// libraries -#include - -// pin manager object -GSMPIN PINManager; - -// save input in serial by user -String user_input = ""; - -// authenticated with PIN code -boolean auth = false; - -// serial monitor result messages -String oktext = "OK"; -String errortext = "ERROR"; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } - - Serial.println("Change PIN example\n"); - PINManager.begin(); - - // check if the SIM have pin lock - while (!auth) { - int pin_query = PINManager.isPIN(); - if (pin_query == 1) { - // if SIM is locked, enter PIN code - Serial.print("Enter PIN code: "); - user_input = readSerial(); - // check PIN code - if (PINManager.checkPIN(user_input) == 0) { - auth = true; - PINManager.setPINUsed(true); - Serial.println(oktext); - } else { - // if PIN code was incorrected - Serial.println("Incorrect PIN. Remember that you have 3 opportunities."); - } - } else if (pin_query == -1) { - // PIN code is locked, user must enter PUK code - Serial.println("PIN locked. Enter PUK code: "); - String puk = readSerial(); - Serial.print("Now, enter a new PIN code: "); - user_input = readSerial(); - // check PUK code - if (PINManager.checkPUK(puk, user_input) == 0) { - auth = true; - PINManager.setPINUsed(true); - Serial.println(oktext); - } else { - // if PUK o the new PIN are incorrect - Serial.println("Incorrect PUK or invalid new PIN. Try again!."); - } - } else if (pin_query == -2) { - // the worst case, PIN and PUK are locked - Serial.println("PIN & PUK locked. Use PIN2/PUK2 in a mobile phone."); - while (true); - } else { - // SIM does not requires authetication - Serial.println("No pin necessary."); - auth = true; - } - } - - // start GSM shield - Serial.print("Checking register in GSM network..."); - if (PINManager.checkReg() == 0) { - Serial.println(oktext); - } - // if you are connect by roaming - else if (PINManager.checkReg() == 1) { - Serial.println("ROAMING " + oktext); - } else { - // error connection - Serial.println(errortext); - while (true); - } -} - -void loop() { - // Function loop implements pin management user menu - // Only if you SIM use pin lock, you can change PIN code - // user_op variables save user option - - Serial.println("Choose an option:\n1 - On/Off PIN."); - if (PINManager.getPINUsed()) { - Serial.println("2 - Change PIN."); - } - String user_op = readSerial(); - if (user_op == "1") { - Serial.println("Enter your PIN code:"); - user_input = readSerial(); - // activate/deactivate PIN lock - PINManager.switchPIN(user_input); - } else if (user_op == "2" & PINManager.getPINUsed()) { - Serial.println("Enter your actual PIN code:"); - String oldPIN = readSerial(); - Serial.println("Now, enter your new PIN code:"); - String newPIN = readSerial(); - // change PIN - PINManager.changePIN(oldPIN, newPIN); - } else { - Serial.println("Incorrect option. Try again!."); - } - delay(1000); -} - -/* - Read input serial - */ -String readSerial() { - String text = ""; - while (1) { - while (Serial.available() > 0) { - char inChar = Serial.read(); - if (inChar == '\n') { - return text; - } - if (inChar != '\r') { - text += inChar; - } - } - } -} diff --git a/libraries/GSM/examples/Tools/TestGPRS/TestGPRS.ino b/libraries/GSM/examples/Tools/TestGPRS/TestGPRS.ino deleted file mode 100644 index 85a8bc8bc8..0000000000 --- a/libraries/GSM/examples/Tools/TestGPRS/TestGPRS.ino +++ /dev/null @@ -1,190 +0,0 @@ -/* - - This sketch test the GSM shield's ability to connect to a - GPERS network. It asks for APN information through the - serial monitor and tries to connect to arduino.cc. - - Circuit: - * GSM shield attached - * SIM card with data plan - - Created 18 Jun 2012 - by David del Peral - - This example code is part of the public domain - - http://www.arduino.cc/en/Tutorial/GSMToolsTestGPRS - - */ - -// libraries -#include - -// PIN Number -#define PINNUMBER "" - -// initialize the library instance -GSM gsmAccess; // GSM access: include a 'true' parameter for debug enabled -GPRS gprsAccess; // GPRS access -GSMClient client; // Client service for TCP connection - -// messages for serial monitor response -String oktext = "OK"; -String errortext = "ERROR"; - -// URL and path (for example: arduino.cc) -char url[] = "arduino.cc"; -char urlproxy[] = "http://www.arduino.cc"; -char path[] = "/"; - -// variable for save response obtained -String response = ""; - -// use a proxy -boolean use_proxy = false; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } -} - -void loop() { - use_proxy = false; - - // start GSM shield - // if your SIM has PIN, pass it as a parameter of begin() in quotes - Serial.print("Connecting GSM network..."); - if (gsmAccess.begin(PINNUMBER) != GSM_READY) { - Serial.println(errortext); - while (true); - } - Serial.println(oktext); - - // read APN introduced by user - char apn[50]; - Serial.print("Enter your APN: "); - readSerial(apn); - Serial.println(apn); - - // Read APN login introduced by user - char login[50]; - Serial.print("Now, enter your login: "); - readSerial(login); - Serial.println(login); - - // read APN password introduced by user - char password[20]; - Serial.print("Finally, enter your password: "); - readSerial(password); - - // attach GPRS - Serial.println("Attaching to GPRS with your APN..."); - if (gprsAccess.attachGPRS(apn, login, password) != GPRS_READY) { - Serial.println(errortext); - } else { - - Serial.println(oktext); - - // read proxy introduced by user - char proxy[100]; - Serial.print("If your carrier uses a proxy, enter it, if not press enter: "); - readSerial(proxy); - Serial.println(proxy); - - // if user introduced a proxy, asks him for proxy port - int pport; - if (proxy[0] != '\0') { - // read proxy port introduced by user - char proxyport[10]; - Serial.print("Enter the proxy port: "); - readSerial(proxyport); - // cast proxy port introduced to integer - pport = (int) proxyport; - use_proxy = true; - Serial.println(proxyport); - } - - // connection with arduino.cc and realize HTTP request - Serial.print("Connecting and sending GET request to arduino.cc..."); - int res_connect; - - // if use a proxy, connect with it - if (use_proxy) { - res_connect = client.connect(proxy, pport); - } else { - res_connect = client.connect(url, 80); - } - - if (res_connect) { - // make a HTTP 1.0 GET request (client sends the request) - client.print("GET "); - - // if use a proxy, the path is arduino.cc URL - if (use_proxy) { - client.print(urlproxy); - } else { - client.print(path); - } - - client.println(" HTTP/1.0"); - client.println(); - Serial.println(oktext); - } else { - // if you didn't get a connection to the server - Serial.println(errortext); - } - Serial.print("Receiving response..."); - - boolean test = true; - while (test) { - // if there are incoming bytes available - // from the server, read and check them - if (client.available()) { - char c = client.read(); - response += c; - - // cast response obtained from string to char array - char responsechar[response.length() + 1]; - response.toCharArray(responsechar, response.length() + 1); - - // if response includes a "200 OK" substring - if (strstr(responsechar, "200 OK") != NULL) { - Serial.println(oktext); - Serial.println("TEST COMPLETE!"); - test = false; - } - } - - // if the server's disconnected, stop the client: - if (!client.connected()) { - Serial.println(); - Serial.println("disconnecting."); - client.stop(); - test = false; - } - } - } -} - -/* - Read input serial - */ -int readSerial(char result[]) { - int i = 0; - while (1) { - while (Serial.available() > 0) { - char inChar = Serial.read(); - if (inChar == '\n') { - result[i] = '\0'; - return 0; - } - if (inChar != '\r') { - result[i] = inChar; - i++; - } - } - } -} diff --git a/libraries/GSM/examples/Tools/TestModem/TestModem.ino b/libraries/GSM/examples/Tools/TestModem/TestModem.ino deleted file mode 100644 index 5ee42219bb..0000000000 --- a/libraries/GSM/examples/Tools/TestModem/TestModem.ino +++ /dev/null @@ -1,70 +0,0 @@ -/* - - This example tests to see if the modem of the - GSM shield is working correctly. You do not need - a SIM card for this example. - - Circuit: - * GSM shield attached - - Created 12 Jun 2012 - by David del Peral - modified 21 Nov 2012 - by Tom Igoe - - http://www.arduino.cc/en/Tutorial/GSMToolsTestModem - - This sample code is part of the public domain - - */ - -// libraries -#include - -// modem verification object -GSMModem modem; - -// IMEI variable -String IMEI = ""; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } - - // start modem test (reset and check response) - Serial.print("Starting modem test..."); - if (modem.begin()) { - Serial.println("modem.begin() succeeded"); - } else { - Serial.println("ERROR, no modem answer."); - } -} - -void loop() { - // get modem IMEI - Serial.print("Checking IMEI..."); - IMEI = modem.getIMEI(); - - // check IMEI response - if (IMEI != NULL) { - // show IMEI in serial monitor - Serial.println("Modem's IMEI: " + IMEI); - // reset modem to check booting: - Serial.print("Resetting modem..."); - modem.begin(); - // get and check IMEI one more time - if (modem.getIMEI() != NULL) { - Serial.println("Modem is functoning properly"); - } else { - Serial.println("Error: getIMEI() failed after modem.begin()"); - } - } else { - Serial.println("Error: Could not get IMEI"); - } - // do nothing: - while (true); -} - diff --git a/libraries/GSM/examples/Tools/TestWebServer/TestWebServer.ino b/libraries/GSM/examples/Tools/TestWebServer/TestWebServer.ino deleted file mode 100644 index d3939e11a0..0000000000 --- a/libraries/GSM/examples/Tools/TestWebServer/TestWebServer.ino +++ /dev/null @@ -1,82 +0,0 @@ -/* - Basic Web Server - - A simple web server that replies with nothing, but prints the client's request - and the server IP address. - - Circuit: - * GSM shield attached - - created - by David Cuartielles - modified 21 Nov 2012 - by Tom Igoe - - http://www.arduino.cc/en/Tutorial/GSMToolsTestWebServer - - This example code is part of the public domain - */ -#include - -// PIN Number -#define PINNUMBER "" - -// APN data -#define GPRS_APN "GPRS_APN" // replace your GPRS APN -#define GPRS_LOGIN "login" // replace with your GPRS login -#define GPRS_PASSWORD "password" // replace with your GPRS password - - -// initialize the library instance -GPRS gprs; -GSM gsmAccess; // include a 'true' parameter for debug enabled -GSMServer server(80); // port 80 (http default) - -// timeout -const unsigned long __TIMEOUT__ = 10 * 1000; - -void setup() { - // initialize serial communications and wait for port to open: - Serial.begin(9600); - while (!Serial) { - ; // wait for serial port to connect. Needed for Leonardo only - } - - Serial.println("starting,.."); - // connection state - boolean connected = true; - - // Start GSM shield - // If your SIM has PIN, pass it as a parameter of begin() in quotes - while (!connected) { - if ((gsmAccess.begin(PINNUMBER) == GSM_READY) & - (gprs.attachGPRS(GPRS_APN, GPRS_LOGIN, GPRS_PASSWORD) == GPRS_READY)) { - connected = true; - } else { - Serial.println("Not connected"); - delay(1000); - } - } - - Serial.println("Connected to GPRS network"); - - // start server - server.begin(); - - //Get IP. - IPAddress LocalIP = gprs.getIPAddress(); - Serial.println("Server IP address="); - Serial.println(LocalIP); -} - -void loop() { - GSMClient client = server.available(); - - if (client) { - if (client.available()) { - Serial.write(client.read()); - } - } - -} - diff --git a/libraries/GSM/extras/License.txt b/libraries/GSM/extras/License.txt deleted file mode 100644 index 4114b2b23c..0000000000 --- a/libraries/GSM/extras/License.txt +++ /dev/null @@ -1,142 +0,0 @@ -GNU LESSER GENERAL PUBLIC LICENSE - -Version 2.1, February 1999 - -Copyright (C) 1991, 1999 Free Software Foundation, Inc. -51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -Everyone is permitted to copy and distribute verbatim copies -of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -END OF TERMS AND CONDITIONS diff --git a/libraries/GSM/keywords.txt b/libraries/GSM/keywords.txt deleted file mode 100644 index 4a44464add..0000000000 --- a/libraries/GSM/keywords.txt +++ /dev/null @@ -1,72 +0,0 @@ -####################################### -# Syntax Coloring Map For GSM -####################################### -# Class -####################################### - -GSM KEYWORD1 GSM -GSMVoiceCall KEYWORD1 GSMVCSConstructor -GSM_SMS KEYWORD1 GSMSMSConstructor -GPRS KEYWORD1 GPRSConstructor -GSMClient KEYWORD1 GSMClientConstructor -GSMServer KEYWORD1 GSMServerConstructor -GSMModem KEYWORD1 GSMModemConstructor -GSMScanner KEYWORD1 GSMScannerConstructor -GSMPIN KEYWORD1 GSMPINConstructor -GSMBand KEYWORD1 GSMBandConstructor - -####################################### -# Methods and Functions -####################################### - -begin KEYWORD2 -shutdown KEYWORD2 -gatVoiceCallStatus KEYWORD2 -ready KEYWORD2 -voiceCall KEYWORD2 -answerCall KEYWORD2 -hangCall KEYWORD2 -retrieveCallingNumber KEYWORD2 -beginSMS KEYWORD2 -endSMS KEYWORD2 -remoteNumber KEYWORD2 -attachGPRS KEYWORD2 -begnWrite KEYWORD2 -endWrite KEYWORD2 -getIMEI KEYWORD2 -getCurrentCarrier KEYWORD2 -getSignalStrength KEYWORD2 -readNetworks KEYWORD2 -isPIN KEYWORD2 -checkPIN KEYWORD2 -checkPUK KEYWORD2 -changePIN KEYWORD2 -switchPIN KEYWORD2 -checkReg KEYWORD2 -getPINUsed KEYWORD2 -setPINUsed KEYWORD2 -getBand KEYWORD2 -setBand KEYWORD2 -getvoiceCallStatus KEYWORD2 - -####################################### -# Constants -####################################### - -ERROR LITERAL1 -IDLE LITERAL1 -CONNECTING LITERAL1 -GSM_READY LITERAL1 -GPRS_READY LITERAL1 -TRANSPARENT_CONNECTED LITERAL1 -IDLE_CALL LITERAL1 -CALLING LITERAL1 -RECEIVINGCALL LITERAL1 -TALKING LITERAL1 -GSM_MODE_UNDEFINED LITERAL1 -GSM_MODE_EGSM LITERAL1 -GSM_MODE_DCS LITERAL1 -GSM_MODE_PCS LITERAL1 -GSM_MODE_EGSM_DCS LITERAL1 -GSM_MODE_GSM850_PCS LITERAL1 -GSM_MODE_GSM850_EGSM_DCS_PCS LITERAL1 diff --git a/libraries/GSM/library.properties b/libraries/GSM/library.properties deleted file mode 100644 index 201a0fe6c0..0000000000 --- a/libraries/GSM/library.properties +++ /dev/null @@ -1,9 +0,0 @@ -name=GSM -version=1.0.5 -author=Arduino -maintainer=Arduino -sentence=Enables GSM/GRPS network connection using the Arduino GSM Shield. For all Arduino boards BUT Arduino DUE. -paragraph=Use this library to make/receive voice calls, to send and receive SMS with the Quectel M10 GSM module.
          This library also allows you to connect to internet through the GPRS networks. You can either use web Clients and Servers.
          -category=Communication -url=http://www.arduino.cc/en/Reference/GSM -architectures=stm32 diff --git a/libraries/GSM/src/DEFAULT.h b/libraries/GSM/src/DEFAULT.h deleted file mode 100644 index 4707f4c252..0000000000 --- a/libraries/GSM/src/DEFAULT.h +++ /dev/null @@ -1,24 +0,0 @@ -/* -This file is part of GSM3ShieldV2 library developed by Arduino.org (http://arduino.org). - - GSM3ShieldV2 library is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - GSM3ShieldV2 library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GSM3ShieldV2 library. If not, see . -*/ - -#define DEFAULT_AlertSoundMode 0 -#define DEFAULT_RingerSoundLevel 10 -#define DEFAULT_Channel 1 -#define DEFAULT_MicrophoneGainLevel 10 -#define DEFAULT_LoudSpeakerVolumeLevel 30 -#define DEFAULT_muteControl 0 -#define DEFAULT_speakerMode 1 \ No newline at end of file diff --git a/libraries/GSM/src/GSM.h b/libraries/GSM/src/GSM.h deleted file mode 100644 index 19d61bd795..0000000000 --- a/libraries/GSM/src/GSM.h +++ /dev/null @@ -1,80 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino - - -Added support for Arduino GSM Shield 2 -Modified Apr. 2015 -by Arduino.org team (http://arduino.org) - -*/ -#ifndef _GSM3SIMPLIFIERFILE_ -#define _GSM3SIMPLIFIERFILE_ - -// This file simplifies the use of the GSM3 library -// First we include everything. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define GSM GSM3ShieldV1AccessProvider -#define GPRS GSM3ShieldV1DataNetworkProvider -#define GSMClient GSM3MobileClientService -#define GSMServer GSM3MobileServerService -#define GSMVoiceCall GSM3VoiceCallService -#define GSM_SMS GSM3SMSService - -#define GSMPIN GSM3ShieldV1PinManagement -#define GSMModem GSM3ShieldV1ModemVerification -#define GSMCell GSM3ShieldV1CellManagement -#define GSMBand GSM3ShieldV1BandManagement -#define GSMScanner GSM3ShieldV1ScanNetworks - - -//#define GPRSPosition GSM3ShieldV2 -#define GSM2 GSM3ShieldV2 -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3CircularBuffer.cpp b/libraries/GSM/src/GSM3CircularBuffer.cpp deleted file mode 100644 index a2aa58eb1a..0000000000 --- a/libraries/GSM/src/GSM3CircularBuffer.cpp +++ /dev/null @@ -1,317 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -GSM3CircularBuffer::GSM3CircularBuffer(GSM3CircularBufferManager* mgr) -{ - head=0; - tail=0; - cbm=mgr; -} - -int GSM3CircularBuffer::write(char c) -{ - byte aux=(tail+1)& __BUFFERMASK__; - if(aux!=head) - { - theBuffer[tail]=c; - // Lets put an extra zero at the end, so we can - // read chains as we like. - // This is not exactly perfect, we are always 1+ behind the head - theBuffer[aux]=0; - tail=aux; - return 1; - } - return 0; -} - -char GSM3CircularBuffer::read() -{ - char res; - if(head!=tail) - { - res=theBuffer[head]; - head=(head+1)& __BUFFERMASK__; - //if(cbm) - // cbm->spaceAvailable(); - return res; - } - else - { - return 0; - } -} - -char GSM3CircularBuffer::peek(int increment) -{ - char res; - byte num_aux; - - if (tail>head) num_aux = tail-head; - else num_aux = 128 - head + tail; - - if(increment < num_aux) - { - res=theBuffer[head]; - return res; - } - else - { - return 0; - } -} - -void GSM3CircularBufferManager::spaceAvailable(){return;}; - -void GSM3CircularBuffer::flush() -{ - head=tail; -} - -char* GSM3CircularBuffer::nextString() -{ - while(head!=tail) - { - head=(head+1) & __BUFFERMASK__; - if(theBuffer[head]==0) - { - head=(head+1) & __BUFFERMASK__; - return (char*)theBuffer+head; - } - } - return 0; -} - - -bool GSM3CircularBuffer::locate(const char* reference) -{ - - return locate(reference, head, tail, 0, 0); -} - -bool GSM3CircularBuffer::chopUntil(const char* reference, bool movetotheend, bool usehead) -{ - byte from, to; - - if(locate(reference, head, tail, &from, &to)) - { - if(usehead) - { - if(movetotheend) - head=(to+1) & __BUFFERMASK__; - else - head=from; - } - else - { - if(movetotheend) - tail=(to+1) & __BUFFERMASK__; - else - tail=from; - } - return true; - } - else - { - return false; - } -} - -bool GSM3CircularBuffer::locate(const char* reference, byte thishead, byte thistail, byte* from, byte* to) -{ - int refcursor=0; - bool into=false; - byte b2, binit; - bool possible=1; - - if(reference[0]==0) - return true; - - for(byte b1=thishead; b1!=thistail;b1=(b1+1)& __BUFFERMASK__) - { - possible = 1; - b2 = b1; - while (possible&&(b2!=thistail)) - { - if(theBuffer[b2]==reference[refcursor]) - { - if(!into) - binit=b2; - into=true; - refcursor++; - if(reference[refcursor]==0) - { - if(from) - *from=binit; - if(to) - *to=b2; - return true; - } - } - else if (into==true) - { - possible = 0; - into=false; - refcursor=0; - } - b2=(b2+1)& __BUFFERMASK__; - } - } - return false; -} - -bool GSM3CircularBuffer::extractSubstring(const char* from, const char* to, char* buffer, int bufsize) -{ - byte t1; - byte h2; - byte b; - int i; - -//DEBUG -//Serial.println("Beginning extractSubstring"); -//Serial.print("head,tail=");Serial.print(int(head));Serial.print(",");Serial.println(int(tail)); - - if(!locate(from, head, tail, 0, &t1)) - return false; - -//DEBUG -//Serial.println("Located chain from."); - - t1++; //To point the next. - if(!locate(to, t1, tail, &h2, 0)) - return false; - -//DEBUG -//Serial.println("Located chain to."); -/*Serial.print("t1=");Serial.println(int(t1)); -Serial.print("h2=");Serial.println(int(h2));*/ - - - for(i=0,b=t1;i='0')&&(c<='9')) - { - anyfound=true; - res=(res*10)+(int)c-48; - } - else - { - if(negative) - res=(-1)*res; - return res; - } - } - if(negative) - res=(-1)*res; - return res; -} - -void GSM3CircularBuffer::debugBuffer() -{ - byte h1=head; - byte t1=tail; - Serial.println(); - Serial.print(h1); - Serial.print(" "); - Serial.print(t1); - Serial.print('>'); - for(byte b=h1; b!=t1; b=(b+1)& __BUFFERMASK__) - printCharDebug(theBuffer[b]); - Serial.println(); -} - -void GSM3CircularBuffer::printCharDebug(uint8_t c) -{ - if((c>31)&&(c<127)) - Serial.print((char)c); - else - { - Serial.print('%'); - Serial.print(c); - Serial.print('%'); - } -} - -bool GSM3CircularBuffer::retrieveBuffer(char* buffer, int bufsize, int& SizeWritten) -{ - byte b; - int i; - - /*for(i=0,b=head;i -#include - -#ifndef byte -#define byte uint8_t -#endif - -// These values have to be interrelated -// To-Do: may we have just one? (BUFFERMASK) -#define __BUFFERSIZE__ 128 -#define __BUFFERMASK__ 0x7F - -class GSM3CircularBufferManager -{ - public: - - /** If there is spaceAvailable in the buffer, lets send a XON - */ - virtual void spaceAvailable(); -}; - -class GSM3CircularBuffer -{ - private: - // Buffer pointers. - // head=tail means buffer empty - // tail=head-1 means buffer full - // tail=head+1 means just one char (pointed by head) - // REMEMBER. head can be moved only by the main program - // REMEMBER. tail can be moved only by the other thread (interrupts) - // REMEMBER. head and tail can move only FORWARD - volatile byte head; // First written one - volatile byte tail; // Last written one. - - GSM3CircularBufferManager* cbm; // Circular buffer manager - - // The buffer - volatile byte theBuffer[__BUFFERSIZE__]; - - /** Checks if a substring exists in the buffer - @param reference Substring - @param thishead Head - @param thistail Tail - @param from Initial byte position - @param to Final byte position - @return true if exists, in otherwise return false - */ - bool locate(const char* reference, byte thishead, byte thistail, byte* from=0, byte* to=0); - - public: - - /** Constructor - @param mgr Circular buffer manager - */ - GSM3CircularBuffer(GSM3CircularBufferManager* mgr=0); - - // TO-DO.Check if this formule runs too at the buffer limit - - /** Get available bytes in circular buffer - @return available bytes - */ - inline byte availableBytes(){ return ((head-(tail+1))&__BUFFERMASK__);}; - - /** Stored bytes in circular buffer - @return stored bytes - */ - inline byte storedBytes(){ return ((tail-head)&__BUFFERMASK__);}; - - /** Write a character in circular buffer - @param c Character - @return 1 if successful - */ - int write(char c); - - /** Returns a character and moves the pointer - @return character - */ - char read(); - - /** Returns a character but does not move the pointer. - @param increment Increment - @return character - */ - char peek(int increment); - - /** Returns a pointer to the head of the buffer - @return buffer with pointer in head - */ - inline char* firstString(){return (char*)theBuffer+head;}; - - /** Go forward one string - @return buffer with one string advance - */ - char* nextString(); - - /** Flush circular buffer - */ - void flush(); - - /** Get tail - @return tail - */ - inline byte getTail(){return tail;}; - - /** Get head - @return head - */ - inline byte getHead(){return head;}; - - // Only can be executed from the interrupt! - /** Delete circular buffer to the end - @param from Initial byte position - */ - inline void deleteToTheEnd(byte from){tail=from;}; - - /** Checks if a substring exists in the buffer - move=0, dont move, =1,put head at the beginning of the string, =2, put head at the end - @param reference - @return true if exists, in otherwise return false - */ - bool locate(const char* reference); - - /** Locates reference. If found, moves head (or tail) to the beginning (or end) - @param reference - @param movetotheend - @param head - @return true if successful - */ - bool chopUntil(const char* reference, bool movetotheend, bool head=true); - - /** Reads an integer from the head. Stops with first non blank, non number character - @return integer from the head - */ - int readInt(); - - // Caveat: copies the first bytes until buffer is full - - /** Extract a substring from circular buffer - @param from Initial byte position - @param to Final byte position - @param buffer Buffer for copy substring - @param bufsize Buffer size - @return true if successful, false if substring does not exists - */ - bool extractSubstring(const char* from, const char* to, char* buffer, int bufsize); - - /** Retrieve all the contents of buffer from head to tail - @param buffer - @param bufsize - @param SizeWritten - @return true if successful - */ - bool retrieveBuffer(char* buffer, int bufsize, int& SizeWritten); - - /** Debug function to print the buffer after receiving data from the modem. - */ - void debugBuffer(); - - /** Utility: dump character if printable, else, put in %x% - @param c Character - */ - static void printCharDebug(uint8_t c); -}; - - -#endif diff --git a/libraries/GSM/src/GSM3IO.h b/libraries/GSM/src/GSM3IO.h deleted file mode 100644 index da1e784768..0000000000 --- a/libraries/GSM/src/GSM3IO.h +++ /dev/null @@ -1,59 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifdef TTOPEN_V1 - #define __POWERPIN__ 5 - #define __RESETPIN__ 6 -#else - #define __RESETPIN__ 7 -#endif - -#if defined(__AVR_ATmega328P__) - #ifdef TTOPEN_V1 - #define __TXPIN__ 3 - #define __RXPIN__ 4 - #define __RXINT__ 3 - #else - #define __TXPIN__ 3 - #define __RXPIN__ 2 - #define __RXINT__ 3 - #endif -#elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) - #define __TXPIN__ 3 - #define __RXPIN__ 10 - #define __RXINT__ 4 -#elif defined(__AVR_ATmega32U4__) - #define __TXPIN__ 3 - #define __RXPIN__ 8 - #define __RXINT__ 3 -#endif diff --git a/libraries/GSM/src/GSM3MobileAccessProvider.cpp b/libraries/GSM/src/GSM3MobileAccessProvider.cpp deleted file mode 100644 index 225069b2b9..0000000000 --- a/libraries/GSM/src/GSM3MobileAccessProvider.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3MobileAccessProvider* theGSM3MobileAccessProvider; diff --git a/libraries/GSM/src/GSM3MobileAccessProvider.h b/libraries/GSM/src/GSM3MobileAccessProvider.h deleted file mode 100644 index b9b8d0f278..0000000000 --- a/libraries/GSM/src/GSM3MobileAccessProvider.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILEACCESSPROVIDER_ -#define _GSM3MOBILEACCESSPROVIDER_ - -enum GSM3_NetworkStatus_t { GSM_ERROR, IDLE, CONNECTING, GSM_READY, GPRS_READY, TRANSPARENT_CONNECTED, OFF}; - -class GSM3MobileAccessProvider -{ - public: - // Access functions - //Configuration functions. - /** Establish GSM connection - @param pin PIN code - @param restart Determines if hardware restart - @param synchronous Determines sync mode - @return If synchronous, GSM3_NetworkStatus_t. If asynchronous, returns 0. - */ - virtual inline GSM3_NetworkStatus_t begin(char* pin=0,bool restart=true, bool synchronous=true)=0; - - /** Check network access status - @return 1 if Alive, 0 if down - */ - virtual inline int isAccessAlive()=0; - - /** Shutdown the modem (power off really) - @return true if successful - */ - virtual inline bool shutdown()=0; - - /** Secure shutdown the modem (power off really) - @return always true - */ - virtual inline bool secureShutdown()=0; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; -}; - -#endif diff --git a/libraries/GSM/src/GSM3MobileCellManagement.cpp b/libraries/GSM/src/GSM3MobileCellManagement.cpp deleted file mode 100644 index 5db2717f86..0000000000 --- a/libraries/GSM/src/GSM3MobileCellManagement.cpp +++ /dev/null @@ -1,34 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include diff --git a/libraries/GSM/src/GSM3MobileCellManagement.h b/libraries/GSM/src/GSM3MobileCellManagement.h deleted file mode 100644 index 035dfee996..0000000000 --- a/libraries/GSM/src/GSM3MobileCellManagement.h +++ /dev/null @@ -1,53 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILECELLMANAGEMENT_ -#define _GSM3MOBILECELLMANAGEMENT_ - -#include - -class GSM3MobileCellManagement -{ - public: - - virtual inline int getLocation() {return 0;}; - - virtual inline int getICCID() {return 0;}; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; -}; - -#endif diff --git a/libraries/GSM/src/GSM3MobileClientProvider.cpp b/libraries/GSM/src/GSM3MobileClientProvider.cpp deleted file mode 100644 index 0de3ceea70..0000000000 --- a/libraries/GSM/src/GSM3MobileClientProvider.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3MobileClientProvider* theGSM3MobileClientProvider; diff --git a/libraries/GSM/src/GSM3MobileClientProvider.h b/libraries/GSM/src/GSM3MobileClientProvider.h deleted file mode 100644 index a771ff46d1..0000000000 --- a/libraries/GSM/src/GSM3MobileClientProvider.h +++ /dev/null @@ -1,156 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_MOBILECLIENTPROVIDER__ -#define __GSM3_MOBILECLIENTPROVIDER__ - -#include -#include - -class GSM3MobileClientProvider -{ - protected: - - uint8_t sockets; - - public: - - /** Constructor */ - GSM3MobileClientProvider(){}; - - /** Minimum socket - @return socket - */ - virtual inline int minSocket()=0; - - /** Maximum socket - @return socket - */ - virtual inline int maxSocket()=0; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; - - /** Get status socket client - @param socket Socket - @return 1 if connected - */ - virtual bool getStatusSocketClient(uint8_t socket)=0; - - // Socket management - - /** Get socket - @param socket Socket - @return socket - */ - virtual int getSocket(int socket=-1)=0; - - /** Release socket - @param socket Socket - */ - virtual void releaseSocket(int socket)=0; - - // Client socket functions - - /** Connect to a server via TCP connection - @param server Server name or IP address in a String - @param port Port - @param id_socket Socket - @return 0 if command running, 1 if success, otherwise error - */ - virtual int connectTCPClient(const char* server, int port, int id_socket)=0; - - /** Connect to a server (by IP address) via TCP connection - @param add IP address in IPAddress format - @param port Port - @param id_socket Socket - @return 0 if command running, 1 if success, otherwise error - */ - virtual int connectTCPClient(IPAddress add, int port, int id_socket)=0; - - /** Begin writing through a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - virtual void beginWriteSocket(bool client1Server0, int id_socket)=0; - - /** Write through a socket. MUST go after beginWriteSocket() - @param c character to be written - */ - virtual void writeSocket(uint8_t c)=0; - - /** Write through a socket. MUST go after beginWriteSocket() - @param buf characters to be written (final 0 will not be written) - */ - virtual void writeSocket(const char* buf)=0; - - /** Finish current writing - */ - virtual void endWriteSocket()=0; - - /** Check if there are data to be read in socket. - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if there are data available, 4 if no data, otherwise error - */ - virtual int availableSocket(bool client, int id_socket)=0; - - /** Read data (get a character) available in socket - @return character - */ - virtual int readSocket()=0; - - /** Flush socket - */ - virtual void flushSocket()=0; - - /** Get a character but will not advance the buffer head - @return character - */ - virtual int peekSocket()=0; - - /** Close a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Socket - @return 0 if command running, 1 if success, otherwise error - */ - virtual int disconnectTCP(bool client1Server0, int idsocket)=0; - -}; - -extern GSM3MobileClientProvider* theGSM3MobileClientProvider; - -#endif diff --git a/libraries/GSM/src/GSM3MobileClientService.cpp b/libraries/GSM/src/GSM3MobileClientService.cpp deleted file mode 100644 index 7fcb4fe653..0000000000 --- a/libraries/GSM/src/GSM3MobileClientService.cpp +++ /dev/null @@ -1,260 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -// While there is only a shield (ShieldV1) we will include it by default -#include -GSM3ShieldV1ClientProvider theShieldV1ClientProvider; - - -#define GSM3MOBILECLIENTSERVICE_CLIENT 0x01 // 1: This side is Client. 0: This side is Server -#define GSM3MOBILECLIENTSERVICE_WRITING 0x02 // 1: TRUE 0: FALSE -#define GSM3MOBILECLIENTSERVICE_SYNCH 0x04 // 1: TRUE, compatible with other clients 0: FALSE - -#define __TOUTBEGINWRITE__ 10000 - - -GSM3MobileClientService::GSM3MobileClientService(bool synch) -{ - flags = GSM3MOBILECLIENTSERVICE_CLIENT; - if(synch) - flags |= GSM3MOBILECLIENTSERVICE_SYNCH; - mySocket=255; -} - -GSM3MobileClientService::GSM3MobileClientService(int socket, bool synch) -{ - // We are creating a socket on an existing, occupied one. - flags=0; - if(synch) - flags |= GSM3MOBILECLIENTSERVICE_SYNCH; - mySocket=socket; - theGSM3MobileClientProvider->getSocket(socket); - -} - -// Returns 0 if last command is still executing -// 1 if success -// >1 if error -int GSM3MobileClientService::ready() -{ - return theGSM3MobileClientProvider->ready(); -} - -int GSM3MobileClientService::connect(IPAddress add, uint16_t port) -{ - if(theGSM3MobileClientProvider==0) - return 2; - - // TODO: ask for the socket id - mySocket=theGSM3MobileClientProvider->getSocket(); - - if(mySocket<0) - return 2; - - int res=theGSM3MobileClientProvider->connectTCPClient(add, port, mySocket); - if(flags & GSM3MOBILECLIENTSERVICE_SYNCH) - res=waitForAnswer(); - - return res; -}; - -int GSM3MobileClientService::connect(const char *host, uint16_t port) -{ - - if(theGSM3MobileClientProvider==0) - return 2; - // TODO: ask for the socket id - mySocket=theGSM3MobileClientProvider->getSocket(); - - if(mySocket<0) - return 2; - - int res=theGSM3MobileClientProvider->connectTCPClient(host, port, mySocket); - if(flags & GSM3MOBILECLIENTSERVICE_SYNCH) - res=waitForAnswer(); - - return res; -} - -int GSM3MobileClientService::waitForAnswer() -{ - unsigned long m; - m=millis(); - int res; - - while(((millis()-m)< __TOUTBEGINWRITE__ )&&(ready()==0)) - delay(100); - - res=ready(); - - // If we get something different from a 1, we are having a problem - if(res!=1) - res=0; - - return res; -} - -void GSM3MobileClientService::beginWrite(bool sync) -{ - flags |= GSM3MOBILECLIENTSERVICE_WRITING; - theGSM3MobileClientProvider->beginWriteSocket(flags & GSM3MOBILECLIENTSERVICE_CLIENT, mySocket); - if(sync) - waitForAnswer(); -} - -size_t GSM3MobileClientService::write(uint8_t c) -{ - if(!(flags & GSM3MOBILECLIENTSERVICE_WRITING)) - beginWrite(true); - theGSM3MobileClientProvider->writeSocket(c); - return 1; -} - -size_t GSM3MobileClientService::write(const uint8_t* buf) -{ - if(!(flags & GSM3MOBILECLIENTSERVICE_WRITING)) - beginWrite(true); - theGSM3MobileClientProvider->writeSocket((const char*)(buf)); - return strlen((const char*)buf); -} - -size_t GSM3MobileClientService::write(const uint8_t* buf, size_t sz) -{ - if(!(flags & GSM3MOBILECLIENTSERVICE_WRITING)) - beginWrite(true); - for(unsigned int i=0;iwriteSocket(buf[i]); - return sz; -} - -void GSM3MobileClientService::endWrite(bool sync) -{ - flags ^= GSM3MOBILECLIENTSERVICE_WRITING; - theGSM3MobileClientProvider->endWriteSocket(); - if(sync) - waitForAnswer(); -} - -uint8_t GSM3MobileClientService::connected() -{ - if(mySocket==255) - return 0; - return theGSM3MobileClientProvider->getStatusSocketClient(mySocket); -} - -GSM3MobileClientService::operator bool() -{ - return connected()==1; -}; - -int GSM3MobileClientService::available() -{ - int res; - - // Even if not connected, we are looking for available data - - if(flags & GSM3MOBILECLIENTSERVICE_WRITING) - endWrite(true); - - res=theGSM3MobileClientProvider->availableSocket(flags & GSM3MOBILECLIENTSERVICE_CLIENT,mySocket); - if(flags & GSM3MOBILECLIENTSERVICE_SYNCH) - res=waitForAnswer(); - - return res; -} - -int GSM3MobileClientService::read(uint8_t *buf, size_t size) -{ - unsigned int i; - uint8_t c; - - for(i=0;ireadSocket(flags & GSM3MOBILECLIENTSERVICE_CLIENT, (char *)(buf), size, mySocket); - - return res; -*/ -} - -int GSM3MobileClientService::read() -{ - if(flags & GSM3MOBILECLIENTSERVICE_WRITING) - endWrite(true); - int c=theGSM3MobileClientProvider->readSocket(); - return c; -} - -int GSM3MobileClientService::peek() -{ - if(flags & GSM3MOBILECLIENTSERVICE_WRITING) - endWrite(true); - return theGSM3MobileClientProvider->peekSocket(/*mySocket, false*/); -} - -void GSM3MobileClientService::flush() -{ - if(flags & GSM3MOBILECLIENTSERVICE_WRITING) - endWrite(true); - theGSM3MobileClientProvider->flushSocket(/*mySocket*/); - if(flags & GSM3MOBILECLIENTSERVICE_SYNCH) - waitForAnswer(); - -} - -void GSM3MobileClientService::stop() -{ - if(flags & GSM3MOBILECLIENTSERVICE_WRITING) - endWrite(true); - theGSM3MobileClientProvider->disconnectTCP(flags & GSM3MOBILECLIENTSERVICE_CLIENT, mySocket); - theGSM3MobileClientProvider->releaseSocket(mySocket); - mySocket = 0; - if(flags & GSM3MOBILECLIENTSERVICE_SYNCH) - waitForAnswer(); -} - diff --git a/libraries/GSM/src/GSM3MobileClientService.h b/libraries/GSM/src/GSM3MobileClientService.h deleted file mode 100644 index 5a36a975c9..0000000000 --- a/libraries/GSM/src/GSM3MobileClientService.h +++ /dev/null @@ -1,162 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILECLIENTSERVICE_ -#define _GSM3MOBILECLIENTSERVICE_ - -#include -#include - - -class GSM3MobileClientService : public Client -{ - private: - - uint8_t mySocket; - uint8_t flags; - - /** Blocks waiting for an answer - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int waitForAnswer(); - - public: - - /** Constructor - @param synch Sync mode - */ - GSM3MobileClientService(bool synch=true); - - /** Constructor - @param socket Socket - @param synch Sync mode - */ - GSM3MobileClientService(int socket, bool synch); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - - // we take this function out as IPAddress is complex to bring to - // version 1. - /** Connect to server by IP address - @param (IPAddress) - @param (uint16_t) - @return returns 0 if last command is still executing, 1 success, 2 if there are no resources - */ - inline int connect(IPAddress, uint16_t); - - /** Connect to server by hostname - @param host Hostname - @param port Port - @return returns 0 if last command is still executing, 1 success, 2 if there are no resources - */ - int connect(const char *host, uint16_t port); - - /** Initialize write in request - @param sync Sync mode - */ - void beginWrite(bool sync=false); - - /** Write a character in request - @param c Character - @return size - */ - size_t write(uint8_t c); - - /** Write a characters buffer in request - @param buf Buffer - @return buffer size - */ - size_t write(const uint8_t *buf); - - /** Write a characters buffer with size in request - @param (uint8_t*) Buffer - @param (size_t) Buffer size - @return buffer size - */ - size_t write(const uint8_t*, size_t); - - /** Finish write request - @param sync Sync mode - */ - void endWrite(bool sync=false); - - /** Check if connected to server - @return 1 if connected - */ - uint8_t connected(); - - operator bool(); - - /** Read from response buffer and copy size specified to buffer - @param buf Buffer - @param size Buffer size - @return bytes read - */ - int read(uint8_t *buf, size_t size); - - /** Read a character from response buffer - @return character - */ - int read(); - - /** Check if exists a response available - @return 1 if exists, 0 if not exists - */ - int available(); - - /** Read a character from response buffer but does not move the pointer. - @return character - */ - int peek(); - - /** Flush response buffer - */ - void flush(); - - /** Stop client - */ - void stop(); - - /** Get socket - @return socket - */ - inline int getSocket(){return (int)mySocket;}; - - -}; - - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3MobileDataNetworkProvider.cpp b/libraries/GSM/src/GSM3MobileDataNetworkProvider.cpp deleted file mode 100644 index c57c341687..0000000000 --- a/libraries/GSM/src/GSM3MobileDataNetworkProvider.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -// GSM3MobileDataNetworkProvider* theGSM3MobileDataNetworkProvider; diff --git a/libraries/GSM/src/GSM3MobileDataNetworkProvider.h b/libraries/GSM/src/GSM3MobileDataNetworkProvider.h deleted file mode 100644 index bffd381fa7..0000000000 --- a/libraries/GSM/src/GSM3MobileDataNetworkProvider.h +++ /dev/null @@ -1,62 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILEDATANETWORKPROVIDER_ -#define _GSM3MOBILEDATANETWORKPROVIDER_ - -#include - -// This class is not really useful, but serves as a guideline for programmers -// We keep it but it should never be linked -class GSM3MobileDataNetworkProvider -{ - public: - - /** Attach to GPRS/GSM network - @param networkId APN GPRS - @param user Username - @param pass Password - @return connection status - */ - virtual GSM3_NetworkStatus_t networkAttach(char* networId, char* user, char* pass)=0; - - /** Detach GPRS/GSM network - @return connection status - */ - virtual GSM3_NetworkStatus_t networkDetach()=0; - -}; - -extern GSM3MobileDataNetworkProvider* theGSM3MobileDataNetworkProvider; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3MobileMockupProvider.cpp b/libraries/GSM/src/GSM3MobileMockupProvider.cpp deleted file mode 100644 index e3eba258d3..0000000000 --- a/libraries/GSM/src/GSM3MobileMockupProvider.cpp +++ /dev/null @@ -1,194 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include -//#include -#include - - -GSM3MobileMockupProvider::GSM3MobileMockupProvider() -{ - lineStatus=IDLE; - msgExample="Hello#World"; - msgIndex=0; -} - -int GSM3MobileMockupProvider::begin(char* pin) -{ - Serial.println("GSM3MobileMockupProvider::begin()"); - return 0; -} - -int GSM3MobileMockupProvider::ready() -{ - Serial.println("GSM3MobileMockupProvider::ready()"); - return 1; -} - -int GSM3MobileMockupProvider::beginSMS(const char* number) -{ - Serial.println("SM3MobileMockupProvider::beginSMS()"); - return 0; -} - -void GSM3MobileMockupProvider::writeSMS(char c) -{ - Serial.print(c); -} - -int GSM3MobileMockupProvider::endSMS() -{ - Serial.println("GSM3MobileMockupProvider::endSMS()"); - return 1; -} - -int GSM3MobileMockupProvider::availableSMS() -{ - Serial.println("GSM3MobileMockupProvider::availableSMS()"); - return 120; -} - -int GSM3MobileMockupProvider::peek() -{ - return (int)'H'; -} - -int GSM3MobileMockupProvider::remoteSMSNumber(char* number, int nlength) -{ - if(nlength>=13) - strcpy(number, "+34630538546"); - return 12; -} - - -void GSM3MobileMockupProvider::flushSMS() -{ - Serial.println("GSM3MobileMockupProvider::flushSMS()"); -} - -int GSM3MobileMockupProvider::readSMS() -{ - if(msgExample[msgIndex]==0) - { - msgIndex=0; - return 0; - } - else - { - msgIndex++; - return msgExample[msgIndex-1]; - }; -} - -int GSM3MobileMockupProvider::connectTCPClient(const char* server, int port, int id_socket) -{ - Serial.println("GSM3MobileMockupProvider::connectTCPClient()"); - Serial.print(server);Serial.print(":");Serial.print(port);Serial.print("-");Serial.println(id_socket); - return 1; -} - -void GSM3MobileMockupProvider::writeSocket(const uint8_t *buf, size_t size, int id_socket) -{ - unsigned int i; - for(i=0;i=minSocket())&&(socket<=maxSocket())) - return 1; - else - return 0; -}; -*/ - -int GSM3MobileMockupProvider::readSocket(uint8_t *buf, size_t size, int idsocket) -{ - unsigned int i; - unsigned int l=strlen(msgExample); - for(i=0;(i12)) - strcpy("192.168.1.1", localIP); - return 1; -} - -bool GSM3MobileMockupProvider::getSocketModemStatus(uint8_t s) -{ - // Feeling lazy - return true; -} - diff --git a/libraries/GSM/src/GSM3MobileMockupProvider.h b/libraries/GSM/src/GSM3MobileMockupProvider.h deleted file mode 100644 index 90bacbc5ef..0000000000 --- a/libraries/GSM/src/GSM3MobileMockupProvider.h +++ /dev/null @@ -1,255 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILEMOCKUPPROVIDER_ -#define _GSM3MOBILEMOCKUPPROVIDER_ - -#include -#include - -class GSM3MobileMockupProvider: public GSM3MobileNetworkProvider -{ - private: - // Introducing this status is quite "heavy". But something like this should - // be added to ShieldV1. Or not. - // Note, in ShieldV1 there is no "RECEIVINGSMS" status. - enum GSM3_modemlinest_e { IDLE, WAITINGANSWER, SENDINGSMS}; - GSM3_modemlinest_e lineStatus; - const char* msgExample; - int msgIndex; - - public: - - /** Minimum socket - @return 1 - */ - inline int minSocket(){return 1;}; - - /** Maximum socket - @return 8 - */ - inline int maxSocket(){return 8;}; - - /** Constructor */ - GSM3MobileMockupProvider(); - - /** Get network status - @return network status - */ - inline GSM3_NetworkStatus_t getStatus(){return GSM_ERROR;}; - - /** Get voice call status - @return call status - */ - inline GSM3_voiceCall_st getvoiceCallStatus(){return IDLE_CALL;}; - - /** Get last command status - @return Returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - inline void closeCommand(int code){}; - - //Configuration functions. - - /** Begin connection - @param pin PIN code - @return - */ - int begin(char* pin=0); - - /** Check if is modem alive - @return 0 - */ - inline int isModemAlive(){return 0;}; - - /** Shutdown the modem (power off really) - @return true if successful - */ - inline bool shutdown(){return false;}; - - //Call functions - - /** Launch a voice call - @param number Phone number to be called - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - inline int voiceCall(const char* number){return 0;}; - - /** Answer a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - inline int answerCall(){return 0;}; - - /** Hang a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - inline int hangCall(){return 0;}; - - /** Retrieve phone number of caller - @param buffer Buffer for copy phone number - @param bufsize Buffer size - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - inline int retrieveCallingNumber(char* buffer, int*& bufsize){return 0;}; - - // SMS functions - - /** Begin a SMS to send it - @param number Destination - @return error command if it exists - */ - int beginSMS(const char* number); - - /** End SMS - @return error command if it exists - */ - int endSMS(); - - /** Check if SMS available and prepare it to be read - @return error command if it exists - */ - int availableSMS(); - - /** Read a byte but do not advance the buffer header (circular buffer) - @return character - */ - int peek(); - - /** Delete the SMS from Modem memory and proccess answer - */ - void flushSMS(); - - /** Read sender number phone - @param number Buffer for save number phone - @param nlength Buffer length - @return 1 success, >1 error - */ - int remoteSMSNumber(char* number, int nlength); - - /** Read one char for SMS buffer (advance circular buffer) - @return character - */ - int readSMS(); - - /** Write a SMS character by character - @param c Character - */ - void writeSMS(char c); - - // Socket functions - - /** Connect to a remote TCP server - @param server String with IP or server name - @param port Remote port number - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int connectTCPClient(const char* server, int port, int id_socket); - - // Attention to parameter rewriting in ShieldV1 - /** Write buffer information into a socket - @param buf Buffer - @param size Buffer size - @param idsocket Socket - */ - void writeSocket(const uint8_t *buf, size_t size, int idsocket); - - // ShieldV1 will have two reading mechanisms: - // Mechanism 1: Call AT+QIRD for size bytes. Put them in the circular buffer, - // fill buf. Take care to xon/xoff effect, as we may copy just a part of the - // incoming bytes. - /** Read socket and put information in a buffer - @param buf Buffer - @param size Buffer size - @param idsocket Socket - @return - */ - int readSocket(uint8_t *buf, size_t size, int idsocket); - - // Mechanism 2 in ShieldV1: - // When called "available()" or "read()" reuse readSocket code to execute - // QIRD SYNCHRONOUSLY. Ask the modem for 1500 bytes but do not copy them anywhere, - // leave data in the circular buffer. Put buffer head at the start of received data. - // Peek() will get a character but will not advance the buffer head. - // Read() will get one character. XON/XOFF will take care of buffer filling - // If Read() gets to the end of the QIRD response, execute again QIRD SYNCHRONOUSLY - // If the user executes flush(), execute read() until there is nothing more to read() - // (the modem gives no way to empty the socket of incoming data) - - /** Check if there are data to be read in socket. - @param idsocket Local socket number - @return 0 if command running, 1 if there are data available, 4 if no data, otherwise error - */ - int availableSocket(int idsocket); - - /** Read data (get a character) available in socket - @param idsocket Socket - @param advance Determines if advance the buffer head - @return character - */ - int readSocket(int idsocket, bool advance=true); - - /** Flush socket - @param idsocket Socket - */ - void flushSocket(int idsocket); - - // This is the same in ShieldV1 - /** Close a socket - @param idsocket Socket - @return 0 if command running, 1 if success, otherwise error - */ - int disconnectTCP(int idsocket); - - // TCP Server. Attention. Changing the int*&. We'll receive a buffer for the IP - // If the pointer ins NULL just forget it - // I think that opening a server does not occupy a socket. Is that true? - /** Establish a TCP connection - @param port Port - @param localIP IP address - @param localIPlength IP address size in characters - @return command error if exists - */ - int connectTCPServer(int port, char* localIP, int* localIPlength); - - // Modem sockets status. Return TRUE if the modem thinks the socket is occupied. - // This should be detected through an unrequisited response - /** Get modem status - @param s Socket - @return modem status (true if connected) - */ - bool getSocketModemStatus(uint8_t s); - - -}; -#endif diff --git a/libraries/GSM/src/GSM3MobileNetworkProvider.cpp b/libraries/GSM/src/GSM3MobileNetworkProvider.cpp deleted file mode 100644 index c9fe01af31..0000000000 --- a/libraries/GSM/src/GSM3MobileNetworkProvider.cpp +++ /dev/null @@ -1,71 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3MobileNetworkProvider* theProvider; - -GSM3MobileNetworkProvider::GSM3MobileNetworkProvider() -{ - socketsAsServer=0x0000; -}; - - -int GSM3MobileNetworkProvider::getNewOccupiedSocketAsServer() -{ - int i; - for(i=minSocketAsServer(); i<=maxSocketAsServer(); i++) - { - if ((!(socketsAsServer&(0x0001< -#include -#include -#include - -class GSM3MobileNetworkProvider -{ - private: - - /** Restart hardware - @return 1 if successful - */ - int HWrestart(); - - uint16_t socketsAsServer; // Server socket - - /** Get modem status - @param s Socket - @return modem status (true if connected) - */ - virtual inline bool getSocketAsServerModemStatus(int s){return false;}; - - public: - - /** minSocketAsServer - @return 0 - */ - virtual inline int minSocketAsServer(){return 0;}; - - /** maxSocketAsServer - @return 0 - */ - virtual inline int maxSocketAsServer(){return 0;}; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; - - /** Constructor */ - GSM3MobileNetworkProvider(); - - /** Get network status - @return network status - */ - virtual inline GSM3_NetworkStatus_t getStatus(){return GSM_ERROR;}; - - /** Get socket client status - @param socket Socket - @return 1 if connected, 0 otherwise - */ - bool getStatusSocketClient(uint8_t socket); - - /** Close a AT command - @param code Close code - */ - virtual inline void closeCommand(int code){}; - - /** Establish a TCP connection - @param port Port - @param localIP IP address - @param localIPlength IP address size in characters - @return command error if exists - */ - virtual inline int connectTCPServer(int port, char* localIP, int localIPlength){return 0;}; - - /** Get local IP address - @param LocalIP Buffer for save IP address - @param LocalIPlength Buffer size - */ - virtual inline int getIP(char* LocalIP, int LocalIPlength){return 0;}; - - /** Get new occupied socket - @return -1 if no new socket has been occupied - */ - int getNewOccupiedSocketAsServer(); - - /** Get socket status as server - @param socket Socket to get status - @return socket status - */ - bool getStatusSocketAsServer(uint8_t socket); - - /** Close a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int disconnectTCP(bool client1Server0, int idsocket){return 1;}; - - /** Release socket - @param socket Socket - */ - void releaseSocket(int socket){}; - -}; - -extern GSM3MobileNetworkProvider* theProvider; - -#endif diff --git a/libraries/GSM/src/GSM3MobileNetworkRegistry.cpp b/libraries/GSM/src/GSM3MobileNetworkRegistry.cpp deleted file mode 100644 index 5e22f3af81..0000000000 --- a/libraries/GSM/src/GSM3MobileNetworkRegistry.cpp +++ /dev/null @@ -1,51 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3MobileNetworkRegistry::GSM3MobileNetworkRegistry() -{ - theProvider=0; -}; - -void GSM3MobileNetworkRegistry::registerMobileNetworkProvider(GSM3MobileNetworkProvider* provider) -{ - theProvider=provider; -} - -GSM3MobileNetworkProvider* GSM3MobileNetworkRegistry::getMobileNetworkProvider() -{ - return theProvider; -} - -GSM3MobileNetworkRegistry theMobileNetworkRegistry; diff --git a/libraries/GSM/src/GSM3MobileNetworkRegistry.h b/libraries/GSM/src/GSM3MobileNetworkRegistry.h deleted file mode 100644 index de4397725f..0000000000 --- a/libraries/GSM/src/GSM3MobileNetworkRegistry.h +++ /dev/null @@ -1,63 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILENETWORKREGISTRY_ -#define _GSM3MOBILENETWORKREGISTRY_ -#include - -class GSM3MobileNetworkRegistry -{ - private: - - GSM3MobileNetworkProvider* theProvider; // Network provider - - public: - - /** Constructor */ - GSM3MobileNetworkRegistry(); - - /** Register in mobile network provider - @param provider Provider - */ - void registerMobileNetworkProvider(GSM3MobileNetworkProvider* provider); - - /** Returns network provider object pointer - @return mobile network provider - */ - GSM3MobileNetworkProvider* getMobileNetworkProvider(); - -}; - -extern GSM3MobileNetworkRegistry theMobileNetworkRegistry; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3MobileSMSProvider.cpp b/libraries/GSM/src/GSM3MobileSMSProvider.cpp deleted file mode 100644 index e5575ceb87..0000000000 --- a/libraries/GSM/src/GSM3MobileSMSProvider.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3MobileSMSProvider* theGSM3SMSProvider; diff --git a/libraries/GSM/src/GSM3MobileSMSProvider.h b/libraries/GSM/src/GSM3MobileSMSProvider.h deleted file mode 100644 index aa72711014..0000000000 --- a/libraries/GSM/src/GSM3MobileSMSProvider.h +++ /dev/null @@ -1,91 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILESMSPROVIDER_ -#define _GSM3MOBILESMSPROVIDER_ - -class GSM3MobileSMSProvider -{ - public: - - /** Begin a SMS to send it - @param to Destination - @return error command if it exists - */ - virtual inline int beginSMS(const char* to){return 0;}; - - /** Write a SMS character by character - @param c Character - */ - virtual inline void writeSMS(const char c){}; - - /** End SMS - @return error command if it exists - */ - virtual inline int endSMS(){return 0;}; - - /** Check if SMS available and prepare it to be read - @return number of bytes in a received SMS - */ - virtual inline int availableSMS(){return 0;}; - - /** Read a byte but do not advance the buffer header (circular buffer) - @return character - */ - virtual inline int peekSMS(){return 0;}; - - /** Delete the SMS from Modem memory and proccess answer - */ - virtual inline void flushSMS(){return;}; - - /** Read sender number phone - @param number Buffer for save number phone - @param nlength Buffer length - @return 1 success, >1 error - */ - virtual inline int remoteSMSNumber(char* number, int nlength){return 0;}; - - /** Read one char for SMS buffer (advance circular buffer) - @return character - */ - virtual inline int readSMS(){return 0;}; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; -}; - -extern GSM3MobileSMSProvider* theGSM3SMSProvider; - -#endif diff --git a/libraries/GSM/src/GSM3MobileServerProvider.cpp b/libraries/GSM/src/GSM3MobileServerProvider.cpp deleted file mode 100644 index d101bbab2a..0000000000 --- a/libraries/GSM/src/GSM3MobileServerProvider.cpp +++ /dev/null @@ -1,39 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#include - -GSM3MobileServerProvider* theGSM3MobileServerProvider; - - diff --git a/libraries/GSM/src/GSM3MobileServerProvider.h b/libraries/GSM/src/GSM3MobileServerProvider.h deleted file mode 100644 index e4eb9c5030..0000000000 --- a/libraries/GSM/src/GSM3MobileServerProvider.h +++ /dev/null @@ -1,95 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_MOBILESERVERPROVIDER__ -#define __GSM3_MOBILESERVERPROVIDER__ - - -#include -#include -#include - - -class GSM3MobileServerProvider -{ - /** Get socket status - @param s Socket - @return modem status (true if connected) - */ - virtual bool getSocketAsServerModemStatus(int s)=0; - - public: - - /** minSocketAsServer - @return socket - */ - virtual int minSocketAsServer()=0; - - /** maxSocketAsServer - @return socket - */ - virtual int maxSocketAsServer()=0; - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; - - /** Constructor */ - GSM3MobileServerProvider(){}; - - /** Connect server to TCP port - @param port TCP port - @return command error if exists - */ - virtual int connectTCPServer(int port)=0; - //virtual int getIP(char* LocalIP, int LocalIPlength)=0; - - /** Get new occupied socket as server - @return return -1 if no new socket has been occupied - */ - virtual int getNewOccupiedSocketAsServer()=0; - - /** Get socket status - @param socket Socket - @return socket status (true if connected) - */ - virtual bool getStatusSocketAsServer(uint8_t socket)=0; - - // virtual int disconnectTCP(bool client1Server0, int idsocket)=0; - -}; - -extern GSM3MobileServerProvider* theGSM3MobileServerProvider; - -#endif diff --git a/libraries/GSM/src/GSM3MobileServerService.cpp b/libraries/GSM/src/GSM3MobileServerService.cpp deleted file mode 100644 index 861bf5d05b..0000000000 --- a/libraries/GSM/src/GSM3MobileServerService.cpp +++ /dev/null @@ -1,160 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - - -#define __TOUTSERVER__ 10000 -#define BUFFERSIZETWEET 100 - -#define GSM3MOBILESERVERSERVICE_SYNCH 0x01 // 1: TRUE, compatible with other clients 0: FALSE - -// While there is only a shield (ShieldV1) we will include it by default -#include -GSM3ShieldV1ServerProvider theShieldV1ServerProvider; - - -GSM3MobileServerService::GSM3MobileServerService(uint8_t port, bool synch) -{ - mySocket=0; - _port=port; - flags = 0; - - // If synchronous - if(synch) - flags |= GSM3MOBILESERVERSERVICE_SYNCH; -} - -// Returns 0 if last command is still executing -// 1 if success -// >1 if error -int GSM3MobileServerService::ready() -{ - return theGSM3MobileServerProvider->ready(); -} - -void GSM3MobileServerService::begin() -{ - if(theGSM3MobileServerProvider==0) - return; - theGSM3MobileServerProvider->connectTCPServer(_port); - - if(flags & GSM3MOBILESERVERSERVICE_SYNCH) - waitForAnswer(); -} - -GSM3MobileClientService GSM3MobileServerService::available(bool synch) -{ - int newSocket; - // In case we are debugging, we'll need to force a look at the buffer - ready(); - - newSocket=theGSM3MobileServerProvider->getNewOccupiedSocketAsServer(); - - // Instatiate new client. If we are synch, the client is synchronous/blocking - GSM3MobileClientService client((uint8_t)(newSocket), (flags & GSM3MOBILESERVERSERVICE_SYNCH)); - - return client; -} - -size_t GSM3MobileServerService::write(uint8_t c) -{ -// Adapt to the new, lean implementation -// theGSM3MobileServerProvider->writeSocket(c); - return 1; -} - -void GSM3MobileServerService::beginWrite() -{ -// Adapt to the new, lean implementation -// theGSM3MobileServerProvider->beginWriteSocket(local1Remote0, mySocket); -} - -size_t GSM3MobileServerService::write(const uint8_t* buf) -{ -// Adapt to the new, lean implementation -// theGSM3MobileServerProvider->writeSocket((const char*)(buf)); - return strlen((const char*)buf); -} - -size_t GSM3MobileServerService::write(const uint8_t* buf, size_t sz) -{ -// Adapt to the new, lean implementation -// theGSM3MobileServerProvider->writeSocket((const char*)(buf)); - return strlen((const char*)buf); -} - -void GSM3MobileServerService::endWrite() -{ -// Adapt to the new, lean implementation -// theGSM3MobileServerProvider->endWriteSocket(); -} - -void GSM3MobileServerService::stop() -{ - - // Review, should be the server? - theGSM3MobileClientProvider->disconnectTCP(local1Remote0, mySocket); - if(flags & GSM3MOBILESERVERSERVICE_SYNCH) - waitForAnswer(); - theGSM3MobileClientProvider->releaseSocket(mySocket); - mySocket = -1; -} - - -/*int GSM3MobileServerService::getIP(char* LocalIP, int LocalIPlength) -{ - return theGSM3MobileServerProvider->getIP(LocalIP, LocalIPlength); -}*/ - -int GSM3MobileServerService::waitForAnswer() -{ - unsigned long m; - m=millis(); - int res; - - while(((millis()-m)< __TOUTSERVER__ )&&(ready()==0)) - delay(10); - - res=ready(); - - // If we get something different from a 1, we are having a problem - if(res!=1) - res=0; - - return res; -} - - diff --git a/libraries/GSM/src/GSM3MobileServerService.h b/libraries/GSM/src/GSM3MobileServerService.h deleted file mode 100644 index 12165eed1b..0000000000 --- a/libraries/GSM/src/GSM3MobileServerService.h +++ /dev/null @@ -1,124 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILESERVERSERVICE_ -#define _GSM3MOBILESERVERSERVICE_ - -#include -#include -#include - -class GSM3MobileServerService : public Server -{ - private: - - uint8_t _port; // Port - uint8_t mySocket; // Actual socket - uint8_t flags; - bool local1Remote0; - - /** Internal utility, used in synchronous calls - @return operation result, 1 if success, 0 otherwise - */ - int waitForAnswer(); - - public: - - /** Constructor - @param port Port - @param synch True if the server acts synchronously - */ - GSM3MobileServerService(uint8_t port, bool synch=true); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - - /** Initialize server - */ - void begin(); - - /** Check if there is an incoming client request - @param synch If true, the returned client is synchronous or - blocking. - @return Client if successful, else error - */ - GSM3MobileClientService available(bool synch=true); - - // Just to keep in line with Ethernet. - // Write to every open socket... - //void write(uint8_t); - //void write(const uint8_t *buf, size_t size); - - /** Begin write in socket - */ - void beginWrite(); - - /** Write character in socket - @param c Character - @return size - */ - size_t write(uint8_t c); - - /** Write buffer in socket - @param buf Buffer - @return size - */ - size_t write(const uint8_t *buf); - - /** Write buffer in socket with size - @param buf Buffer - @param sz Buffer size - @return size - */ - size_t write(const uint8_t *buf, size_t sz); - - /** End write in socket - */ - void endWrite(); - - /** Stop server - */ - void stop(); - - // we take this function out as IPAddress is complex to bring to - // version 1. - // inline int connect(IPAddress ip, uint16_t port){return 0;}; - // Returns 2 if there are no resources - //int getIP(char* LocalIP, int LocalIPlength); - -}; - - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3MobileVoiceProvider.cpp b/libraries/GSM/src/GSM3MobileVoiceProvider.cpp deleted file mode 100644 index 57c132932d..0000000000 --- a/libraries/GSM/src/GSM3MobileVoiceProvider.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -//GSM3MobileVoiceProvider* theGSM3MobileVoiceProvider; diff --git a/libraries/GSM/src/GSM3MobileVoiceProvider.h b/libraries/GSM/src/GSM3MobileVoiceProvider.h deleted file mode 100644 index add06c19f0..0000000000 --- a/libraries/GSM/src/GSM3MobileVoiceProvider.h +++ /dev/null @@ -1,88 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3MOBILEVOICEPROVIDER_ -#define _GSM3MOBILEVOICEPROVIDER_ - -enum GSM3_voiceCall_st { IDLE_CALL, CALLING, RECEIVINGCALL, TALKING}; - -class GSM3MobileVoiceProvider -{ - public: - - /** Initialize the object relating it to the general infrastructure - @param - @return void - */ - virtual void initialize(){}; - - /** Launch a voice call - @param number Phone number to be called - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - virtual int voiceCall(const char* number)=0; - - /** Answer a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - virtual int answerCall()=0; - - /** Hang a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - virtual int hangCall()=0; - - /** Retrieve phone number of caller - @param buffer Buffer for copy phone number - @param bufsize Buffer size - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - virtual int retrieveCallingNumber(char* buffer, int bufsize)=0; - - /** Returns voice call status - @return voice call status - */ - virtual GSM3_voiceCall_st getvoiceCallStatus()=0; - - /** Set voice call status - @param status New status for voice call - */ - virtual void setvoiceCallStatus(GSM3_voiceCall_st status)=0; - - /** Get last command status - @return Returns 0 if last command is still executing, 1 success, >1 error - */ - virtual int ready()=0; -}; - -#endif diff --git a/libraries/GSM/src/GSM3SMSService.cpp b/libraries/GSM/src/GSM3SMSService.cpp deleted file mode 100644 index 378dc2cc82..0000000000 --- a/libraries/GSM/src/GSM3SMSService.cpp +++ /dev/null @@ -1,126 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -// While there is only a shield (ShieldV1) we will include it by default -#include -GSM3ShieldV1SMSProvider theShieldV1SMSProvider; - -#define GSM3SMSSERVICE_SYNCH 0x01 // 1: synchronous 0: asynchronous -#define __TOUT__ 10000 - - -GSM3SMSService::GSM3SMSService(bool synch) -{ - if(synch) - flags |= GSM3SMSSERVICE_SYNCH; -} - -// Returns 0 if last command is still executing -// 1 if success -// >1 if error -int GSM3SMSService::ready() -{ - return theGSM3SMSProvider->ready(); -} - -int GSM3SMSService::beginSMS(const char *number) -{ - return waitForAnswerIfNeeded(theGSM3SMSProvider->beginSMS(number)); -}; - -int GSM3SMSService::endSMS() -{ - return waitForAnswerIfNeeded(theGSM3SMSProvider->endSMS()); -}; - -size_t GSM3SMSService::write(uint8_t c) -{ - theGSM3SMSProvider->writeSMS(c); - return 1; -} - -void GSM3SMSService::flush() -{ - theGSM3SMSProvider->flushSMS(); - waitForAnswerIfNeeded(1); -}; - -int GSM3SMSService::available() -{ - return waitForAnswerIfNeeded(theGSM3SMSProvider->availableSMS()); -}; - -int GSM3SMSService::remoteNumber(char* number, int nlength) -{ - return theGSM3SMSProvider->remoteSMSNumber(number, nlength); - -} - -int GSM3SMSService::read() -{ - return theGSM3SMSProvider->readSMS(); -}; -int GSM3SMSService::peek() -{ - return theGSM3SMSProvider->peekSMS(); -}; - -int GSM3SMSService::waitForAnswerIfNeeded(int returnvalue) -{ - // If synchronous - if(flags & GSM3SMSSERVICE_SYNCH ) - { - unsigned long m; - m=millis(); - // Wait for __TOUT__ - while(((millis()-m)< __TOUT__ )&&(ready()==0)) - delay(100); - // If everything was OK, return 1 - // else (timeout or error codes) return 0; - if(ready()==1) - return 1; - else - return 0; - } - // If not synchronous just kick ahead the coming result - return ready(); -} - - - - - diff --git a/libraries/GSM/src/GSM3SMSService.h b/libraries/GSM/src/GSM3SMSService.h deleted file mode 100644 index 878be114b2..0000000000 --- a/libraries/GSM/src/GSM3SMSService.h +++ /dev/null @@ -1,110 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SMSSERVICE_ -#define _GSM3SMSSERVICE_ - -#include -#include - -class GSM3SMSService : public Stream -{ - private: - - uint8_t flags; - - /** Makes synchronous the functions, if needed - @param returnvalue Return value - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int waitForAnswerIfNeeded(int returnvalue); - - public: - - /** Constructor - @param synch Determines sync mode - */ - GSM3SMSService(bool synch=true); - - /** Write a character in SMS message - @param c Character - @return size - */ - size_t write(uint8_t c); - - /** Begin a SMS to send it - @param to Destination - @return error command if it exists - */ - int beginSMS(const char* to); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - - /** End SMS - @return error command if it exists - */ - int endSMS(); - - /** Check if SMS available and prepare it to be read - @return number of bytes in a received SMS - */ - int available(); - - /** Read sender number phone - @param number Buffer for save number phone - @param nlength Buffer length - @return 1 success, >1 error - */ - int remoteNumber(char* number, int nlength); - - /** Read one char for SMS buffer (advance circular buffer) - @return byte - */ - int read(); - - /** Read a byte but do not advance the buffer header (circular buffer) - @return byte - */ - int peek(); - - /** Delete the SMS from Modem memory and proccess answer - */ - void flush(); - -}; - - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1.cpp b/libraries/GSM/src/GSM3ShieldV1.cpp deleted file mode 100644 index b478472aa3..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -#define __RESETPIN__ 7 -#define __TOUTLOCALCOMS__ 500 -#define __TOUTSHUTDOWN__ 5000 -#define __TOUTMODEMCONFIGURATION__ 5000//equivalent to 30000 because of time in interrupt routine. -#define __TOUTAT__ 1000 -#define __TOUTSMS__ 7000 -#define __TOUTCALL__ 15000 -#define __TOUTGPRS__ 10000 -#define __NCLIENTS_MAX__ 3 - -//Constructor. -GSM3ShieldV1::GSM3ShieldV1(bool db) -{ - theGSM3ShieldV1ModemCore.setCommandCounter(1); - socketsAccepted=0; - theGSM3ShieldV1ModemCore.registerUMProvider(this); - theProvider=this; -} - -//Response management. -void GSM3ShieldV1::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - - default: - break; - } -} - -//Function for 2 sec delay inside an interruption. -void GSM3ShieldV1::delayInsideInterrupt2seg() -{ - for (int k=0;k<40;k++) theGSM3ShieldV1ModemCore.gss.tunedDelay(50000); -} - -///////////////////////////////////////////////////////UNSOLICITED RESULT CODE (URC) FUNCTIONS/////////////////////////////////////////////////////////////////// - -//URC recognize. -bool GSM3ShieldV1::recognizeUnsolicitedEvent(byte oldTail) -{ - -//int nlength; -char auxLocate [15]; - //POWER DOWN. - prepareAuxLocate(PSTR("POWER DOWN"), auxLocate); - if(theGSM3ShieldV1ModemCore.gss.cb.locate(auxLocate)) - { - theGSM3ShieldV1ModemCore.gss.cb.flush(); - return true; - } - - return false; -} - - - diff --git a/libraries/GSM/src/GSM3ShieldV1.h b/libraries/GSM/src/GSM3ShieldV1.h deleted file mode 100644 index db52f7b0e0..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1.h +++ /dev/null @@ -1,137 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SHIELDV1__ -#define __GSM3_SHIELDV1__ - -#include -#include -#include -#include - - -class GSM3ShieldV1 : public GSM3MobileNetworkProvider, public GSM3ShieldV1BaseProvider -{ - // General code, for modem management - private: - - /** Delay inside an interrupt (2 seconds) - */ - void delayInsideInterrupt2seg(); - - // Code for SMS Service - private: - - - long commandMillis; - bool commandSent; - - const char* pinConfig; //PIN. - char* accessPoint; //APN. - char* userName; //User. - char* passw; //Password. - const char* remoteID; //Server. - - char* dataSocket; //Data socket. - int local_Port; //Local Port. - char* local_IP; //Local IP. - int local_IP_Length; //Local IP length. - - - int socketDataSize; //Size of socket data to be read. - int socketDataSizeWritten; //Number of socket data written in buffer not to overflow the buffer - - int socketsAccepted; //Status for remote clients accepted of closed. - - public: - - /** Constructor **/ - GSM3ShieldV1(bool debug=false); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Parse modem response - @param rsp Returns true if expected response exists - @param string1 Substring expected in response - @param string2 Second substring expected in response - @return true if parsed successful - */ - bool genericParse_rsp2(bool& rsp, char* string1, char* string2); - - /** Recognize URC - @param oldTail - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte oldTail); - - /** Receive answer - @return true if successful - */ - bool answerReceived(); - - /** Receive socket - @param id_socket Socket ID - @return true if successful - */ - bool socketReceived(int id_socket); - - /** Update active ID sockets - @param active Active sockets - @param ID Id for update - */ - void update_activeIDsockets (bool active, int ID); - - /** Assign ID to socket - @param ID Id to assign to socket - @return true if successful - */ - bool assignIDsocket (int& ID); - - /** Close data socket - @return true if successful - */ - bool closedDataSocket(); //Flag closed current data socket. - - //bool writeIncomingCalls(char* bufferForCallerId) If isn't zero, doesn't wait calls -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1AccessProvider.cpp b/libraries/GSM/src/GSM3ShieldV1AccessProvider.cpp deleted file mode 100644 index 87b5b62d12..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1AccessProvider.cpp +++ /dev/null @@ -1,364 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include -#include "GSM3IO.h" - -#define __TOUTSHUTDOWN__ 5000 -#define __TOUTMODEMCONFIGURATION__ 5000//equivalent to 30000 because of time in interrupt routine. -#define __TOUTAT__ 1000 - -const char _command_AT[] PROGMEM = "AT"; -const char _command_CGREG[] PROGMEM = "AT+CGREG?"; - - -GSM3ShieldV1AccessProvider::GSM3ShieldV1AccessProvider(bool debug) -{ - theGSM3ShieldV1ModemCore.setDebug(debug); - -} - -void GSM3ShieldV1AccessProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case MODEMCONFIG: - ModemConfigurationContinue(); - break; - case ALIVETEST: - isModemAliveContinue(); - break; - - default: - break; - } -} - -///////////////////////////////////////////////////////CONFIGURATION FUNCTIONS/////////////////////////////////////////////////////////////////// - -// Begin -// Restart or start the modem -// May be synchronous -GSM3_NetworkStatus_t GSM3ShieldV1AccessProvider::begin(char* pin, bool restart, bool synchronous) -{ - pinMode(__RESETPIN__, OUTPUT); - - #ifdef TTOPEN_V1 - pinMode(__POWERPIN__, OUTPUT); - digitalWrite(__POWERPIN__, HIGH); - #endif - - // If asked for modem restart, restart - if (restart) - HWrestart(); - else - HWstart(); - - theGSM3ShieldV1ModemCore.gss.begin(9600); - - if(NULL != theGSM3MobileVoiceProvider) - theGSM3MobileVoiceProvider->linkToModemProvider(); - - // Launch modem configuration commands - ModemConfiguration(pin); - // If synchronous, wait till ModemConfiguration is over - if(synchronous) - { - // if we shorten this delay, the command fails - while(ready()==0) - delay(1000); - } - return getStatus(); -} - -//HWrestart. -int GSM3ShieldV1AccessProvider::HWrestart() -{ - #ifdef TTOPEN_V1 - digitalWrite(__POWERPIN__, HIGH); - delay(1000); - #endif - - theGSM3ShieldV1ModemCore.setStatus(IDLE); - digitalWrite(__RESETPIN__, HIGH); - delay(12000); - digitalWrite(__RESETPIN__, LOW); - delay(1000); - - return 1; //configandwait(pin); -} - -//HWrestart. -int GSM3ShieldV1AccessProvider::HWstart() -{ - theGSM3ShieldV1ModemCore.setStatus(IDLE); - digitalWrite(__RESETPIN__, HIGH); - delay(2000); - digitalWrite(__RESETPIN__, LOW); - //delay(1000); - - return 1; //configandwait(pin); -} - -//Initial configuration main function. -int GSM3ShieldV1AccessProvider::ModemConfiguration(char* pin) -{ - theGSM3ShieldV1ModemCore.setPhoneNumber(pin); - theGSM3ShieldV1ModemCore.openCommand(this,MODEMCONFIG); - theGSM3ShieldV1ModemCore.setStatus(CONNECTING); - ModemConfigurationContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Initial configuration continue function. -void GSM3ShieldV1AccessProvider::ModemConfigurationContinue() -{ - bool resp; - - // 1: Send AT - // 2: Wait AT OK and SetPin or CGREG - // 3: Wait Pin OK and CGREG - // 4: Wait CGREG and Flow SW control or CGREG - // 5: Wait IFC OK and SMS Text Mode - // 6: Wait SMS text Mode OK and Calling line identification - // 7: Wait Calling Line Id OK and Echo off - // 8: Wait for OK and COLP command for connecting line identification. - // 9: Wait for OK. - int ct=theGSM3ShieldV1ModemCore.getCommandCounter(); - if(ct==1) - { - // Launch AT - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_AT); - } - else if(ct==2) - { - // Wait for AT - OK. - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // OK received - if(theGSM3ShieldV1ModemCore.getPhoneNumber() && (theGSM3ShieldV1ModemCore.getPhoneNumber()[0]!=0)) - { - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CPIN="), false); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - theGSM3ShieldV1ModemCore.genericCommand_rqc(theGSM3ShieldV1ModemCore.getPhoneNumber()); - } - else - { - //DEBUG - //Serial.println("AT+CGREG?"); - theGSM3ShieldV1ModemCore.setCommandCounter(4); - theGSM3ShieldV1ModemCore.takeMilliseconds(); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_CGREG); - } - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==3) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - theGSM3ShieldV1ModemCore.setCommandCounter(4); - theGSM3ShieldV1ModemCore.takeMilliseconds(); - theGSM3ShieldV1ModemCore.delayInsideInterrupt(2000); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_CGREG); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==4) - { - char auxLocate1 [12]; - char auxLocate2 [12]; - prepareAuxLocate(PSTR("+CGREG: 0,1"), auxLocate1); - prepareAuxLocate(PSTR("+CGREG: 0,5"), auxLocate2); - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, auxLocate1, auxLocate2)) - { - if(resp) - { - theGSM3ShieldV1ModemCore.setCommandCounter(5); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+IFC=1,1")); - } - else - { - // If not, launch command again - if(theGSM3ShieldV1ModemCore.takeMilliseconds() > __TOUTMODEMCONFIGURATION__) - { - theGSM3ShieldV1ModemCore.closeCommand(3); - } - else - { - theGSM3ShieldV1ModemCore.delayInsideInterrupt(2000); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_CGREG); - } - } - } - } - else if(ct==5) - { - // 5: Wait IFC OK - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - //Delay for SW flow control being active. - theGSM3ShieldV1ModemCore.delayInsideInterrupt(2000); - // 9: SMS Text Mode - theGSM3ShieldV1ModemCore.setCommandCounter(6); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CMGF=1")); - } - } - else if(ct==6) - { - // 6: Wait SMS text Mode OK - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - //Calling line identification - theGSM3ShieldV1ModemCore.setCommandCounter(7); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CLIP=1")); - } - } - else if(ct==7) - { - // 7: Wait Calling Line Id OK - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Echo off - theGSM3ShieldV1ModemCore.setCommandCounter(8); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("ATE0")); - } - } - else if(ct==8) - { - // 8: Wait ATEO OK, send COLP - // In Arduino Mega, attention, take away the COLP step - // It looks as we can only have 8 steps - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - theGSM3ShieldV1ModemCore.setCommandCounter(9); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+COLP=1")); - } - } - else if(ct==9) - { - // 9: Wait ATCOLP OK - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if (resp) - { - theGSM3ShieldV1ModemCore.setStatus(GSM_READY); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } -} - -//Alive Test main function. -int GSM3ShieldV1AccessProvider::isAccessAlive() -{ - theGSM3ShieldV1ModemCore.setCommandError(0); - theGSM3ShieldV1ModemCore.setCommandCounter(1); - theGSM3ShieldV1ModemCore.openCommand(this,ALIVETEST); - isModemAliveContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Alive Test continue function. -void GSM3ShieldV1AccessProvider::isModemAliveContinue() -{ -bool rsp; -switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_AT); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(rsp)) - { - if (rsp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Shutdown. -bool GSM3ShieldV1AccessProvider::shutdown() -{ - unsigned long m; - bool resp; - char auxLocate [18]; - - // It makes no sense to have an asynchronous shutdown - pinMode(__RESETPIN__, OUTPUT); - digitalWrite(__RESETPIN__, HIGH); - delay(1500); - digitalWrite(__RESETPIN__, LOW); - theGSM3ShieldV1ModemCore.setStatus(IDLE); - theGSM3ShieldV1ModemCore.gss.close(); - - m=millis(); - prepareAuxLocate(PSTR("POWER DOWN"), auxLocate); - while((millis()-m) < __TOUTSHUTDOWN__) - { - delay(1); - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, auxLocate)) - return resp; - } - return false; -} - -//Secure shutdown. -bool GSM3ShieldV1AccessProvider::secureShutdown() -{ - // It makes no sense to have an asynchronous shutdown - pinMode(__RESETPIN__, OUTPUT); - digitalWrite(__RESETPIN__, HIGH); - delay(900); - digitalWrite(__RESETPIN__, LOW); - theGSM3ShieldV1ModemCore.setStatus(OFF); - theGSM3ShieldV1ModemCore.gss.close(); - -#ifdef TTOPEN_V1 - _delay_ms(12000); - digitalWrite(__POWERPIN__, LOW); -#endif - - return true; -} diff --git a/libraries/GSM/src/GSM3ShieldV1AccessProvider.h b/libraries/GSM/src/GSM3ShieldV1AccessProvider.h deleted file mode 100644 index 638fb5f176..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1AccessProvider.h +++ /dev/null @@ -1,121 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SHIELDV1ACCESSPROVIDER_ -#define _GSM3SHIELDV1ACCESSPROVIDER_ - -#include -#include -#include - -class GSM3ShieldV1AccessProvider : public GSM3MobileAccessProvider, public GSM3ShieldV1BaseProvider -{ - private: - - /** Initialize main modem configuration - @param pin PIN code - @return command error if exists - */ - int ModemConfiguration(char* pin); - - /** Continue to modem configuration function - */ - void ModemConfigurationContinue(); - - /** Continue to check if modem alive function - */ - void isModemAliveContinue(); - - - public: - - /** Constructor - @param debug Determines debug mode - */ - - GSM3ShieldV1AccessProvider(bool debug=false); - - /** Start the GSM/GPRS modem, attaching to the GSM network - @param pin SIM PIN number (4 digits in a string, example: "1234"). If - NULL the SIM has no configured PIN. - @param restart Restart the modem. Default is TRUE. The modem receives - a signal through the Ctrl/D7 pin. If it is shut down, it will - start-up. If it is running, it will restart. Takes up to 10 - seconds - @param synchronous If TRUE the call only returns after the Start is complete - or fails. If FALSE the call will return inmediately. You have - to call repeatedly ready() until you get a result. Default is TRUE. - @return If synchronous, GSM3_NetworkStatus_t. If asynchronous, returns 0. - */ - GSM3_NetworkStatus_t begin(char* pin=0,bool restart=true, bool synchronous=true); - - /** Check network access status - @return 1 if Alive, 0 if down - */ - int isAccessAlive(); - - /** Shutdown the modem (power off really) - @return true if successful - */ - bool shutdown(); - - /** Secure shutdown the modem (power off really) - @return true if successful - */ - bool secureShutdown(); - - /** Returns 0 if last command is still executing - @return 1 if success, >1 if error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Returns modem status - @return modem network status - */ - inline GSM3_NetworkStatus_t getStatus(){return theGSM3ShieldV1ModemCore.getStatus();}; - - void manageResponse(byte from, byte to); - - /** Restart the modem (will shut down if running) - @return 1 if success, >1 if error - */ - int HWrestart(); - - /** Start the modem (will not shut down if running) - @return 1 if success, >1 if error - */ - int HWstart(); - -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1BandManagement.cpp b/libraries/GSM/src/GSM3ShieldV1BandManagement.cpp deleted file mode 100644 index 48132dfb10..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1BandManagement.cpp +++ /dev/null @@ -1,100 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3ShieldV1BandManagement::GSM3ShieldV1BandManagement(bool trace): modem(trace) -{ - quectelStrings[UNDEFINED]=""; - quectelStrings[EGSM_MODE]="\"EGSM_MODE\""; - quectelStrings[DCS_MODE]="\"DCS_MODE\""; - quectelStrings[PCS_MODE]="\"PCS_MODE\""; - quectelStrings[EGSM_DCS_MODE]="\"EGSM_DCS_MODE\""; - quectelStrings[GSM850_PCS_MODE]="\"GSM850_PCS_MODE\""; - quectelStrings[GSM850_EGSM_DCS_PCS_MODE]="\"GSM850_EGSM_DCS_PCS_MODE\""; -} - -GSM3_NetworkStatus_t GSM3ShieldV1BandManagement::begin() -{ - // check modem response - modem.begin(); - - // reset hardware - modem.restartModem(); - - return IDLE; -} - -String GSM3ShieldV1BandManagement::getBand() -{ - String modemResponse=modem.writeModemCommand("AT+QBAND?", 2000); - - for(GSM3GSMBand i=GSM850_EGSM_DCS_PCS_MODE;i>UNDEFINED;i=(GSM3GSMBand)((int)i-1)) - { - if(modemResponse.indexOf(quectelStrings[i])>=0) - return quectelStrings[i]; - } - - Serial.print("Unrecognized modem answer:"); - Serial.println(modemResponse); - - return ""; -} - -bool GSM3ShieldV1BandManagement::setBand(String band) -{ - String command; - String modemResponse; - bool found=false; - - command="AT+QBAND="; - for(GSM3GSMBand i=EGSM_MODE;((i<=GSM850_EGSM_DCS_PCS_MODE)&&(!found));i=(GSM3GSMBand)((int)i+1)) - { - String aux=quectelStrings[i]; - if(aux.indexOf(band)>=0) - { - command+=aux; - found=true; - } - } - - if(!found) - return false; - // Quad-band takes an awful lot of time - modemResponse=modem.writeModemCommand(command, 15000); - - if(modemResponse.indexOf("QBAND")>=0) - return true; - else - return false; -} diff --git a/libraries/GSM/src/GSM3ShieldV1BandManagement.h b/libraries/GSM/src/GSM3ShieldV1BandManagement.h deleted file mode 100644 index 8a17c098c9..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1BandManagement.h +++ /dev/null @@ -1,96 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3SHIELDV1BANDMANAGEMENT__ -#define __GSM3SHIELDV1BANDMANAGEMENT__ - -// This class executes band management functions for the ShieldV1 -#include - -#define NUMBEROFBANDS 7 -#define GSM_MODE_UNDEFINED "UNDEFINED" -#define GSM_MODE_EGSM "EGSM_MODE" -#define GSM_MODE_DCS "DCS_MODE" -#define GSM_MODE_PCS "PCS_MODE" -#define GSM_MODE_EGSM_DCS "EGSM_DCS_MODE" -#define GSM_MODE_GSM850_PCS "GSM850_PCS_MODE" -#define GSM_MODE_GSM850_EGSM_DCS_PCS "GSM850_EGSM_DCS_PCS_MODE" - -typedef enum {UNDEFINED, EGSM_MODE, DCS_MODE, PCS_MODE, EGSM_DCS_MODE, GSM850_PCS_MODE, GSM850_EGSM_DCS_PCS_MODE} GSM3GSMBand; - -// -// These are the bands and scopes: -// -// E-GSM(900) -// DCS(1800) -// PCS(1900) -// E-GSM(900)+DCS(1800) ex: Europe -// GSM(850)+PCS(1900) Ex: USA, South Am. -// GSM(850)+E-GSM(900)+DCS(1800)+PCS(1900) - -class GSM3ShieldV1BandManagement -{ - private: - - GSM3ShieldV1DirectModemProvider modem; // Direct access to modem - - const char* quectelStrings[NUMBEROFBANDS];// = {"\"EGSM_MODE\"", "\"DCS_MODE\"", "\"PCS_MODE\"", - //"\"EGSM_DCS_MODE\"", "\"GSM850_PCS_MODE\"", - //"\"GSM850_EGSM_DCS_PCS_MODE\""}; - - - public: - - /** Constructor - @param trace If true, dumps all AT dialogue to Serial - */ - GSM3ShieldV1BandManagement(bool trace=false); - - /** Forces modem hardware restart, so we begin from scratch - @return always returns IDLE status - */ - GSM3_NetworkStatus_t begin(); - - /** Get current modem work band - @return current modem work band - */ - String getBand(); - - /** Changes the modem operating band - @param band Desired new band - @return true if success, false otherwise - */ - bool setBand(String band); - -}; -#endif diff --git a/libraries/GSM/src/GSM3ShieldV1BaseProvider.cpp b/libraries/GSM/src/GSM3ShieldV1BaseProvider.cpp deleted file mode 100644 index a5dd71fc38..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1BaseProvider.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -// Returns 0 if last command is still executing -// 1 if success -// >1 if error -int GSM3ShieldV1BaseProvider::ready() -{ - theGSM3ShieldV1ModemCore.manageReceivedData(); - return theGSM3ShieldV1ModemCore.getCommandError(); -}; - -void GSM3ShieldV1BaseProvider::prepareAuxLocate(PGM_P str, char auxLocate[]) -{ - int i=0; - char c; - - do - { - c=pgm_read_byte_near(str + i); - auxLocate[i]=c; - i++; - } while (c!=0); -} - diff --git a/libraries/GSM/src/GSM3ShieldV1BaseProvider.h b/libraries/GSM/src/GSM3ShieldV1BaseProvider.h deleted file mode 100644 index 8f03947cd1..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1BaseProvider.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SHIELDV1BASEPROVIDER_ -#define _GSM3SHIELDV1BASEPROVIDER_ - -#include - -enum GSM3_commandType_e { XON, NONE, MODEMCONFIG, ALIVETEST, BEGINSMS, ENDSMS, AVAILABLESMS, FLUSHSMS, - VOICECALL, ANSWERCALL, HANGCALL, RETRIEVECALLINGNUMBER, - ATTACHGPRS, DETACHGPRS, CONNECTTCPCLIENT, DISCONNECTTCP, BEGINWRITESOCKET, ENDWRITESOCKET, - AVAILABLESOCKET, FLUSHSOCKET, CONNECTSERVER, GETIP, GETCONNECTSTATUS, GETLOCATION, GETICCID}; - -class GSM3ShieldV1BaseProvider -{ - public: - - /** Get last command status - @return Returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - - /** This function locates strings from PROGMEM in the buffer - @param str PROGMEN - @param auxLocate Buffer where to locate strings - */ - void prepareAuxLocate(PGM_P str, char auxLocate[]); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - virtual void manageResponse(byte from, byte to); - - /** Recognize URC - @param from - @return true if successful (default: false) - */ - virtual bool recognizeUnsolicitedEvent(byte from){return false;}; - -}; - -#endif diff --git a/libraries/GSM/src/GSM3ShieldV1CellManagement.cpp b/libraries/GSM/src/GSM3ShieldV1CellManagement.cpp deleted file mode 100644 index 2419ed8e6a..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1CellManagement.cpp +++ /dev/null @@ -1,204 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include - -GSM3ShieldV1CellManagement::GSM3ShieldV1CellManagement() -{ -} - -bool GSM3ShieldV1CellManagement::parseQCCID_available(bool& rsp) -{ - char c; - bool iccidFound = false; - int i = 0; - - while(((c = theGSM3ShieldV1ModemCore.theBuffer().read()) != 0) & (i < 19)) - { - if((c < 58) & (c > 47)) - iccidFound = true; - - if(iccidFound) - { - bufferICCID[i] = c; - i++; - } - } - bufferICCID[i]=0; - - return true; -} - -bool GSM3ShieldV1CellManagement::parseQENG_available(bool& rsp) -{ - char c; - char location[50] = ""; - int i = 0; - - if (!(theGSM3ShieldV1ModemCore.theBuffer().chopUntil("+QENG: ", true))) - rsp = false; - else - rsp = true; - - if (!(theGSM3ShieldV1ModemCore.theBuffer().chopUntil("+QENG:", true))) - rsp = false; - else - rsp = true; - - while(((c = theGSM3ShieldV1ModemCore.theBuffer().read()) != 0) & (i < 50)) - { - location[i] = c; - i++; - } - location[i]=0; - - char* res_tok = strtok(location, ","); - res_tok=strtok(NULL, ","); - strcpy(countryCode, res_tok); - res_tok=strtok(NULL, ","); - strcpy(networkCode, res_tok); - res_tok=strtok(NULL, ","); - strcpy(locationArea, res_tok); - res_tok=strtok(NULL, ","); - strcpy(cellId, res_tok); - - return true; -} - -int GSM3ShieldV1CellManagement::getLocation(char *country, char *network, char *area, char *cell) -{ - if((theGSM3ShieldV1ModemCore.getStatus() != GSM_READY) && (theGSM3ShieldV1ModemCore.getStatus() != GPRS_READY)) - return 2; - - countryCode=country; - networkCode=network; - locationArea=area; - cellId=cell; - - theGSM3ShieldV1ModemCore.openCommand(this,GETLOCATION); - getLocationContinue(); - - unsigned long timeOut = millis(); - while(((millis() - timeOut) < 5000) & (ready() == 0)); - - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -void GSM3ShieldV1CellManagement::getLocationContinue() -{ - bool resp; - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.gss.tunedDelay(3000); - delay(3000); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QENG=1"), false); - theGSM3ShieldV1ModemCore.print("\r"); - break; - case 2: - if (theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - theGSM3ShieldV1ModemCore.gss.tunedDelay(3000); - delay(3000); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QENG?"), false); - theGSM3ShieldV1ModemCore.print("\r"); - } - else theGSM3ShieldV1ModemCore.closeCommand(1); - break; - case 3: - if (resp) - { - parseQENG_available(resp); - theGSM3ShieldV1ModemCore.closeCommand(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(2); - break; - } -} - -int GSM3ShieldV1CellManagement::getICCID(char *iccid) -{ - if((theGSM3ShieldV1ModemCore.getStatus() != GSM_READY) && (theGSM3ShieldV1ModemCore.getStatus() != GPRS_READY)) - return 2; - - bufferICCID=iccid; - theGSM3ShieldV1ModemCore.openCommand(this,GETICCID); - getICCIDContinue(); - - unsigned long timeOut = millis(); - while(((millis() - timeOut) < 5000) & (ready() == 0)); - - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -void GSM3ShieldV1CellManagement::getICCIDContinue() -{ - bool resp; - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QCCID"), false); - theGSM3ShieldV1ModemCore.print("\r"); - break; - case 2: - if (theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - parseQCCID_available(resp); - theGSM3ShieldV1ModemCore.closeCommand(2); - } - else theGSM3ShieldV1ModemCore.closeCommand(1); - break; - } -} - -void GSM3ShieldV1CellManagement::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case GETLOCATION: - getLocationContinue(); - break; - case GETICCID: - getICCIDContinue(); - break; - - default: - break; - } -} diff --git a/libraries/GSM/src/GSM3ShieldV1CellManagement.h b/libraries/GSM/src/GSM3ShieldV1CellManagement.h deleted file mode 100644 index 78307da3b0..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1CellManagement.h +++ /dev/null @@ -1,92 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SHIELDV1CELLMANAGEMENT__ -#define __GSM3_SHIELDV1CELLMANAGEMENT__ - -#include -#include -#include - -class GSM3ShieldV1CellManagement : public GSM3MobileCellManagement, public GSM3ShieldV1BaseProvider -{ - public: - - /** Constructor - */ - GSM3ShieldV1CellManagement(); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** getLocation - @return current cell location - */ - int getLocation(char *country, char *network, char *area, char *cell); - - /** getICCID - */ - int getICCID(char *iccid); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - private: - - char *countryCode; - char *networkCode; - char *locationArea; - char *cellId; - - char *bufferICCID; - - /** Continue to getLocation function - */ - void getLocationContinue(); - - /** Continue to getICCID function - */ - void getICCIDContinue(); - - bool parseQENG_available(bool& rsp); - - bool parseQCCID_available(bool& rsp); - -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1ClientProvider.cpp b/libraries/GSM/src/GSM3ShieldV1ClientProvider.cpp deleted file mode 100644 index 86ad84a58a..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ClientProvider.cpp +++ /dev/null @@ -1,330 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -GSM3ShieldV1ClientProvider::GSM3ShieldV1ClientProvider() -{ - theGSM3MobileClientProvider=this; -}; - -//Response management. -void GSM3ShieldV1ClientProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case CONNECTTCPCLIENT: - connectTCPClientContinue(); - break; - case FLUSHSOCKET: - flushSocketContinue(); - break; - - default: - break; - } -} - -//Connect TCP main function. -int GSM3ShieldV1ClientProvider::connectTCPClient(const char* server, int port, int id_socket) -{ - theGSM3ShieldV1ModemCore.setPort(port); - idSocket = id_socket; - - theGSM3ShieldV1ModemCore.setPhoneNumber((char*)server); - theGSM3ShieldV1ModemCore.openCommand(this,CONNECTTCPCLIENT); - theGSM3ShieldV1ModemCore.registerUMProvider(this); - connectTCPClientContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -int GSM3ShieldV1ClientProvider::connectTCPClient(IPAddress add, int port, int id_socket) -{ - remoteIP=add; - theGSM3ShieldV1ModemCore.setPhoneNumber(0); - return connectTCPClient(0, port, id_socket); -} - -//Connect TCP continue function. -void GSM3ShieldV1ClientProvider::connectTCPClientContinue() -{ - bool resp; - // 0: Dot or DNS notation activation - // 1: Disable SW flow control - // 2: Waiting for IFC OK - // 3: Start-up TCP connection "AT+QIOPEN" - // 4: Wait for connection OK - // 5: Wait for CONNECT - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIDNSIP="), false); - if ((theGSM3ShieldV1ModemCore.getPhoneNumber()!=0)&& - ((*(theGSM3ShieldV1ModemCore.getPhoneNumber())<'0')||((*(theGSM3ShieldV1ModemCore.getPhoneNumber())>'9')))) - { - theGSM3ShieldV1ModemCore.print('1'); - theGSM3ShieldV1ModemCore.print('\r'); - } - else - { - theGSM3ShieldV1ModemCore.print('0'); - theGSM3ShieldV1ModemCore.print('\r'); - } - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - //Response received - if(resp) - { - // AT+QIOPEN - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIOPEN="),false); - theGSM3ShieldV1ModemCore.print("\"TCP\",\""); - if(theGSM3ShieldV1ModemCore.getPhoneNumber()!=0) - { - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPhoneNumber()); - } - else - { - remoteIP.printTo(theGSM3ShieldV1ModemCore); - } - theGSM3ShieldV1ModemCore.print('"'); - theGSM3ShieldV1ModemCore.print(','); - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPort()); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - if(resp) - { - // OK Received - // Great. Go for the next step - theGSM3ShieldV1ModemCore.setCommandCounter(4); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 4: - char auxLocate [12]; - prepareAuxLocate(PSTR("CONNECT\r\n"), auxLocate); - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp,auxLocate)) - { - // Response received - if(resp) - { - // Received CONNECT OK - // Great. We're done - theGSM3ShieldV1ModemCore.setStatus(TRANSPARENT_CONNECTED); - theGSM3ShieldV1ModemCore.theBuffer().chopUntil(auxLocate, true); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - - } -} - -//Disconnect TCP main function. -int GSM3ShieldV1ClientProvider::disconnectTCP(bool client1Server0, int id_socket) -{ - // id Socket does not really mean anything, in this case we have - // only one socket running - theGSM3ShieldV1ModemCore.openCommand(this,DISCONNECTTCP); - - // If we are not closed, launch the command -//[ZZ] if(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED) -// { - delay(1000); - theGSM3ShieldV1ModemCore.print("+++"); - delay(1000); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QICLOSE")); - theGSM3ShieldV1ModemCore.setStatus(GPRS_READY); -// } - // Looks like it runs everytime, so we simply flush to death and go on - do - { - // Empty the local buffer, and tell the modem to XON - // If meanwhile we receive a DISCONNECT we should detect it as URC. - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - // Give some time for the buffer to refill - delay(100); - theGSM3ShieldV1ModemCore.closeCommand(1); - }while(theGSM3ShieldV1ModemCore.theBuffer().storedBytes()>0); - - theGSM3ShieldV1ModemCore.unRegisterUMProvider(this); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - - -//Write socket first chain main function. -void GSM3ShieldV1ClientProvider::beginWriteSocket(bool client1Server0, int id_socket) -{ -} - - -//Write socket next chain function. -void GSM3ShieldV1ClientProvider::writeSocket(const char* buf) -{ - if(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED) - theGSM3ShieldV1ModemCore.print(buf); -} - -//Write socket character function. -void GSM3ShieldV1ClientProvider::writeSocket(uint8_t c) -{ - if(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED) - theGSM3ShieldV1ModemCore.print((char)c); -} - -//Write socket last chain main function. -void GSM3ShieldV1ClientProvider::endWriteSocket() -{ -} - - -//Available socket main function. -int GSM3ShieldV1ClientProvider::availableSocket(bool client1Server0, int id_socket) -{ - - if(!(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED)) - theGSM3ShieldV1ModemCore.closeCommand(4); - - if(theGSM3ShieldV1ModemCore.theBuffer().storedBytes()) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(4); - - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -int GSM3ShieldV1ClientProvider::readSocket() -{ - char charSocket; - - if(theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==/*0*/__BUFFERSIZE__) - { - return 0; - } - - charSocket = theGSM3ShieldV1ModemCore.theBuffer().read(); - - if(theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==100) - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - - return charSocket; - -} - -//Read socket main function. -int GSM3ShieldV1ClientProvider::peekSocket() -{ - return theGSM3ShieldV1ModemCore.theBuffer().peek(0); -} - - -//Flush SMS main function. -void GSM3ShieldV1ClientProvider::flushSocket() -{ - theGSM3ShieldV1ModemCore.openCommand(this,FLUSHSOCKET); - - flushSocketContinue(); -} - -//Send SMS continue function. -void GSM3ShieldV1ClientProvider::flushSocketContinue() -{ - // If we have incomed data - if(theGSM3ShieldV1ModemCore.theBuffer().storedBytes()>0) - { - // Empty the local buffer, and tell the modem to XON - // If meanwhile we receive a DISCONNECT we should detect it as URC. - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - } - else - { - //We're done - theGSM3ShieldV1ModemCore.closeCommand(1); - } -} - -// URC recognize. -// Yes, we recognize "closes" in client mode -bool GSM3ShieldV1ClientProvider::recognizeUnsolicitedEvent(byte oldTail) -{ - char auxLocate [12]; - prepareAuxLocate(PSTR("CLOSED"), auxLocate); - - if((theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED) & theGSM3ShieldV1ModemCore.theBuffer().chopUntil(auxLocate, false, false)) - { - theGSM3ShieldV1ModemCore.setStatus(GPRS_READY); - theGSM3ShieldV1ModemCore.unRegisterUMProvider(this); - return true; - } - - return false; -} - -int GSM3ShieldV1ClientProvider::getSocket(int socket) -{ - return 0; -} - -void GSM3ShieldV1ClientProvider::releaseSocket(int socket) -{ - -} - -bool GSM3ShieldV1ClientProvider::getStatusSocketClient(uint8_t socket) -{ - return (theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED); - -}; - - - diff --git a/libraries/GSM/src/GSM3ShieldV1ClientProvider.h b/libraries/GSM/src/GSM3ShieldV1ClientProvider.h deleted file mode 100644 index fa2f8b58a8..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ClientProvider.h +++ /dev/null @@ -1,181 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SHIELDV1CLIENTPROVIDER__ -#define __GSM3_SHIELDV1CLIENTPROVIDER__ - -#include -#include - -class GSM3ShieldV1ClientProvider : public GSM3MobileClientProvider, public GSM3ShieldV1BaseProvider -{ - private: - - int remotePort; //Current operation remote port. - IPAddress remoteIP; // Remote IP address - int idSocket; // Remote ID socket. - - - /** Continue to connect TCP client function - */ - void connectTCPClientContinue(); - - /** Continue to available socket function - */ - void availableSocketContinue(); - - /** Continue to flush socket function - */ - void flushSocketContinue(); - - public: - - /** Constructor */ - GSM3ShieldV1ClientProvider(); - - /** minSocket - @return 0 - */ - int minSocket(){return 0;}; - - /** maxSocket - @return 0 - */ - int maxSocket(){return 0;}; - - /** Connect to a remote TCP server - @param server String with IP or server name - @param port Remote port number - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int connectTCPClient(const char* server, int port, int id_socket); - - /** Connect to a remote TCP server - @param add Remote IP address - @param port Remote port number - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int connectTCPClient(IPAddress add, int port, int id_socket); - - /** Begin writing through a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - void beginWriteSocket(bool client1Server0, int id_socket); - - /** Write through a socket. MUST go after beginWriteSocket() - @param buf characters to be written (final 0 will not be written) - */ - void writeSocket(const char* buf); - - /** Write through a socket. MUST go after beginWriteSocket() - @param c character to be written - */ - void writeSocket(uint8_t c); - - /** Finish current writing - */ - void endWriteSocket(); - - /** Check if there are data to be read in socket. - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if there are data available, 4 if no data, otherwise error - */ - int availableSocket(bool client, int id_socket); // With "available" and "readSocket" ask the modem for 1500 bytes. - - /** Read data (get a character) available in socket - @return character - */ - int readSocket(); //If Read() gets to the end of the QIRD response, execute again QIRD SYNCHRONOUSLY - - /** Flush socket - */ - void flushSocket(); - - /** Get a character but will not advance the buffer head - @return character - */ - int peekSocket(); - - /** Close a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Socket - @return 0 if command running, 1 if success, otherwise error - */ - int disconnectTCP(bool client1Server0, int id_socket); - - /** Recognize unsolicited event - @param oldTail - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte from); - - /** Manages modem response - @param from Initial byte position - @param to Final byte position - */ - void manageResponse(byte from, byte to); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - // Client socket management, just to be compatible - // with the Multi option - - /** Get socket - @param socket Socket - @return socket - */ - int getSocket(int socket=-1); - - /** Release socket - @param socket Socket - */ - void releaseSocket(int socket); - - /** Get socket client status - @param socket Socket - @return 1 if connected, 0 otherwise - */ - bool getStatusSocketClient(uint8_t socket); - -}; - - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.cpp b/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.cpp deleted file mode 100644 index 88372d6cb5..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.cpp +++ /dev/null @@ -1,401 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -const char _command_CGATT[] PROGMEM = "AT+CGATT="; -const char _command_SEPARATOR[] PROGMEM = "\",\""; - -//Attach GPRS main function. -GSM3_NetworkStatus_t GSM3ShieldV1DataNetworkProvider::attachGPRS(char* apn, char* user_name, char* password, bool synchronous) -{ - user = user_name; - passwd = password; - // A sad use of byte reuse - theGSM3ShieldV1ModemCore.setPhoneNumber(apn); - - theGSM3ShieldV1ModemCore.openCommand(this,ATTACHGPRS); - theGSM3ShieldV1ModemCore.setStatus(CONNECTING); - - attachGPRSContinue(); - - // If synchronous, wait till attach is over, or not. - if(synchronous) - { - // if we shorten this delay, the command fails - while(ready()==0) - delay(100); - } - - return theGSM3ShieldV1ModemCore.getStatus(); -} - -//Atthach GPRS continue function. -void GSM3ShieldV1DataNetworkProvider::attachGPRSContinue() -{ - bool resp; - // 1: Attach to GPRS service "AT+CGATT=1" - // 2: Wait attach OK and Set the context 0 as FGCNT "AT+QIFGCNT=0" - // 3: Wait context OK and Set bearer type as GPRS, APN, user name and pasword "AT+QICSGP=1..." - // 4: Wait bearer OK and Enable the function of MUXIP "AT+QIMUX=1" - // 5: Wait for disable MUXIP OK and Set the session mode as non transparent "AT+QIMODE=0" - // 6: Wait for session mode OK and Enable notification when data received "AT+QINDI=1" - // 8: Wait domain name OK and Register the TCP/IP stack "AT+QIREGAPP" - // 9: Wait for Register OK and Activate FGCNT "AT+QIACT" - // 10: Wait for activate OK - - int ct=theGSM3ShieldV1ModemCore.getCommandCounter(); - if(ct==1) - { - //AT+CGATT - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_CGATT,false); - theGSM3ShieldV1ModemCore.print(1); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - } - else if(ct==2) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - //AT+QIFGCNT - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIFGCNT=0")); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==3) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // Great. Go for the next step - //DEBUG - //Serial.println("AT+QICSGP."); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QICSGP=1,\""),false); - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPhoneNumber()); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_SEPARATOR,false); - theGSM3ShieldV1ModemCore.print(user); - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_SEPARATOR,false); - theGSM3ShieldV1ModemCore.print(passwd); - theGSM3ShieldV1ModemCore.print("\"\r"); - theGSM3ShieldV1ModemCore.setCommandCounter(4); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==4) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // AT+QIMUX=1 for multisocket - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIMUX=0")); - theGSM3ShieldV1ModemCore.setCommandCounter(5); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==5) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - //AT+QIMODE=0 for multisocket - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIMODE=1")); - theGSM3ShieldV1ModemCore.setCommandCounter(6); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==6) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // AT+QINDI=1 - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QINDI=1")); - theGSM3ShieldV1ModemCore.setCommandCounter(8); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==8) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // AT+QIREGAPP - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIREGAPP")); - theGSM3ShieldV1ModemCore.setCommandCounter(9); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==9) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if(resp) - { - // AT+QIACT - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIACT")); - theGSM3ShieldV1ModemCore.setCommandCounter(10); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - else if(ct==10) - { - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if (resp) - { - theGSM3ShieldV1ModemCore.setStatus(GPRS_READY); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - } -} - -//Detach GPRS main function. -GSM3_NetworkStatus_t GSM3ShieldV1DataNetworkProvider::detachGPRS(bool synchronous) -{ - theGSM3ShieldV1ModemCore.openCommand(this,DETACHGPRS); - theGSM3ShieldV1ModemCore.setStatus(CONNECTING); - detachGPRSContinue(); - - if(synchronous) - { - while(ready()==0) - delay(1); - } - - return theGSM3ShieldV1ModemCore.getStatus(); -} - -void GSM3ShieldV1DataNetworkProvider::detachGPRSContinue() -{ - bool resp; - // 1: Detach to GPRS service "AT+CGATT=0" - // 2: Wait dettach +PDP DEACT - // 3: Wait for OK - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //AT+CGATT=0 - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_CGATT,false); - theGSM3ShieldV1ModemCore.print(0); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - char auxLocate[12]; - prepareAuxLocate(PSTR("+PDP DEACT"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - if(resp) - { - // Received +PDP DEACT; - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // OK received - if (resp) - { - theGSM3ShieldV1ModemCore.setStatus(GSM_READY); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - break; - } -} - -//QILOCIP parse. -bool GSM3ShieldV1DataNetworkProvider::parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp) -{ - if (!(theGSM3ShieldV1ModemCore.theBuffer().extractSubstring("\r\n","\r\n", LocalIP, LocalIPlength))) - rsp = false; - else - rsp = true; - return true; -} - -//Get IP main function. -int GSM3ShieldV1DataNetworkProvider::getIP(char* LocalIP, int LocalIPlength) -{ - theGSM3ShieldV1ModemCore.setPhoneNumber(LocalIP); - theGSM3ShieldV1ModemCore.setPort(LocalIPlength); - theGSM3ShieldV1ModemCore.openCommand(this,GETIP); - getIPContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -void GSM3ShieldV1DataNetworkProvider::getIPContinue() -{ - - bool resp; - // 1: Read Local IP "AT+QILOCIP" - // 2: Waiting for IP. - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //AT+QILOCIP - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QILOCIP")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseQILOCIP_rsp(theGSM3ShieldV1ModemCore.getPhoneNumber(), theGSM3ShieldV1ModemCore.getPort(), resp)) - { - if (resp) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - break; - } -} - -//Get IP with IPAddress object -IPAddress GSM3ShieldV1DataNetworkProvider::getIPAddress() { - char ip_temp[15]=""; - getIP(ip_temp, 15); - unsigned long m=millis(); - - while((millis()-m)<10*1000 && (!ready())){ - // wait for a response from the modem: - delay(100); - } - IPAddress ip; - inet_aton(ip_temp, ip); - return ip; -} - -int GSM3ShieldV1DataNetworkProvider::inet_aton(const char* aIPAddrString, IPAddress& aResult) -{ - // See if we've been given a valid IP address - const char* p =aIPAddrString; - while (*p && - ( (*p == '.') || (*p >= '0') || (*p <= '9') )) - { - p++; - } - - if (*p == '\0') - { - // It's looking promising, we haven't found any invalid characters - p = aIPAddrString; - int segment =0; - int segmentValue =0; - while (*p && (segment < 4)) - { - if (*p == '.') - { - // We've reached the end of a segment - if (segmentValue > 255) - { - // You can't have IP address segments that don't fit in a byte - return 0; - } - else - { - aResult[segment] = (byte)segmentValue; - segment++; - segmentValue = 0; - } - } - else - { - // Next digit - segmentValue = (segmentValue*10)+(*p - '0'); - } - p++; - } - // We've reached the end of address, but there'll still be the last - // segment to deal with - if ((segmentValue > 255) || (segment > 3)) - { - // You can't have IP address segments that don't fit in a byte, - // or more than four segments - return 0; - } - else - { - aResult[segment] = (byte)segmentValue; - return 1; - } - } - else - { - return 0; - } -} - -//Response management. -void GSM3ShieldV1DataNetworkProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case ATTACHGPRS: - attachGPRSContinue(); - break; - case DETACHGPRS: - detachGPRSContinue(); - break; - case GETIP: - getIPContinue(); - break; - - default: - break; - } -} diff --git a/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.h b/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.h deleted file mode 100644 index 012a0ca541..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1DataNetworkProvider.h +++ /dev/null @@ -1,140 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SHIELDV1DATANETWORKPROVIDER_ -#define _GSM3SHIELDV1DATANETWORKPROVIDER_ - -#include -#include -#include -#include - -class GSM3ShieldV1DataNetworkProvider : public GSM3MobileDataNetworkProvider, public GSM3ShieldV1BaseProvider -{ - private: - - char* user; // Username for GPRS - char* passwd; // Password for GPRS - - /** Continue to attach GPRS function - */ - void attachGPRSContinue(); - - /** Continue to detach GPRS function - */ - void detachGPRSContinue(); - - /** Parse QILOCIP response - @param LocalIP Buffer for save local IP address - @param LocalIPlength Buffer size - @param rsp Returns true if expected response exists - @return true if command executed correctly - */ - bool parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp); - - /** Continue to get IP function - */ - void getIPContinue(); - - /** Implementation of inet_aton standard function - @param aIPAddrString IP address in characters buffer - @param aResult IP address in IPAddress format - @return 1 if the address is successfully converted, or 0 if the conversion failed - */ - int inet_aton(const char* aIPAddrString, IPAddress& aResult); - - public: - - /** Attach to GPRS/GSM network - @param networkId APN GPRS - @param user Username - @param pass Password - @return connection status - */ - GSM3_NetworkStatus_t networkAttach(char* networkId, char* user, char* pass) - { - return attachGPRS(networkId, user, pass); - }; - - /** Detach GPRS/GSM network - @return connection status - */ - GSM3_NetworkStatus_t networkDetach(){ return detachGPRS();}; - - /** Attach to GPRS service - @param apn APN GPRS - @param user_name Username - @param password Password - @param synchronous Sync mode - @return connection status - */ - GSM3_NetworkStatus_t attachGPRS(char* apn, char* user_name, char* password, bool synchronous=true); - - /** Detach GPRS service - @param synchronous Sync mode - @return connection status - */ - GSM3_NetworkStatus_t detachGPRS(bool synchronous=true); - - /** Returns 0 if last command is still executing - @return 1 if success, >1 if error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Get network status (connection) - @return status - */ - inline GSM3_NetworkStatus_t getStatus(){return theGSM3ShieldV1ModemCore.getStatus();}; - - /** Get actual assigned IP address - @param LocalIP Buffer for copy IP address - @param LocalIPlength Buffer length - @return command error if exists - */ - int getIP(char* LocalIP, int LocalIPlength); - - /** Get actual assigned IP address in IPAddress format - @return IP address in IPAddress format - */ - IPAddress getIPAddress(); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.cpp b/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.cpp deleted file mode 100644 index 454b27f622..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include -#include - -#define __RESETPIN__ 7 - -//Constructor -GSM3ShieldV1DirectModemProvider::GSM3ShieldV1DirectModemProvider(bool t) -{ - trace=t; -}; - -void GSM3ShieldV1DirectModemProvider::begin() -{ - theGSM3ShieldV1ModemCore.gss.begin(9600); -} - -void GSM3ShieldV1DirectModemProvider::restartModem() -{ - pinMode(__RESETPIN__, OUTPUT); - digitalWrite(__RESETPIN__, HIGH); - delay(12000); - digitalWrite(__RESETPIN__, LOW); - delay(1000); - -} - -//To enable the debug process -void GSM3ShieldV1DirectModemProvider::connect() -{ - theGSM3ShieldV1ModemCore.registerActiveProvider(this); -} - -//To disable the debug process -void GSM3ShieldV1DirectModemProvider::disconnect() -{ - theGSM3ShieldV1ModemCore.registerActiveProvider(0); -} - -//Write to the modem by means of SoftSerial -size_t GSM3ShieldV1DirectModemProvider::write(uint8_t c) -{ - return theGSM3ShieldV1ModemCore.write(c); -} - -//Detect if data to be read -int/*bool*/ GSM3ShieldV1DirectModemProvider::available() -{ - if (theGSM3ShieldV1ModemCore.gss.cb.peek(1)) return 1; - else return 0; -} - -//Read data -int/*char*/ GSM3ShieldV1DirectModemProvider::read() -{ - int dataRead; - dataRead = theGSM3ShieldV1ModemCore.gss.cb.read(); - //In case last char in xof mode. - if (!(theGSM3ShieldV1ModemCore.gss.cb.peek(0))) { - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - delay(100); - } - return dataRead; -} - -//Peek data -int/*char*/ GSM3ShieldV1DirectModemProvider::peek() -{ - return theGSM3ShieldV1ModemCore.gss.cb.peek(0); -} - -//Flush data -void GSM3ShieldV1DirectModemProvider::flush() -{ - return theGSM3ShieldV1ModemCore.gss.cb.flush(); -} - -String GSM3ShieldV1DirectModemProvider::writeModemCommand(String ATcommand, int responseDelay) -{ - if(trace) - Serial.println(ATcommand); - - // Flush other texts - flush(); - - //Enter debug mode. - connect(); - //Send the AT command. - println(ATcommand); - - delay(responseDelay); - - //Get response data from modem. - String result = ""; - if(trace) - theGSM3ShieldV1ModemCore.gss.cb.debugBuffer(); - - while (available()) - { - char c = read(); - result += c; - } - if(trace) - Serial.println(result); - //Leave the debug mode. - disconnect(); - return result; -} diff --git a/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.h b/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.h deleted file mode 100644 index 2d20412b47..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1DirectModemProvider.h +++ /dev/null @@ -1,118 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#ifndef __GSM3DIRECTMODEMPROVIDER__ -#define __GSM3DIRECTMODEMPROVIDER__ - -#include -#include -#include -#include -#include - -class GSM3ShieldV1DirectModemProvider : public GSM3ShieldV1BaseProvider, public Stream -{ - private: - - bool trace; - - public: - - /** Constructor - @param trace if true, dumps all AT dialogue to Serial - */ - GSM3ShieldV1DirectModemProvider(bool trace=false); - - /** - */ - void begin(); - - /** - */ - void restartModem(); - - /** Enable the debug process. - */ - void connect(); - - /** Disable the debug process. - */ - void disconnect(); - - /** Debug write to modem by means of SoftSerial. - @param c Character - @return size - */ - size_t write(uint8_t c); - - /** Check for incoming bytes in buffer - @return - */ - int available(); - - /** Read from circular buffer - @return character - */ - int read(); - - /** Read from circular buffer, but do not delete it - @return character - */ - int peek(); - - /** Empty circular buffer - */ - void flush(); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to){}; - - /** Recognize unsolicited event - @param from - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte from){return false;}; - - /** Send AT command to modem - @param command AT command - @param delay Time to wait for response - @return response from modem - */ - String writeModemCommand(String command, int delay); -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1ModemCore.cpp b/libraries/GSM/src/GSM3ShieldV1ModemCore.cpp deleted file mode 100644 index a9f5af6479..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ModemCore.cpp +++ /dev/null @@ -1,231 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -GSM3ShieldV1ModemCore theGSM3ShieldV1ModemCore; - -char* __ok__="OK"; - -GSM3ShieldV1ModemCore::GSM3ShieldV1ModemCore() : gss() -{ - gss.registerMgr(this); - _dataInBufferFrom=0; - _dataInBufferTo=0; - commandError=1; - commandCounter=0; - ongoingCommand=NONE; - takeMilliseconds(); - - for(int i=0;irecognizeUnsolicitedEvent(from); - } - } - if((!recognized)&&(activeProvider)) - activeProvider->manageResponse(from, to); -} - - -void GSM3ShieldV1ModemCore::openCommand(GSM3ShieldV1BaseProvider* provider, GSM3_commandType_e c) -{ - activeProvider=provider; - commandError=0; - commandCounter=1; - ongoingCommand=c; - _dataInBufferFrom=0; - _dataInBufferTo=0; - -}; - -size_t GSM3ShieldV1ModemCore::writePGM(PGM_P str, bool CR) -{ - int i=0; - char c; - - do - { - c=pgm_read_byte_near(str + i); - if(c!=0) - write(c); - i++; - } while (c!=0); - if(CR) - print("\r"); - - return 1; -} - -size_t GSM3ShieldV1ModemCore::write(uint8_t c) -{ - if(_debug) - GSM3CircularBuffer::printCharDebug(c); - return gss.write(c); -} - -unsigned long GSM3ShieldV1ModemCore::takeMilliseconds() -{ - unsigned long now=millis(); - unsigned long delta; - delta=now-milliseconds; - milliseconds=now; - return delta; -} - -void GSM3ShieldV1ModemCore::delayInsideInterrupt(unsigned long milliseconds) -{ - for (unsigned long k=0;k -#include -#include -#include - -#define UMPROVIDERS 3 - -class GSM3ShieldV1ModemCore : public GSM3SoftSerialMgr, public Print -{ - private: - - // Phone number, used when calling, sending SMS and reading calling numbers - // Also PIN in modem configuration - // Also APN - // Also remote server - char* phoneNumber; - - // Working port. Port used in the ongoing command, while opening a server - // Also for IP address length - int port; - - // 0 = ongoing - // 1 = OK - // 2 = Error. Incorrect state - // 3 = Unexpected modem message - // 4 = OK but not available data. - uint8_t commandError; - - // Counts the steps by the command - uint8_t commandCounter; - - // Presently ongoing command - GSM3_commandType_e ongoingCommand; - - // Enable/disable debug - bool _debug; - byte _dataInBufferFrom; - byte _dataInBufferTo; - - // This is the modem (known) status - GSM3_NetworkStatus_t _status; - - GSM3ShieldV1BaseProvider* UMProvider[UMPROVIDERS]; - GSM3ShieldV1BaseProvider* activeProvider; - - // Private function for anage message - void manageMsgNow(byte from, byte to); - - unsigned long milliseconds; - - public: - - /** Constructor */ - GSM3ShieldV1ModemCore(); - - GSM3SoftSerial gss; // Direct access to modem - - /** Get phone number - @return phone number - */ - char *getPhoneNumber(){return phoneNumber;}; - - /** Establish a new phone number - @param n Phone number - */ - void setPhoneNumber(char *n){phoneNumber=n;}; - - /** Get port used - @return port - */ - int getPort(){return port;}; - - /** Establish a new port for use - @param p Port - */ - void setPort(int p){port=p;}; - - /** Get command error - @return command error - */ - uint8_t getCommandError(){return commandError;}; - - /** Establish a command error - @param n Command error - */ - void setCommandError(uint8_t n){commandError=n;}; - - /** Get command counter - @return command counter - */ - uint8_t getCommandCounter(){return commandCounter;}; - - /** Set command counter - @param c Initial value - */ - void setCommandCounter(uint8_t c){commandCounter=c;}; - - /** Get ongoing command - @return command - */ - GSM3_commandType_e getOngoingCommand(){return ongoingCommand;}; - - /** Set ongoing command - @param c New ongoing command - */ - void setOngoingCommand(GSM3_commandType_e c){ongoingCommand=c;}; - - /** Open command - @param activeProvider Active provider - @param c Command for open - */ - void openCommand(GSM3ShieldV1BaseProvider* activeProvider, GSM3_commandType_e c); - - /** Close command - @param code Close code - */ - void closeCommand(int code); - - // These functions allow writing to the SoftwareSerial - // If debug is set, dump to the console - - /** Write a character in serial - @param c Character - @return size - */ - size_t write(uint8_t c); - - /** Write PGM - @param str Buffer for write - @param CR Carriadge return adding automatically - @return size - */ - virtual size_t writePGM(PGM_P str, bool CR=true); - - /** Establish debug mode - @param db Boolean that indicates debug on or off - */ - void setDebug(bool db){_debug=db;}; - - /** Generic response parser - @param rsp Returns true if expected response exists - @param string Substring expected in response - @param string2 Second substring expected in response - @return true if parsed correctly - */ - bool genericParse_rsp(bool& rsp, char* string=0, char* string2=0); - - /** Generates a generic AT command request from PROGMEM buffer - @param str Buffer with AT command - @param addCR Carriadge return adding automatically - */ - void genericCommand_rq(PGM_P str, bool addCR=true); - - /** Generates a generic AT command request from a simple char buffer - @param str Buffer with AT command - @param addCR Carriadge return adding automatically - */ - void genericCommand_rqc(const char* str, bool addCR=true); - - /** Returns the circular buffer - @return circular buffer - */ - inline GSM3CircularBuffer& theBuffer(){return gss.cb;}; - - /** Establish a new network status - @param status Network status - */ - inline void setStatus(GSM3_NetworkStatus_t status) { _status = status; }; - - /** Returns actual network status - @return network status - */ - inline GSM3_NetworkStatus_t getStatus() { return _status; }; - - /** Register provider as willing to receive unsolicited messages - @param provider Pointer to provider able to receive unsolicited messages - */ - void registerUMProvider(GSM3ShieldV1BaseProvider* provider); - - /** unegister provider as willing to receive unsolicited messages - @param provider Pointer to provider able to receive unsolicited messages - */ - void unRegisterUMProvider(GSM3ShieldV1BaseProvider* provider); - - - /** Register a provider as "dialoguing" talking in facto with the modem - @param provider Pointer to provider receiving responses - */ - void registerActiveProvider(GSM3ShieldV1BaseProvider* provider){activeProvider=provider;}; - - /** Needed to manage the SoftSerial. Receives the call when received data - If _debugging, no code is called - @param from Starting byte to read - @param to Last byte to read - */ - void manageMsg(byte from, byte to); - - /** If _debugging, this call is assumed to be made out of interrupts - Prints incoming info and calls manageMsgNow - */ - void manageReceivedData(); - - /** Chronometer. Measure milliseconds from last call - @return milliseconds from las time function was called - */ - unsigned long takeMilliseconds(); - - /** Delay for interrupts - @param milliseconds Delay time in milliseconds - */ - void delayInsideInterrupt(unsigned long milliseconds); -}; - -extern GSM3ShieldV1ModemCore theGSM3ShieldV1ModemCore; - -#endif diff --git a/libraries/GSM/src/GSM3ShieldV1ModemVerification.cpp b/libraries/GSM/src/GSM3ShieldV1ModemVerification.cpp deleted file mode 100644 index f6afae86ad..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ModemVerification.cpp +++ /dev/null @@ -1,73 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#include - -// constructor -GSM3ShieldV1ModemVerification::GSM3ShieldV1ModemVerification() -{ -}; - -// reset the modem for direct access -int GSM3ShieldV1ModemVerification::begin() -{ - int result=0; - String modemResponse; - - // check modem response - modemAccess.begin(); - - // reset hardware - modemAccess.restartModem(); - - modemResponse=modemAccess.writeModemCommand("AT", 1000); - if(modemResponse.indexOf("OK")>=0) - result=1; - modemResponse=modemAccess.writeModemCommand("ATE0", 1000); - return result; -} - -// get IMEI -String GSM3ShieldV1ModemVerification::getIMEI() -{ - String number(""); - // AT command for obtain IMEI - String modemResponse = modemAccess.writeModemCommand("AT+GSN", 2000); - // Parse and check response - char res_to_compare[modemResponse.length()]; - modemResponse.toCharArray(res_to_compare, modemResponse.length()); - if(strstr(res_to_compare,"OK") != NULL) - number = modemResponse.substring(1, 17); - return number; -} diff --git a/libraries/GSM/src/GSM3ShieldV1ModemVerification.h b/libraries/GSM/src/GSM3ShieldV1ModemVerification.h deleted file mode 100644 index 98dbc49888..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ModemVerification.h +++ /dev/null @@ -1,64 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SHIELDV1MODEMVERIFICATION_ -#define _GSM3SHIELDV1MODEMVERIFICATION_ - -#include -#include - -class GSM3ShieldV1ModemVerification -{ - - private: - - GSM3ShieldV1DirectModemProvider modemAccess; - GSM3ShieldV1AccessProvider gsm; // Access provider to GSM/GPRS network - - public: - - /** Constructor */ - GSM3ShieldV1ModemVerification(); - - /** Check modem response and restart it - */ - int begin(); - - /** Obtain modem IMEI (command AT) - @return modem IMEI number - */ - String getIMEI(); - -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1MultiClientProvider.cpp b/libraries/GSM/src/GSM3ShieldV1MultiClientProvider.cpp deleted file mode 100644 index c75ee300f6..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1MultiClientProvider.cpp +++ /dev/null @@ -1,619 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -const char _command_MultiQISRVC[] PROGMEM = "AT+QISRVC="; - -#define __TOUTFLUSH__ 10000 - -GSM3ShieldV1MultiClientProvider::GSM3ShieldV1MultiClientProvider() -{ - theGSM3MobileClientProvider=this; - theGSM3ShieldV1ModemCore.registerUMProvider(this); -}; - -//Response management. -void GSM3ShieldV1MultiClientProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case XON: - if (flagReadingSocket) - { -// flagReadingSocket = 0; - fullBufferSocket = (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()<3); - } - else theGSM3ShieldV1ModemCore.setOngoingCommand(NONE); - break; - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case CONNECTTCPCLIENT: - connectTCPClientContinue(); - break; - case DISCONNECTTCP: - disconnectTCPContinue(); - break; - case BEGINWRITESOCKET: - beginWriteSocketContinue(); - break; - case ENDWRITESOCKET: - endWriteSocketContinue(); - break; - case AVAILABLESOCKET: - availableSocketContinue(); - break; - case FLUSHSOCKET: - fullBufferSocket = (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()<3); - flushSocketContinue(); - break; - - default: - break; - } -} - -//Connect TCP main function. -int GSM3ShieldV1MultiClientProvider::connectTCPClient(const char* server, int port, int id_socket) -{ - theGSM3ShieldV1ModemCore.setPort(port); - idSocket = id_socket; - - theGSM3ShieldV1ModemCore.setPhoneNumber((char*)server); - theGSM3ShieldV1ModemCore.openCommand(this,CONNECTTCPCLIENT); - connectTCPClientContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -int GSM3ShieldV1MultiClientProvider::connectTCPClient(IPAddress add, int port, int id_socket) -{ - remoteIP=add; - theGSM3ShieldV1ModemCore.setPhoneNumber(0); - return connectTCPClient(0, port, id_socket); -} - -//Connect TCP continue function. -void GSM3ShieldV1MultiClientProvider::connectTCPClientContinue() -{ - bool resp; - // 0: Dot or DNS notation activation - // 1: Disable SW flow control - // 2: Waiting for IFC OK - // 3: Start-up TCP connection "AT+QIOPEN" - // 4: Wait for connection OK - // 5: Wait for CONNECT - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIDNSIP="), false); - if ((theGSM3ShieldV1ModemCore.getPhoneNumber()!=0)&& - ((*(theGSM3ShieldV1ModemCore.getPhoneNumber())<'0')||((*(theGSM3ShieldV1ModemCore.getPhoneNumber())>'9')))) - { - theGSM3ShieldV1ModemCore.print('1'); - theGSM3ShieldV1ModemCore.print('\r'); - } - else - { - theGSM3ShieldV1ModemCore.print('0'); - theGSM3ShieldV1ModemCore.print('\r'); - } - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - //Response received - if(resp) - { - // AT+QIOPEN - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIOPEN="),false); - theGSM3ShieldV1ModemCore.print(idSocket); - theGSM3ShieldV1ModemCore.print(",\"TCP\",\""); - if(theGSM3ShieldV1ModemCore.getPhoneNumber()!=0) - { - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPhoneNumber()); - } - else - { - remoteIP.printTo(theGSM3ShieldV1ModemCore); - } - theGSM3ShieldV1ModemCore.print('"'); - theGSM3ShieldV1ModemCore.print(','); - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPort()); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - if(resp) - { - // OK Received - // Great. Go for the next step - theGSM3ShieldV1ModemCore.setCommandCounter(4); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 4: - char auxLocate [12]; - prepareAuxLocate(PSTR("CONNECT OK"), auxLocate); - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp,auxLocate)) - { - // Response received - if(resp) - { - // Received CONNECT OK - // Great. We're done - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - - } -} - -//Disconnect TCP main function. -int GSM3ShieldV1MultiClientProvider::disconnectTCP(bool client1Server0, int id_socket) -{ - idSocket = id_socket; - - // First of all, we will flush the socket synchronously - unsigned long m; - m=millis(); - flushSocket(); - while(((millis()-m)< __TOUTFLUSH__ )&&(ready()==0)) - delay(10); - - // Could not flush the communications... strange - if(ready()==0) - { - theGSM3ShieldV1ModemCore.setCommandError(2); - return theGSM3ShieldV1ModemCore.getCommandError(); - } - - // Set up the command - client1_server0 = client1Server0; - flagReadingSocket=0; - theGSM3ShieldV1ModemCore.openCommand(this,DISCONNECTTCP); - disconnectTCPContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Disconnect TCP continue function -void GSM3ShieldV1MultiClientProvider::disconnectTCPContinue() -{ - bool resp; - // 1: Send AT+QISRVC - // 2: "AT+QICLOSE" - // 3: Wait for OK - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_MultiQISRVC, false); - if (client1_server0) theGSM3ShieldV1ModemCore.print('1'); - else theGSM3ShieldV1ModemCore.print('2'); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - // Parse response to QISRVC - theGSM3ShieldV1ModemCore.genericParse_rsp(resp); - if(resp) - { - // Send QICLOSE command - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QICLOSE="),false); - theGSM3ShieldV1ModemCore.print(idSocket); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else - theGSM3ShieldV1ModemCore.closeCommand(3); - break; - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - theGSM3ShieldV1ModemCore.setCommandCounter(0); - if (resp) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Write socket first chain main function. -void GSM3ShieldV1MultiClientProvider::beginWriteSocket(bool client1Server0, int id_socket) -{ - idSocket = id_socket; - client1_server0 = client1Server0; - theGSM3ShieldV1ModemCore.openCommand(this,BEGINWRITESOCKET); - beginWriteSocketContinue(); -} - -//Write socket first chain continue function. -void GSM3ShieldV1MultiClientProvider::beginWriteSocketContinue() -{ - bool resp; - // 1: Send AT+QISRVC - // 2: Send AT+QISEND - // 3: wait for > and Write text - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - // AT+QISRVC - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_MultiQISRVC, false); - if (client1_server0) - theGSM3ShieldV1ModemCore.print('1'); - else - theGSM3ShieldV1ModemCore.print('2'); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - if(resp) - { - // AT+QISEND - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QISEND="), false); - theGSM3ShieldV1ModemCore.print(idSocket); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else - { - theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - break; - case 3: - char aux[2]; - aux[0]='>'; - aux[1]=0; - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, aux)) - { - if(resp) - { - // Received ">" - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else - { - theGSM3ShieldV1ModemCore.closeCommand(3); - } - } - break; - } -} - -//Write socket next chain function. -void GSM3ShieldV1MultiClientProvider::writeSocket(const char* buf) -{ - theGSM3ShieldV1ModemCore.print(buf); -} - -//Write socket character function. -void GSM3ShieldV1MultiClientProvider::writeSocket(char c) -{ - theGSM3ShieldV1ModemCore.print(c); -} - -//Write socket last chain main function. -void GSM3ShieldV1MultiClientProvider::endWriteSocket() -{ - theGSM3ShieldV1ModemCore.openCommand(this,ENDWRITESOCKET); - endWriteSocketContinue(); -} - -//Write socket last chain continue function. -void GSM3ShieldV1MultiClientProvider::endWriteSocketContinue() -{ - bool resp; - // 1: Write text (ctrl-Z) - // 2: Wait for OK - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.write(26); // Ctrl-Z - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // OK received - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Available socket main function. -int GSM3ShieldV1MultiClientProvider::availableSocket(bool client1Server0, int id_socket) -{ - if(flagReadingSocket==1) - { - theGSM3ShieldV1ModemCore.setCommandError(1); - return 1; - } - client1_server0 = client1Server0; - idSocket = id_socket; - theGSM3ShieldV1ModemCore.openCommand(this,AVAILABLESOCKET); - availableSocketContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Available socket continue function. -void GSM3ShieldV1MultiClientProvider::availableSocketContinue() -{ - bool resp; - // 1: AT+QIRD - // 2: Wait for OK and Next necessary AT+QIRD - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QIRD=0,"),false); - if (client1_server0) - theGSM3ShieldV1ModemCore.print('1'); - else - theGSM3ShieldV1ModemCore.print('2'); - theGSM3ShieldV1ModemCore.print(','); - theGSM3ShieldV1ModemCore.print(idSocket); - theGSM3ShieldV1ModemCore.print(",1500"); - // theGSM3ShieldV1ModemCore.print(",120"); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseQIRD_head(resp)) - { - if (!resp) - { - theGSM3ShieldV1ModemCore.closeCommand(4); - } - else - { - flagReadingSocket=1; - theGSM3ShieldV1ModemCore.closeCommand(1); - } - } - else - { - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Read Socket Parse head. -bool GSM3ShieldV1MultiClientProvider::parseQIRD_head(bool& rsp) -{ - char _qird [8]; - prepareAuxLocate(PSTR("+QIRD:"), _qird); - fullBufferSocket = (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()<3); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(_qird)) - { - theGSM3ShieldV1ModemCore.theBuffer().chopUntil(_qird, true); - // Saving more memory, reuse _qird - _qird[0]='\n'; - _qird[1]=0; - theGSM3ShieldV1ModemCore.theBuffer().chopUntil(_qird, true); - rsp = true; - return true; - } - else if(theGSM3ShieldV1ModemCore.theBuffer().locate("OK")) - { - rsp = false; - return true; - } - else - { - rsp = false; - return false; - } -} -/* -//Read socket main function. -int GSM3ShieldV1MultiClientProvider::readSocket() -{ - char charSocket; - charSocket = theGSM3ShieldV1ModemCore.theBuffer().read(); - //Case buffer not full - if (!fullBufferSocket) - { - //The last part of the buffer after data is CRLFOKCRLF - if (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==125) - { - //Start again availableSocket function. - flagReadingSocket=0; - theGSM3ShieldV1ModemCore.openCommand(this,AVAILABLESOCKET); - availableSocketContinue(); - } - } - else if (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==127) - { - // The buffer is full, no more action is possible until we have read() - theGSM3ShieldV1ModemCore.theBuffer().flush(); - flagReadingSocket = 1; - theGSM3ShieldV1ModemCore.openCommand(this,XON); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - //A small delay to assure data received after xon. - delay(10); - } - //To distinguish the case no more available data in socket. - if (ready()==1) - return charSocket; - else - return 0; -} -*/ -int GSM3ShieldV1MultiClientProvider::readSocket() -{ - char charSocket; - - if(theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==0) - { - Serial.println();Serial.println("*"); - return 0; - } - - charSocket = theGSM3ShieldV1ModemCore.theBuffer().read(); - //Case buffer not full - if (!fullBufferSocket) - { - //The last part of the buffer after data is CRLFOKCRLF - if (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==125) - { - //Start again availableSocket function. - flagReadingSocket=0; - theGSM3ShieldV1ModemCore.openCommand(this,AVAILABLESOCKET); - availableSocketContinue(); - } - } - else if (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()>=100) - { - // The buffer was full, we have to let the data flow again - // theGSM3ShieldV1ModemCore.theBuffer().flush(); - flagReadingSocket = 1; - theGSM3ShieldV1ModemCore.openCommand(this,XON); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - //A small delay to assure data received after xon. - delay(100); - if(theGSM3ShieldV1ModemCore.theBuffer().availableBytes() >=6) - fullBufferSocket=false; - } - - return charSocket; - -} - -//Read socket main function. -int GSM3ShieldV1MultiClientProvider::peekSocket() -{ - return theGSM3ShieldV1ModemCore.theBuffer().peek(0); -} - - -//Flush SMS main function. -void GSM3ShieldV1MultiClientProvider::flushSocket() -{ - flagReadingSocket=0; - theGSM3ShieldV1ModemCore.openCommand(this,FLUSHSOCKET); - flushSocketContinue(); -} - -//Send SMS continue function. -void GSM3ShieldV1MultiClientProvider::flushSocketContinue() -{ - //bool resp; - // 1: Deleting SMS - // 2: wait for OK - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //DEBUG - //Serial.println("Flushing Socket."); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - if (fullBufferSocket) - { - //Serial.println("Buffer flushed."); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - } - else - { - //Serial.println("Socket flushed completely."); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - break; - } -} - -//URC recognize. -// Momentarily, we will not recognize "closes" in client mode -bool GSM3ShieldV1MultiClientProvider::recognizeUnsolicitedEvent(byte oldTail) -{ - return false; -} - -int GSM3ShieldV1MultiClientProvider::getSocket(int socket) -{ - if(socket==-1) - { - int i; - for(i=minSocket(); i<=maxSocket(); i++) - { - if (!(sockets&(0x0001<8) - return 0; - if(sockets&(0x0001< -#include - -class GSM3ShieldV1MultiClientProvider : public GSM3MobileClientProvider, public GSM3ShieldV1BaseProvider -{ - private: - - int remotePort; // Current operation remote port - int idSocket; // Remote ID socket - IPAddress remoteIP; // Remote IP address - - uint16_t sockets; - - /** Continue to connect TCP client function - */ - void connectTCPClientContinue(); - - /** Continue to disconnect TCP client function - */ - void disconnectTCPContinue(); - - /** Continue to begin socket for write function - */ - void beginWriteSocketContinue(); - - /** Continue to end write socket function - */ - void endWriteSocketContinue(); - - /** Continue to available socket function - */ - void availableSocketContinue(); - - /** Continue to flush socket function - */ - void flushSocketContinue(); - - // GATHER! - bool flagReadingSocket; //In case socket data being read, update fullBufferSocket in the next buffer. - bool fullBufferSocket; //To detect if the socket data being read needs another buffer. - bool client1_server0; //1 Client, 0 Server. - - /** Parse QIRD response - @param rsp Returns true if expected response exists - @return true if command executed correctly - */ - bool parseQIRD_head(bool& rsp); - - public: - - /** Constructor */ - GSM3ShieldV1MultiClientProvider(); - - /** Minimum socket - @return 0 - */ - int minSocket(){return 0;}; - - /** Maximum socket - @return 5 - */ - int maxSocket(){return 5;}; - - /** Connect to a remote TCP server - @param server String with IP or server name - @param port Remote port number - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int connectTCPClient(const char* server, int port, int id_socket); - - /** Connect to a remote TCP server - @param add Remote IP address - @param port Remote port number - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int connectTCPClient(IPAddress add, int port, int id_socket); - - /** Begin writing through a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - void beginWriteSocket(bool client1Server0, int id_socket); - - /** Write through a socket. MUST go after beginWriteSocket() - @param buf characters to be written (final 0 will not be written) - */ - void writeSocket(const char* buf); - - /** Write through a socket. MUST go after beginWriteSocket() - @param c character to be written - */ - void writeSocket(char c); - - /** Finish current writing - */ - void endWriteSocket(); - - /** Check if there are data to be read in socket. - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if there are data available, 4 if no data, otherwise error - */ - int availableSocket(bool client, int id_socket); // With "available" and "readSocket" ask the modem for 1500 bytes. - - /** Read a character from socket - @return socket - */ - int readSocket(); //If Read() gets to the end of the QIRD response, execute again QIRD SYNCHRONOUSLY - - /** Flush socket - */ - void flushSocket(); - - /** Get a character but will not advance the buffer head - @return character - */ - int peekSocket(); - - /** Close a socket - @param client1Server0 1 if modem acts as client, 0 if acts as server - @param id_socket Local socket number - @return 0 if command running, 1 if success, otherwise error - */ - int disconnectTCP(bool client1Server0, int id_socket); - - /** Recognize unsolicited event - @param from - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte from); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Get client socket - @param socket - @return socket - */ - int getSocket(int socket=-1); - - /** Release socket - @param socket Socket for release - */ - void releaseSocket(int socket); - - /** Get socket client status - @param socket Socket - @return socket client status - */ - bool getStatusSocketClient(uint8_t socket); - -}; - - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1MultiServerProvider.cpp b/libraries/GSM/src/GSM3ShieldV1MultiServerProvider.cpp deleted file mode 100644 index c43568ba48..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1MultiServerProvider.cpp +++ /dev/null @@ -1,393 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -#define __NCLIENTS_MAX__ 3 - -const char _command_QILOCIP[] PROGMEM = "AT+QILOCIP"; - -GSM3ShieldV1MultiServerProvider::GSM3ShieldV1MultiServerProvider() -{ - theGSM3MobileServerProvider=this; - socketsAsServer=0; - socketsAccepted=0; - theGSM3ShieldV1ModemCore.registerUMProvider(this); -}; - -//Response management. -void GSM3ShieldV1MultiServerProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case CONNECTSERVER: - connectTCPServerContinue(); - break; - case GETIP: - getIPContinue(); - break; - - default: - break; - } -} - -//Connect Server main function. -int GSM3ShieldV1MultiServerProvider::connectTCPServer(int port) -{ - // We forget about LocalIP as it has no real use, the modem does whatever it likes - theGSM3ShieldV1ModemCore.setPort(port); - theGSM3ShieldV1ModemCore.openCommand(this,CONNECTSERVER); - connectTCPServerContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Connect Server continue function. -void GSM3ShieldV1MultiServerProvider::connectTCPServerContinue() -{ - - bool resp; - // 1: Read Local IP "AT+QILOCIP" - // 2: Waiting for IP and Set local port "AT+QILPORT" - // 3: Waiting for QILPOR OK andConfigure as server "AT+QISERVER" - // 4: Wait for SERVER OK - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //"AT+QILOCIP." - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_QILOCIP); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - //Not IP storing but the command is necessary. - //if(parseQILOCIP_rsp(local_IP, local_IP_Length, resp)) - // This awful trick saves some RAM bytes - char aux[3]; - aux[0]='\r';aux[1]='\n';aux[2]=0; - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, aux)) - { - //Response received - if(resp) - { - // Great. Go for the next step - // AT+QILPORT - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QILPORT=\"TCP\","),false); - theGSM3ShieldV1ModemCore.print( theGSM3ShieldV1ModemCore.getPort()); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - if(resp) - { - // OK received - // Great. Go for the next step - // AT+QISERVER - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QISERVER=0,"),false); - theGSM3ShieldV1ModemCore.print(__NCLIENTS_MAX__); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(4); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 4: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - // OK received, kathapoon, chessespoon - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//QILOCIP parse. -bool GSM3ShieldV1MultiServerProvider::parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp) -{ - if (!(theGSM3ShieldV1ModemCore.theBuffer().extractSubstring("\r\n","\r\n", LocalIP, LocalIPlength))) - rsp = false; - else - rsp = true; - return true; -} - -//Get IP main function. -int GSM3ShieldV1MultiServerProvider::getIP(char* LocalIP, int LocalIPlength) -{ - theGSM3ShieldV1ModemCore.setPhoneNumber(LocalIP); - theGSM3ShieldV1ModemCore.setPort(LocalIPlength); - theGSM3ShieldV1ModemCore.openCommand(this,GETIP); - getIPContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -void GSM3ShieldV1MultiServerProvider::getIPContinue() -{ - - bool resp; - // 1: Read Local IP "AT+QILOCIP" - // 2: Waiting for IP. - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //AT+QILOCIP - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_QILOCIP); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseQILOCIP_rsp(theGSM3ShieldV1ModemCore.getPhoneNumber(), theGSM3ShieldV1ModemCore.getPort(), resp)) - { - if (resp) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -bool GSM3ShieldV1MultiServerProvider::getSocketAsServerModemStatus(int s) -{ - if (socketsAccepted&(0x0001< -#include - -class GSM3ShieldV1MultiServerProvider : public GSM3MobileServerProvider, public GSM3ShieldV1BaseProvider -{ - private: - - // Used sockets - uint8_t socketsAsServer; - uint8_t socketsAccepted; - - /** Continue to connect TCP server function - */ - void connectTCPServerContinue(); - - /** Continue to get IP function - */ - void getIPContinue(); - - /** Release socket - @param socket Socket - */ - void releaseSocket(int socket); - - /** Parse QILOCIP response - @param LocalIP Buffer for save local IP address - @param LocalIPlength Buffer size - @param rsp Returns if expected response exists - @return true if command executed correctly - */ - bool parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp); - - public: - - /** Constructor */ - GSM3ShieldV1MultiServerProvider(); - - /** minSocketAsServer - @return 0 - */ - int minSocketAsServer(){return 0;}; - - /** maxSocketAsServer - @return 0 - */ - int maxSocketAsServer(){return 4;}; - - /** Get modem status - @param s - @return modem status (true if connected) - */ - bool getSocketAsServerModemStatus(int s); - - /** Get new occupied socket as server - @return command error if exists - */ - int getNewOccupiedSocketAsServer(); - - /** Connect server to TCP port - @param port TCP port - @return command error if exists - */ - int connectTCPServer(int port); - - /** Get server IP address - @param LocalIP Buffer for copy IP address - @param LocalIPlength Length of buffer - @return command error if exists - */ - int getIP(char* LocalIP, int LocalIPlength); - -// int disconnectTCP(bool client1Server0, int id_socket); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Get socket status as server - @param socket Socket to get status - @return socket status - */ - bool getStatusSocketAsServer(uint8_t socket); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** Recognize unsolicited event - @param oldTail - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte oldTail); - - -}; - -#endif diff --git a/libraries/GSM/src/GSM3ShieldV1PinManagement.cpp b/libraries/GSM/src/GSM3ShieldV1PinManagement.cpp deleted file mode 100644 index 5a5504816d..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1PinManagement.cpp +++ /dev/null @@ -1,203 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#include - -// constructor -GSM3ShieldV1PinManagement::GSM3ShieldV1PinManagement() -{ -}; - -// reset the modem for direct access -void GSM3ShieldV1PinManagement::begin() -{ - modemAccess.begin(); - - // reset hardware - gsm.HWrestart(); - - pin_used = false; - - // check modem response - modemAccess.writeModemCommand("AT", 1000); - modemAccess.writeModemCommand("ATE0", 1000); -} - -/* - Check PIN status -*/ -int GSM3ShieldV1PinManagement::isPIN() -{ - String res = modemAccess.writeModemCommand("AT+CPIN?",1000); - // Check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "READY") != NULL) - return 0; - else if(strstr(res_to_compare, "SIM PIN") != NULL) - return 1; - else if(strstr(res_to_compare, "SIM PUK") != NULL) - return -1; - else - return -2; -} - -/* - Check PIN code -*/ -int GSM3ShieldV1PinManagement::checkPIN(String pin) -{ - String res = modemAccess.writeModemCommand("AT+CPIN=" + pin,1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "OK") == NULL) - return -1; - else - return 0; -} - -/* - Check PUK code -*/ -int GSM3ShieldV1PinManagement::checkPUK(String puk, String pin) -{ - String res = modemAccess.writeModemCommand("AT+CPIN=\"" + puk + "\",\"" + pin + "\"",1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "OK") == NULL) - return -1; - else - return 0; -} - -/* - Change PIN code -*/ -void GSM3ShieldV1PinManagement::changePIN(String old, String pin) -{ - String res = modemAccess.writeModemCommand("AT+CPWD=\"SC\",\"" + old + "\",\"" + pin + "\"",2000); - Serial.println(res); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "OK") != NULL) - Serial.println("Pin changed succesfully."); - else - Serial.println("ERROR"); -} - -/* - Switch PIN status -*/ -void GSM3ShieldV1PinManagement::switchPIN(String pin) -{ - String res = modemAccess.writeModemCommand("AT+CLCK=\"SC\",2",1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "0") != NULL) - { - res = modemAccess.writeModemCommand("AT+CLCK=\"SC\",1,\"" + pin + "\"",1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "OK") == NULL) - { - Serial.println("ERROR"); - pin_used = false; - } - else - { - Serial.println("OK. PIN lock on."); - pin_used = true; - } - } - else if(strstr(res_to_compare, "1") != NULL) - { - res = modemAccess.writeModemCommand("AT+CLCK=\"SC\",0,\"" + pin + "\"",1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "OK") == NULL) - { - Serial.println("ERROR"); - pin_used = true; - } - else - { - Serial.println("OK. PIN lock off."); - pin_used = false; - } - } - else - { - Serial.println("ERROR"); - } -} - -/* - Check registrer -*/ -int GSM3ShieldV1PinManagement::checkReg() -{ - delay(5000); - String res = modemAccess.writeModemCommand("AT+CREG?",1000); - // check response - char res_to_compare[res.length()]; - res.toCharArray(res_to_compare, res.length()); - if(strstr(res_to_compare, "1") != NULL) - return 0; - else if(strstr(res_to_compare, "5") != NULL) - return 1; - else - return -1; -} - -/* - Return if PIN lock is used -*/ -bool GSM3ShieldV1PinManagement::getPINUsed() -{ - return pin_used; -} - -/* - Set if PIN lock is used -*/ -void GSM3ShieldV1PinManagement::setPINUsed(bool used) -{ - pin_used = used; -} diff --git a/libraries/GSM/src/GSM3ShieldV1PinManagement.h b/libraries/GSM/src/GSM3ShieldV1PinManagement.h deleted file mode 100644 index d5924ea1fe..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1PinManagement.h +++ /dev/null @@ -1,103 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3SHIELDV1PINMANAGEMENT_ -#define _GSM3SHIELDV1PINMANAGEMENT_ - -#include -#include - -class GSM3ShieldV1PinManagement -{ - - private: - - GSM3ShieldV1AccessProvider gsm; // GSM access required for network register with PIN code - GSM3ShieldV1DirectModemProvider modemAccess; - bool pin_used; // determines if pin lock is activated - - public: - - /** Constructor */ - GSM3ShieldV1PinManagement(); - - /** Check modem response and restart it - */ - void begin(); - - /** Check if PIN lock or PUK lock is activated - @return 0 if PIN lock is off, 1 if PIN lock is on, -1 if PUK lock is on, -2 if error exists - */ - int isPIN(); - - /** Check if PIN code is correct and valid - @param pin PIN code - @return 0 if is correct, -1 if is incorrect - */ - int checkPIN(String pin); - - /** Check if PUK code is correct and establish new PIN code - @param puk PUK code - @param pin New PIN code - @return 0 if successful, otherwise return -1 - */ - int checkPUK(String puk, String pin); - - /** Change PIN code - @param old Old PIN code - @param pin New PIN code - */ - void changePIN(String old, String pin); - - /** Change PIN lock status - @param pin PIN code - */ - void switchPIN(String pin); - - /** Check if modem was registered in GSM/GPRS network - @return 0 if modem was registered, 1 if modem was registered in roaming, -1 if error exists - */ - int checkReg(); - - /** Return if PIN lock is used - @return true if PIN lock is used, otherwise, return false - */ - bool getPINUsed(); - - /** Set PIN lock status - @param used New PIN lock status - */ - void setPINUsed(bool used); -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1SMSProvider.cpp b/libraries/GSM/src/GSM3ShieldV1SMSProvider.cpp deleted file mode 100644 index ac7d3aac36..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1SMSProvider.cpp +++ /dev/null @@ -1,330 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -GSM3ShieldV1SMSProvider::GSM3ShieldV1SMSProvider() -{ - theGSM3SMSProvider=this; -}; - -//Send SMS begin function. -int GSM3ShieldV1SMSProvider::beginSMS(const char* to) -{ - if((theGSM3ShieldV1ModemCore.getStatus() != GSM_READY)&&(theGSM3ShieldV1ModemCore.getStatus() != GPRS_READY)) - return 2; - - theGSM3ShieldV1ModemCore.setPhoneNumber((char*)to); - theGSM3ShieldV1ModemCore.openCommand(this,BEGINSMS); - beginSMSContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Send SMS continue function. -void GSM3ShieldV1SMSProvider::beginSMSContinue() -{ - bool resp; - // 1: Send AT - // 2: wait for > and write text - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CMGS=\""), false); - theGSM3ShieldV1ModemCore.print(theGSM3ShieldV1ModemCore.getPhoneNumber()); - theGSM3ShieldV1ModemCore.print("\"\r"); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, ">")) - { - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Send SMS write function. -void GSM3ShieldV1SMSProvider::writeSMS(char c) -{ - theGSM3ShieldV1ModemCore.write(c); -} - -//Send SMS begin function. -int GSM3ShieldV1SMSProvider::endSMS() -{ - theGSM3ShieldV1ModemCore.openCommand(this,ENDSMS); - endSMSContinue(); - while(ready()==0) delay(100); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Send SMS continue function. -void GSM3ShieldV1SMSProvider::endSMSContinue() -{ - bool resp; - // 1: Send #26 - // 2: wait for OK - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.write(26); - theGSM3ShieldV1ModemCore.print("\r"); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if (resp) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Available SMS main function. -int GSM3ShieldV1SMSProvider::availableSMS() -{ - flagReadingSMS = 0; - theGSM3ShieldV1ModemCore.openCommand(this,AVAILABLESMS); - availableSMSContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Available SMS continue function. -void GSM3ShieldV1SMSProvider::availableSMSContinue() -{ - // 1: AT+CMGL="REC UNREAD",1 - // 2: Receive +CMGL: _id_ ... READ","_numero_" ... \n_mensaje_\nOK - // 3: Send AT+CMGD= _id_ - // 4: Receive OK - // 5: Remaining SMS text in case full buffer. - // This implementation really does not care much if the modem aswers trash to CMGL - bool resp; - //int msglength_aux; - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CMGL=\"REC UNREAD\",1")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseCMGL_available(resp)) - { - if (!resp) theGSM3ShieldV1ModemCore.closeCommand(4); - else theGSM3ShieldV1ModemCore.closeCommand(1); - } - break; - } - -} - -//SMS available parse. -bool GSM3ShieldV1SMSProvider::parseCMGL_available(bool& rsp) -{ - fullBufferSMS = (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()<=4); - if (!(theGSM3ShieldV1ModemCore.theBuffer().chopUntil("+CMGL:", true))) - rsp = false; - else - rsp = true; - idSMS=theGSM3ShieldV1ModemCore.theBuffer().readInt(); - - //If there are 2 SMS in buffer, response is ...CRLFCRLF+CMGL - twoSMSinBuffer = theGSM3ShieldV1ModemCore.theBuffer().locate("\r\n\r\n+"); - - checkSecondBuffer = 0; - - return true; -} - -//remoteNumber SMS function. -int GSM3ShieldV1SMSProvider::remoteSMSNumber(char* number, int nlength) -{ - theGSM3ShieldV1ModemCore.theBuffer().extractSubstring("READ\",\"", "\"", number, nlength); - - return 1; -} - -//remoteNumber SMS function. -int GSM3ShieldV1SMSProvider::readSMS() -{ - char charSMS; - //First char. - if (!flagReadingSMS) - { - flagReadingSMS = 1; - theGSM3ShieldV1ModemCore.theBuffer().chopUntil("\n", true); - } - charSMS = theGSM3ShieldV1ModemCore.theBuffer().read(); - - //Second Buffer. - if (checkSecondBuffer) - { - checkSecondBuffer = 0; - twoSMSinBuffer = theGSM3ShieldV1ModemCore.theBuffer().locate("\r\n\r\n+"); - } - - //Case the last char in buffer. - if ((!twoSMSinBuffer)&&fullBufferSMS&&(theGSM3ShieldV1ModemCore.theBuffer().availableBytes()==127)) - { - theGSM3ShieldV1ModemCore.theBuffer().flush(); - fullBufferSMS = 0; - checkSecondBuffer = 1; - theGSM3ShieldV1ModemCore.openCommand(this,XON); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - delay(10); - - return charSMS; - } - //Case two SMS in buffer - else if (twoSMSinBuffer) - { - if (theGSM3ShieldV1ModemCore.theBuffer().locate("\r\n\r\n+")) - { - return charSMS; - } - else - { - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.openCommand(this,XON); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - delay(10); - return 0; - } - } - //Case 1 SMS and buffer not full - else if (!fullBufferSMS) - { - if (theGSM3ShieldV1ModemCore.theBuffer().locate("\r\n\r\nOK")) - { - return charSMS; - } - else - { - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.openCommand(this,XON); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - delay(10); - return 0; - } - } - //Case to read all the chars in buffer to the end. - else - { - return charSMS; - } -} - -//Read socket main function. -int GSM3ShieldV1SMSProvider::peekSMS() -{ - if (!flagReadingSMS) - { - flagReadingSMS = 1; - theGSM3ShieldV1ModemCore.theBuffer().chopUntil("\n", true); - } - - return theGSM3ShieldV1ModemCore.theBuffer().peek(0); -} - -//Flush SMS main function. -void GSM3ShieldV1SMSProvider::flushSMS() -{ - - //With this, sms data can fill up to 2x128+5x128 bytes. - for (int aux = 0;aux<5;aux++) - { - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - delay(10); - } - - theGSM3ShieldV1ModemCore.openCommand(this,FLUSHSMS); - flushSMSContinue(); -} - -//Send SMS continue function. -void GSM3ShieldV1SMSProvider::flushSMSContinue() -{ - bool resp; - // 1: Deleting SMS - // 2: wait for OK - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.setCommandCounter(2); - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CMGD="), false); - theGSM3ShieldV1ModemCore.print(idSMS); - theGSM3ShieldV1ModemCore.print("\r"); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -void GSM3ShieldV1SMSProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { -/* case XON: - if (flagReadingSocket) - { -// flagReadingSocket = 0; - fullBufferSocket = (theGSM3ShieldV1ModemCore.theBuffer().availableBytes()<3); - } - else theGSM3ShieldV1ModemCore.openCommand(this,NONE); - break; -*/ case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case BEGINSMS: - beginSMSContinue(); - break; - case ENDSMS: - endSMSContinue(); - break; - case AVAILABLESMS: - availableSMSContinue(); - break; - case FLUSHSMS: - flushSMSContinue(); - break; - - default: - break; - } -} diff --git a/libraries/GSM/src/GSM3ShieldV1SMSProvider.h b/libraries/GSM/src/GSM3ShieldV1SMSProvider.h deleted file mode 100644 index 408da338e1..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1SMSProvider.h +++ /dev/null @@ -1,130 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SHIELDV1SMSPROVIDER__ -#define __GSM3_SHIELDV1SMSPROVIDER__ - -#include -#include -#include - - -class GSM3ShieldV1SMSProvider : public GSM3MobileSMSProvider, public GSM3ShieldV1BaseProvider -{ - public: - GSM3ShieldV1SMSProvider(); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** Begin a SMS to send it - @param to Destination - @return error command if it exists - */ - inline int beginSMS(const char* to); - - /** Write a SMS character by character - @param c Character - */ - inline void writeSMS(char c); - - /** End SMS - @return error command if it exists - */ - inline int endSMS(); - - /** Check if SMS available and prepare it to be read - @return number of bytes in a received SMS - */ - int availableSMS(); - - /** Read a byte but do not advance the buffer header (circular buffer) - @return character - */ - int peekSMS(); - - /** Delete the SMS from Modem memory and proccess answer - */ - void flushSMS(); - - /** Read sender number phone - @param number Buffer for save number phone - @param nlength Buffer length - @return 1 success, >1 error - */ - int remoteSMSNumber(char* number, int nlength); //Before reading the SMS, read the phone number. - - /** Read one char for SMS buffer (advance circular buffer) - @return character - */ - int readSMS(); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - private: - - int idSMS; // Id from current SMS being read. - bool flagReadingSMS; // To detect first SMS char if not yet reading. - bool fullBufferSMS; // To detect if the SMS being read needs another buffer. - bool twoSMSinBuffer; // To detect if the buffer has more than 1 SMS. - bool checkSecondBuffer; // Pending to detect if the second buffer has more than 1 SMS. - - /** Continue to begin SMS function - */ - void beginSMSContinue(); - - /** Continue to end SMS function - */ - void endSMSContinue(); - - /** Continue to available SMS function - */ - void availableSMSContinue(); - - /** Continue to flush SMS function - */ - void flushSMSContinue(); - - /** Parse CMGL response - @param rsp Returns true if expected response exists - @return true if command executed correctly - */ - bool parseCMGL_available(bool& rsp); -}; -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1ScanNetworks.cpp b/libraries/GSM/src/GSM3ShieldV1ScanNetworks.cpp deleted file mode 100644 index 8b5d5e4989..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ScanNetworks.cpp +++ /dev/null @@ -1,126 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#include - -GSM3ShieldV1ScanNetworks::GSM3ShieldV1ScanNetworks(bool trace): modem(trace) -{ -} - -GSM3_NetworkStatus_t GSM3ShieldV1ScanNetworks::begin() -{ - modem.begin(); - modem.restartModem(); - // check modem response - modem.writeModemCommand("AT", 1000); - modem.writeModemCommand("ATE0", 1000); - return IDLE; -} - -String GSM3ShieldV1ScanNetworks::getCurrentCarrier() -{ - String modemResponse = modem.writeModemCommand("AT+COPS?", 2000); - - // Parse and check response - char res_to_split[modemResponse.length()]; - modemResponse.toCharArray(res_to_split, modemResponse.length()); - if(strstr(res_to_split,"ERROR") == NULL){ - // Tokenizer - char *ptr_token; - ptr_token = strtok(res_to_split, "\""); - ptr_token = strtok(NULL, "\""); - String final_result = ptr_token; - return final_result; - }else{ - return String(NULL); - } -} - -String GSM3ShieldV1ScanNetworks::getSignalStrength() -{ - String modemResponse = modem.writeModemCommand("AT+CSQ", 2000); - char res_to_split[modemResponse.length()]; - modemResponse.toCharArray(res_to_split, modemResponse.length()); - if((strstr(res_to_split,"ERROR") == NULL) | (strstr(res_to_split,"99") == NULL)){ - // Tokenizer - char *ptr_token; - ptr_token = strtok(res_to_split, ":"); - ptr_token = strtok(NULL, ":"); - ptr_token = strtok(ptr_token, ","); - String final_result = ptr_token; - final_result.trim(); - return final_result; - }else{ - return String(NULL); - } -} - -String GSM3ShieldV1ScanNetworks::readNetworks() -{ - String modemResponse = modem.writeModemCommand("AT+COPS=?",20000); - String result; - bool inQuotes=false; - int quoteCounter=0; - for(unsigned int i=0; i -#include - -class GSM3ShieldV1ScanNetworks -{ - private: - GSM3ShieldV1DirectModemProvider modem; - - public: - - /** Constructor - @param trace if true, dumps all AT dialogue to Serial - @return - - */ - GSM3ShieldV1ScanNetworks(bool trace=false); - - /** begin (forces modem hardware restart, so we begin from scratch) - @return Always returns IDLE status - */ - GSM3_NetworkStatus_t begin(); - - /** Read current carrier - @return Current carrier - */ - String getCurrentCarrier(); - - /** Obtain signal strength - @return Signal Strength - */ - String getSignalStrength(); - - /** Search available carriers - @return A string with list of networks available - */ - String readNetworks(); -}; - -#endif \ No newline at end of file diff --git a/libraries/GSM/src/GSM3ShieldV1ServerProvider.cpp b/libraries/GSM/src/GSM3ShieldV1ServerProvider.cpp deleted file mode 100644 index 463fba6d34..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ServerProvider.cpp +++ /dev/null @@ -1,241 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include -#include - -GSM3ShieldV1ServerProvider::GSM3ShieldV1ServerProvider() -{ - theGSM3MobileServerProvider=this; -}; - -//Response management. -void GSM3ShieldV1ServerProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case NONE: - theGSM3ShieldV1ModemCore.gss.cb.deleteToTheEnd(from); - break; - case CONNECTSERVER: - connectTCPServerContinue(); - break; - /*case GETIP: - getIPContinue(); - break;*/ - - default: - break; - } -} - -//Connect Server main function. -int GSM3ShieldV1ServerProvider::connectTCPServer(int port) -{ - // We forget about LocalIP as it has no real use, the modem does whatever it likes - theGSM3ShieldV1ModemCore.setPort(port); - theGSM3ShieldV1ModemCore.openCommand(this,CONNECTSERVER); - // From this moment on we wait for a call - connectTCPServerContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Connect Server continue function. -void GSM3ShieldV1ServerProvider::connectTCPServerContinue() -{ - - bool resp; - // 1: Read Local IP "AT+QILOCIP" - // 2: Waiting for IP and Set local port "AT+QILPORT" - // 3: Waiting for QILPOR OK andConfigure as server "AT+QISERVER" - // 4: Wait for SERVER OK - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //"AT+QILOCIP." - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QILOCIP")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - //Not IP storing but the command is necessary. - //if(parseQILOCIP_rsp(local_IP, local_IP_Length, resp)) - // This awful trick saves some RAM bytes - char aux[3]; - aux[0]='\r';aux[1]='\n';aux[2]=0; - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp, aux)) - { - //Response received - if(resp) - { - // Great. Go for the next step - // AT+QILPORT - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QILPORT=\"TCP\","),false); - theGSM3ShieldV1ModemCore.print( theGSM3ShieldV1ModemCore.getPort()); - theGSM3ShieldV1ModemCore.print('\r'); - theGSM3ShieldV1ModemCore.setCommandCounter(3); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 3: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - if(resp) - { - // OK received - // Great. Go for the next step - // AT+QISERVER - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+QISERVER"),true); - theGSM3ShieldV1ModemCore.setCommandCounter(4); - } - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - case 4: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - // Response received - // OK received, kathapoon, chessespoon - if (resp) - { - theGSM3ShieldV1ModemCore.registerUMProvider(this); - theGSM3ShieldV1ModemCore.closeCommand(1); - } - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//QILOCIP parse. -/*bool GSM3ShieldV1ServerProvider::parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp) -{ - if (!(theGSM3ShieldV1ModemCore.theBuffer().extractSubstring("\r\n","\r\n", LocalIP, LocalIPlength))) - rsp = false; - else - rsp = true; - return true; -} - -//Get IP main function. -int GSM3ShieldV1ServerProvider::getIP(char* LocalIP, int LocalIPlength) -{ - theGSM3ShieldV1ModemCore.setPhoneNumber(LocalIP); - theGSM3ShieldV1ModemCore.setPort(LocalIPlength); - theGSM3ShieldV1ModemCore.openCommand(this,GETIP); - getIPContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -void GSM3ShieldV1ServerProvider::getIPContinue() -{ - - bool resp; - // 1: Read Local IP "AT+QILOCIP" - // 2: Waiting for IP. - - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //AT+QILOCIP - theGSM3ShieldV1ModemCore.genericCommand_rq(_command_MonoQILOCIP); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseQILOCIP_rsp(theGSM3ShieldV1ModemCore.getPhoneNumber(), theGSM3ShieldV1ModemCore.getPort(), resp)) - { - if (resp) - theGSM3ShieldV1ModemCore.closeCommand(1); - else - theGSM3ShieldV1ModemCore.closeCommand(3); - } - theGSM3ShieldV1ModemCore.theBuffer().flush(); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - break; - } -}*/ - -bool GSM3ShieldV1ServerProvider::getSocketAsServerModemStatus(int s) -{ - if(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED) - return true; - else - return false; -} - - -//URC recognize. -bool GSM3ShieldV1ServerProvider::recognizeUnsolicitedEvent(byte oldTail) -{ - - //int nlength; - char auxLocate [15]; - - //REMOTE SOCKET CLOSED. - prepareAuxLocate(PSTR("CLOSED\r\n"), auxLocate); - if(theGSM3ShieldV1ModemCore.gss.cb.locate(auxLocate)) - { - //To detect remote socket closed for example inside socket data. - theGSM3ShieldV1ModemCore.setStatus(GPRS_READY); - } - - - //REMOTE SOCKET ACCEPTED. - prepareAuxLocate(PSTR("CONNECT\r\n"), auxLocate); - if(theGSM3ShieldV1ModemCore.gss.cb.locate(auxLocate)) - { - //To detect remote socket closed for example inside socket data. - theGSM3ShieldV1ModemCore.theBuffer().chopUntil(auxLocate, true); - theGSM3ShieldV1ModemCore.gss.spaceAvailable(); - theGSM3ShieldV1ModemCore.setStatus(TRANSPARENT_CONNECTED); - return true; - } - - return false; -} - -bool GSM3ShieldV1ServerProvider::getStatusSocketAsServer(uint8_t socket) -{ - return(theGSM3ShieldV1ModemCore.getStatus()==TRANSPARENT_CONNECTED); -}; - -void GSM3ShieldV1ServerProvider::releaseSocket(int socket) -{ -} - -int GSM3ShieldV1ServerProvider::getNewOccupiedSocketAsServer() -{ - return 0; -} diff --git a/libraries/GSM/src/GSM3ShieldV1ServerProvider.h b/libraries/GSM/src/GSM3ShieldV1ServerProvider.h deleted file mode 100644 index 93fcd89a56..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1ServerProvider.h +++ /dev/null @@ -1,126 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SHIELDV1SERVERPROVIDER__ -#define __GSM3_SHIELDV1SERVERPROVIDER__ - -#include -#include - -class GSM3ShieldV1ServerProvider : public GSM3MobileServerProvider, public GSM3ShieldV1BaseProvider -{ - private: - - /** Continue to connect to server with TCP protocol function - */ - void connectTCPServerContinue(); - - /** Continue to get IP address function - */ - //void getIPContinue(); - - /** Parse QILOCIP response - @param LocalIP Buffer for save local IP address - @param LocalIPlength Buffer size - @param rsp Returns if expected response exists - @return true if command executed correctly - */ - //bool parseQILOCIP_rsp(char* LocalIP, int LocalIPlength, bool& rsp); - - /** Release socket - @param socket Socket - */ - void releaseSocket(int socket); - - public: - - /** Constructor */ - GSM3ShieldV1ServerProvider(); - - /** minSocketAsServer - @return 0 - */ - int minSocketAsServer(){return 0;}; - - /** maxSocketAsServer - @return 0 - */ - int maxSocketAsServer(){return 0;}; - - /** Get modem status - @param s Socket - @return modem status (true if connected) - */ - bool getSocketAsServerModemStatus(int s); - - /** Get new occupied socket as server - @return return -1 if no new socket has been occupied - */ - int getNewOccupiedSocketAsServer(); - - /** Connect server to TCP port - @param port TCP port - @return command error if exists - */ - int connectTCPServer(int port); - - //int getIP(char* LocalIP, int LocalIPlength); -// int disconnectTCP(bool client1Server0, int id_socket); - - /** Get last command status - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Get socket status as server - @param socket Socket to get status - @return socket status - */ - bool getStatusSocketAsServer(uint8_t socket); - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - /** Recognize unsolicited event - @param oldTail - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte oldTail); - - -}; - -#endif diff --git a/libraries/GSM/src/GSM3ShieldV1VoiceProvider.cpp b/libraries/GSM/src/GSM3ShieldV1VoiceProvider.cpp deleted file mode 100644 index 1560f33324..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1VoiceProvider.cpp +++ /dev/null @@ -1,269 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -static bool enableVoiceCall = false; - -GSM3ShieldV1VoiceProvider* theGSM3MobileVoiceProvider; - -GSM3ShieldV1VoiceProvider::GSM3ShieldV1VoiceProvider() -{ - phonelength=0; - _VoiceCallServiceEnable=false; - theGSM3MobileVoiceProvider=this; -} - -void GSM3ShieldV1VoiceProvider::initialize() -{ - theGSM3ShieldV1ModemCore.registerUMProvider(this); -} - -//Voice Call main function. -int GSM3ShieldV1VoiceProvider::voiceCall(const char* to) -{ - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("ATD"),false); - theGSM3ShieldV1ModemCore.print(to); - theGSM3ShieldV1ModemCore.print(";\r"); - setvoiceCallStatus(CALLING); - return 1; -} - -//Retrieve calling number main function. -int GSM3ShieldV1VoiceProvider::retrieveCallingNumber (char* buffer, int bufsize) -{ - theGSM3ShieldV1ModemCore.setPhoneNumber(buffer); - phonelength = bufsize; - theGSM3ShieldV1ModemCore.setCommandError(0); - theGSM3ShieldV1ModemCore.setCommandCounter(1); - theGSM3ShieldV1ModemCore.openCommand(this,RETRIEVECALLINGNUMBER); - retrieveCallingNumberContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Retrieve calling number Continue function. -void GSM3ShieldV1VoiceProvider::retrieveCallingNumberContinue() -{ - // 1: AT+CLCC - // 2: Receive +CLCC: 1,1,4,0,0,"num",129,"" - // This implementation really does not care much if the modem aswers trash to CMGL - //bool resp; - //int msglength_aux; - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("AT+CLCC")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(parseCLCC(theGSM3ShieldV1ModemCore.getPhoneNumber(), phonelength)) - { - theGSM3ShieldV1ModemCore.closeCommand(1); - } - break; - } -} - -//CLCC parse. -bool GSM3ShieldV1VoiceProvider::parseCLCC(char* number, int nlength) -{ - theGSM3ShieldV1ModemCore.theBuffer().extractSubstring("+CLCC: 1,1,4,0,0,\"","\"", number, nlength); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - return true; -} - -//Answer Call main function. -int GSM3ShieldV1VoiceProvider::answerCall() -{ - theGSM3ShieldV1ModemCore.setCommandError(0); - theGSM3ShieldV1ModemCore.setCommandCounter(1); - theGSM3ShieldV1ModemCore.openCommand(this,ANSWERCALL); - answerCallContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Answer Call continue function. -void GSM3ShieldV1VoiceProvider::answerCallContinue() -{ - // 1: ATA - // 2: Waiting for OK - - // This implementation really does not care much if the modem aswers trash to CMGL - bool resp; - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - // ATA ; - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("ATA")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - setvoiceCallStatus(TALKING); - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Hang Call main function. -int GSM3ShieldV1VoiceProvider::hangCall() -{ - theGSM3ShieldV1ModemCore.setCommandError(0); - theGSM3ShieldV1ModemCore.setCommandCounter(1); - theGSM3ShieldV1ModemCore.openCommand(this,HANGCALL); - hangCallContinue(); - return theGSM3ShieldV1ModemCore.getCommandError(); -} - -//Hang Call continue function. -void GSM3ShieldV1VoiceProvider::hangCallContinue() -{ - // 1: ATH - // 2: Waiting for OK - - bool resp; - switch (theGSM3ShieldV1ModemCore.getCommandCounter()) { - case 1: - //ATH - theGSM3ShieldV1ModemCore.genericCommand_rq(PSTR("ATH")); - theGSM3ShieldV1ModemCore.setCommandCounter(2); - break; - case 2: - if(theGSM3ShieldV1ModemCore.genericParse_rsp(resp)) - { - setvoiceCallStatus(IDLE_CALL); - if (resp) theGSM3ShieldV1ModemCore.closeCommand(1); - else theGSM3ShieldV1ModemCore.closeCommand(3); - } - break; - } -} - -//Response management. -void GSM3ShieldV1VoiceProvider::manageResponse(byte from, byte to) -{ - switch(theGSM3ShieldV1ModemCore.getOngoingCommand()) - { - case ANSWERCALL: - answerCallContinue(); - break; - case HANGCALL: - hangCallContinue(); - break; - case RETRIEVECALLINGNUMBER: - retrieveCallingNumberContinue(); - break; - - default: - break; - } -} - -//URC recognize. -bool GSM3ShieldV1VoiceProvider::recognizeUnsolicitedEvent(byte oldTail) -{ - - //int nlength; - char auxLocate [15]; - //RING. - prepareAuxLocate(PSTR("RING"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - // RING - setvoiceCallStatus(RECEIVINGCALL); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - return true; - } - - //CALL ACEPTED. - prepareAuxLocate(PSTR("+COLP:"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - //DEBUG - //Serial.println("Call Accepted."); - setvoiceCallStatus(TALKING); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - return true; - } - - //NO CARRIER. - prepareAuxLocate(PSTR("NO CARRIER"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - //DEBUG - //Serial.println("NO CARRIER received."); - setvoiceCallStatus(IDLE_CALL); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - return true; - } - - //BUSY. - prepareAuxLocate(PSTR("BUSY"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - //DEBUG - //Serial.println("BUSY received."); - setvoiceCallStatus(IDLE_CALL); - theGSM3ShieldV1ModemCore.theBuffer().flush(); - return true; - } - - //CALL RECEPTION. - prepareAuxLocate(PSTR("+CLIP:"), auxLocate); - if(theGSM3ShieldV1ModemCore.theBuffer().locate(auxLocate)) - { - theGSM3ShieldV1ModemCore.theBuffer().flush(); - setvoiceCallStatus(RECEIVINGCALL); - return true; - } - - return false; -} - -void GSM3ShieldV1VoiceProvider::setVoiceCallService(bool status) -{ - //_VoiceCallServiceEnable = status; - - enableVoiceCall = status; -} - -void GSM3ShieldV1VoiceProvider::linkToModemProvider() -{ - //if(_VoiceCallServiceEnable == true) - if(enableVoiceCall == true) - initialize(); -} - - diff --git a/libraries/GSM/src/GSM3ShieldV1VoiceProvider.h b/libraries/GSM/src/GSM3ShieldV1VoiceProvider.h deleted file mode 100644 index d5d4ff11e4..0000000000 --- a/libraries/GSM/src/GSM3ShieldV1VoiceProvider.h +++ /dev/null @@ -1,153 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ - -#ifndef _GSM3SHIELDV1VOICEPROVIDER_ -#define _GSM3SHIELDV1VOICEPROVIDER_ - -#include -#include -#include - -class GSM3ShieldV1VoiceProvider : public GSM3MobileVoiceProvider, public GSM3ShieldV1BaseProvider -{ - public: - - /** Constructor */ - GSM3ShieldV1VoiceProvider(); - - /** initilizer, links with modem provider */ - virtual void initialize(); - - - /** Manages modem response - @param from Initial byte of buffer - @param to Final byte of buffer - */ - void manageResponse(byte from, byte to); - - //Call functions. - - /** Launch a voice call - @param number Phone number to be called - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - int voiceCall(const char* number); - - /** Answer a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - int answerCall(); - - /** Hang a voice call - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - int hangCall(); - - /** Retrieve phone number of caller - @param buffer Buffer for copy phone number - @param bufsize Buffer size - @return If asynchronous, returns 0. If synchronous, 1 if success, other if error - */ - int retrieveCallingNumber(char* buffer, int bufsize); - - /** Get last command status - @return Returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(){return GSM3ShieldV1BaseProvider::ready();}; - - /** Recognize URC - @param oldTail - @return true if successful - */ - bool recognizeUnsolicitedEvent(byte oldTail); - - /** Returns voice call status - @return voice call status - */ - GSM3_voiceCall_st getvoiceCallStatus(){ready(); return _voiceCallstatus;}; - - /** Set voice call status - @param status New status for voice call - */ - void setvoiceCallStatus(GSM3_voiceCall_st status) { _voiceCallstatus = status; }; - - /** Set voice call service status - @param status New status for voice call - */ - void setVoiceCallService(bool status); - - /** Get voice call service status - @return Status of voice call - */ - bool getVoiceCallService() { return _VoiceCallServiceEnable;}; - - /** If voice call service enable, link to modem provider - */ - void linkToModemProvider(); - - private: - - int phonelength; // Phone number length - - GSM3_voiceCall_st _voiceCallstatus; // The voiceCall status - - /** Continue to voice call function - */ - void voiceCallContinue(); - - /** Continue to answer call function - */ - void answerCallContinue(); - - /** Continue to hang call function - */ - void hangCallContinue(); - - /** Continue to retrieve calling number function - */ - void retrieveCallingNumberContinue(); - - /** Parse CLCC response from buffer - @param number Number initial for extract substring of response - @param nlength Substring length - @return true if successful - */ - bool parseCLCC(char* number, int nlength); - - bool _VoiceCallServiceEnable; -}; - -extern GSM3ShieldV1VoiceProvider* theGSM3MobileVoiceProvider; - -#endif diff --git a/libraries/GSM/src/GSM3ShieldV2.cpp b/libraries/GSM/src/GSM3ShieldV2.cpp deleted file mode 100644 index 25e2790334..0000000000 --- a/libraries/GSM/src/GSM3ShieldV2.cpp +++ /dev/null @@ -1,256 +0,0 @@ -/* -This file is part of GSM3ShieldV2 library developed by Arduino.org (http://arduino.org). - - GSM3ShieldV2 library is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - GSM3ShieldV2 library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GSM3ShieldV2 library. If not, see . -*/ - -#include -#include - - -// constructor -GSM3ShieldV2::GSM3ShieldV2(bool db) -{ - debug=db; -} - -GSM3ShieldV2::GSM3ShieldV2() -{ -} - -// get position (longitude and latitude) -String GSM3ShieldV2::getPosition() -{ - String Result = ""; - String number; - // AT command for obtain the current Location - String modemResponse = modemAccess.writeModemCommand("AT+QCELLLOC=1", 1000); - // Parse and check response - char res_to_compare[modemResponse.length()]; - modemResponse.toCharArray(res_to_compare, modemResponse.length()); - if(strstr(res_to_compare,"OK") == NULL) - { - if(debug==true) Serial.println(modemResponse); - Result =" Position not lock "; - } - else - { - if(debug==true) Serial.println(modemResponse); - Result = modemResponse.substring(12, 33); - - } - return Result; -} -// set speaker loudness (this command have not effect. Refer to Quectel M10 datasheet for further informaions ) -String GSM3ShieldV2::speakerLoudness(int level) // set the speaker Volume - // 0: Low speaker volume - // 1: Low speaker volume - // 2: Medium speaker volume - // 3: High speaker volume -{ - String Result ="", modemResponse; - // Send the AT command for set the speaker volume - switch(level) - { - case 0: - modemResponse = modemAccess.writeModemCommand("ATL0",300); // set low volume - break; - - case 1: - modemResponse = modemAccess.writeModemCommand("ATL1",300); // set low volume - break; - - case 2: - modemResponse = modemAccess.writeModemCommand("ATL2",300); // set medium volume - break; - - case 3: - modemResponse = modemAccess.writeModemCommand("ATL3",300); // set High volume - break; - } - - char res_to_compare[modemResponse.length()]; - modemResponse.toCharArray(res_to_compare, modemResponse.length()); - if(strstr(res_to_compare,"OK") == NULL) - { - Result =" Error !"; - if(debug==true) Serial.println(Result); - } - else - { - Result = modemResponse.substring(1, 45); - if(debug==true) Serial.println(Result); - } - - return Result; -} -// set speaker mode -String GSM3ShieldV2::speakerMode(int mode) // Set the speaker on mode - // 0: Speaker is always off - // 1: Speaker is on until TA inform TE that carrier has been detected - // 2: Speaker is always on when TA is off-hook -{ - int spkMode=0; - char Mode[2],command[5]; - - Mode[1]='\0'; - command[4]='\0'; - - spkMode=mode; - if((spkMode < 0) || (spkMode > 2)) spkMode=DEFAULT_speakerMode; - strcpy(command,"ATM"); - itoa(spkMode,Mode,10); - strcat(command,Mode); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - - return modemResponse; - -} -// set alert sound mode -String GSM3ShieldV2::alertSoundMode(int mode) // silent the alert sound - // 0: Normal mode - // 1: Silent mode -{ - int soundMode=0; - char Mode[2],command[10]; - - Mode[1]='\0'; - command[9]='\0'; - - soundMode=mode; - if((soundMode < 0) || (soundMode > 1)) soundMode=DEFAULT_AlertSoundMode; - strcpy(command,"AT+CALM="); - itoa(soundMode,Mode,10); - strcat(command,Mode); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - - return modemResponse; -} -// set ringer sound level -String GSM3ShieldV2::ringerSoundLevel(int level) // Set the ringer volume (0-100) -{ - char command[12], lev[4]; - int ringLevel=level; - if((ringLevel < 0) || (ringLevel > 100)) ringLevel=DEFAULT_RingerSoundLevel; - - command[11]='\0'; - lev[3]='\0'; - strcpy(command,"AT+CRSL="); - itoa(ringLevel,lev,10); - strcat(command,lev); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - return modemResponse; - - -} -// set lodspeaker volume level -String GSM3ShieldV2::loudSpeakerVolumeLevel(int level) // Set the Speaker volume (0-100) -{ - char command[12], lev[4]; - int speakerLevel=level; - if((speakerLevel < 0) || (speakerLevel > 100)) speakerLevel=DEFAULT_LoudSpeakerVolumeLevel; - - command[11]='\0'; - lev[3]='\0'; - strcpy(command,"AT+CLVL="); - itoa(speakerLevel,lev,10); - strcat(command,lev); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - return modemResponse; -} -// set mute control -String GSM3ShieldV2::muteControl(int mode) // switch on or off mute - // 0: Mute off - // 1: Mute on -{ - char command[10], mod[2]; - int muteCtrl=mode; - if((muteCtrl < 0) || (muteCtrl > 1)) muteCtrl=DEFAULT_muteControl; //operazione non permessa - - command[9]='\0'; - mod[1]='\0'; - strcpy(command,"AT+CMUT="); - itoa(muteCtrl,mod,10); - strcat(command,mod); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - return modemResponse; -} -// set microphone gain -String GSM3ShieldV2::microphoneGainLevel(int channel, int gain) // Set the microphone channel and level - // Channel: - // 0: Normal Microphone - // 1: Headset Microphone - // 2: Loudspeaker Microphone - // Gain: (0-15) -{ - char chn[2], gn[3],command[13]; - - chn[1]='\0'; - gn[2]='\0'; - command[12]='\0'; - - if((channel < 0) || (channel > 2)) itoa(DEFAULT_Channel,chn,10); - else itoa(channel,chn,10); - - if((gain < 0) || (gain > 15)) itoa(DEFAULT_MicrophoneGainLevel,gn,10); - else itoa(gain,gn,10); - - strcpy(command,"AT+QMIC="); - strcat(command,chn); - strcat(command,","); - strcat(command,gn); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - return modemResponse; - -} -// set audio channel -String GSM3ShieldV2::swapAudioChannel(int channel) // Set the audio channel - // 0: Normal audio channel - // 1: headset audio channel - // 2: Loudspeaker audio chanel -{ - char chn[2], command[12]; - - chn[1]='\0'; - command[11]='\0'; - - if((channel < 0) || (channel > 2)) itoa(DEFAULT_Channel,chn,10); - else itoa(channel,chn,10); - strcpy(command,"AT+QAUDCH="); - strcat(command,chn); - String modemResponse=modemAccess.writeModemCommand(command,300); - if(debug==true) Serial.println(modemResponse); - return modemResponse; -} -// set the module echo mode (Refer Quectel M10 datasheet for further informaions) -void GSM3ShieldV2::CommandEcho(int value) -{ - switch(value) - { - case 0: modemAccess.writeModemCommand("ATE0",300); - break; - - case 1: modemAccess.writeModemCommand("ATE1",300); - break; - - default: - break; - } -} diff --git a/libraries/GSM/src/GSM3ShieldV2.h b/libraries/GSM/src/GSM3ShieldV2.h deleted file mode 100644 index 56f6fa2c51..0000000000 --- a/libraries/GSM/src/GSM3ShieldV2.h +++ /dev/null @@ -1,90 +0,0 @@ -/* -This file is part of GSM3ShieldV2 library developed by Arduino.org (http://arduino.org). - - GSM3ShieldV2 library is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - GSM3ShieldV2 library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GSM3ShieldV2 library. If not, see . -*/ - -#ifndef _GSM3SHIELDV2_ -#define _GSM3SHIELDV2_ - -#include -#include -#include -#include -#include -#include -#include -#include - -class GSM3ShieldV2 -{ - - private: - - GSM3ShieldV1DirectModemProvider modemAccess; - GSM3ShieldV1AccessProvider gsm; // Access provider to GSM/GPRS network - - public: - - /** Constructor */ - GSM3ShieldV2(); - GSM3ShieldV2(bool db); - - bool debug=false; - - String getPosition(); // Get Current Location - - // Aded for voice call debug - String speakerLoudness(int level); // set the speaker Volume - // 0: Low speaker volume - // 1: Low speaker volume - // 2: Medium speaker volume - // 3: High speaker volume - - String speakerMode(int mode); // Set the speaker on mode - // 0: Speaker is always off - // 1: Speaker is on until TA inform TE that carrier has been detected - // 2: Speaker is always on when TA is off-hook - - String alertSoundMode(int mode); // silent the alert sound - // 0: Normal mode - // 1: Silent mode - - String ringerSoundLevel(int level); // Set the ringer volume (0-100) - - String loudSpeakerVolumeLevel(int level); // Set the Speaker volume (0-100) - - String muteControl(int mode); // switch on or off mute - // 0: Mute off - // 1: Mute on - - String microphoneGainLevel(int channel, int gain); // Set the microphone channel and level - // Channel: - // 0: Normal Microphone - // 1: Headset Microphone - // 2: Loudspeaker Microphone - // Gain: (0-15) - - String swapAudioChannel(int channel); // Set the audio channel - // 0: Normal audio channel - // 1: headset audio channel - // 2: Loudspeaker audio chanel - - void CommandEcho(int value); // 0: command echo OFF - // 1: command echo ON - -}; - -#endif - diff --git a/libraries/GSM/src/GSM3SoftSerial.cpp b/libraries/GSM/src/GSM3SoftSerial.cpp deleted file mode 100644 index 5393871d7d..0000000000 --- a/libraries/GSM/src/GSM3SoftSerial.cpp +++ /dev/null @@ -1,228 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telef�nica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include "GSM3SoftSerial.h" -#include "GSM3IO.h" -#include -#include "pins_arduino.h" -//#include - -#define __XON__ 0x11 -#define __XOFF__ 0x13 - -#define _GSMSOFTSERIALFLAGS_ESCAPED_ 0x01 -#define _GSMSOFTSERIALFLAGS_SENTXOFF_ 0x02 - -GSM3SoftSerial* GSM3SoftSerial::_activeObject=0; - -GSM3SoftSerial::GSM3SoftSerial(): cb(this){} - -void GSM3SoftSerial::begin(long speed) -{ - _activeObject=this; - _flags=0; - - uart_emul_init(UART1_EMUL_E,speed); - uart_emul_attached_handler(&_timer, this->handle_interrupt); -} - -void GSM3SoftSerial::close() -{ - _activeObject=0; - uart_emul_deinit(UART1_EMUL_E); -} - -size_t GSM3SoftSerial::write(uint8_t c) -{ - // Characters to be escaped under XON/XOFF control with Quectel - if(c==0x11) - { - this->finalWrite(0x77); - return this->finalWrite(0xEE); - } - - if(c==0x13) - { - this->finalWrite(0x77); - return this->finalWrite(0xEC); - } - - if(c==0x77) - { - this->finalWrite(0x77); - return this->finalWrite(0x88); - } - - return this->finalWrite(c); -} - -size_t GSM3SoftSerial::finalWrite(uint8_t c) -{ - return uart_emul_write(UART1_EMUL_E, c); -} - -void GSM3SoftSerial::tunedDelay(uint16_t delay) -{ - delayInsideIT(delay); -} - -void GSM3SoftSerial::handle_interrupt() -{ - if(_activeObject) - _activeObject->recv(); -} - -void GSM3SoftSerial::recv() -{ - bool firstByte=true; - byte thisHead; - - uint8_t d = 0; - bool morebytes=false; - bool fullbuffer=false; - - if( ((_flags & _GSMSOFTSERIALFLAGS_SENTXOFF_) == _GSMSOFTSERIALFLAGS_SENTXOFF_) - && (uart_emul_available(UART1_EMUL_E) < UART_RCV_SIZE) - && (cb.availableBytes() > 6) ) - { - finalWrite(__XON__); - _flags &= ~_GSMSOFTSERIALFLAGS_SENTXOFF_; - } else { - if(uart_emul_available(UART1_EMUL_E) >= UART_RCV_SIZE) { - finalWrite(__XOFF__); - _flags |= _GSMSOFTSERIALFLAGS_SENTXOFF_; - } - - if(uart_emul_available(UART1_EMUL_E) > 0) - { - do - { - if(cb.availableBytes() < 6) { - fullbuffer=1; - if((_flags & _GSMSOFTSERIALFLAGS_SENTXOFF_) != _GSMSOFTSERIALFLAGS_SENTXOFF_) { - finalWrite(__XOFF__); - _flags |= _GSMSOFTSERIALFLAGS_SENTXOFF_; - } - } - - d = uart_emul_read(UART1_EMUL_E); - - if(keepThisChar(&d)) - { - cb.write(d); - if(firstByte) - { - firstByte=false; - thisHead=cb.getTail(); - } - } - - morebytes=false; - - if((uart_emul_available(UART1_EMUL_E) > 0) && (fullbuffer == 0)) - morebytes=true; - - }while(morebytes); - - //Just to be sure that thisHead is initialized! - if(firstByte) - thisHead=cb.getTail(); - - // If we find a line feed, we are at the end of a paragraph - // check! - if (fullbuffer) - { - // And... go handle it! - if(mgr) - mgr->manageMsg(thisHead, cb.getTail()); - } - else if(d==10) - { - // And... go handle it! - if(mgr) - mgr->manageMsg(thisHead, cb.getTail()); - } - else if (d==32) - { - // And... go handle it! - if(mgr) - mgr->manageMsg(thisHead, cb.getTail()); - } - } - } -} - -bool GSM3SoftSerial::keepThisChar(uint8_t* c) -{ - // Horrible things for Quectel XON/XOFF - // 255 is the answer to a XOFF - // It comes just once - if((*c==255)&&(_flags & _GSMSOFTSERIALFLAGS_SENTXOFF_)) - { - //_flags ^= _GSMSOFTSERIALFLAGS_SENTXOFF_; - return false; - } - - // 0x77, w, is the escape character - if(*c==0x77) - { - _flags |= _GSMSOFTSERIALFLAGS_ESCAPED_; - return false; - } - - // and these are the escaped codes - if(_flags & _GSMSOFTSERIALFLAGS_ESCAPED_) - { - if(*c==0xEE) - *c=0x11; - else if(*c==0xEC) - *c=0x13; - else if(*c==0x88) - *c=0x77; - - _flags ^= _GSMSOFTSERIALFLAGS_ESCAPED_; - return true; - } - - return true; -} - -void GSM3SoftSerial::spaceAvailable() -{ - // If there is spaceAvailable in the buffer, lets send a XON - //finalWrite((byte)__XON__); -} - - -// This is here to avoid problems with Arduino compiler -void GSM3SoftSerialMgr::manageMsg(byte from, byte to){}; diff --git a/libraries/GSM/src/GSM3SoftSerial.h b/libraries/GSM/src/GSM3SoftSerial.h deleted file mode 100644 index f2a445a67d..0000000000 --- a/libraries/GSM/src/GSM3SoftSerial.h +++ /dev/null @@ -1,139 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telef�nica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef __GSM3_SOFTSERIAL__ -#define __GSM3_SOFTSERIAL__ - -// An adaptation of NewSoftSerial for Modem Shields -// Assumes directly that Serial is attached to Pins 2 and 3, not inverse -// We are implementing it because NewSoftSerial does not deal correctly with floods -// of data -#include "GSM3CircularBuffer.h" -#include -#include - -class GSM3SoftSerialMgr -{ - public: - - /** Manages soft serial message - @param from Initial byte - @param to Final byte - */ - virtual void manageMsg(byte from, byte to); -}; - -// This class manages software serial communications -// Changing it so it doesn't know about modems or whatever - -class GSM3SoftSerial : public GSM3CircularBufferManager -{ - private: - - uint8_t _receiveBitMask; - volatile uint8_t *_receivePortRegister; - uint8_t _transmitBitMask; - volatile uint8_t *_transmitPortRegister; - - static GSM3SoftSerial* _activeObject; - GSM3SoftSerialMgr* mgr; - - uint8_t _flags; - - stimer_t _timer; - - /** Receive - */ - void recv(); - - void setComsReceived(); - - /** Write a character in serial connection, final action after escaping - @param c Character - @return 1 if succesful, 0 if transmission delay = 0 - */ - virtual size_t finalWrite(uint8_t); - - /** Decide, attending to escapes, if the received character should we - kept, forgotten, or changed - @param c Character, may be changed - @return 1 if shall be kept, 0 if forgotten - */ - bool keepThisChar(uint8_t* c); - - // Checks the buffer for well-known events. - //bool recognizeUnsolicitedEvent(byte oldTail); - - public: - - /** Tuned delay in microcontroller - @param delay Time to delay - */ - static /*inline */void tunedDelay(uint16_t delay); - - GSM3CircularBuffer cb; // Circular buffer - - /** Register serial manager - @param manager Serial manager - */ - inline void registerMgr(GSM3SoftSerialMgr* manager){mgr=manager;}; - - /** If there is spaceAvailable in the buffer, lets send a XON - */ - void spaceAvailable(); - - /** Write a character in serial connection - @param c Character - @return 1 if succesful, 0 if transmission delay = 0 - */ - virtual size_t write(uint8_t); - - /** Constructor */ - GSM3SoftSerial(); - - /** Establish serial connection - @param speed Baudrate - @return none - */ - void begin(long speed); - - /** Manage interruptions - */ - static inline void handle_interrupt(); - - /** Close serial connection - */ - void close(); -}; - -#endif diff --git a/libraries/GSM/src/GSM3VoiceCallService.cpp b/libraries/GSM/src/GSM3VoiceCallService.cpp deleted file mode 100644 index 84cacd8988..0000000000 --- a/libraries/GSM/src/GSM3VoiceCallService.cpp +++ /dev/null @@ -1,145 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#include -#include - -#include - -// While there is only a shield (ShieldV1) we will include it by default -GSM3ShieldV1VoiceProvider theShieldV1VoiceProvider; - -#define GSM3VOICECALLSERVICE_SYNCH 0x01 // 1: synchronous 0: asynchronous -#define __TOUT__ 10000 - -GSM3VoiceCallService::GSM3VoiceCallService(bool synch) -{ - if(synch) - flags |= GSM3VOICECALLSERVICE_SYNCH; - - if(NULL == theGSM3MobileVoiceProvider) - theGSM3MobileVoiceProvider = &theShieldV1VoiceProvider; - - theGSM3MobileVoiceProvider->setVoiceCallService(true); -} - -GSM3_voiceCall_st GSM3VoiceCallService::getvoiceCallStatus() -{ - if(&theGSM3MobileVoiceProvider==0) - return IDLE_CALL; - - return theGSM3MobileVoiceProvider->getvoiceCallStatus(); -} - -int GSM3VoiceCallService::ready() -{ - if(&theGSM3MobileVoiceProvider==0) - return 0; - - return theGSM3MobileVoiceProvider->ready(); -} - -int GSM3VoiceCallService::voiceCall(const char* to, unsigned long timeout) -{ - if(&theGSM3MobileVoiceProvider==0) - return 0; - - if(flags & GSM3VOICECALLSERVICE_SYNCH ) - { - theGSM3MobileVoiceProvider->voiceCall(to); - unsigned long m; - m=millis(); - // Wait an answer for timeout - while(((millis()-m)< timeout )&&(getvoiceCallStatus()==CALLING)) - delay(100); - - if(getvoiceCallStatus()==TALKING) - return 1; - else - return 0; - } - else - { - return theGSM3MobileVoiceProvider->voiceCall(to); - } - -} - -int GSM3VoiceCallService::answerCall() -{ - if(&theGSM3MobileVoiceProvider==0) - return 0; - - return waitForAnswerIfNeeded(theGSM3MobileVoiceProvider->answerCall()); -} - -int GSM3VoiceCallService::hangCall() -{ - if(&theGSM3MobileVoiceProvider==0) - return 0; - - return waitForAnswerIfNeeded(theGSM3MobileVoiceProvider->hangCall());; -} - -int GSM3VoiceCallService::retrieveCallingNumber(char* buffer, int bufsize) -{ - if(&theGSM3MobileVoiceProvider==0) - return 0; - - return waitForAnswerIfNeeded(theGSM3MobileVoiceProvider->retrieveCallingNumber(buffer, bufsize)); -} - -int GSM3VoiceCallService::waitForAnswerIfNeeded(int returnvalue) -{ - // If synchronous - if(flags & GSM3VOICECALLSERVICE_SYNCH ) - { - unsigned long m; - m=millis(); - // Wait for __TOUT__ - while(((millis()-m)< __TOUT__ )&&(ready()==0)) - delay(100); - // If everything was OK, return 1 - // else (timeout or error codes) return 0; - if(ready()==1) - return 1; - else - return 0; - } - // If not synchronous just kick ahead the coming result - return ready(); -} - - - - diff --git a/libraries/GSM/src/GSM3VoiceCallService.h b/libraries/GSM/src/GSM3VoiceCallService.h deleted file mode 100644 index f9e2e0ee00..0000000000 --- a/libraries/GSM/src/GSM3VoiceCallService.h +++ /dev/null @@ -1,103 +0,0 @@ -/* -This file is part of the GSM3 communications library for Arduino --- Multi-transport communications platform --- Fully asynchronous --- Includes code for the Arduino-Telefonica GSM/GPRS Shield V1 --- Voice calls --- SMS --- TCP/IP connections --- HTTP basic clients - -This library has been developed by Telefónica Digital - PDI - -- Physical Internet Lab, as part as its collaboration with -Arduino and the Open Hardware Community. - -September-December 2012 - -This library is free software; you can redistribute it and/or -modify it under the terms of the GNU Lesser General Public -License as published by the Free Software Foundation; either -version 2.1 of the License, or (at your option) any later version. - -This library is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public -License along with this library; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -The latest version of this library can always be found at -https://github.com/BlueVia/Official-Arduino -*/ -#ifndef _GSM3VOICECALLSERVICE_ -#define _GSM3VOICECALLSERVICE_ - -#include -#include - -class GSM3VoiceCallService -{ - private: - uint8_t flags; - - /** Make synchronous the functions, if needed - @param returnvalue Return value - @return returns 0 if last command is still executing, 1 success, >1 error - */ - int waitForAnswerIfNeeded(int returnvalue); - - public: - /** Service creation - @param synch If true, the service calls are synchronois - */ - GSM3VoiceCallService(bool synch=true); - - /** Voice call status - @return Status of the voice call, as described in GSM3MobileVoiceProvider.h - { IDLE_CALL, CALLING, RECEIVINGCALL, TALKING}; - */ - GSM3_voiceCall_st getvoiceCallStatus(); - - /** Get last command status - @return Returns 0 if last command is still executing, 1 success, >1 error - */ - int ready(); - - /** Place a voice call. If asynchronous, returns while ringing. If synchronous - returns if the call is stablished or cancelled. - @param to Receiver number. Country extension can be used or not. - Char buffer should not be released or used until command is over - @param timeout In millisecods. Time ringing before closing the call. - Only used in synchronous mode. - If zero, ring undefinitely - @return In asynchronous mode returns 0 if last command is still executing, 1 success, >1 error - In synchronous mode returns 1 if the call is placed, 0 if not. - */ - int voiceCall(const char* to, unsigned long timeout=30000); - - /** Accept an incoming voice call - @return In asynchronous mode returns 0 if last command is still executing, 1 success, >1 error - In synchronous mode returns 1 if the call is answered, 0 if not. - */ - int answerCall(); - - /** Hang a stablished call or an incoming ring - @return In asynchronous mode returns 0 if last command is still executing, 1 success, >1 error - In synchronous mode returns 1 if the call is answered, 0 if not. - */ - int hangCall(); - - /** Retrieve the calling number, put it in buffer - @param buffer pointer to the buffer memory - @param bufsize size of available memory area, at least should be 10 characters - @return In asynchronous mode returns 0 if last command is still executing, 1 success, >1 error - In synchronous mode returns 1 if the number is correcty taken 0 if not - */ - int retrieveCallingNumber(char* buffer, int bufsize); -}; - - - -#endif From 0a38d46f8522f512b7567d367db6070531d6aeba Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 19 Sep 2018 14:46:22 +0200 Subject: [PATCH 058/109] Remove uart emulation which is not maintained (and not functional) and will be replaced by an official SoftwareSerial port. See #267. Signed-off-by: Frederic.Pillon --- cores/arduino/board.h | 2 - cores/arduino/stm32/hal_uart_emul.c | 1237 ----------------------- cores/arduino/stm32/hal_uart_emul.h | 417 -------- cores/arduino/stm32/uart_emul.c | 424 -------- cores/arduino/stm32/uart_emul.h | 82 -- variants/NUCLEO_F302R8/PeripheralPins.c | 1 - variants/board_template/variant.h | 5 - 7 files changed, 2168 deletions(-) delete mode 100644 cores/arduino/stm32/hal_uart_emul.c delete mode 100644 cores/arduino/stm32/hal_uart_emul.h delete mode 100644 cores/arduino/stm32/uart_emul.c delete mode 100644 cores/arduino/stm32/uart_emul.h diff --git a/cores/arduino/board.h b/cores/arduino/board.h index 00e207e62a..c008f24981 100644 --- a/cores/arduino/board.h +++ b/cores/arduino/board.h @@ -12,7 +12,6 @@ extern "C"{ #include "clock.h" #include "core_callback.h" #include "digital_io.h" -#include "hal_uart_emul.h" #include "hw_config.h" #include "low_power.h" #include "rtc.h" @@ -21,7 +20,6 @@ extern "C"{ #include "timer.h" #include "twi.h" #include "uart.h" -#include "uart_emul.h" #ifdef USBCON #include "usb_interface.h" #endif //USBCON diff --git a/cores/arduino/stm32/hal_uart_emul.c b/cores/arduino/stm32/hal_uart_emul.c deleted file mode 100644 index 0da6b2cc11..0000000000 --- a/cores/arduino/stm32/hal_uart_emul.c +++ /dev/null @@ -1,1237 +0,0 @@ -/** - ****************************************************************************** - * @file hal_uart_emul.c - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 - * @brief Adaptation from stm32f4xx_hal_uart_emul.c - * UART Emulation HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter (UART Emulation): - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART Emulation HAL driver can be used as follows: - - (#) Declare a UART_Emul_HandleTypeDef handle structure. - - (#) Initialize the UART Emulation low level resources by implementing the HAL_UART_Emul_MspInit() API: - (##) Enable the UART_EMUL clock - (##) UART Emulation port declaration - (+++) UART pins configuration: TxPinNumber and RxPinNumber - (+++) Enable the clock for the GPIOs - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, - and Mode(Receiver/Transmitter) in the huart Emul Init structure. - - (#) Initialize the UART Emulation registers software by calling the HAL_UART_Emul_Init() API. - - -@- The specific UART Emulaion Handle (Transmission complete, Reception complete - and Transfer Error) will be managed using the macros HAL_UART_Emul_TxCpltCallback(), - HAL_UART_Emul_RxCpltCallback() and __HAL_UART_Emul_TranferError() inside the transmit - and receive process. - - -@- These API's(HAL_UART_Emul_Init() configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_UART_Emul_MspInit() API. - - (#) Three modes of operations are available within this driver: - - *** UART Emulation mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode (IT) using HAL_UART_Emul_Transmit() - (+) At transmission end of transfer HAL_UART_Emul_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_Emul_TxCpltCallback - (+) Receive an amount of data in non blocking mode (IT) using HAL_UART_Emul_Receive() - - (+) At reception end of transfer HAL_UART_Emul_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_Emul_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_Emul_ErrorCallback - - *** UART Emulation HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in UART Emulation HAL driver. - - (+) __HAL_UART_EMUL_GET_FLAG : Checks whether the specified UART Emulation flag is set or not - (+) __HAL_UART_EMUL_CLEAR_FLAG : Clears the specified UART Emulation pending flag - (+) __HAL_UART_EMUL_SET_FLAG : Set the specified UART Emulation flag - - [..] - (@) You can refer to the UART Emulation HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

          © COPYRIGHT(c) 2015 STMicroelectronics

          - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(TIM1_BASE) && defined(UART_EMUL_RX) && defined(UART_EMUL_TX) -/* Includes ------------------------------------------------------------------*/ -#include "hal_uart_emul.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup UART_EMUL_HAL_Driver - * @brief HAL UART Emulation module driver - * @{ - */ -//#ifdef HAL_UART_EMUL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* DMA Handle declaration */ -static DMA_HandleTypeDef hdma_tx; -static DMA_HandleTypeDef hdma_rx; -/* Timer handler declaration */ -static TIM_HandleTypeDef TimHandle; - -/* UART Emulation Handle */ -static UART_Emul_HandleTypeDef *huart_emul; - -/* First Buffer for format data in reception mode */ -static uint32_t *pFirstBuffer_Rx[RX_BUFFER_SIZE]; - -/* Second Buffer for format data in reception mode */ -static uint32_t *pSecondBuffer_Rx[RX_BUFFER_SIZE]; - -/* First Buffer for format data in transmission mode */ -static uint32_t *pFirstBuffer_Tx[TX_BUFFER_SIZE]; - -/* Second Buffer for format data in transmission mode */ -static uint32_t *pSecondBuffer_Tx[TX_BUFFER_SIZE]; - -/* Private function prototypes -----------------------------------------------*/ -static void UART_Emul_SetConfig (UART_Emul_HandleTypeDef *huart); -static void UART_Emul_SetConfig_DMATx(void); -static void UART_Emul_SetConfig_DMARx(void); -static void UART_Emul_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_Emul_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_Emul_DMAError(DMA_HandleTypeDef *hdma); -static void UART_Emul_TransmitFrame(UART_Emul_HandleTypeDef *huart); -static void UART_Emul_ReceiveFrame(UART_Emul_HandleTypeDef *huart, uint32_t *pData); -static void UART_Emul_TransmitFormatFrame(UART_Emul_HandleTypeDef *huart , uint8_t pData, uint32_t *pBuffer_Tx); -static uint8_t UART_Emul_ReceiveFormatFrame(UART_Emul_HandleTypeDef *huart, uint32_t *pBuffer, uint8_t pFrame); - - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup UART_Private_Functions - * @{ - */ - -/** @defgroup UART_Emulation_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - This subsection provides a set of functions allowing to initialize the UART Emulation - in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate (4800 up 115200) - (++) Word Length (5 bit up 9 bit) - (++) Stop Bit (1 or 2 stop bit) - (++) Parity: If the parity is enabled, then the MSB bit of the data to be transmitted - is changed by the parity bit. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the UART Emulation mode according to the specified parameters in - * the UART_Emul_InitTypeDef and create the associated handle. - * @param huart: UART Emulation handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Emul_Init(UART_Emul_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - if (huart->State == HAL_UART_EMUL_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_Emul_MspInit(huart); - } - - /* Get Structure for uart emul Handle */ - huart_emul = huart; - - /* Set the TIM state */ - huart->State = HAL_UART_EMUL_STATE_BUSY; - - /* Set the UART Emulation Communication parameters */ - UART_Emul_SetConfig(huart); - - /* Initialize the UART Emulation state */ - huart->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - huart->State = HAL_UART_EMUL_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the UART Emulation . - * @param huart: UART Emulation handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Emul_DeInit(UART_Emul_HandleTypeDef *huart) -{ - /* Check the UART Emulation handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - huart->State = HAL_UART_EMUL_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_UART_Emul_MspDeInit(huart); - - huart->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - huart->State = HAL_UART_EMUL_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the UART Emulation MSP. - * @param huart: UART Emulation Handle - * @retval None - */ -__weak void HAL_UART_Emul_MspInit(UART_Emul_HandleTypeDef *huart) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_UART_Emul_MspInit could be implemented in the user file - */ -} - -/** - * @brief UART Emulation MSP DeInit. - * @param huart: UART Emulation handle - * @retval None - */ -__weak void HAL_UART_Emul_MspDeInit(UART_Emul_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_Emul_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Emulation_Group2 IO operation functions - * @brief UART Emulation Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There is one mode of transfer: - (++) Non-Blocking mode: The communication is performed using DMA, - this APIs returns the HAL status. - The end of the data processing will be indicated through the - DMA IRQ - - The HAL_UART_Emul_TxCpltCallback(), HAL_UART_Emul_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or receive process. - The HAL_UART_Emul_ErrorCallback() user callback will be executed when - a communication error is detected. - - (#) Non Blocking mode functions with DMA are: - (++) HAL_UART_Emul_Transmit_DMA() - (++) HAL_UART_Emul_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: - (++) HAL_UART_Emul_TxCpltCallback() - (++) HAL_UART_Emul_RxCpltCallback() - (++) HAL_UART_Emul_ErrorCallback() - - [..] - -@endverbatim - * @{ - */ -/** - * @brief Sends an amount of data - * @param huart: UART Emulation handle - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Emul_Transmit_DMA(UART_Emul_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = huart->State; - if ((tmp == HAL_UART_EMUL_STATE_READY) || (tmp == HAL_UART_EMUL_STATE_BUSY_RX)) - { - if ((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - huart->TxXferSize = Size; - huart->pTxBuffPtr = pData; - huart->TxXferCount = 1; - huart->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - if (huart->State == HAL_UART_EMUL_STATE_BUSY_RX) - { - huart->State = HAL_UART_EMUL_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_EMUL_STATE_BUSY_TX; - } - - /* Set the UART Emulation DMA transfer complete callback */ - TimHandle.hdma[TIM_DMA_Handle_Tx]->XferCpltCallback = UART_Emul_DMATransmitCplt; - - /* Set the DMA error callback */ - TimHandle.hdma[TIM_DMA_Handle_Tx]->XferErrorCallback = UART_Emul_DMAError; - - /* Format first Frame to be sent */ - if (huart->TxXferCount == FIRST_BYTE) - { - /* Format Frame to be sent */ - UART_Emul_TransmitFormatFrame(huart, *(pData), (uint32_t*)pFirstBuffer_Tx); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(UART_EMUL_TX_TIMER_INSTANCE, TIM_Channel_Tx, TIM_CCx_ENABLE); - - /* Send Frames */ - UART_Emul_TransmitFrame(huart); - } - - if ((huart->TxXferCount == FIRST_BYTE) && (huart->TxXferCount < Size)) - { - /* Format Second Frame to be sent */ - UART_Emul_TransmitFormatFrame(huart, *(pData + huart->TxXferCount), (uint32_t*)pSecondBuffer_Tx); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param huart: UART Emulation handle - * @param pData: Data to be received - * @param Size: Amount of data to be received - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Emul_Receive_DMA(UART_Emul_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t tmp = 0; - - tmp = huart->State; - if ((tmp == HAL_UART_EMUL_STATE_READY) || (tmp == HAL_UART_EMUL_STATE_BUSY_TX)) - { - if ((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = 1; - - huart->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - - /* Check if a transmit process is ongoing or not */ - if (huart->State == HAL_UART_EMUL_STATE_BUSY_TX) - { - huart->State = HAL_UART_EMUL_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_EMUL_STATE_BUSY_RX; - } - - /* Set the UART Emulation DMA transfer complete callback */ - TimHandle.hdma[TIM_DMA_Handle_Rx]->XferCpltCallback = UART_Emul_DMAReceiveCplt; - - /* Set the DMA error callback */ - TimHandle.hdma[TIM_DMA_Handle_Rx]->XferErrorCallback = UART_Emul_DMAError; - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(UART_EMUL_RX_TIMER_INSTANCE, TIM_Channel_Rx, TIM_CCx_ENABLE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Initializes the UART Emulation Transfer Complete. - * @param huart: UART Emulation Handle - * @retval None - */ -__weak void HAL_UART_Emul_RxCpltCallback(UART_Emul_HandleTypeDef *huart) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_UART_Emul_TransferComplet could be implemented in the user file - */ -} - -/** - * @} - */ -/*=============================================================================== - ##### Interrupt Handlers used in UART Emulation ##### - =============================================================================== -*/ - -/** -* @brief This function handles DMA interrupt request for TC. -* @param None -* @retval None -*/ -void UART_EMUL_RX_DMA_IRQHandler(void) -{ - /* Increment Counter of Frame */ - huart_emul->RxXferCount ++; - - /* Enable External interrupt for next Frame */ - EXTI->IMR |= huart_emul->Init.RxPinNumber; - - if (__HAL_DMA_GET_FLAG(TimHandle.hdma[TIM_DMA_Handle_Rx], __HAL_DMA_GET_TE_FLAG_INDEX(TimHandle.hdma[TIM_DMA_Handle_Rx])) != RESET) - { - UART_Emul_DMAError(&hdma_rx); - } - - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(TimHandle.hdma[TIM_DMA_Handle_Rx], __HAL_DMA_GET_TC_FLAG_INDEX(TimHandle.hdma[TIM_DMA_Handle_Rx])); - - /* Transfer complete callback */ - TimHandle.hdma[TIM_DMA_Handle_Rx]->XferCpltCallback(TimHandle.hdma[TIM_DMA_Handle_Rx]); -} - -/** - * @brief EXTI line detection callbacks - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -void UART_EMUL_EXTI_RX(void/*uint16_t GPIO_Pin*/) -{ - uint32_t tmpreceive = 0; - uint32_t tmpformat = 0; - uint32_t tmpdata = 0; - - /* Disable EXTI line Rx */ - EXTI->IMR &= ~huart_emul->Init.RxPinNumber; - - if ((huart_emul->RxXferCount % 2) != 0) - { - tmpreceive = (uint32_t)pFirstBuffer_Rx; - tmpformat = (uint32_t)pSecondBuffer_Rx; - } - else - { - tmpreceive = (uint32_t)pSecondBuffer_Rx; - tmpformat = (uint32_t)pFirstBuffer_Rx; - } - - /* Start receiver mode in the reference point*/ - UART_Emul_ReceiveFrame(huart_emul, (uint32_t*)tmpreceive); - - if (huart_emul->RxXferCount > 1) -{ - /* Format frame */ - *(uint8_t*)((huart_emul->pRxBuffPtr) + (huart_emul->RxXferCount - 2)) = UART_Emul_ReceiveFormatFrame(huart_emul, (uint32_t*)tmpformat, (uint8_t)tmpdata); - } -} - -/** -* @brief This function handles DMA interrupt request for TC. -* @param None -* @retval None -*/ -void UART_EMUL_TX_DMA_IRQHandler(void) -{ - if (__HAL_DMA_GET_FLAG(TimHandle.hdma[TIM_DMA_Handle_Tx], __HAL_DMA_GET_TE_FLAG_INDEX(TimHandle.hdma[TIM_DMA_Handle_Tx])) != RESET) - { - UART_Emul_DMAError(&hdma_tx); - } - - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(TimHandle.hdma[TIM_DMA_Handle_Tx], __HAL_DMA_GET_TC_FLAG_INDEX(TimHandle.hdma[TIM_DMA_Handle_Tx])); - - /* Transfer complete callback */ - TimHandle.hdma[TIM_DMA_Handle_Tx]->XferCpltCallback(TimHandle.hdma[TIM_DMA_Handle_Tx]); -} - -/** - * @brief This function handles UART Emulation request. - * @param huart: UART Emulation handle - * @retval None - */ -void HAL_UART_Emul_IRQHandler(UART_Emul_HandleTypeDef *huart) -{ - uint32_t tmp = 0; - - tmp = __HAL_UART_EMUL_GET_FLAG(huart, UART_EMUL_FLAG_PE); - /* UART Emulation parity error occurred */ - if (tmp != RESET) - { - __HAL_UART_EMUL_CLEAR_FLAG(huart, UART_EMUL_FLAG_PE); - - huart->ErrorCode |= HAL_UART_EMUL_ERROR_PE; - } - - tmp = __HAL_UART_EMUL_GET_FLAG(huart, UART_EMUL_FLAG_FE); - /* UART Emulation frame error occurred */ - if (tmp != RESET) - { - __HAL_UART_EMUL_CLEAR_FLAG(huart, UART_EMUL_FLAG_FE); - - huart->ErrorCode |= HAL_UART_EMUL_ERROR_FE; - } - - tmp = __HAL_UART_EMUL_GET_FLAG(huart, UART_EMUL_FLAG_TC); - /* UART Emulation in mode Transmitter */ - if ((tmp != RESET)) - { - __HAL_UART_EMUL_CLEAR_FLAG(huart, UART_EMUL_FLAG_TC); - } - - tmp = __HAL_UART_EMUL_GET_FLAG(huart, UART_EMUL_FLAG_RC); - /* UART Emulation in mode Receiver */ - if ((tmp != RESET)) - { - __HAL_UART_EMUL_CLEAR_FLAG(huart, UART_EMUL_FLAG_RC); - } - - if (huart->ErrorCode != HAL_UART_EMUL_ERROR_NONE) - { - /* Set the UART Emulation state ready to be able to start again the process */ - huart->State = HAL_UART_EMUL_STATE_READY; - - HAL_UART_Emul_ErrorCallback(huart); - } -} - -/** - * @} - */ - -/** @defgroup UART_Emulation_Group3 Peripheral State and Errors functions - * @brief UART Emulation State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - UART Emulation communication process, return Peripheral Errors occured during communication - process - (+) HAL_UART_Emul_GetState() API can be helpful to check in run-time the state of the UART Emulation. - (+) HAL_UART_Emul_GetError() check in run-time errors that could be occured durung communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the UART Emulation state. - * @param huart: UART Emulation handle - * @retval HAL state - */ -HAL_UART_Emul_StateTypeDef HAL_UART_Emul_GetState(UART_Emul_HandleTypeDef *huart) -{ - return huart->State; -} - -/** -* @brief Return the UART Emulation error code -* @param huart : pointer to UART_Emul_HandleTypeDef structure that contains - * the configuration information for the specified UART Emulation. -* @retval UART Emulation Error Code -*/ -uint32_t HAL_UART_Emul_GetError(UART_Emul_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} - -/** - * @} - */ -/*=============================================================================== - ##### Private function for UART Emulation ##### - =============================================================================== -*/ - -/** - * @brief This function is executed in case of Receive Complete for last frame. - * @param None - * @retval None - */ -static void UART_Emul_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - uint32_t tmpformat = 0; - uint32_t tmpdata = 0; - if (huart_emul->RxXferCount > huart_emul->RxXferSize) - { - /*Enable EXTI line Rx */ - //EXTI->IMR |= huart_emul->Init.RxPinNumber; - - /* Disable the Peripheral */ - __HAL_DMA_DISABLE(&hdma_rx); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(&TimHandle, TIM_DMA_source_Rx); - - if ((huart_emul->RxXferCount % 2) == 0) - { - tmpformat = (uint32_t)pFirstBuffer_Rx; - } - - else - { - tmpformat = (uint32_t)pSecondBuffer_Rx; - } - - /* Formatted Last Frame */ - *(uint8_t*)((huart_emul->pRxBuffPtr) + (huart_emul->RxXferCount - 2)) = UART_Emul_ReceiveFormatFrame(huart_emul, (uint32_t*)tmpformat, (uint8_t)tmpdata); - - /* Set RC flag receiver complete */ - __HAL_UART_EMUL_SET_FLAG(huart_emul, UART_EMUL_FLAG_RC); - - /* De_Initialize counter frame for Rx */ - huart_emul->RxXferCount = 0; - - /* Initialize the UART Emulation state */ - huart_emul->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - - /* Check if a transmit process is ongoing or not */ - if (huart_emul->State == HAL_UART_EMUL_STATE_BUSY_TX_RX) - { - huart_emul->State = HAL_UART_EMUL_STATE_BUSY_TX; - } - else - { - huart_emul->State = HAL_UART_EMUL_STATE_READY; - } - - /* Handle for UART Emulation Receive Complete */ - HAL_UART_Emul_RxCpltCallback(huart_emul); - } -} - -/** - * @brief Receives an amount of Frames. - * @param huart: UART Emulation handle - * @param pData: Frame to be Received - * @retval None -*/ -static void UART_Emul_ReceiveFrame(UART_Emul_HandleTypeDef *huart, uint32_t *pData) -{ - uint32_t tmp_sr =0; - uint32_t tmp_ds =0; - uint32_t tmp_size =0; - uint32_t tmp_arr =0; - - tmp_arr = UART_EMUL_RX_TIMER_INSTANCE->ARR; - tmp_ds = (uint32_t)pData; - tmp_sr = (uint32_t) & (huart->RxPortName->IDR); - tmp_size = __HAL_UART_EMUL_FRAME_LENGTH(huart); - - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(&hdma_rx, DMA_IT_TC); - - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(&hdma_rx, DMA_IT_TE); - -#if defined (STM32F0xx) || defined (STM32F3xx) - /* Configure DMA Stream data length */ - hdma_rx.Instance->CNDTR = tmp_size; - - /* Configure DMA Stream source address */ - hdma_rx.Instance->CPAR = tmp_sr; - - /* Configure DMA Stream destination address */ - hdma_rx.Instance->CMAR = tmp_ds; -#else - /* Configure DMA Stream data length */ - hdma_rx.Instance->NDTR = tmp_size; - - /* Configure DMA Stream source address */ - hdma_rx.Instance->PAR = tmp_sr; - - /* Configure DMA Stream destination address */ - hdma_rx.Instance->M0AR = tmp_ds; -#endif - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(&hdma_rx); - - if ((huart_emul->RxXferCount == 1)||(huart->State != HAL_UART_EMUL_STATE_BUSY_TX_RX)) - { - UART_EMUL_RX_TIMER_INSTANCE->CCR2 = ((UART_EMUL_RX_TIMER_INSTANCE->CNT + (tmp_arr / 2)) % tmp_arr); - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(&TimHandle, TIM_DMA_source_Rx); - - /* Enable Timer */ - __HAL_TIM_ENABLE(&TimHandle); -} - -/** - * @brief Configures the UART Emulation peripheral - + Enable clock for all peripherals Timer, GPIO - + DMA Configuration channel, Stream, Mode,... - * @param huart: UART Emulation handle - * @retval None - */ -static void UART_Emul_SetConfig (UART_Emul_HandleTypeDef *huart) -{ - uint32_t bit_time = 0; - - /* Check the parameters */ - assert_param(IS_UART_EMUL_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_EMUL_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_EMUL_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_EMUL_MODE(huart->Init.Mode)); - assert_param(IS_UART_EMUL_MODE(huart->Init.Parity)); - - /* Init Bit Time */ - if((HAL_RCC_GetSysClockFreq()/HAL_RCC_GetPCLK2Freq()== 1) | (HAL_RCC_GetSysClockFreq()/HAL_RCC_GetPCLK2Freq()== 2)) - { - bit_time = ((uint32_t) ((HAL_RCC_GetSysClockFreq()/huart->Init.BaudRate) - 1)); - } - else - { - bit_time = ((uint32_t) (((HAL_RCC_GetPCLK2Freq()*2)/huart->Init.BaudRate) - 1)); - } - - /*##-1- Configure the Timer peripheral in Bit Delay ##############*/ - /* Initialize TIM peripheral as follow: - + Period = TimerPeriod - + Prescaler = 0 - + ClockDivision = 0 - + Counter direction = Up - */ - TimHandle.Instance = UART_EMUL_TX_TIMER_INSTANCE; - TimHandle.Init.Period = bit_time; - TimHandle.Init.Prescaler = 0; - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - HAL_TIM_Base_Init(&TimHandle); - - if (huart->Init.Mode == UART_EMUL_MODE_TX) - { - /* Configure UART Emulation in Transmission mode */ - UART_Emul_SetConfig_DMATx(); - } - else if (huart->Init.Mode == UART_EMUL_MODE_RX) - { - /* Configure UART Emulation in Reception mode */ - UART_Emul_SetConfig_DMARx(); - } - else - { - /* Configure UART Emulation in full-duplex mode */ - UART_Emul_SetConfig_DMATx(); - UART_Emul_SetConfig_DMARx(); - } -} - -/** - * @brief Configures the DMA for UART Emulation transmission. - + DMA Configuration channel, Stream, Mode, ... - * @param None - * @retval None - */ -static void UART_Emul_SetConfig_DMATx(void) -{ - /* Init Idle */ - HAL_GPIO_WritePin((huart_emul->TxPortName), (huart_emul->Init.TxPinNumber), GPIO_PIN_SET); - - /*##-1- Configure DMA For UART Emulation TX #############################*/ - /* Set the parameters to be configured */ - hdma_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; /* Transfer mode */ - hdma_tx.Init.PeriphInc = DMA_PINC_DISABLE; /* Peripheral increment mode Disable */ - hdma_tx.Init.MemInc = DMA_MINC_ENABLE; /* Memory increment mode Enable */ - hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD ; /* Peripheral data alignment : Word */ - hdma_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD ; /* memory data alignment : Word */ - hdma_tx.Init.Mode = DMA_NORMAL; /* Normal DMA mode */ - hdma_tx.Init.Priority = DMA_PRIORITY_HIGH; /* Priority level : High */ -#ifdef STM32F4xx - hdma_tx.Init.Channel = DMA_Channel_Tx; /* Channel used */ - hdma_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; /* FIFO mode disable */ - hdma_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; /* FIFO threshold level */ - hdma_tx.Init.MemBurst = DMA_MBURST_SINGLE; /* Memory Burst transfer */ - hdma_tx.Init.PeriphBurst = DMA_PBURST_SINGLE; /* Periph Burst transfer */ -#endif - - /* Set hdma_tim instance */ - hdma_tx.Instance = DMA_Stream_Tx; - hdma_tx.Parent = TimHandle.hdma[TIM_DMA_Handle_Tx]; - /* Link hdma_tim to hdma[ ] ( channel Tx or Rx) */ - __HAL_LINKDMA(&TimHandle, hdma[TIM_DMA_Handle_Tx] , hdma_tx); - - /* Initialize TIMx DMA handle */ - HAL_DMA_Init(TimHandle.hdma[TIM_DMA_Handle_Tx]); - - /*##-2- NVIC configuration for DMA transfer complete interrupt ###########*/ - HAL_NVIC_SetPriority(UART_EMUL_TX_DMA_IRQn, 3, 3); - HAL_NVIC_EnableIRQ(UART_EMUL_TX_DMA_IRQn); -} - -/** - * @brief Configures the DMA for UART Emulation reception. - + DMA Configuration channel, Stream, Mode, ... - * @param None - * @retval None - */ -static void UART_Emul_SetConfig_DMARx(void) -{ - /*##-1- Configure DMA For UART Emulation RX #############################*/ - /* Set the parameters to be configured */ - hdma_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; /* Transfer mode */ - hdma_rx.Init.PeriphInc = DMA_PINC_DISABLE; /* Peripheral increment mode Disable */ - hdma_rx.Init.MemInc = DMA_MINC_ENABLE; /* Memory increment mode Enable */ - hdma_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD ; /* Peripheral data alignment : Word */ - hdma_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD ; /* memory data alignment : Word */ - hdma_rx.Init.Mode = DMA_NORMAL; /* Normal DMA mode */ - hdma_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; /* Priority level : very High */ -#if defined(STM32F4xx) - hdma_rx.Init.Channel = DMA_Channel_Rx; /* Channel used */ - hdma_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; /* FIFO mode disable */ - hdma_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; /* FIFO threshold level */ - hdma_rx.Init.MemBurst = DMA_MBURST_SINGLE; /* Memory Burst transfer */ - hdma_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; /* Periph Burst transfer */ -#endif - /* Set hdma_tim instance */ - hdma_rx.Instance = DMA_Stream_Rx; - - /* Link hdma_tim to hdma[ ] ( channel Tx or Rx) */ - __HAL_LINKDMA(&TimHandle, hdma[TIM_DMA_Handle_Rx], hdma_rx); - - /* Initialize TIMx DMA handle */ - HAL_DMA_Init(TimHandle.hdma[TIM_DMA_Handle_Rx]); - - /*##-2- NVIC configuration for DMA transfer complete interrupt ###########*/ - HAL_NVIC_SetPriority(UART_EMUL_RX_DMA_IRQn, 0, 1); - HAL_NVIC_EnableIRQ(UART_EMUL_RX_DMA_IRQn); -} - -/** - * @brief Format Frame in Receiver mode. - * @param huart: UART Emulation handle - * @param pBuffer: pointer of receiver Buffer - * @param pFrame: pointer of Frame - * @retval None -*/ -static uint8_t UART_Emul_ReceiveFormatFrame(UART_Emul_HandleTypeDef *huart, uint32_t *pBuf, uint8_t Data) -{ - uint32_t counter = 0; - uint32_t length = 0; - uint32_t tmp = 0; - uint32_t cntparity = 0; - - if (huart->Init.Parity != UART_EMUL_PARITY_NONE) - { - /* Get Length of frame */ - length = huart->Init.WordLength -1 ; - } - else - { - /* Get Length of frame */ - length = huart->Init.WordLength; - } - - if ((pBuf[huart->Init.WordLength+1]&huart->Init.RxPinNumber) != huart->Init.RxPinNumber) - { - /* UART Emulation frame error occurred */ - __HAL_UART_EMUL_SET_FLAG(huart_emul, UART_EMUL_FLAG_FE); - - huart->ErrorCode |= HAL_UART_EMUL_ERROR_FE; - - /* Disable External interrupt for next Frame */ - EXTI->IMR &= ~huart_emul->Init.RxPinNumber; - - /* Handle for UART Emulation Error */ - HAL_UART_Emul_ErrorCallback(huart); - - tmp = RESET; - } - else - { - /* format data */ - for (counter = 0; counter < length; counter++) - { - if ((pBuf[counter+1]&(huart->Init.RxPinNumber)) == (huart->Init.RxPinNumber)) - { - Data = (0x01 << counter) | Data; - cntparity ++; - } - } - /* Parity Bit */ - if (huart->Init.Parity == UART_EMUL_PARITY_ODD) - { - - if (((cntparity % 2) != SET) && ((pBuf[length+1]&huart->Init.RxPinNumber) != huart->Init.RxPinNumber)) - { - /* Set flag PE */ - __HAL_UART_EMUL_SET_FLAG(huart, UART_EMUL_FLAG_PE); - - HAL_UART_Emul_ErrorCallback(huart); - } - } - if (huart->Init.Parity == UART_EMUL_PARITY_EVEN) - { - - if (((cntparity % 2) != RESET) && ((pBuf[length+1]&huart->Init.RxPinNumber) != huart->Init.RxPinNumber)) - { - /* UART Emulation parity error occurred */ - __HAL_UART_EMUL_SET_FLAG(huart, UART_EMUL_FLAG_PE); - - huart->ErrorCode |= HAL_UART_EMUL_ERROR_PE; - - HAL_UART_Emul_ErrorCallback(huart); - } - } - - /* Reset counter parity */ - cntparity = 0; - - tmp = Data; - } - - return tmp; -} - -/** - * @brief This function formats one Frame - * @param UART Emulation Handle - * @param pdata pinteur in data - * @retval None - */ -static void UART_Emul_TransmitFormatFrame(UART_Emul_HandleTypeDef *huart , uint8_t Data, uint32_t *pBuffer_Tx) -{ - uint32_t counter = 0; - uint32_t bitmask = 0; - uint32_t length = 0; - uint32_t cntparity = 0; - - length = huart->Init.WordLength; - - /* Get the Pin Number */ - bitmask = (uint32_t)huart->Init.TxPinNumber; - - /* with no parity */ - if(huart->Init.Parity == 0x00) - { - for (counter = 0; counter < length; counter++) - { - if (((Data >> counter)&BitMask) != 0) - { - pBuffer_Tx[counter+1] = bitmask; - } - else - { - pBuffer_Tx[counter+1] = (bitmask << 16); - } - } - } - /* with parity */ - else - { - for (counter = 0; counter < length-1; counter++) - { - if (((Data >> counter)&BitMask) != 0) - { - pBuffer_Tx[counter+1] = bitmask; - cntparity ++; - } - else - { - pBuffer_Tx[counter+1] = (bitmask << 16); - } - } - } - - switch (huart->Init.Parity) - { - case UART_EMUL_PARITY_ODD: - { - /* Initialize Parity Bit */ - if ((cntparity % 2) != SET) - { - pBuffer_Tx[length] = bitmask; - } - else - { - pBuffer_Tx[length] = (bitmask << 16); - } - - } - break; - case UART_EMUL_PARITY_EVEN: - { - /* Initialize Parity Bit */ - if ((cntparity % 2) != SET) - { - pBuffer_Tx[length] = (bitmask << 16); - } - else - { - pBuffer_Tx[length] = bitmask; - } - } - break; - default: - break; - } - /* Initialize Bit Start */ - pBuffer_Tx[0] = (bitmask << 16); - - if (huart->Init.StopBits == UART_EMUL_STOPBITS_1) - { - /* Initialize Bit Stop */ - pBuffer_Tx[length+1] = bitmask; - } - else - { - /* Initialize Bit Stop */ - pBuffer_Tx[length+1] = bitmask; - pBuffer_Tx[length+2] = bitmask; - } - /* Reset counter parity */ - cntparity = 0; -} - -/** - * @brief Sends an amount of Frames - * @param huart: UART Emulation handle - * @param pData: Frame to be sent - * @retval None - */ -static void UART_Emul_TransmitFrame(UART_Emul_HandleTypeDef *huart) -{ - uint32_t tmp_sr = 0; - uint32_t tmp_ds = 0; - uint32_t tmp_size = 0; - - - if ((huart_emul->TxXferCount % 2 ) != 0) - { - tmp_sr = (uint32_t)pFirstBuffer_Tx; - } - else - { - tmp_sr = (uint32_t)pSecondBuffer_Tx; - } - - tmp_ds = (uint32_t) & ((huart->TxPortName)->BSRR); - - tmp_size = __HAL_UART_EMUL_FRAME_LENGTH(huart); - -#if defined (STM32F0xx) || defined (STM32F3xx) - /* Configure DMA Stream data length */ - hdma_rx.Instance->CNDTR = tmp_size; - - /* Configure DMA Stream source address */ - hdma_rx.Instance->CPAR = tmp_sr; - - /* Configure DMA Stream destination address */ - hdma_rx.Instance->CMAR = tmp_ds; -#else - /* Configure DMA Stream data length */ - hdma_tx.Instance->NDTR = tmp_size; - - /* Configure DMA Stream destination address */ - hdma_tx.Instance->PAR = tmp_ds; - - /* Configure DMA Stream source address */ - hdma_tx.Instance->M0AR = tmp_sr; -#endif - - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(&hdma_tx, DMA_IT_TC); - - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(&hdma_tx, DMA_IT_TE); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(&hdma_tx); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(&TimHandle, TIM_DMA_source_Tx); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(&TimHandle); -} - -/** - * @brief This function is executed in case of Transfer Complete of a Frame. - * @param None - * @retval None - */ -static void UART_Emul_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - uint32_t tmpbuffer = 0; - - /* Incremente Counter of frame */ - huart_emul->TxXferCount++; - - if (huart_emul->TxXferCount <= huart_emul->TxXferSize) - { - /* Call UART Emulation Transmit frame for next Frame */ - UART_Emul_TransmitFrame(huart_emul); - - if ((huart_emul->TxXferCount % 2 ) != 0) - { - tmpbuffer = (uint32_t)pSecondBuffer_Tx; - } - else - { - tmpbuffer = (uint32_t)pFirstBuffer_Tx; - } - /* Format second Data to be sent */ - UART_Emul_TransmitFormatFrame(huart_emul, *(huart_emul->pTxBuffPtr + huart_emul->TxXferCount), (uint32_t*)tmpbuffer); - } - else - { - /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(TimHandle.hdma[TIM_DMA_Handle_Tx], DMA_IT_TC); - - /* Set TC flag in the status register software */ - __HAL_UART_EMUL_SET_FLAG(huart_emul, UART_EMUL_FLAG_TC); - - /* Disable the Peripheral */ - __HAL_DMA_DISABLE(&hdma_tx); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(&TimHandle, TIM_DMA_source_Tx); - - /* De_Initialize counter frame for Tx */ - huart_emul->TxXferCount = 0; - - /* Initialize the UART Emulation state */ - huart_emul->ErrorCode = HAL_UART_EMUL_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - if (huart_emul->State == HAL_UART_EMUL_STATE_BUSY_TX_RX) - { - huart_emul->State = HAL_UART_EMUL_STATE_BUSY_RX; - } - else - { - huart_emul->State = HAL_UART_EMUL_STATE_READY; - } - /* Handle for UART Emulation Transfer Complete */ - HAL_UART_Emul_TxCpltCallback(huart_emul); - } -} - -/** - * @brief This function is executed in case of error of Transfer occurrence. - * @param hdma : DMA Handle - * @retval None - */ -static void UART_Emul_DMAError(DMA_HandleTypeDef *hdma) -{ - /* UART Emulation frame error occurred */ - __HAL_UART_EMUL_SET_FLAG(huart_emul, UART_EMUL_FLAG_FE); - - huart_emul->ErrorCode |= HAL_UART_EMUL_ERROR_FE; - - HAL_UART_Emul_ErrorCallback(huart_emul); -} - -/** - * @brief Initializes the UART Emulation Transfer Complete. - * @param huart: UART Emulation Handle - * @retval None - */ -__weak void HAL_UART_Emul_TxCpltCallback(UART_Emul_HandleTypeDef *huart) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_UART_Emul_TransferComplete could be implemented in the user file - */ -} - -/** - * @brief UART Emulation error callbacks. - * @param huart: UART Emulation handle - * @retval None - */ -__weak void HAL_UART_Emul_ErrorCallback(UART_Emul_HandleTypeDef *huart) -{ - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -//#endif /* HAL_UART_EMUL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -#endif //TIM1_BASE && UART_EMUL_RX && UART_EMUL_TX -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/arduino/stm32/hal_uart_emul.h b/cores/arduino/stm32/hal_uart_emul.h deleted file mode 100644 index 8de76b5b56..0000000000 --- a/cores/arduino/stm32/hal_uart_emul.h +++ /dev/null @@ -1,417 +0,0 @@ -/** - ****************************************************************************** - * @file hal_uart_emul.h - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 - * @brief Adaptation from stm32f4xx_hal_uart_emul.h - * Header file of UART Emulation HAL module. - ****************************************************************************** - * @attention - * - *

          © COPYRIGHT(c) 2015 STMicroelectronics

          - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HAL_UART_EMUL_H -#define __HAL_UART_EMUL_H - -#if defined(TIM1_BASE) && defined(UART_EMUL_RX) && defined(UART_EMUL_TX) -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART_EMUL_HAL_Driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief UART Emulation Init Structure definition - */ -typedef struct -{ - uint8_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Emul_Mode */ - - uint32_t BaudRate; /*!< This member configures the UART communication baud rate.*/ - - - uint8_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UART_Emul_Word_Length */ - - uint8_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Emul_Stop_Bits */ - - - uint8_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Emul_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data*/ - - uint16_t RxPinNumber; /*!< Specifies the number of Receiver Pin. - This parameter can be a value of @ref GPIO_pins_define */ - - uint16_t TxPinNumber; /*!< Specifies the number of Transmitter Pin. - his parameter can be a value of @ref GPIO_pins_define */ -}UART_Emul_InitTypeDef; - -/** - * @brief HAL UART Emulation State structures definition - */ -typedef enum -{ - HAL_UART_EMUL_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_UART_EMUL_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_EMUL_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_UART_EMUL_STATE_BUSY_TX = 0x04, /*!< Data Transmission process is ongoing */ - HAL_UART_EMUL_STATE_BUSY_RX = 0x08, /*!< Data Reception process is ongoing */ - HAL_UART_EMUL_STATE_BUSY_TX_RX = 0x10, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_EMUL_STATE_ERROR = 0x20 /*!< Error */ - -}HAL_UART_Emul_StateTypeDef; - -/** - * @brief HAL UART Emulation Error Code structure definition - */ -typedef enum -{ - HAL_UART_EMUL_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_EMUL_ERROR_FE = 0x01, /*!< frame error */ - HAL_UART_EMUL_ERROR_RE = 0x02, /*!< receiver error */ - HAL_UART_EMUL_ERROR_PE = 0x04 /*!< transfer error */ -}HAL_UART_Emul_ErrorTypeDef; - -/** - * @brief Universal Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint8_t SR; /*!< UART Emulation Status register software */ - -} UART_Emul_TypeDef; - -/** - * @brief UART Emulation handle Structure definition - */ -typedef struct -{ - UART_Emul_TypeDef Instance; /* Instance for UART Emulation register */ - - UART_Emul_InitTypeDef Init; /* UART Emulation communication parameters */ - - uint8_t *pTxBuffPtr; /* Pointer to UART Emulation Tx transfer Buffer */ - - uint16_t TxXferSize; /* UART Emulation Tx Transfer size */ - - uint16_t TxXferCount; /* UART Emulation Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /* Pointer to UART Emulation Rx transfer Buffer */ - - uint16_t RxXferSize; /* UART Emulation Rx Transfer size */ - - uint16_t RxXferCount; /* UART Emulation Rx Transfer Counter */ - - GPIO_TypeDef *RxPortName; /* UART Emulation Rx port name */ - - GPIO_TypeDef *TxPortName; /* UART Emulation Tx port name */ - - __IO HAL_UART_Emul_StateTypeDef State; /* UART Emulation communication state */ - - __IO HAL_UART_Emul_ErrorTypeDef ErrorCode; /* UART Emulation Error code */ - -}UART_Emul_HandleTypeDef; - - - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Emulation_Exported_Constants - * @{ - */ - -/** @defgroup UART_Emul_Word_Length - * @{ - */ - -#define UART_EMUL_WORDLENGTH_5B ((uint8_t)0x05) -#define UART_EMUL_WORDLENGTH_6B ((uint8_t)0x06) -#define UART_EMUL_WORDLENGTH_7B ((uint8_t)0x07) -#define UART_EMUL_WORDLENGTH_8B ((uint8_t)0x08) -#define UART_EMUL_WORDLENGTH_9B ((uint8_t)0x09) -#define IS_UART_EMUL_WORD_LENGTH(LENGTH) (((LENGTH) == UART_EMUL_WORDLENGTH_5B)||\ - ((LENGTH) == UART_EMUL_WORDLENGTH_6B)||\ - ((LENGTH) == UART_EMUL_WORDLENGTH_7B)||\ - ((LENGTH) == UART_EMUL_WORDLENGTH_8B)||\ - ((LENGTH) == UART_EMUL_WORDLENGTH_9B)) -/** - * @} - */ - -/** @defgroup UART_Emul_Stop_Bits - * @{ - */ -#define UART_EMUL_STOPBITS_1 ((uint8_t)0x01) -#define UART_EMUL_STOPBITS_2 ((uint8_t)0x02) -#define IS_UART_EMUL_STOPBITS(STOPBITS) (((STOPBITS) == UART_EMUL_STOPBITS_1)||\ - ((STOPBITS) == UART_EMUL_STOPBITS_2)) - -/** - * @} - */ - -/** @defgroup UART_Emul_Parity - * @{ - */ -#define UART_EMUL_PARITY_NONE ((uint8_t)0x00) -#define UART_EMUL_PARITY_EVEN ((uint8_t)0x01) -#define UART_EMUL_PARITY_ODD ((uint8_t)0x02) -#define IS_UART_EMUL_PARITY(PARITY) (((PARITY) == UART_EMUL_PARITY_NONE) || \ - ((PARITY) == UART_EMUL_PARITY_EVEN) || \ - ((PARITY) == UART_EMUL_PARITY_ODD)) -/** - * @} - */ - -/** @defgroup UART_Emul_Mode - * @{ - */ -#define UART_EMUL_MODE_RX ((uint8_t)0x01) -#define UART_EMUL_MODE_TX ((uint8_t)0x02) -#define UART_EMUL_MODE_TX_RX ((uint8_t)0x03) -#define IS_UART_EMUL_MODE(MODE) (((MODE) == UART_EMUL_MODE_RX) || \ - ((MODE) == UART_EMUL_MODE_TX ) || \ - ((MODE) == UART_EMUL_MODE_TX_RX )) -/** - * @} - */ - -/** @defgroup UART_Emul_Flags - * Elements values convention: 0xXX - * - 0xXX : Flag mask in the SR register software - * @{ - */ -#define UART_EMUL_FLAG_RC ((uint8_t)0x01) -#define UART_EMUL_FLAG_TC ((uint8_t)0x02) -#define UART_EMUL_FLAG_FE ((uint8_t)0x04) -#define UART_EMUL_FLAG_PE ((uint8_t)0x08) - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup Baudrate_Constants - * @{ - */ - -/** - * - */ -#define BAUDRATE_4800 ((uint32_t)0x12C0) /* Baudrate Selection 4800 */ -#define BAUDRATE_9600 ((uint32_t)0x2580) /* Baudrate Selection 9600 */ -#define BAUDRATE_14400 ((uint32_t)0x3840) /* Baudrate Selection 14400 */ -#define BAUDRATE_19200 ((uint32_t)0x4b00) /* Baudrate Selection 19200 */ -#define BAUDRATE_38400 ((uint32_t)0x9600) /* Baudrate Selection 38400 */ -#define BAUDRATE_57600 ((uint32_t)0xE100) /* Baudrate Selection 57600 */ -#define BAUDRATE_115200 ((uint32_t)0x1C200) /* Baudrate Selection 115200 */ -#define IS_UART_EMUL_BAUDRATE(BaudRate) (((BaudRate) == BAUDRATE_4800 ) || \ - ((BaudRate) == BAUDRATE_9600 ) || \ - ((BaudRate) == BAUDRATE_14400 ) || \ - ((BaudRate) == BAUDRATE_19200 ) || \ - ((BaudRate) == BAUDRATE_38400 ) || \ - ((BaudRate) == BAUDRATE_57600 ) || \ - ((BaudRate) == BAUDRATE_115200)) -/** - * @} - */ - - /** @defgroup UART Emulation constant - * @{ - */ - -#define FIRST_BYTE ((uint8_t)0x01) -#define BitMask ((uint8_t)0x01) -#define RX_BUFFER_SIZE ((uint8_t)0x0C) -#define TX_BUFFER_SIZE ((uint8_t)0x0C) - -/* Definition Handler for UART Emulation receive mode */ - -#ifdef STM32F0xx -#define UART_EMUL_TX_DMA_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler -#define UART_EMUL_RX_DMA_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler - -#define UART_EMUL_TX_DMA_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn -#define UART_EMUL_RX_DMA_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn -#elif defined(STM32F3xx) -#define UART_EMUL_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler -#define UART_EMUL_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler - -#define UART_EMUL_TX_DMA_IRQn DMA2_Channel1_IRQn -#define UART_EMUL_RX_DMA_IRQn DMA2_Channel3_IRQn -#elif defined(STM32F4xx) -#define UART_EMUL_TX_DMA_IRQHandler DMA2_Stream1_IRQHandler -#define UART_EMUL_RX_DMA_IRQHandler DMA2_Stream2_IRQHandler - -#define UART_EMUL_TX_DMA_IRQn DMA2_Stream1_IRQn -#define UART_EMUL_RX_DMA_IRQn DMA2_Stream2_IRQn -#endif - -/* Defenition of UART Emulation timer */ -#define UART_EMUL_TX_TIMER_INSTANCE TIM1 -#define UART_EMUL_RX_TIMER_INSTANCE TIM1 - -#define TIM_DMA_Handle_Tx TIM_DMA_ID_CC1 -#define TIM_DMA_Handle_Rx TIM_DMA_ID_CC2 - -#define TIM_Channel_Tx TIM_CHANNEL_1 -#define TIM_Channel_Rx TIM_CHANNEL_2 - -#define TIM_DMA_source_Tx TIM_DMA_CC1 -#define TIM_DMA_source_Rx TIM_DMA_CC2 - -#ifdef STM32F4xx -#define DMA_Channel_Tx DMA_CHANNEL_6 -#define DMA_Channel_Rx DMA_CHANNEL_6 -#endif - -#ifdef DMA2_Stream1 -#define DMA_Stream_Tx DMA2_Stream1 -#define DMA_Stream_Rx DMA2_Stream2 -#else -#define DMA_Stream_Tx DMA2_Channel1 -#define DMA_Stream_Rx DMA2_Channel3 -#endif -/* Exported macro ------------------------------------------------------------*/ - -/** @brief Checks whether the specified UART Emulation flag is set or not. - * @param __HANDLE__: specifies the UART Emulation Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg UART_EMUL_FLAG_RC: Receiver Complete flag - * @arg UART_EMUL_FLAG_TC: Transmission Complete flag - * @arg UART_EMUL_FLAG_FE: Framing Error flag - * @arg UART_EMUL_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_EMUL_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance.SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified UART Emulation flag. - * @param __HANDLE__: specifies the UART Emulation Handle. - * - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg UART_EMUL_FLAG_RC : Receiver Complet. - * @arg UART_EMUL_FLAG_TC : Transmitter Complet. - * @arg UART_EMUL_FLAG_FE : Frame Error. - * @arg UART_EMUL_FLAG_PE : Parity Error. - * - * @retval None - */ -#define __HAL_UART_EMUL_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance.SR &= ~(__FLAG__)) - -/** @brief Set the specified UART Emulation flag. - * @param __HANDLE__: specifies the UART Emulation Handle. - * - * @param __FLAG__: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg UART_EMUL_FLAG_RC : Receiver Complete. - * @arg UART_EMUL_FLAG_TC : Transmitter Complete. - * @arg UART_EMUL_FLAG_FE : Frame Error. - * @arg UART_EMUL_FLAG_PE : Parity Error. - * - * @retval None - */ -#define __HAL_UART_EMUL_SET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance.SR |= (__FLAG__)) - -/** @brief Determinate the length for the frame . - * @param __HANDLE__: specifies the UART Emulation Handle. - * @param None - * @retval None - */ -#define __HAL_UART_EMUL_FRAME_LENGTH(__HANDLE__) (uint16_t)((__HANDLE__)->Init.WordLength + (__HANDLE__)->Init.StopBits + 1) - -/** @brief Enable the clock for UART Emulation. - * clock in the peripherique used in this driver Timer and DMA - * @param None - * @retval None - */ -#define __UART_EMUL_CLK_ENABLE() __HAL_RCC_TIM1_CLK_ENABLE();\ - __HAL_RCC_DMA2_CLK_ENABLE(); - -/** @brief Disable the clock for UART Emulation. - * clock in the peripherique used in this emulation Timer and DMA - * @param None - * @retval None - */ -#define __UART_EMUL_CLK_DISABLE() __HAL_RCC_TIM1_CLK_DISABLE();\ - __HAL_RCC_DMA2_CLK_DISABLE(); - - -/* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_UART_Emul_Init(UART_Emul_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Emul_DeInit(UART_Emul_HandleTypeDef *huart); -void HAL_UART_Emul_MspInit(UART_Emul_HandleTypeDef *huart); -void HAL_UART_Emul_MspDeInit(UART_Emul_HandleTypeDef *huart); - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_UART_Emul_Transmit_DMA(UART_Emul_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Emul_Receive_DMA(UART_Emul_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -void HAL_UART_Emul_IRQHandler(UART_Emul_HandleTypeDef *huart); -void HAL_UART_Emul_RxCpltCallback(UART_Emul_HandleTypeDef *huart); -void HAL_UART_Emul_TxCpltCallback(UART_Emul_HandleTypeDef *huart); -void HAL_UART_Emul_ErrorCallback(UART_Emul_HandleTypeDef *huart); -void UART_EMUL_EXTI_RX(void); - -/* Peripheral State functions **************************************************/ -HAL_UART_Emul_StateTypeDef HAL_UART_Emul_GetState(UART_Emul_HandleTypeDef *huart); -uint32_t HAL_UART_Emul_GetError(UART_Emul_HandleTypeDef *huart); -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif -#endif //TIM1_BASE -#endif /* __HAL_UART_EMUL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/arduino/stm32/uart_emul.c b/cores/arduino/stm32/uart_emul.c deleted file mode 100644 index 79b77350a0..0000000000 --- a/cores/arduino/stm32/uart_emul.c +++ /dev/null @@ -1,424 +0,0 @@ -/** - ****************************************************************************** - * @file uart_emul.c - * @author WI6LABS - * @version V1.0.0 - * @date 25-April-2017 - * @brief provide the UART Emulation interface - * - ****************************************************************************** - * @attention - * - *

          © COPYRIGHT(c) 2017 STMicroelectronics

          - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ -#include "debug.h" -#include "uart_emul.h" -#include "digital_io.h" -#include "interrupt.h" -#include "Arduino.h" - -#if defined(TIM1_BASE) && defined(UART_EMUL_RX) && defined(UART_EMUL_TX) -#ifdef __cplusplus - extern "C" { -#endif - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/// @brief number of received characters -#define EMUL_TIMER_PERIOD 100 - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/// @brief defines the global attributes of the UART -typedef struct { - UART_Emul_TypeDef uartEmul_typedef; - PinName pin_tx; - PinName pin_rx; - void (*uart_rx_irqHandle)(void); - uint8_t rxpData[UART_RCV_SIZE]; - volatile uint32_t data_available; - volatile uint8_t begin; - volatile uint8_t end; - uart_option_e uart_option; - stimer_t *_timer; -}uart_emul_conf_t; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ -/// @brief uart caracteristics -static UART_Emul_HandleTypeDef g_UartEmulHandle[NB_UART_EMUL_MANAGED]; - -static uart_emul_conf_t g_uartEmul_config[NB_UART_EMUL_MANAGED] = { - { - .uartEmul_typedef = {UART1_EMUL_E}, - .pin_tx = UART_EMUL_TX, .pin_rx = UART_EMUL_RX, - .uart_rx_irqHandle = NULL, - .data_available = 0, - .begin = 0, - .end = 0, - .uart_option = EMULATED_UART_E, - ._timer = NULL - } -}; - -//@brief just a simple buffer for the uart reception -uint8_t g_rx_data[1]; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ -static void uart_emul_timer_irq(stimer_t *obj) {UNUSED(obj); g_uartEmul_config[UART1_EMUL_E].uart_rx_irqHandle();} - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/******************************* EMULATED UART ********************************/ -/** - * @brief Initializes the UART Emulation MSP. - * @param huart: UART Emulation Handle - * @retval None - */ -void HAL_UART_Emul_MspInit(UART_Emul_HandleTypeDef *huart) -{ - GPIO_InitTypeDef GPIO_InitStruct; - GPIO_TypeDef *port_rx; - GPIO_TypeDef *port_tx; - UNUSED(huart); - - // Enable GPIO clock - port_rx = set_GPIO_Port_Clock(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_rx)); - port_tx = set_GPIO_Port_Clock(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_tx)); - - // Enable GPIO TX/RX clock - __UART_EMUL_CLK_ENABLE(); - - // Enable GPIO TX/RX clock - GPIO_InitStruct.Pin = STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_tx); - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - - // UART TX GPIO pin configuration - HAL_GPIO_Init(port_tx, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_rx); - GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - - // UART RX GPIO pin configuration - HAL_GPIO_Init(port_rx, &GPIO_InitStruct); - stm32_interrupt_enable(port_rx, STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_rx), - UART_EMUL_EXTI_RX, GPIO_MODE_IT_FALLING); - /*HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);*/ -} - -/** - * @brief UART Emulation MSP DeInit. - * @param huart: UART Emulation handle - * @retval None - */ -void HAL_UART_Emul_MspDeInit(UART_Emul_HandleTypeDef *huart) -{ - GPIO_TypeDef *port_rx = get_GPIO_Port(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_rx)); - GPIO_TypeDef *port_tx = get_GPIO_Port(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_tx)); - UNUSED(huart); - - __UART_EMUL_CLK_DISABLE(); - - HAL_GPIO_DeInit(port_tx, STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_tx)); - HAL_GPIO_DeInit(port_rx, STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_rx)); - - stm32_interrupt_disable(port_rx, STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_rx)); -} - -/** - * @brief Function called to initialize the emulated uart interface - * @param serial_id : one of the defined serial interface - * @param baudRate : baudrate to apply to the uart : 4800 or 9600 //TODO bug if baud rate > 9600 - * @retval None - */ -void uart_emul_init(uart_emul_id_e uart_id, uint32_t baudRate) -{ - GPIO_TypeDef *port_tx = get_GPIO_Port(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_tx)); - if(uart_id>=NB_UART_EMUL_MANAGED) { - return; - } - - g_UartEmulHandle[uart_id].Init.Mode = UART_EMUL_MODE_TX_RX; - g_UartEmulHandle[uart_id].Init.BaudRate = baudRate; - g_UartEmulHandle[uart_id].Init.WordLength = UART_EMUL_WORDLENGTH_8B; - g_UartEmulHandle[uart_id].Init.StopBits = UART_EMUL_STOPBITS_1; - g_UartEmulHandle[uart_id].Init.Parity = UART_EMUL_PARITY_NONE; - g_UartEmulHandle[uart_id].Init.RxPinNumber = STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_rx); - g_UartEmulHandle[uart_id].Init.TxPinNumber = STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_tx); - g_UartEmulHandle[uart_id].RxPortName = get_GPIO_Port(STM_PORT(g_uartEmul_config[UART1_EMUL_E].pin_rx)); - g_UartEmulHandle[uart_id].TxPortName = port_tx; - - if(HAL_UART_Emul_Init(&g_UartEmulHandle[uart_id])!= HAL_OK) { - return; - } - - if (HAL_UART_Emul_Receive_DMA(&g_UartEmulHandle[uart_id], g_rx_data, 1) != HAL_OK) { - return; - } - - uart_emul_flush(uart_id); - - HAL_GPIO_WritePin(port_tx, STM_GPIO_PIN(g_uartEmul_config[UART1_EMUL_E].pin_tx), GPIO_PIN_SET); -} - -/** - * @brief Function called to deinitialize the emulated uart interface - * @param serial_id : one of the defined serial interface - * @retval None - */ -void uart_emul_deinit(uart_emul_id_e uart_id) -{ - if(uart_id>=NB_UART_EMUL_MANAGED) { - return; - } - - HAL_UART_Emul_DeInit(&g_UartEmulHandle[uart_id]); -} - -/** - * @brief Function returns the amount of data available - * @param serial_id : one of the defined serial interface - * @retval The number of serial data available - int - */ -int uart_emul_available(uart_emul_id_e uart_id) -{ - if(uart_id>=NB_UART_EMUL_MANAGED) { - return 0; - } - - return g_uartEmul_config[uart_id].data_available; -} - -/** - * @brief Return the first element of the rx buffer - * @param serial_id : one of the defined serial interface - * @retval The first byte of incoming serial data available (or -1 if no data is available) - int - */ -int8_t uart_emul_read(uart_emul_id_e uart_id) -{ - int8_t data = -1; - - if(uart_id>=NB_UART_EMUL_MANAGED) { - return data; - } - - if(g_uartEmul_config[uart_id].data_available > 0) { - - data = g_uartEmul_config[uart_id].rxpData[g_uartEmul_config[uart_id].begin++]; - - if(g_uartEmul_config[uart_id].begin >= UART_RCV_SIZE) { - g_uartEmul_config[uart_id].begin = 0; - } - - g_uartEmul_config[uart_id].data_available--; - } - - return data; -} - -/** - * @brief write the data on the uart - * @param serial_id : one of the defined serial interface - * @param data : byte to write - * @retval The number of bytes written - */ -size_t uart_emul_write(uart_emul_id_e uart_id, uint8_t data) -{ - if(uart_id>=NB_UART_EMUL_MANAGED) { - return 0; - } - - while(HAL_UART_Emul_Transmit_DMA(&g_UartEmulHandle[uart_id], &data, 1) != HAL_OK); - return 1; -} - -/** - * @brief Return the first element of the rx buffer without removing it from - * the buffer - * @param serial_id : one of the defined serial interface - * @retval The first byte of incoming serial data available (or -1 if no data is available) - int - */ -int8_t uart_emul_peek(uart_emul_id_e uart_id) -{ - int8_t data = -1; - - if(uart_id>=NB_UART_EMUL_MANAGED) { - return data; - } - - if(g_uartEmul_config[uart_id].data_available > 0) { - data = g_uartEmul_config[uart_id].rxpData[g_uartEmul_config[uart_id].begin]; - } - - return data; -} - -/** - * @brief Flush the content of the RX buffer - * @param serial_id : one of the defined serial interface - * @retval None - */ -void uart_emul_flush(uart_emul_id_e uart_id) -{ - if(uart_id>=NB_UART_EMUL_MANAGED) { - return; - } - - g_uartEmul_config[uart_id].data_available = 0; - g_uartEmul_config[uart_id].end = 0; - g_uartEmul_config[uart_id].begin = 0; -} - -/** - * @brief Read receive byte from uart - * @param UartHandle : pointer on the uart reference - * @param byte : byte to read - * @retval None - */ -static void uart_emul_getc(uart_emul_id_e uart_id, uint8_t byte) -{ - if((uart_id >= NB_UART_EMUL_MANAGED) || - (g_uartEmul_config[uart_id].data_available >= UART_RCV_SIZE)) { - return; - } - - g_uartEmul_config[uart_id].rxpData[g_uartEmul_config[uart_id].end++] = byte; - if(g_uartEmul_config[uart_id].end >= UART_RCV_SIZE) { - g_uartEmul_config[uart_id].end = 0; - } - g_uartEmul_config[uart_id].data_available++; -} - -/** - * @brief - * @param irq : pointer to function to call - * @retval None - */ -void uart_emul_attached_handler(stimer_t *obj, void (*irqHandle)(void)) -{ - obj->timer = TIMER_UART_EMULATED; - TimerHandleInit(obj, EMUL_TIMER_PERIOD - 1, (uint16_t)(HAL_RCC_GetHCLKFreq() / 1000) - 1); //50ms - g_uartEmul_config[UART1_EMUL_E].uart_rx_irqHandle = irqHandle; - g_uartEmul_config[UART1_EMUL_E]._timer = obj; - attachIntHandle(obj, uart_emul_timer_irq); -} - -/** - * @brief Initializes the UART Emulation Transfer Complete. - * @param huart: UART Emulation Handle - * @retval None - */ -void HAL_UART_Emul_RxCpltCallback(UART_Emul_HandleTypeDef *huart) -{ - uart_emul_getc(UART1_EMUL_E, *huart->pRxBuffPtr); - HAL_UART_Emul_Receive_DMA(&g_UartEmulHandle[UART1_EMUL_E], g_rx_data, 1); - - if(g_uartEmul_config[UART1_EMUL_E].uart_rx_irqHandle != NULL) { - if(uart_emul_available(UART1_EMUL_E) < (UART_RCV_SIZE / 2)) { - setTimerCounter((stimer_t *)g_uartEmul_config[UART1_EMUL_E]._timer->timer, 0); - } - else if(uart_emul_available(UART1_EMUL_E) < (UART_RCV_SIZE/4*3)) { - setTimerCounter((stimer_t *)g_uartEmul_config[UART1_EMUL_E]._timer->timer, EMUL_TIMER_PERIOD - 1); - } - else { - g_uartEmul_config[UART1_EMUL_E].uart_rx_irqHandle(); - } - } -} - -/*void HAL_UART_Emul_ErrorCallback(UART_Emul_HandleTypeDef *huart) -{ - debug("UART EMUL RX ERROR\n"); -}*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif //TIM1_BASE && UART_EMUL_RX && UART_EMUL_TX -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cores/arduino/stm32/uart_emul.h b/cores/arduino/stm32/uart_emul.h deleted file mode 100644 index 0ea5582d98..0000000000 --- a/cores/arduino/stm32/uart_emul.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - ****************************************************************************** - * @file uart_emul.h - * @author WI6LABS - * @version V1.0.0 - * @date 25-April-2017 - * @brief Header for uart emulation module - ****************************************************************************** - * @attention - * - *

          © COPYRIGHT(c) 2017 STMicroelectronics

          - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __UART_EMUL_H -#define __UART_EMUL_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32_def.h" -#include "timer.h" - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -typedef enum { - UART1_EMUL_E = 0, - NB_UART_EMUL_MANAGED -} uart_emul_id_e; - -typedef enum { - NATIVE_UART_E = 0, - EMULATED_UART_E = 1, - NB_UART_OPTION -} uart_option_e; - -/* Exported constants --------------------------------------------------------*/ -#define UART_RCV_SIZE 128 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void uart_emul_init(uart_emul_id_e uart_id, uint32_t baudRate); -void uart_emul_deinit(uart_emul_id_e uart_id); -int uart_emul_available(uart_emul_id_e uart_id); -int8_t uart_emul_read(uart_emul_id_e uart_id); -size_t uart_emul_write(uart_emul_id_e uart_id, uint8_t data); -int8_t uart_emul_peek(uart_emul_id_e uart_id); -void uart_emul_flush(uart_emul_id_e uart_id); -void uart_emul_attached_handler(stimer_t *obj, void (*irqHandle)(void)); - -#ifdef __cplusplus -} -#endif - -#endif /* __UART_EMUL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_F302R8/PeripheralPins.c b/variants/NUCLEO_F302R8/PeripheralPins.c index 6925350c5f..db2bc4f6df 100644 --- a/variants/NUCLEO_F302R8/PeripheralPins.c +++ b/variants/NUCLEO_F302R8/PeripheralPins.c @@ -99,7 +99,6 @@ const PinMap PinMap_I2C_SCL[] = { #ifdef HAL_TIM_MODULE_ENABLED // TIM2 is commented out, because it is used by us_ticker. -// TIM17 is used for TIMER_UART_EMULATED const PinMap PinMap_PWM[] = { // {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 {PA_1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N diff --git a/variants/board_template/variant.h b/variants/board_template/variant.h index 018f98077d..6a6e5e7d17 100644 --- a/variants/board_template/variant.h +++ b/variants/board_template/variant.h @@ -111,7 +111,6 @@ enum { // Timer Definitions //Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c #define TIMER_TONE TIMx -//#define TIMER_UART_EMULATED TIMx // Do not use basic timer: OC is required #define TIMER_SERVO TIMx //TODO: advanced-control timers don't work @@ -126,10 +125,6 @@ enum { // DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART //#define DEBUG_PINNAME_TX PX_n // PinName used for TX -// UART Emulation (uncomment if needed, required TIM1) -//#define UART_EMUL_RX PX_n // PinName used for RX -//#define UART_EMUL_TX PX_n // PinName used for TX - // Default pin used for 'Serial' instance (ex: ST-Link) // Mandatory for Firmata #define PIN_SERIAL_RX x From c5017df708ca3b639fe332a9e8ca83c63f25cf40 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 19 Sep 2018 14:52:30 +0200 Subject: [PATCH 059/109] Remove non standard API delayInsideIT() code should have been in the method: void GSM3SoftSerial::tunedDelay(uint16_t delay) It was introduced as an API to support built-in GSM library on Nucleo-L476RG and is not relevant for other. Fix #250 Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/clock.c | 34 ---------------------------------- cores/arduino/stm32/clock.h | 1 - 2 files changed, 35 deletions(-) diff --git a/cores/arduino/stm32/clock.c b/cores/arduino/stm32/clock.c index 0088a61143..ffe0ad79ff 100644 --- a/cores/arduino/stm32/clock.c +++ b/cores/arduino/stm32/clock.c @@ -87,40 +87,6 @@ void SysTick_Handler(void) osSystickHandler(); } -/** - * @brief Function provides us delay (required by some arduino libraries). - * Can be called inside an interrupt. - * @param None - * @retval None - */ -void delayInsideIT(uint32_t delay_us) -{ - uint32_t nb_loop; -#if defined (STM32F0xx) || defined (STM32L0xx) - nb_loop = (((HAL_RCC_GetHCLKFreq() / 1000000)/5)*delay_us)+1; /* uS (divide by 4 because each loop take about 4 cycles including nop +1 is here to avoid delay of 0 */ - __asm__ volatile( - "1: " "\n\t" - " nop " "\n\t" - " sub %0, %0, #1 " "\n\t" - " bne 1b " "\n\t" - : "=r" (nb_loop) - : "0"(nb_loop) - : "r3" - ); -#else - nb_loop = (((HAL_RCC_GetHCLKFreq() / 1000000)/4)*delay_us)+1; /* uS (divide by 4 because each loop take about 4 cycles including nop +1 is here to avoid delay of 0 */ - __asm__ volatile( - "1: " "\n\t" - " nop " "\n\t" - " subs.w %0, %0, #1 " "\n\t" - " bne 1b " "\n\t" - : "=r" (nb_loop) - : "0"(nb_loop) - : "r3" - ); -#endif -} - /** * @brief Enable the specified clock if not already set * @param source: clock source: LSE_CLOCK, LSI_CLOCK, HSI_CLOCK or HSE_CLOCK diff --git a/cores/arduino/stm32/clock.h b/cores/arduino/stm32/clock.h index 635f7abc25..57a327eb14 100644 --- a/cores/arduino/stm32/clock.h +++ b/cores/arduino/stm32/clock.h @@ -60,7 +60,6 @@ typedef enum { /* Exported functions ------------------------------------------------------- */ uint32_t GetCurrentMilli(void); uint32_t GetCurrentMicro(void); -void delayInsideIT(uint32_t delay_us); void enableClock(sourceClock_t source); #ifdef __cplusplus From e9dbcd31516cd10197565d0883e6440140f553a5 Mon Sep 17 00:00:00 2001 From: Nils Hasenbanck Date: Sat, 15 Sep 2018 09:05:08 +0200 Subject: [PATCH 060/109] [EEPROM emulation] Rework for buffered access The current EEPROM emulation didn't had any buffered access to the data on the flash. Every access to a byte would trigger a whole page read / write. For writes it would mean, that the whole page would be erased. For backward compability we will keep the current functions as they are, but will add functions to fill/flush the buffer and read from it. The buffer size is static and is one page in size. Fixes: #296 Signed-off-by: Nils Hasenbanck --- cores/arduino/stm32/stm32_eeprom.c | 64 ++++++++++++++++++------------ cores/arduino/stm32/stm32_eeprom.h | 9 ++++- 2 files changed, 46 insertions(+), 27 deletions(-) diff --git a/cores/arduino/stm32/stm32_eeprom.c b/cores/arduino/stm32/stm32_eeprom.c index 99de58b26a..4fc3725ff4 100644 --- a/cores/arduino/stm32/stm32_eeprom.c +++ b/cores/arduino/stm32/stm32_eeprom.c @@ -136,7 +136,7 @@ static inline uint32_t get_flash_end(void) { /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ -static uint8_t tmpEE[E2END] = {0}; +static uint8_t eeprom_buffer[E2END] = {0}; /** * @} @@ -145,58 +145,72 @@ static uint8_t tmpEE[E2END] = {0}; /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes * @{ */ -void get_data_from_flash(void); -void set_data_to_flash(void); /** * @} */ /** - * @brief Function read a byte from eeprom - * @param __p : address to read + * @brief Function reads a byte from emulated eeprom (flash) + * @param pos : address to read * @retval byte : data read from eeprom */ -uint8_t eeprom_read_byte(const uint16_t __p) +uint8_t eeprom_read_byte(const uint16_t pos) { - uint8_t byte = 0; + eeprom_buffer_fill(); + return eeprom_buffered_read_byte(pos); +} - get_data_from_flash(); - byte = tmpEE[__p]; +/** + * @brief Function writes a byte to emulated eeprom (flash) + * @param pos : address to write + * @param value : value to write + * @retval none + */ +void eeprom_write_byte(uint16_t pos, uint8_t value) +{ + eeprom_buffered_write_byte(pos, value); + eeprom_buffer_flush(); +} - return byte; +/** + * @brief Function reads a byte from the eeprom buffer + * @param pos : address to read + * @retval byte : data read from eeprom + */ +uint8_t eeprom_buffered_read_byte(const uint16_t pos) +{ + return eeprom_buffer[pos]; } /** - * @brief Function write a byte to eeprom - * @param __p : address to write - * @param __value : value to write + * @brief Function writes a byte to the eeprom buffer + * @param pos : address to write + * @param value : value to write * @retval none */ -void eeprom_write_byte(uint16_t __p, uint8_t __value) +void eeprom_buffered_write_byte(uint16_t pos, uint8_t value) { - tmpEE[__p] = __value; - set_data_to_flash(); + eeprom_buffer[pos] = value; } /** - * @brief The function read into the flash. + * @brief This function copies the data from flash into the buffer * @param none * @retval none */ -void get_data_from_flash(void) +void eeprom_buffer_fill(void) { - memcpy(tmpEE, (uint8_t*)(FLASH_BASE_ADDRESS), E2END); + memcpy(eeprom_buffer, (uint8_t*)(FLASH_BASE_ADDRESS), E2END); } /** - * @brief The function write into the flash. + * @brief This function writes the buffer content into the flash * @param none * @retval none */ -void set_data_to_flash(void) +void eeprom_buffer_flush(void) { - //copy in flash FLASH_EraseInitTypeDef EraseInitStruct; uint32_t offset = 0; uint32_t address = FLASH_BASE_ADDRESS; @@ -240,12 +254,12 @@ void set_data_to_flash(void) if(HAL_FLASHEx_Erase(&EraseInitStruct, &pageError) == HAL_OK) { while(address < address_end) { #if defined(STM32L0xx) || defined(STM32L1xx) - memcpy(&data, tmpEE + offset, sizeof(uint32_t)); + memcpy(&data, eeprom_buffer + offset, sizeof(uint32_t)); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data) == HAL_OK) { address += 4; offset += 4; #else - data = *((uint64_t*)(((uint8_t*)tmpEE + offset))); + data = *((uint64_t*)(((uint8_t*)eeprom_buffer + offset))); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data) == HAL_OK) { address += 8; @@ -273,7 +287,7 @@ void set_data_to_flash(void) if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) == HAL_OK) { while(address < address_end) { - memcpy(&data, tmpEE + offset, sizeof(uint32_t)); + memcpy(&data, eeprom_buffer + offset, sizeof(uint32_t)); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data) == HAL_OK) { address += 4; offset += 4; diff --git a/cores/arduino/stm32/stm32_eeprom.h b/cores/arduino/stm32/stm32_eeprom.h index 75b373fc4c..9670d85c9c 100644 --- a/cores/arduino/stm32/stm32_eeprom.h +++ b/cores/arduino/stm32/stm32_eeprom.h @@ -58,8 +58,13 @@ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ -uint8_t eeprom_read_byte(const uint16_t __p); -void eeprom_write_byte(uint16_t __p, uint8_t __value); +uint8_t eeprom_read_byte(const uint16_t pos); +void eeprom_write_byte(uint16_t pos, uint8_t value); + +void eeprom_buffer_fill(); +void eeprom_buffer_flush(); +uint8_t eeprom_buffered_read_byte(const uint16_t pos); +void eeprom_buffered_write_byte(uint16_t pos, uint8_t value); #ifdef __cplusplus } From 7f15089767ad2f871f124926d2ed4409a00886ca Mon Sep 17 00:00:00 2001 From: Nils Hasenbanck Date: Sat, 15 Sep 2018 09:11:33 +0200 Subject: [PATCH 061/109] [EEPROM emulation] Clean up code Clean up also the old references to the original author/version/date since we already refactored this code quite well. The copyright notice of course is still intact. Signed-off-by: Nils Hasenbanck --- cores/arduino/stm32/stm32_eeprom.c | 107 +++++------------------------ cores/arduino/stm32/stm32_eeprom.h | 7 +- 2 files changed, 19 insertions(+), 95 deletions(-) diff --git a/cores/arduino/stm32/stm32_eeprom.c b/cores/arduino/stm32/stm32_eeprom.c index 4fc3725ff4..1cc8c55b06 100644 --- a/cores/arduino/stm32/stm32_eeprom.c +++ b/cores/arduino/stm32/stm32_eeprom.c @@ -1,11 +1,7 @@ /** ****************************************************************************** - * @file eeprom.c - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 - * @brief provide emulated eeprom from flash - * + * @file stm32_eeprom.c + * @brief Provides emulated eeprom from flash ****************************************************************************** * @attention * @@ -35,17 +31,7 @@ * ****************************************************************************** */ -/** @addtogroup CMSIS - * @{ - */ -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ #include "stm32_eeprom.h" #include @@ -53,22 +39,8 @@ extern "C" { #endif -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ -// We use the last page of the flash to store data (to prevent code overwritten). +/* Use the last page of the flash to store data in order to prevent overwritting + program data */ #if defined (STM32F0xx) || defined (STM32F1xx) || defined(STM32L1xx) #if defined (FLASH_BANK2_END) #define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_BANK2_END + 1) - FLASH_PAGE_SIZE)) @@ -76,7 +48,7 @@ #define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_BANK1_END + 1) - FLASH_PAGE_SIZE)) #else #define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_END + 1) - FLASH_PAGE_SIZE)) -#endif // FLASH_BANK2_END +#endif /* FLASH_BANK2_END */ #elif defined (STM32F2xx) || defined (STM32F4xx) || defined (STM32F7xx) #define FLASH_BASE_ADDRESS ((uint32_t)(FLASH_END + 1) - FLASH_PAGE_SIZE) #define FLASH_DATA_SECTOR ((uint32_t)(FLASH_SECTOR_TOTAL - 1)) @@ -116,47 +88,20 @@ static inline uint32_t get_flash_end(void) { #define FLASH_BANK_NUMBER FLASH_BANK_1 #else #define FLASH_BANK_NUMBER FLASH_BANK_2 -#endif // FLASH_BANK_2 -// Flash base address +#endif /* FLASH_BANK_2 */ +/* Flash base address */ #define FLASH_PAGE_NUMBER ((uint32_t)((FLASH_SIZE / FLASH_PAGE_SIZE) - 1)) #define FLASH_BASE_ADDRESS ((uint32_t)(FLASH_BASE + (FLASH_PAGE_NUMBER * FLASH_PAGE_SIZE))) #endif -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ static uint8_t eeprom_buffer[E2END] = {0}; -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - /** * @brief Function reads a byte from emulated eeprom (flash) * @param pos : address to read * @retval byte : data read from eeprom */ -uint8_t eeprom_read_byte(const uint16_t pos) -{ +uint8_t eeprom_read_byte(const uint16_t pos) { eeprom_buffer_fill(); return eeprom_buffered_read_byte(pos); } @@ -167,8 +112,7 @@ uint8_t eeprom_read_byte(const uint16_t pos) * @param value : value to write * @retval none */ -void eeprom_write_byte(uint16_t pos, uint8_t value) -{ +void eeprom_write_byte(uint16_t pos, uint8_t value) { eeprom_buffered_write_byte(pos, value); eeprom_buffer_flush(); } @@ -178,8 +122,7 @@ void eeprom_write_byte(uint16_t pos, uint8_t value) * @param pos : address to read * @retval byte : data read from eeprom */ -uint8_t eeprom_buffered_read_byte(const uint16_t pos) -{ +uint8_t eeprom_buffered_read_byte(const uint16_t pos) { return eeprom_buffer[pos]; } @@ -189,8 +132,7 @@ uint8_t eeprom_buffered_read_byte(const uint16_t pos) * @param value : value to write * @retval none */ -void eeprom_buffered_write_byte(uint16_t pos, uint8_t value) -{ +void eeprom_buffered_write_byte(uint16_t pos, uint8_t value) { eeprom_buffer[pos] = value; } @@ -199,8 +141,7 @@ void eeprom_buffered_write_byte(uint16_t pos, uint8_t value) * @param none * @retval none */ -void eeprom_buffer_fill(void) -{ +void eeprom_buffer_fill(void) { memcpy(eeprom_buffer, (uint8_t*)(FLASH_BASE_ADDRESS), E2END); } @@ -209,8 +150,7 @@ void eeprom_buffer_fill(void) * @param none * @retval none */ -void eeprom_buffer_flush(void) -{ +void eeprom_buffer_flush(void) { FLASH_EraseInitTypeDef EraseInitStruct; uint32_t offset = 0; uint32_t address = FLASH_BASE_ADDRESS; @@ -220,12 +160,12 @@ void eeprom_buffer_flush(void) uint32_t pageError = 0; uint64_t data = 0; - // ERASING page + /* ERASING page */ EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; #ifdef STM32L4xx EraseInitStruct.Banks = FLASH_BANK_NUMBER; EraseInitStruct.Page = FLASH_PAGE_NUMBER; -#else // STM32F4xx +#else #ifdef STM32F1xx EraseInitStruct.Banks = FLASH_BANK_1; #endif @@ -276,7 +216,7 @@ void eeprom_buffer_flush(void) uint32_t SectorError = 0; uint32_t data = 0; - // ERASING page + /* ERASING page */ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; EraseInitStruct.Sector = FLASH_DATA_SECTOR; @@ -284,8 +224,7 @@ void eeprom_buffer_flush(void) HAL_FLASH_Unlock(); - if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) == HAL_OK) - { + if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) == HAL_OK) { while(address < address_end) { memcpy(&data, eeprom_buffer + offset, sizeof(uint32_t)); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data) == HAL_OK) { @@ -300,18 +239,6 @@ void eeprom_buffer_flush(void) #endif } - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ #ifdef __cplusplus } #endif diff --git a/cores/arduino/stm32/stm32_eeprom.h b/cores/arduino/stm32/stm32_eeprom.h index 9670d85c9c..fb52027978 100644 --- a/cores/arduino/stm32/stm32_eeprom.h +++ b/cores/arduino/stm32/stm32_eeprom.h @@ -1,9 +1,6 @@ /** ****************************************************************************** * @file stm32_eeprom.h - * @author WI6LABS - * @version V1.0.0 - * @date 01-August-2016 * @brief Header for eeprom module ****************************************************************************** * @attention @@ -50,8 +47,8 @@ /* Exported constants --------------------------------------------------------*/ #if defined (STM32F2xx) || defined (STM32F4xx) || defined (STM32F7xx) -//FLASH_SECTOR_SIZE -#define FLASH_PAGE_SIZE ((uint32_t)(16*1024)) //16kB page +/* FLASH_SECTOR_SIZE */ +#define FLASH_PAGE_SIZE ((uint32_t)(16*1024)) /* 16kB page */ #endif #define E2END FLASH_PAGE_SIZE From 090a366c9d008bb8f3eedc0b4635ed5493ea3d3c Mon Sep 17 00:00:00 2001 From: edogaldo Date: Wed, 19 Sep 2018 16:28:08 +0200 Subject: [PATCH 062/109] BLUE_F407VE_Mini - first commit new variant --- boards.txt | 13 + variants/BLUE_F407VE_Mini/PeripheralPins.c | 358 ++++++++++++++ variants/BLUE_F407VE_Mini/PinNamesVar.h | 25 + variants/BLUE_F407VE_Mini/ldscript.ld | 189 ++++++++ .../BLUE_F407VE_Mini/stm32f4xx_hal_conf.h | 443 ++++++++++++++++++ variants/BLUE_F407VE_Mini/variant.cpp | 181 +++++++ variants/BLUE_F407VE_Mini/variant.h | 211 +++++++++ 7 files changed, 1420 insertions(+) create mode 100644 variants/BLUE_F407VE_Mini/PeripheralPins.c create mode 100644 variants/BLUE_F407VE_Mini/PinNamesVar.h create mode 100644 variants/BLUE_F407VE_Mini/ldscript.ld create mode 100644 variants/BLUE_F407VE_Mini/stm32f4xx_hal_conf.h create mode 100644 variants/BLUE_F407VE_Mini/variant.cpp create mode 100644 variants/BLUE_F407VE_Mini/variant.h diff --git a/boards.txt b/boards.txt index 7b4b4e5f39..9fae61d635 100644 --- a/boards.txt +++ b/boards.txt @@ -522,6 +522,19 @@ GenF4.menu.pnum.BLACK_F407VE.build.product_line=STM32F407xx GenF4.menu.pnum.BLACK_F407VE.build.variant=BLACK_F407VE GenF4.menu.pnum.BLACK_F407VE.build.cmsis_lib_gcc=arm_cortexM4l_math +# Blue F407VE mini: http://wiki.stm32duino.com/index.php?title=Vcc-gnd.com_STM32F407VET6_Mini +# Support: Serial1 (USART1 on PA10, PA9) +# Default SPI: SPI (SPI1 on PB3,PB4,PB5) +GenF4.menu.pnum.BLUE_F407VE_MINI=Blue F407VE mini +GenF4.menu.pnum.BLUE_F407VE_MINI.upload.maximum_size=524288 +GenF4.menu.pnum.BLUE_F407VE_MINI.upload.maximum_data_size=131072 +GenF4.menu.pnum.BLUE_F407VE_MINI.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +GenF4.menu.pnum.BLUE_F407VE_MINI.build.board=BLUE_F407VE_MINI +GenF4.menu.pnum.BLUE_F407VE_MINI.build.series=STM32F4xx +GenF4.menu.pnum.BLUE_F407VE_MINI.build.product_line=STM32F407xx +GenF4.menu.pnum.BLUE_F407VE_MINI.build.variant=BLUE_F407VE_MINI +GenF4.menu.pnum.BLUE_F407VE_MINI.build.cmsis_lib_gcc=arm_cortexM4l_math + # Upload menu GenF4.menu.upload_method.STLink=STLink GenF4.menu.upload_method.STLink.upload.protocol=STLink diff --git a/variants/BLUE_F407VE_Mini/PeripheralPins.c b/variants/BLUE_F407VE_Mini/PeripheralPins.c new file mode 100644 index 0000000000..68e5b9684d --- /dev/null +++ b/variants/BLUE_F407VE_Mini/PeripheralPins.c @@ -0,0 +1,358 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32F407V(E-G)Tx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 -> BUT K_UP +// {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 -> BUT K_UP +// {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 -> BUT K_UP + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 +// {PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 +// {PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 +// {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 +// {PA_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 +// {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 +// {PA_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 +// {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 +// {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 +// {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 -> LED D2 +// {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 -> LED D2 +// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 -> LED D3 +// {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 -> LED D3 +// {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 +// {PB_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 +// {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 +// {PC_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PC_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 +// {PC_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 +// {PC_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 +// {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 +// {PC_2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 +// {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 +// {PC_3, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 +// {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 +// {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PC_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_6, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_7, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_CAN_MODULE_ENABLED +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NP, 0} +}; +#endif + +//*** ETHERNET *** + +#ifdef HAL_ETH_MODULE_ENABLED +const PinMap PinMap_Ethernet[] = { + {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS + {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK + {PA_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO + {PA_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL + {PA_7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV + {PB_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 + {PB_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 + {PB_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT + {PB_8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER + {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN + {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 + {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 + {PC_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC + {PC_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 + {PC_3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK + {PC_4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 + {PC_5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 + {PE_2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 + {NC, NP, 0} +}; +#endif + +//*** QUADSPI *** + +//*** No QUADSPI *** diff --git a/variants/BLUE_F407VE_Mini/PinNamesVar.h b/variants/BLUE_F407VE_Mini/PinNamesVar.h new file mode 100644 index 0000000000..b65ff1991e --- /dev/null +++ b/variants/BLUE_F407VE_Mini/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = NC, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/BLUE_F407VE_Mini/ldscript.ld b/variants/BLUE_F407VE_Mini/ldscript.ld new file mode 100644 index 0000000000..9f411268a0 --- /dev/null +++ b/variants/BLUE_F407VE_Mini/ldscript.ld @@ -0,0 +1,189 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F407VETx Device with +** 512KByte FLASH, 128KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text ALIGN(8): + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata ALIGN(4): + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/variants/BLUE_F407VE_Mini/stm32f4xx_hal_conf.h b/variants/BLUE_F407VE_Mini/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..20dc9696cc --- /dev/null +++ b/variants/BLUE_F407VE_Mini/stm32f4xx_hal_conf.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/BLUE_F407VE_Mini/variant.cpp b/variants/BLUE_F407VE_Mini/variant.cpp new file mode 100644 index 0000000000..9129d86617 --- /dev/null +++ b/variants/BLUE_F407VE_Mini/variant.cpp @@ -0,0 +1,181 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +// This array allows to wrap Arduino pin number(Dx or x) +// to STM32 PinName (PX_n) +const PinName digitalPin[] = { + // Left Side + //Ext //Int + //5V //5V + //5V //5V + //3V3 //3V3 + //3V3 //3V3 + //GND //GND + PE_2, PE_3, // D0, D1 + PE_4, PE_5, // PE_4: BUT K0, PE_5: BUT K1 + PE_6, PC_13, + PC_0, PC_1, + PC_2, PC_3, + //VREF- //VREF+ + PA_0, PA_1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA_2, PA_3, + PA_4, PA_5, + PA_6, PA_7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PC_4, PC_5, + PB_0, PB_1, // D20, D21 + PE_7, PE_8, + PE_9, PE_10, + PE_11, PE_12, + PE_13, PE_14, + PE_15, PB_10, // D30, D31 + PB_11, PB_12, + PB_13, PB_14, + // Right Side + //Int //Ext + //3V3 //3V3 + //3V3 //3V3 + //BOOT0 //BOOT1 + //GND //GND + //GND //GND + PE_1, PE_0, + PB_9, PB_8, + PB_7, PB_6, // D40, D41 + PB_5, PB_3, + PD_7, PD_6, + PD_5, PD_4, + PD_3, PD_2, + PD_1, PD_0, // D50, D51 + PC_12, PC_11, + PC_10, PA_15, + PA_12, PA_11, // PA_11: USB_DM, PA_12: USB_DP + PA_10, PA_9, + PA_8, PC_9, // D60, D61 + PC_8, PC_7, + PC_6, PD_15, + PD_14, PD_13, + PD_12, PD_11, + PD_10, PD_9, // D70, D71 + PD_8, PB_15, + PB_4, + // Analog pins + PA_0, // D75 + PA_1, + PA_2, + PA_3, + PA_4, + PA_5, // D80 + PB_0, + PB_1, + PC_0, + PC_1, + PC_2, + PC_3, + PC_4, + PC_5 +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /**Configure the Systick interrupt time + */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /**Configure the Systick + */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h new file mode 100644 index 0000000000..6b7fabb4b3 --- /dev/null +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -0,0 +1,211 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +enum { + // Left Side + //Ext //Int + //5V //5V + //5V //5V + //3V3 //3V3 + //3V3 //3V3 + //GND //GND + PE2, PE3, // D0, D1 + PE4, PE5, // PE_4: BUT K0, PE_5: BUT K1 + PE6, PC13, + PC0, PC1, + PC2, PC3, + //VREF- //VREF+ + PA0, PA1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA2, PA3, + PA4, PA5, + PA6, PA7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PC4, PC5, + PB0, PB1, // D20, D21 + PE7, PE8, + PE9, PE10, + PE11, PE12, + PE13, PE14, + PE15, PB10, // D30, D31 + PB11, PB12, + PB13, PB14, + // Right Side + //Int //Ext + //3V3 //3V3 + //3V3 //3V3 + //BOOT0 //BOOT1 + //GND //GND + //GND //GND + PE1, PE0, + PB9, PB8, + PB7, PB6, // D40, D41 + PB5, PB3, + PD7, PD6, + PD5, PD4, + PD3, PD2, + PD1, PD0, // D50, D51 + PC12, PC11, + PC10, PA15, + PA12, PA11, // PA_11: USB_DM, PA_12: USB_DP + PA10, PA9, + PA8, PC9, // D60, D61 + PC8, PC7, + PC6, PD15, + PD14, PD13, + PD12, PD11, + PD10, PD9, // D70, D71 + PD8, PB15, + PB4, + // Analog pins + PA0_A, // D75 + PA1_A, + PA2_A, + PA3_A, + PA4_A, + PA5_A, // D80 + PB0_A, + PB1_A, + PC0_A, + PC1_A, + PC2_A, + PC3_A, + PC4_A, + PC5_A, + PEND +}; + +// This must be a literal with the same value as PEND +#define NUM_DIGITAL_PINS 89 +// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 14 +#define NUM_ANALOG_FIRST 75 + +// Below ADC, DAC and PWM definitions already done in the core +// Could be redefined here if needed +// ADC resolution is 12bits +//#define ADC_RESOLUTION 12 +//#define DACC_RESOLUTION 12 + +// PWM resolution +//#define PWM_RESOLUTION 8 +//#define PWM_FREQUENCY 1000 +//#define PWM_MAX_DUTY_CYCLE 255 + +// On-board LED pin number +#define LED_D2 PA6 +#define LED_D3 PA7 +#define LED_BUILTIN LED_D2 +#define LED_GREEN LED_D2 + +// On-board user button +#define BTN_K_UP PA0 +#define BTN_K0 PE4 +#define BTN_K1 PE5 +#define USER_BTN BTN_K0 + +// Below SPI and I2C definitions already done in the core +// Could be redefined here if differs from the default one +// SPI Definitions +#define PIN_SPI_SS PB7 // NRF24 connector +#define PIN_SPI_SS1 PB0 // W25Q16 (on board flash) +#define PIN_SPI_MOSI PB5 // NRF24 connector & W25Q16 (on board flash) +#define PIN_SPI_MISO PB4 // NRF24 connector & W25Q16 (on board flash) +#define PIN_SPI_SCK PB3 // NRF24 connector & W25Q16 (on board flash) + +// I2C Definitions +#define PIN_WIRE_SDA PB9 +#define PIN_WIRE_SCL PB8 + +// Timer Definitions +//Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c +#define TIMER_TONE TIM6 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work + +// UART Definitions +// Define here Serial instance number to map on Serial generic name +#define SERIAL_UART_INSTANCE 1 //ex: 2 for Serial2 (USART2) +// DEBUG_UART could be redefined to print on another instance than 'Serial' +//#define DEBUG_UART ((USART_TypeDef *) U(S)ARTX) // ex: USART3 +// DEBUG_UART baudrate, default: 9600 if not defined +//#define DEBUG_UART_BAUDRATE x +// DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART +//#define DEBUG_PINNAME_TX PX_n // PinName used for TX + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#define PIN_SERIAL_RX PA10 +#define PIN_SERIAL_TX PA9 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial1 +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From 92a4362c0ccbc46bf576c2cd642f0b7af84f7fd7 Mon Sep 17 00:00:00 2001 From: edogaldo Date: Wed, 19 Sep 2018 16:47:06 +0200 Subject: [PATCH 063/109] BLUE_F407VE_Mini - 2nd commit --- variants/BLUE_F407VE_Mini/PeripheralPins.c | 24 +++++++++++----------- variants/BLUE_F407VE_Mini/variant.cpp | 8 ++++---- variants/BLUE_F407VE_Mini/variant.h | 18 ++++++---------- 3 files changed, 22 insertions(+), 28 deletions(-) diff --git a/variants/BLUE_F407VE_Mini/PeripheralPins.c b/variants/BLUE_F407VE_Mini/PeripheralPins.c index 68e5b9684d..8a184e98b6 100644 --- a/variants/BLUE_F407VE_Mini/PeripheralPins.c +++ b/variants/BLUE_F407VE_Mini/PeripheralPins.c @@ -42,9 +42,9 @@ #ifdef HAL_ADC_MODULE_ENABLED const PinMap PinMap_ADC[] = { - {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 -> BUT K_UP -// {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 -> BUT K_UP -// {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 -> BUT K_UP + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 +// {PA_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 +// {PA_0, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // {PA_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // {PA_1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 @@ -58,10 +58,10 @@ const PinMap PinMap_ADC[] = { // {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 -// {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 -> LED D2 -// {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 -> LED D2 -// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 -> LED D3 -// {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 -> LED D3 +// {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 +// {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 +// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 +// {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 {PB_0, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 @@ -101,7 +101,7 @@ const PinMap PinMap_DAC[] = { #ifdef HAL_I2C_MODULE_ENABLED const PinMap PinMap_I2C_SDA[] = { {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // LED {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, {NC, NP, 0} @@ -158,8 +158,8 @@ const PinMap PinMap_PWM[] = { {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - LED + {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - LED {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N @@ -295,7 +295,7 @@ const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // LED {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {NC, NP, 0} @@ -319,7 +319,7 @@ const PinMap PinMap_CAN_RD[] = { const PinMap PinMap_CAN_TD[] = { {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_6, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // LED {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NP, 0} diff --git a/variants/BLUE_F407VE_Mini/variant.cpp b/variants/BLUE_F407VE_Mini/variant.cpp index 9129d86617..a19ceeb6c8 100644 --- a/variants/BLUE_F407VE_Mini/variant.cpp +++ b/variants/BLUE_F407VE_Mini/variant.cpp @@ -46,15 +46,15 @@ const PinName digitalPin[] = { //3V3 //3V3 //GND //GND PE_2, PE_3, // D0, D1 - PE_4, PE_5, // PE_4: BUT K0, PE_5: BUT K1 + PE_4, PE_5, PE_6, PC_13, PC_0, PC_1, PC_2, PC_3, //VREF- //VREF+ - PA_0, PA_1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA_0, PA_1, // D10, D11 PA_2, PA_3, PA_4, PA_5, - PA_6, PA_7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PA_6, PA_7, PC_4, PC_5, PB_0, PB_1, // D20, D21 PE_7, PE_8, @@ -72,7 +72,7 @@ const PinName digitalPin[] = { //GND //GND //GND //GND PE_1, PE_0, - PB_9, PB_8, + PB_9, PB_8, // PB_9: LED (active LOW) PB_7, PB_6, // D40, D41 PB_5, PB_3, PD_7, PD_6, diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h index 6b7fabb4b3..139f20d0a7 100644 --- a/variants/BLUE_F407VE_Mini/variant.h +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -54,15 +54,15 @@ enum { //3V3 //3V3 //GND //GND PE2, PE3, // D0, D1 - PE4, PE5, // PE_4: BUT K0, PE_5: BUT K1 + PE4, PE5, PE6, PC13, PC0, PC1, PC2, PC3, //VREF- //VREF+ - PA0, PA1, // D10, D11 PA_0(WK_UP): BUT K_UP) + PA0, PA1, // D10, D11 PA2, PA3, PA4, PA5, - PA6, PA7, // PA_6: LED D2, PA_7: LED D3 (active LOW) + PA6, PA7, PC4, PC5, PB0, PB1, // D20, D21 PE7, PE8, @@ -80,7 +80,7 @@ enum { //GND //GND //GND //GND PE1, PE0, - PB9, PB8, + PB9, PB8, // PB_9: LED (active LOW) PB7, PB6, // D40, D41 PB5, PB3, PD7, PD6, @@ -135,16 +135,10 @@ enum { //#define PWM_MAX_DUTY_CYCLE 255 // On-board LED pin number -#define LED_D2 PA6 -#define LED_D3 PA7 -#define LED_BUILTIN LED_D2 -#define LED_GREEN LED_D2 +#define LED_BUILTIN PB9 // On-board user button -#define BTN_K_UP PA0 -#define BTN_K0 PE4 -#define BTN_K1 PE5 -#define USER_BTN BTN_K0 +//#define BTN_K_UP PA0 - no user button // Below SPI and I2C definitions already done in the core // Could be redefined here if differs from the default one From 9c100059de46aa5cb412e7cc74731e9b4d9b6c20 Mon Sep 17 00:00:00 2001 From: edogaldo Date: Wed, 19 Sep 2018 19:27:04 +0200 Subject: [PATCH 064/109] BLUE_F407VE_Mini - 3rd commit --- variants/BLUE_F407VE_Mini/variant.cpp | 153 ++++++++++++++--------- variants/BLUE_F407VE_Mini/variant.h | 170 ++++++++++++++++---------- 2 files changed, 202 insertions(+), 121 deletions(-) diff --git a/variants/BLUE_F407VE_Mini/variant.cpp b/variants/BLUE_F407VE_Mini/variant.cpp index a19ceeb6c8..158cc854a0 100644 --- a/variants/BLUE_F407VE_Mini/variant.cpp +++ b/variants/BLUE_F407VE_Mini/variant.cpp @@ -38,71 +38,112 @@ extern "C" { // This array allows to wrap Arduino pin number(Dx or x) // to STM32 PinName (PX_n) const PinName digitalPin[] = { - // Left Side - //Ext //Int - //5V //5V - //5V //5V - //3V3 //3V3 - //3V3 //3V3 - //GND //GND - PE_2, PE_3, // D0, D1 - PE_4, PE_5, - PE_6, PC_13, - PC_0, PC_1, - PC_2, PC_3, - //VREF- //VREF+ - PA_0, PA_1, // D10, D11 - PA_2, PA_3, - PA_4, PA_5, - PA_6, PA_7, - PC_4, PC_5, - PB_0, PB_1, // D20, D21 - PE_7, PE_8, - PE_9, PE_10, - PE_11, PE_12, - PE_13, PE_14, - PE_15, PB_10, // D30, D31 - PB_11, PB_12, - PB_13, PB_14, - // Right Side - //Int //Ext - //3V3 //3V3 - //3V3 //3V3 - //BOOT0 //BOOT1 - //GND //GND - //GND //GND - PE_1, PE_0, - PB_9, PB_8, // PB_9: LED (active LOW) - PB_7, PB_6, // D40, D41 - PB_5, PB_3, - PD_7, PD_6, - PD_5, PD_4, - PD_3, PD_2, - PD_1, PD_0, // D50, D51 - PC_12, PC_11, - PC_10, PA_15, - PA_12, PA_11, // PA_11: USB_DM, PA_12: USB_DP - PA_10, PA_9, - PA_8, PC_9, // D60, D61 - PC_8, PC_7, - PC_6, PD_15, - PD_14, PD_13, - PD_12, PD_11, - PD_10, PD_9, // D70, D71 - PD_8, PB_15, - PB_4, +//External (left to right) + //GND + //VBAT + //5V + PE_0, //D0 + PE_2, + PE_4, + PE_6, + PC_14, //OSC32_IN + PC_0, + PC_2, + PA_0, + PA_1, + PA_4, + PA_6, //D10 + PC_4, + PB_0, + PB_2, + PE_8, + PE_9, + PE_11, + PE_13, + PE_15, + PB_11, + PB_13, //D20 + PB_15, + PD_9, + PD_11, + PD_13, + PD_15, + PC_6, + PC_8, + PC_9, + PA_9, + PA_11, //D30 + PA_13, + PA_15, + PC_11, + PC_12, + PD_1, + PD_3, + PD_5, + PD_7, + PB_4, + PB_6, //D40 + PB_8, + //GND + //3V3 + //GND +//Internal (left to right) + //GND + //3V3 + //5V + PE_1, + PE_3, + PE_5, + PC_13, + PC_15, //OSC32_OUT + PC_1, + PC_3, + PA_2, + PA_3, //D50 + PA_5, + PA_7, + PC_5, + PB_1, + PE_7, + PE_10, + PE_12, + PE_14, + PB_10, + PB_12, //D60 + PB_14, + PD_8, + PD_10, + PD_12, + PD_14, + PC_7, + PA_8, + PA_10, + PA_12, + PA_14, //D70 + PC_10, + PD_0, + PD_2, + PD_4, + PD_6, + PB_3, + PB_5, + PB_7, + PB_9, //D79 - LED + //GND + //3V3 + //GND // Analog pins - PA_0, // D75 + PA_0, //D80 PA_1, PA_2, PA_3, PA_4, - PA_5, // D80 + PA_5, PB_0, PB_1, PC_0, PC_1, - PC_2, + PC_2, //D90 PC_3, PC_4, PC_5 diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h index 139f20d0a7..3f3cb50cb9 100644 --- a/variants/BLUE_F407VE_Mini/variant.h +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -46,71 +46,112 @@ extern "C"{ extern const PinName digitalPin[]; enum { - // Left Side - //Ext //Int - //5V //5V - //5V //5V - //3V3 //3V3 - //3V3 //3V3 - //GND //GND - PE2, PE3, // D0, D1 - PE4, PE5, - PE6, PC13, - PC0, PC1, - PC2, PC3, - //VREF- //VREF+ - PA0, PA1, // D10, D11 - PA2, PA3, - PA4, PA5, - PA6, PA7, - PC4, PC5, - PB0, PB1, // D20, D21 - PE7, PE8, - PE9, PE10, - PE11, PE12, - PE13, PE14, - PE15, PB10, // D30, D31 - PB11, PB12, - PB13, PB14, - // Right Side - //Int //Ext - //3V3 //3V3 - //3V3 //3V3 - //BOOT0 //BOOT1 - //GND //GND - //GND //GND - PE1, PE0, - PB9, PB8, // PB_9: LED (active LOW) - PB7, PB6, // D40, D41 - PB5, PB3, - PD7, PD6, - PD5, PD4, - PD3, PD2, - PD1, PD0, // D50, D51 - PC12, PC11, - PC10, PA15, - PA12, PA11, // PA_11: USB_DM, PA_12: USB_DP - PA10, PA9, - PA8, PC9, // D60, D61 - PC8, PC7, - PC6, PD15, - PD14, PD13, - PD12, PD11, - PD10, PD9, // D70, D71 - PD8, PB15, - PB4, +//External (left to right) + //GND + //VBAT + //5V + PE0, //D0 + PE2, + PE4, + PE6, + PC14, //OSC32IN + PC0, + PC2, + PA0, + PA1, + PA4, + PA6, //D10 + PC4, + PB0, + PB2, + PE8, + PE9, + PE11, + PE13, + PE15, + PB11, + PB13, //D20 + PB15, + PD9, + PD11, + PD13, + PD15, + PC6, + PC8, + PC9, + PA9, + PA11, //D30 + PA13, + PA15, + PC11, + PC12, + PD1, + PD3, + PD5, + PD7, + PB4, + PB6, //D40 + PB8, + //GND + //3V3 + //GND +//Internal (left to right) + //GND + //3V3 + //5V + PE1, + PE3, + PE5, + PC13, + PC15, //OSC32OUT + PC1, + PC3, + PA2, + PA3, //D50 + PA5, + PA7, + PC5, + PB1, + PE7, + PE10, + PE12, + PE14, + PB10, + PB12, //D60 + PB14, + PD8, + PD10, + PD12, + PD14, + PC7, + PA8, + PA10, + PA12, + PA14, //D70 + PC10, + PD0, + PD2, + PD4, + PD6, + PB3, + PB5, + PB7, + PB9, //D79 - LED + //GND + //3V3 + //GND // Analog pins - PA0_A, // D75 + PA0_A, //D80 PA1_A, PA2_A, PA3_A, PA4_A, - PA5_A, // D80 + PA5_A, PB0_A, PB1_A, PC0_A, PC1_A, - PC2_A, + PC2_A, //D90 PC3_A, PC4_A, PC5_A, @@ -118,10 +159,10 @@ enum { }; // This must be a literal with the same value as PEND -#define NUM_DIGITAL_PINS 89 +#define NUM_DIGITAL_PINS 94 // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 -#define NUM_ANALOG_FIRST 75 +#define NUM_ANALOG_FIRST 80 // Below ADC, DAC and PWM definitions already done in the core // Could be redefined here if needed @@ -143,15 +184,14 @@ enum { // Below SPI and I2C definitions already done in the core // Could be redefined here if differs from the default one // SPI Definitions -#define PIN_SPI_SS PB7 // NRF24 connector -#define PIN_SPI_SS1 PB0 // W25Q16 (on board flash) -#define PIN_SPI_MOSI PB5 // NRF24 connector & W25Q16 (on board flash) -#define PIN_SPI_MISO PB4 // NRF24 connector & W25Q16 (on board flash) -#define PIN_SPI_SCK PB3 // NRF24 connector & W25Q16 (on board flash) +#define PIN_SPI_SS PB7 +#define PIN_SPI_MOSI PB5 +#define PIN_SPI_MISO PB4 +#define PIN_SPI_SCK PB3 // I2C Definitions -#define PIN_WIRE_SDA PB9 -#define PIN_WIRE_SCL PB8 +#define PIN_WIRE_SDA PB7 +#define PIN_WIRE_SCL PB6 // Timer Definitions //Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c From 5de3bba00839b1a39a8aa0358e0ed17d5a5d472c Mon Sep 17 00:00:00 2001 From: edogaldo Date: Wed, 19 Sep 2018 19:57:14 +0200 Subject: [PATCH 065/109] BLUE_F407VE_Mini - 4th commit --- variants/BLUE_F407VE_Mini/variant.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h index 3f3cb50cb9..ceb9f6c521 100644 --- a/variants/BLUE_F407VE_Mini/variant.h +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -54,7 +54,7 @@ enum { PE2, PE4, PE6, - PC14, //OSC32IN + PC14, //OSC32_IN PC0, PC2, PA0, @@ -80,7 +80,7 @@ enum { PC8, PC9, PA9, - PA11, //D30 + PA11, //D30 - USB_DM PA13, PA15, PC11, @@ -103,7 +103,7 @@ enum { PE3, PE5, PC13, - PC15, //OSC32OUT + PC15, //OSC32_OUT PC1, PC3, PA2, @@ -126,7 +126,7 @@ enum { PC7, PA8, PA10, - PA12, + PA12, //USB_DP PA14, //D70 PC10, PD0, From faf4c03e3b87b5528bf1e5e34694c4457fb7ca29 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 20 Sep 2018 11:52:29 +0200 Subject: [PATCH 066/109] Enable HAL RTC for RemRamV1 board Signed-off-by: Frederic.Pillon --- variants/REMRAM_V1/stm32f7xx_hal_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/REMRAM_V1/stm32f7xx_hal_conf.h b/variants/REMRAM_V1/stm32f7xx_hal_conf.h index 095f069a4f..43a0a63e42 100644 --- a/variants/REMRAM_V1/stm32f7xx_hal_conf.h +++ b/variants/REMRAM_V1/stm32f7xx_hal_conf.h @@ -70,7 +70,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ /* #define HAL_MMC_MODULE_ENABLED */ From 7c1105198e9914ee9abc95ff74c27ce8bb918097 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 20 Sep 2018 11:33:59 +0200 Subject: [PATCH 067/109] [EEPROM] Update to follow library specification https://github.com/arduino/arduino/wiki/arduino-ide-1.5:-library-specification Signed-off-by: Frederic.Pillon --- libraries/EEPROM/library.properties | 8 +++---- libraries/EEPROM/{ => src}/EEPROM.h | 36 ++++++++++++++--------------- 2 files changed, 22 insertions(+), 22 deletions(-) rename libraries/EEPROM/{ => src}/EEPROM.h (96%) diff --git a/libraries/EEPROM/library.properties b/libraries/EEPROM/library.properties index 95e1e4ad86..2d8a7685ad 100644 --- a/libraries/EEPROM/library.properties +++ b/libraries/EEPROM/library.properties @@ -1,9 +1,9 @@ name=EEPROM -version=2.0 +version=2.0.1 author=Arduino, Christopher Andrews -maintainer=Arduino -sentence=Enables reading and writing to the permanent board storage. For all Arduino boards BUT Arduino DUE and Arduino ZERO. -paragraph= +maintainer=stm32duino +sentence=Enables reading and writing to the permanent board storage. +paragraph=This library allows to read and write data in a memory type, the EEPROM, that keeps its content also when the board is powered off. The amount of EEPROM available depends on the microcontroller type. category=Data Storage url=http://www.arduino.cc/en/Reference/EEPROM architectures=stm32 diff --git a/libraries/EEPROM/EEPROM.h b/libraries/EEPROM/src/EEPROM.h similarity index 96% rename from libraries/EEPROM/EEPROM.h rename to libraries/EEPROM/src/EEPROM.h index d1ecbfa56e..9384f6f223 100644 --- a/libraries/EEPROM/EEPROM.h +++ b/libraries/EEPROM/src/EEPROM.h @@ -25,7 +25,7 @@ /*** EERef class. - + This object references an EEPROM cell. Its purpose is to mimic a typical byte of RAM, however its storage is the EEPROM. This class has an overhead of two bytes, similar to storing a pointer to an EEPROM cell. @@ -35,11 +35,11 @@ struct EERef{ EERef( const int index ) : index( index ) {} - + //Access/read members. uint8_t operator*() const { return eeprom_read_byte( /*(uint8_t*)*/ index ); } operator const uint8_t() const { return **this; } - + //Assignment/write members. EERef &operator=( const EERef &ref ) { return *this = *ref; } EERef &operator=( uint8_t in ) { return eeprom_write_byte( /*(uint8_t*)*/ index, in ), *this; } @@ -53,32 +53,32 @@ struct EERef{ EERef &operator |=( uint8_t in ) { return *this = **this | in; } EERef &operator <<=( uint8_t in ) { return *this = **this << in; } EERef &operator >>=( uint8_t in ) { return *this = **this >> in; } - + EERef &update( uint8_t in ) { return in != *this ? *this = in : *this; } - + /** Prefix increment/decrement **/ EERef& operator++() { return *this += 1; } EERef& operator--() { return *this -= 1; } - + /** Postfix increment/decrement **/ - uint8_t operator++ (int){ + uint8_t operator++ (int){ uint8_t ret = **this; return ++(*this), ret; } - uint8_t operator-- (int){ + uint8_t operator-- (int){ uint8_t ret = **this; return --(*this), ret; } - + int index; //Index of current EEPROM cell. }; /*** EEPtr class. - + This object is a bidirectional pointer to EEPROM cells represented by EERef objects. - Just like a normal pointer type, this can be dereferenced and repositioned using + Just like a normal pointer type, this can be dereferenced and repositioned using increment/decrement operators. ***/ @@ -86,14 +86,14 @@ struct EEPtr{ EEPtr( const int index ) : index( index ) {} - + operator const int() const { return index; } EEPtr &operator=( int in ) { return index = in, *this; } - + //Iterator functionality. bool operator!=( const EEPtr &ptr ) { return index != ptr.index; } EERef operator*() { return index; } - + /** Prefix & Postfix increment/decrement **/ EEPtr& operator++() { return ++index, *this; } EEPtr& operator--() { return --index, *this; } @@ -105,7 +105,7 @@ struct EEPtr{ /*** EEPROMClass class. - + This object represents the entire EEPROM space. It wraps the functionality of EEPtr and EERef into a basic interface. This class is also 100% backwards compatible with earlier Arduino core releases. @@ -118,12 +118,12 @@ struct EEPROMClass{ uint8_t read( int idx ) { return EERef( idx ); } void write( int idx, uint8_t val ) { (EERef( idx )) = val; } void update( int idx, uint8_t val ) { EERef( idx ).update( val ); } - + //STL and C++11 iteration capability. EEPtr begin() { return 0x00; } EEPtr end() { return length(); } //Standards requires this to be the item after the last valid entry. The returned pointer is invalid. uint16_t length() { return E2END; } - + //Functionality to 'get' and 'put' objects to and from EEPROM. template< typename T > T &get( int idx, T &t ){ EEPtr e = idx; @@ -131,7 +131,7 @@ struct EEPROMClass{ for( int count = sizeof(T) ; count ; --count, ++e ) *ptr++ = *e; return t; } - + template< typename T > const T &put( int idx, const T &t ){ EEPtr e = idx; const uint8_t *ptr = (const uint8_t*) &t; From 84bee6fdd2be8b1e5df438ffbd158f1e75b70a5a Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 20 Sep 2018 11:43:44 +0200 Subject: [PATCH 068/109] [EEPROM] Fix warnings type qualifiers ignored on function return type [-Wignored-qualifiers] Signed-off-by: Frederic.Pillon --- libraries/EEPROM/src/EEPROM.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/EEPROM/src/EEPROM.h b/libraries/EEPROM/src/EEPROM.h index 9384f6f223..0c029f8202 100644 --- a/libraries/EEPROM/src/EEPROM.h +++ b/libraries/EEPROM/src/EEPROM.h @@ -38,7 +38,7 @@ struct EERef{ //Access/read members. uint8_t operator*() const { return eeprom_read_byte( /*(uint8_t*)*/ index ); } - operator const uint8_t() const { return **this; } + operator uint8_t() const { return **this; } //Assignment/write members. EERef &operator=( const EERef &ref ) { return *this = *ref; } @@ -87,7 +87,7 @@ struct EEPtr{ EEPtr( const int index ) : index( index ) {} - operator const int() const { return index; } + operator int() const { return index; } EEPtr &operator=( int in ) { return index = in, *this; } //Iterator functionality. From b4c5e91d77ae0404a0d0681667c7d2d10be532c2 Mon Sep 17 00:00:00 2001 From: edogaldo Date: Fri, 21 Sep 2018 16:59:46 +0200 Subject: [PATCH 069/109] BLUE_F407VE_Mini - 5th commit --- CI/build/conf/cores_config.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index f07d4736f3..8ec742fca7 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -54,7 +54,7 @@ { "pattern": "STM32SD", "applicable": true, - "boards": [ "DISCO_F746NG", "BLACK_F407VE" ] + "boards": [ "DISCO_F746NG", "BLACK_F407VE", "BLUE_F407VE_Mini" ] }, { "pattern": "/Ethernet/", From dbc46fe5d858064c28153610b3a702a19fe41340 Mon Sep 17 00:00:00 2001 From: edogaldo Date: Fri, 21 Sep 2018 17:43:23 +0200 Subject: [PATCH 070/109] BLUE_F407VE_Mini - 6th commit --- boards.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/boards.txt b/boards.txt index 9fae61d635..25aa003760 100644 --- a/boards.txt +++ b/boards.txt @@ -525,15 +525,15 @@ GenF4.menu.pnum.BLACK_F407VE.build.cmsis_lib_gcc=arm_cortexM4l_math # Blue F407VE mini: http://wiki.stm32duino.com/index.php?title=Vcc-gnd.com_STM32F407VET6_Mini # Support: Serial1 (USART1 on PA10, PA9) # Default SPI: SPI (SPI1 on PB3,PB4,PB5) -GenF4.menu.pnum.BLUE_F407VE_MINI=Blue F407VE mini -GenF4.menu.pnum.BLUE_F407VE_MINI.upload.maximum_size=524288 -GenF4.menu.pnum.BLUE_F407VE_MINI.upload.maximum_data_size=131072 -GenF4.menu.pnum.BLUE_F407VE_MINI.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -GenF4.menu.pnum.BLUE_F407VE_MINI.build.board=BLUE_F407VE_MINI -GenF4.menu.pnum.BLUE_F407VE_MINI.build.series=STM32F4xx -GenF4.menu.pnum.BLUE_F407VE_MINI.build.product_line=STM32F407xx -GenF4.menu.pnum.BLUE_F407VE_MINI.build.variant=BLUE_F407VE_MINI -GenF4.menu.pnum.BLUE_F407VE_MINI.build.cmsis_lib_gcc=arm_cortexM4l_math +GenF4.menu.pnum.BLUE_F407VE_Mini=Blue F407VE mini +GenF4.menu.pnum.BLUE_F407VE_Mini.upload.maximum_size=524288 +GenF4.menu.pnum.BLUE_F407VE_Mini.upload.maximum_data_size=131072 +GenF4.menu.pnum.BLUE_F407VE_Mini.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard +GenF4.menu.pnum.BLUE_F407VE_Mini.build.board=BLUE_F407VE_Mini +GenF4.menu.pnum.BLUE_F407VE_Mini.build.series=STM32F4xx +GenF4.menu.pnum.BLUE_F407VE_Mini.build.product_line=STM32F407xx +GenF4.menu.pnum.BLUE_F407VE_Mini.build.variant=BLUE_F407VE_Mini +GenF4.menu.pnum.BLUE_F407VE_Mini.build.cmsis_lib_gcc=arm_cortexM4l_math # Upload menu GenF4.menu.upload_method.STLink=STLink From 2a31bc41685bff5678b871c8f6f8a914d6d0212f Mon Sep 17 00:00:00 2001 From: ppescher Date: Fri, 21 Sep 2018 18:10:11 +0200 Subject: [PATCH 071/109] Fix input string const-ness to avoid warnings with literal strings --- cores/arduino/Stream.cpp | 8 ++++---- cores/arduino/Stream.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/cores/arduino/Stream.cpp b/cores/arduino/Stream.cpp index d018c31f3c..7e1e984fea 100644 --- a/cores/arduino/Stream.cpp +++ b/cores/arduino/Stream.cpp @@ -90,20 +90,20 @@ void Stream::setTimeout(unsigned long timeout) // sets the maximum number of mi } // find returns true if the target string is found -bool Stream::find(char *target) +bool Stream::find(const char *target) { return findUntil(target, strlen(target), NULL, 0); } // reads data from the stream until the target string of given length is found // returns true if target string is found, false if timed out -bool Stream::find(char *target, size_t length) +bool Stream::find(const char *target, size_t length) { return findUntil(target, length, NULL, 0); } // as find but search ends if the terminator string is found -bool Stream::findUntil(char *target, char *terminator) +bool Stream::findUntil(const char *target, const char *terminator) { return findUntil(target, strlen(target), terminator, strlen(terminator)); } @@ -111,7 +111,7 @@ bool Stream::findUntil(char *target, char *terminator) // reads data from the stream until the target string of the given length is found // search terminated if the terminator string is found // returns true if target string is found, false if terminated or timed out -bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen) +bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen) { if (terminator == NULL) { MultiTarget t[1] = {{target, targetLen, 0}}; diff --git a/cores/arduino/Stream.h b/cores/arduino/Stream.h index 3582a18186..bd5311b84a 100644 --- a/cores/arduino/Stream.h +++ b/cores/arduino/Stream.h @@ -68,21 +68,21 @@ class Stream : public Print void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second unsigned long getTimeout(void) { return _timeout; } - bool find(char *target); // reads data from the stream until the target string is found - bool find(uint8_t *target) { return find ((char *)target); } + bool find(const char *target); // reads data from the stream until the target string is found + bool find(const uint8_t *target) { return find ((const char *)target); } // returns true if target string is found, false if timed out (see setTimeout) - bool find(char *target, size_t length); // reads data from the stream until the target string of given length is found - bool find(uint8_t *target, size_t length) { return find ((char *)target, length); } + bool find(const char *target, size_t length); // reads data from the stream until the target string of given length is found + bool find(const uint8_t *target, size_t length) { return find ((const char *)target, length); } // returns true if target string is found, false if timed out bool find(char target) { return find (&target, 1); } - bool findUntil(char *target, char *terminator); // as find but search ends if the terminator string is found - bool findUntil(uint8_t *target, char *terminator) { return findUntil((char *)target, terminator); } + bool findUntil(const char *target, const char *terminator); // as find but search ends if the terminator string is found + bool findUntil(const uint8_t *target, const char *terminator) { return findUntil((const char *)target, terminator); } - bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen); // as above but search ends if the terminate string is found - bool findUntil(uint8_t *target, size_t targetLen, char *terminate, size_t termLen) {return findUntil((char *)target, targetLen, terminate, termLen); } + bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen); // as above but search ends if the terminate string is found + bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen) {return findUntil((const char *)target, targetLen, terminate, termLen); } long parseInt(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR); // returns the first valid (long) integer value from the current position. From 22cd50c6a3ecec97500b27e73ac5fb8ab320ee1f Mon Sep 17 00:00:00 2001 From: edogaldo Date: Mon, 24 Sep 2018 11:58:14 +0200 Subject: [PATCH 072/109] BLUE_F407VE_Mini - 7th commit --- variants/BLUE_F407VE_Mini/variant.cpp | 4 ++-- variants/BLUE_F407VE_Mini/variant.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/variants/BLUE_F407VE_Mini/variant.cpp b/variants/BLUE_F407VE_Mini/variant.cpp index 158cc854a0..de1b3801ce 100644 --- a/variants/BLUE_F407VE_Mini/variant.cpp +++ b/variants/BLUE_F407VE_Mini/variant.cpp @@ -72,7 +72,7 @@ const PinName digitalPin[] = { PC_8, PC_9, PA_9, - PA_11, //D30 + PA_11, //D30 - USB_DM PA_13, PA_15, PC_11, @@ -118,7 +118,7 @@ const PinName digitalPin[] = { PC_7, PA_8, PA_10, - PA_12, + PA_12, //USB_DP PA_14, //D70 PC_10, PD_0, diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h index ceb9f6c521..d018e24543 100644 --- a/variants/BLUE_F407VE_Mini/variant.h +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -184,10 +184,10 @@ enum { // Below SPI and I2C definitions already done in the core // Could be redefined here if differs from the default one // SPI Definitions -#define PIN_SPI_SS PB7 -#define PIN_SPI_MOSI PB5 -#define PIN_SPI_MISO PB4 -#define PIN_SPI_SCK PB3 +#define PIN_SPI_MOSI PB15 +#define PIN_SPI_MISO PB14 +#define PIN_SPI_SCK PB13 +#define PIN_SPI_SS PB12 // I2C Definitions #define PIN_WIRE_SDA PB7 From 998af8545aa991d5ea2b036edbb0d29dd9070b62 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 25 Sep 2018 16:30:26 +0200 Subject: [PATCH 073/109] [CI] Use real core-api-version if possible Since Arduino 1.8.6, it is possible to get the version using the CLI. Use: -core-api-version string version of core APIs (used to populate ARDUINO #define) (default "10600") instead of: -ide-version string [deprecated] use 'core-api-version' instead (default "10600") Signed-off-by: Frederic.Pillon --- CI/build/arduino-builder.py | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/CI/build/arduino-builder.py b/CI/build/arduino-builder.py index 42cdd2d4ee..234a5488b0 100644 --- a/CI/build/arduino-builder.py +++ b/CI/build/arduino-builder.py @@ -145,6 +145,7 @@ board_options = {} # key: board name, value: options sketch_options = {} # key: sketch pattern, value: options na_sketch_pattern = {} # key: board name, value: sketch pattern list +core_api_version = "10805" # Counter nb_build_passed = 0 @@ -193,6 +194,25 @@ def create_output_log_tree(): createFolder(os.path.join(build_output_dir, board)) +def get_ide_version(): + global core_api_version + try: + output = subprocess.check_output( + [os.path.join(arduino_path, "arduino"), "--version"], + stderr=subprocess.DEVNULL, + ) + res = re.match("\D*(\d)\.(\d+)\.(\d+)", output.decode("utf-8")) + if res: + core_api_version = ( + res.group(1) + res.group(2).zfill(2) + res.group(3).zfill(2) + ) + print("Arduino IDE version used: " + core_api_version) + else: + raise subprocess.CalledProcessError(1, "re") + except subprocess.CalledProcessError as err: + print("Unable to define Arduino IDE version, use default: " + core_api_version) + + def load_core_config(): global core_config global maintainer @@ -482,6 +502,7 @@ def log_sketch_build_result(sketch, boardKo, boardSkipped): f.write("Skipped boards :\n" + "\n".join(boardSkipped)) f.write("\n") + # Log final result def log_final_result(): # Also equal to len(board_type) * len(sketch_list) @@ -569,7 +590,7 @@ def genBasicCommand(b_name, b_type): cmd.append(arduino_lib_path) cmd.append("-libraries") cmd.append(arduino_user_lib_path) - cmd.append("-ide-version=10805") + cmd.append("-core-api-version=" + core_api_version) cmd.append("-warnings=all") if args.verbose: cmd.append("-verbose") @@ -766,6 +787,8 @@ def main(): if args.clean: deleteFolder(root_output_dir) + get_ide_version() + load_core_config() find_board() From 74490382e3a7d7e2c0ade7822eaa3bb42b2cc6e2 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 26 Sep 2018 09:48:22 +0200 Subject: [PATCH 074/109] [CI] Update sketches applicability Signed-off-by: Frederic.Pillon --- CI/build/conf/cores_config.json | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index f07d4736f3..0b5446af86 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -43,7 +43,8 @@ "NUCLEO_F303K8", "BLUEPILL_F103C8", "MAPLEMINI_F103CB", - "RAK811_TRACKER" + "RAK811_TRACKER", + "REMRAM_V1" ] }, { @@ -51,13 +52,18 @@ "applicable": true, "boards": [ "" ] }, + { + "pattern": "eepromReadWrite|eepromTest_Wire1", + "applicable": true, + "boards": [ "" ] + }, { "pattern": "STM32SD", "applicable": true, "boards": [ "DISCO_F746NG", "BLACK_F407VE" ] }, { - "pattern": "/Ethernet/", + "pattern": "Ethernet/", "applicable": false, "boards": [ "NUCLEO_L031K6" ] }, @@ -83,6 +89,11 @@ "pattern": "X_NUCLEO_IKA01A1_HelloWorld.ino|X_NUCLEO_IHM02A1_HelloWorld.ino", "applicable": false, "boards": [ "RAK811_TRACKER" ] + }, + { + "pattern": "StringComparisonOperators.ino", + "applicable": false, + "boards": [ "REMRAM_V1" ] } ] }, From 246190ba9ec1475f87ee52e0b653a07ccfc42bd1 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 24 Sep 2018 10:16:21 +0200 Subject: [PATCH 075/109] [EEPROM] Fix address capablilities Address was limited to 65Kb while on some STM32 series, sector size use could be higher Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/stm32_eeprom.c | 8 ++++---- cores/arduino/stm32/stm32_eeprom.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cores/arduino/stm32/stm32_eeprom.c b/cores/arduino/stm32/stm32_eeprom.c index 1cc8c55b06..c8ea67f479 100644 --- a/cores/arduino/stm32/stm32_eeprom.c +++ b/cores/arduino/stm32/stm32_eeprom.c @@ -101,7 +101,7 @@ static uint8_t eeprom_buffer[E2END] = {0}; * @param pos : address to read * @retval byte : data read from eeprom */ -uint8_t eeprom_read_byte(const uint16_t pos) { +uint8_t eeprom_read_byte(const uint32_t pos) { eeprom_buffer_fill(); return eeprom_buffered_read_byte(pos); } @@ -112,7 +112,7 @@ uint8_t eeprom_read_byte(const uint16_t pos) { * @param value : value to write * @retval none */ -void eeprom_write_byte(uint16_t pos, uint8_t value) { +void eeprom_write_byte(uint32_t pos, uint8_t value) { eeprom_buffered_write_byte(pos, value); eeprom_buffer_flush(); } @@ -122,7 +122,7 @@ void eeprom_write_byte(uint16_t pos, uint8_t value) { * @param pos : address to read * @retval byte : data read from eeprom */ -uint8_t eeprom_buffered_read_byte(const uint16_t pos) { +uint8_t eeprom_buffered_read_byte(const uint32_t pos) { return eeprom_buffer[pos]; } @@ -132,7 +132,7 @@ uint8_t eeprom_buffered_read_byte(const uint16_t pos) { * @param value : value to write * @retval none */ -void eeprom_buffered_write_byte(uint16_t pos, uint8_t value) { +void eeprom_buffered_write_byte(uint32_t pos, uint8_t value) { eeprom_buffer[pos] = value; } diff --git a/cores/arduino/stm32/stm32_eeprom.h b/cores/arduino/stm32/stm32_eeprom.h index fb52027978..a90e5e8b4e 100644 --- a/cores/arduino/stm32/stm32_eeprom.h +++ b/cores/arduino/stm32/stm32_eeprom.h @@ -55,13 +55,13 @@ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ -uint8_t eeprom_read_byte(const uint16_t pos); -void eeprom_write_byte(uint16_t pos, uint8_t value); +uint8_t eeprom_read_byte(const uint32_t pos); +void eeprom_write_byte(uint32_t pos, uint8_t value); void eeprom_buffer_fill(); void eeprom_buffer_flush(); -uint8_t eeprom_buffered_read_byte(const uint16_t pos); -void eeprom_buffered_write_byte(uint16_t pos, uint8_t value); +uint8_t eeprom_buffered_read_byte(const uint32_t pos); +void eeprom_buffered_write_byte(uint32_t pos, uint8_t value); #ifdef __cplusplus } From 6e5b01b8a7c586403291a626a2b033c1e126dd12 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 24 Sep 2018 11:14:55 +0200 Subject: [PATCH 076/109] [EEPROM] Allow FLASH definition to be redefined Fix #248 Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/stm32_eeprom.c | 96 +++++++++++++++++++++--------- cores/arduino/stm32/stm32_eeprom.h | 13 ++-- 2 files changed, 76 insertions(+), 33 deletions(-) diff --git a/cores/arduino/stm32/stm32_eeprom.c b/cores/arduino/stm32/stm32_eeprom.c index c8ea67f479..90aa7ca870 100644 --- a/cores/arduino/stm32/stm32_eeprom.c +++ b/cores/arduino/stm32/stm32_eeprom.c @@ -39,23 +39,51 @@ extern "C" { #endif -/* Use the last page of the flash to store data in order to prevent overwritting - program data */ -#if defined (STM32F0xx) || defined (STM32F1xx) || defined(STM32L1xx) -#if defined (FLASH_BANK2_END) -#define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_BANK2_END + 1) - FLASH_PAGE_SIZE)) -#elif defined (FLASH_BANK1_END) -#define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_BANK1_END + 1) - FLASH_PAGE_SIZE)) +/* Be able to change FLASH_BANK_NUMBER to use if relevant */ +#if !defined(FLASH_BANK_NUMBER) &&\ + (defined(STM32F0xx) || defined(STM32F1xx) ||\ + defined(STM32L1xx) || defined(STM32L4xx)) +/* Fo STM32F0xx, FLASH_BANK_1 is not defined only FLASH_BANK1_END is defined */ +#if defined(STM32F0xx) +#define FLASH_BANK_1 1U +#endif +#if defined(FLASH_BANK_2) +#define FLASH_BANK_NUMBER FLASH_BANK_2 #else -#define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_END + 1) - FLASH_PAGE_SIZE)) -#endif /* FLASH_BANK2_END */ -#elif defined (STM32F2xx) || defined (STM32F4xx) || defined (STM32F7xx) -#define FLASH_BASE_ADDRESS ((uint32_t)(FLASH_END + 1) - FLASH_PAGE_SIZE) +#define FLASH_BANK_NUMBER FLASH_BANK_1 +#endif /* FLASH_BANK_2 */ +#ifndef FLASH_BANK_NUMBER +#error "FLASH_BANK_NUMBER could not be defined" +#endif +#endif /* !FLASH_BANK_NUMBER */ + +/* Be able to change FLASH_DATA_SECTOR to use if relevant */ +#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) +#if !defined(FLASH_DATA_SECTOR) #define FLASH_DATA_SECTOR ((uint32_t)(FLASH_SECTOR_TOTAL - 1)) +#else +#ifndef FLASH_BASE_ADDRESS +#error "FLASH_BASE_ADDRESS have to be defined when FLASH_DATA_SECTOR is defined" +#endif +#endif /* !FLASH_DATA_SECTOR */ +#endif /* STM32F2xx || STM32F4xx || STM32F7xx */ + +/* Be able to change FLASH_PAGE_NUMBER to use if relevant */ +#if !defined(FLASH_PAGE_NUMBER) && defined (STM32L4xx) +#define FLASH_PAGE_NUMBER ((uint32_t)((FLASH_SIZE / FLASH_PAGE_SIZE) - 1)) +#endif /* !FLASH_PAGE_NUMBER */ + +/* Be able to change FLASH_END to use */ +#if !defined(FLASH_END) && !defined(STM32L0xx) +#if defined (STM32F0xx) || defined (STM32F1xx) || defined(STM32L1xx) +#if defined (FLASH_BANK2_END) && (FLASH_BANK_NUMBER == FLASH_BANK_2) +#define FLASH_END FLASH_BANK2_END +#elif defined (FLASH_BANK1_END) && (FLASH_BANK_NUMBER == FLASH_BANK_1) +#define FLASH_END FLASH_BANK1_END +#endif #elif defined (STM32F3xx) static inline uint32_t get_flash_end(void) { uint32_t size; - switch((*((uint16_t *)FLASH_SIZE_DATA_REGISTER))) { case 0x200U: size = 0x0807FFFFU; @@ -76,23 +104,34 @@ static inline uint32_t get_flash_end(void) { size = 0x08003FFFU; break; } - return size; } -#define FLASH_END_ADDR get_flash_end() -#define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_END_ADDR + 1) - FLASH_PAGE_SIZE)) -#elif defined (STM32L0xx) -#define FLASH_BASE_ADDRESS ((uint32_t)(DATA_EEPROM_BASE)) +#define FLASH_END get_flash_end() #elif defined (STM32L4xx) -#ifndef FLASH_BANK_2 -#define FLASH_BANK_NUMBER FLASH_BANK_1 +/* If FLASH_PAGE_NUMBER is defined by user, this is not really end of the flash */ +#define FLASH_END ((uint32_t)(FLASH_BASE + (((FLASH_PAGE_NUMBER +1) * FLASH_PAGE_SIZE))-1)) +#endif +#ifndef FLASH_END +#error "FLASH_END could not be defined" +#endif +#endif /* FLASH_END */ + +/* Be able to change FLASH_BASE_ADDRESS to use */ +#ifndef FLASH_BASE_ADDRESS +/* + * By default, Use the last page of the flash to store data + * in order to prevent overwritting + * program data + */ +#if defined(STM32L0xx) +#define FLASH_BASE_ADDRESS ((uint32_t)(DATA_EEPROM_BASE)) #else -#define FLASH_BANK_NUMBER FLASH_BANK_2 -#endif /* FLASH_BANK_2 */ -/* Flash base address */ -#define FLASH_PAGE_NUMBER ((uint32_t)((FLASH_SIZE / FLASH_PAGE_SIZE) - 1)) -#define FLASH_BASE_ADDRESS ((uint32_t)(FLASH_BASE + (FLASH_PAGE_NUMBER * FLASH_PAGE_SIZE))) +#define FLASH_BASE_ADDRESS ((uint32_t)((FLASH_END + 1) - FLASH_PAGE_SIZE)) +#endif +#ifndef FLASH_BASE_ADDRESS +#error "FLASH_BASE_ADDRESS could not be defined" #endif +#endif /* FLASH_BASE_ADDRESS */ static uint8_t eeprom_buffer[E2END] = {0}; @@ -162,13 +201,12 @@ void eeprom_buffer_flush(void) { /* ERASING page */ EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; -#ifdef STM32L4xx +#if defined(STM32L4xx) || defined(STM32F1xx) EraseInitStruct.Banks = FLASH_BANK_NUMBER; +#endif +#ifdef STM32L4xx EraseInitStruct.Page = FLASH_PAGE_NUMBER; #else -#ifdef STM32F1xx - EraseInitStruct.Banks = FLASH_BANK_1; -#endif EraseInitStruct.PageAddress = FLASH_BASE_ADDRESS; #endif EraseInitStruct.NbPages = 1; @@ -199,7 +237,7 @@ void eeprom_buffer_flush(void) { address += 4; offset += 4; #else - data = *((uint64_t*)(((uint8_t*)eeprom_buffer + offset))); + data = *((uint64_t*)((uint8_t*)eeprom_buffer + offset)); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data) == HAL_OK) { address += 8; diff --git a/cores/arduino/stm32/stm32_eeprom.h b/cores/arduino/stm32/stm32_eeprom.h index a90e5e8b4e..373b62a865 100644 --- a/cores/arduino/stm32/stm32_eeprom.h +++ b/cores/arduino/stm32/stm32_eeprom.h @@ -37,7 +37,7 @@ #define __STM32_EEPROM_H /* Includes ------------------------------------------------------------------*/ -#include "stm32_def.h" +#include "variant.h" #ifdef __cplusplus extern "C" { @@ -45,9 +45,14 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - -#if defined (STM32F2xx) || defined (STM32F4xx) || defined (STM32F7xx) -/* FLASH_SECTOR_SIZE */ +#ifndef FLASH_PAGE_SIZE +/* + * FLASH_PAGE_SIZE is not defined for STM32F2xx, STM32F4xx and STM32F7xx + * Could be redefined in variant.h or using build_opt.h + * Warning: This is not the sector size, only the size used for EEPROM + * emulation. Anyway, all the sector size will be erased. + * So pay attention to not use this sector for other stuff. + */ #define FLASH_PAGE_SIZE ((uint32_t)(16*1024)) /* 16kB page */ #endif #define E2END FLASH_PAGE_SIZE From f72f44c4d1c5ed68edbeb15e621a74ce3647df25 Mon Sep 17 00:00:00 2001 From: sabas1080 Date: Fri, 16 Mar 2018 08:27:48 -0600 Subject: [PATCH 077/109] Add RAK811 LoRa Tracker Board Datasheet: http://docs.rakwireless.com/en/RAK811%20TrackerBoard/Software%20Development/RAK811%20TrackerBoard%20Datasheet%20V1.1.pdf Github: https://github.com/RAKWireless/RAK811_BreakBoard Using RAK 811 Lora Module Datasheet: http://docs.rakwireless.com/en/RAK811/Software%20Development/RAK811%C2%A0Lora%C2%A0Module%C2%A0Datasheet%C2%A0V1.3.pdf http://www.rakwireless.com/en/download/RAK811/Hardware%20Design Signed-off-by: sabas1080 --- boards.txt | 66 +++++ variants/RAK811_TRACKER/PeripheralPins.c | 221 ++++++++++++++ variants/RAK811_TRACKER/PinNamesVar.h | 25 ++ variants/RAK811_TRACKER/ldscript.ld | 169 +++++++++++ variants/RAK811_TRACKER/stm32l1xx_hal_conf.h | 292 +++++++++++++++++++ variants/RAK811_TRACKER/variant.cpp | 146 ++++++++++ variants/RAK811_TRACKER/variant.h | 179 ++++++++++++ 7 files changed, 1098 insertions(+) create mode 100644 variants/RAK811_TRACKER/PeripheralPins.c create mode 100644 variants/RAK811_TRACKER/PinNamesVar.h create mode 100644 variants/RAK811_TRACKER/ldscript.ld create mode 100644 variants/RAK811_TRACKER/stm32l1xx_hal_conf.h create mode 100644 variants/RAK811_TRACKER/variant.cpp create mode 100644 variants/RAK811_TRACKER/variant.h diff --git a/boards.txt b/boards.txt index 7b4b4e5f39..7618e33e30 100644 --- a/boards.txt +++ b/boards.txt @@ -569,6 +569,40 @@ Maple.menu.upload_method.serialMethod=Serial Maple.menu.upload_method.serialMethod.upload.protocol=maple_serial Maple.menu.upload_method.serialMethod.upload.tool=serial_upload +################################################################################ +# RAK boards + +RAK.name=RAKWireless + +RAK.build.vid=0x0483 +RAK.build.pid=0x5711 +RAK.vid.0=0x0483 +RAK.pid.0=0x5711 + +RAK.build.core=arduino +RAK.build.board=RAK +RAK.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} + +# RAK811_TRACKER board +RAK.menu.pnum.RAK811_TRACKER=RAK811 LoRa Tracker +RAK.menu.pnum.RAK811_TRACKER.upload.maximum_size=131072 +RAK.menu.pnum.RAK811_TRACKER.upload.maximum_data_size=16384 +RAK.menu.pnum.RAK811_TRACKER.build.mcu=cortex-m3 +RAK.menu.pnum.RAK811_TRACKER.build.board=RAK811_TRACKER +RAK.menu.pnum.RAK811_TRACKER.build.series=STM32L1xx +RAK.menu.pnum.RAK811_TRACKER.build.product_line=STM32L151xB +RAK.menu.pnum.RAK811_TRACKER.build.variant=RAK811_TRACKER +RAK.menu.pnum.RAK811_TRACKER.build.cmsis_lib_gcc=arm_cortexM3l_math + +# Upload menu +RAK.menu.upload_method.serialMethod=Serial +RAK.menu.upload_method.serialMethod.upload.protocol=maple_serial +RAK.menu.upload_method.serialMethod.upload.tool=serial_upload + +RAK.menu.upload_method.STLink=STLink +RAK.menu.upload_method.STLink.upload.protocol=STLink +RAK.menu.upload_method.STLink.upload.tool=stlink_upload + ############################### # RemRam @@ -653,6 +687,12 @@ Maple.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE Maple.menu.xserial.disabled=Disabled (No Serial) Maple.menu.xserial.disabled.build.xSerial= +RAK.menu.xserial.generic=Enabled with generic Serial +RAK.menu.xserial.none=Enabled without generic Serial +RAK.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +RAK.menu.xserial.disabled=Disabled (No Serial) +RAK.menu.xserial.disabled.build.xSerial= + RemRam.menu.xserial.generic=Enabled with generic Serial RemRam.menu.xserial.none=Enabled without generic Serial RemRam.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -869,6 +909,32 @@ Maple.menu.opt.ogstd=Debug (-g) Maple.menu.opt.ogstd.build.flags.optimize=-g -Og Maple.menu.opt.ogstd.build.flags.ldspecs= +RAK.menu.opt.osstd=Smallest (-Os default) +RAK.menu.opt.oslto=Smallest (-Os) with LTO +RAK.menu.opt.oslto.build.flags.optimize=-Os -flto +RAK.menu.opt.oslto.build.flags.ldspecs=-flto +RAK.menu.opt.o1std=Fast (-O1) +RAK.menu.opt.o1std.build.flags.optimize=-O1 +RAK.menu.opt.o1std.build.flags.ldspecs= +RAK.menu.opt.o1lto=Fast (-O1) with LTO +RAK.menu.opt.o1lto.build.flags.optimize=-O1 -flto +RAK.menu.opt.o1lto.build.flags.ldspecs=-flto +RAK.menu.opt.o2std=Faster (-O2) +RAK.menu.opt.o2std.build.flags.optimize=-O2 +RAK.menu.opt.o2std.build.flags.ldspecs= +RAK.menu.opt.o2lto=Faster (-O2) with LTO +RAK.menu.opt.o2lto.build.flags.optimize=-O2 -flto +RAK.menu.opt.o2lto.build.flags.ldspecs=-flto +RAK.menu.opt.o3std=Fastest (-O3) +RAK.menu.opt.o3std.build.flags.optimize=-O3 +RAK.menu.opt.o3std.build.flags.ldspecs= +RAK.menu.opt.o3lto=Fastest (-O3) with LTO +RAK.menu.opt.o3lto.build.flags.optimize=-O3 -flto +RAK.menu.opt.o3lto.build.flags.ldspecs=-flto +RAK.menu.opt.ogstd=Debug (-g) +RAK.menu.opt.ogstd.build.flags.optimize=-g -Og +RAK.menu.opt.ogstd.build.flags.ldspecs= + RemRam.menu.opt.osstd=Smallest (-Os default) RemRam.menu.opt.oslto=Smallest (-Os) with LTO RemRam.menu.opt.oslto.build.flags.optimize=-Os -flto diff --git a/variants/RAK811_TRACKER/PeripheralPins.c b/variants/RAK811_TRACKER/PeripheralPins.c new file mode 100644 index 0000000000..4762cbb81b --- /dev/null +++ b/variants/RAK811_TRACKER/PeripheralPins.c @@ -0,0 +1,221 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32L151C(6-8-B)Tx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { +// {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - ADC_VBAT +// {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - RADIO_DIO_2 +// {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - RADIO_RF_CTX_PA +// {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - RADIO_SCLK +// {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 - RADIO_MISO +// {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 - RADIO_MOSI +// {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - RADIO_NSS +// {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - RADIO_DIO_1 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 +// {PB_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19 - RADIO_RESET +// {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 - LIS3DH_INT1_PIN +// {PB_15, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21 - LIS3DH_INT2_PIN + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { +// {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 - RADIO_RF_CTX_PA +// {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - RADIO_SCLK + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { +// {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // RADIO_RF_CBT_HF + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // GPS_UART_RX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { +// {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // RADIO_RF_CRX_RX + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // GPS_UART_TX + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ADC_VBAT +// {PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - ADC_VBAT +// {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - RADIO_DIO_2 +// {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - RADIO_DIO_2 +// {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - RADIO_SCLK +// {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - RADIO_MISO +// {PA_6, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - RADIO_MISO +// {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - RADIO_MOSI +// {PA_7, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - RADIO_MOSI +// {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - GPS_POWER_ON_PIN +// {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - RADIO_NSS +// {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - RADIO_DIO_1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - LED2 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - RADIO_RF_CRX_RX +// {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - RADIO_RF_CBT_HF + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 +// {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 +// {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - GPS_UART_TX +// {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - GPS_UART_RX + {PB_12, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 +// {PB_13, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 - RADIO_RESET +// {PB_14, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - LIS3DH_INT1_PIN +// {PB_15, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 - LIS3DH_INT2_PIN + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { +// {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ADC_VBAT + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // UART_TX +// {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // RADIO_RF_CRX_RX + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // GPS_UART_TX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { +// {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // RADIO_DIO_2 + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // UART_RX +// {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // RADIO_RF_CBT_HF + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // GPS_UART_RX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // LED1 +// {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // LIS3DH_INT1_PIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // RADIO_DIO_0 +// {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // RADIO_RESET + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // RADIO_MOSI +// {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // LED1 +// {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // LIS3DH_INT2_PIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // RADIO_MISO +// {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // RADIO_DIO_0 +// {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // LED2 +// {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // LIS3DH_INT1_PIN + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // RADIO_SCLK +// {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // RADIO_RESET + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { +// {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // RADIO_RF_CTX_PA +// {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // GPS_POWER_ON_PIN + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +//*** No CAN_RD *** + +//*** No CAN_TD *** + +//*** ETHERNET *** + +//*** No Ethernet *** + +//*** QUADSPI *** + +//*** No QUADSPI *** diff --git a/variants/RAK811_TRACKER/PinNamesVar.h b/variants/RAK811_TRACKER/PinNamesVar.h new file mode 100644 index 0000000000..0b7fa5cc33 --- /dev/null +++ b/variants/RAK811_TRACKER/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/RAK811_TRACKER/ldscript.ld b/variants/RAK811_TRACKER/ldscript.ld new file mode 100644 index 0000000000..c68f7d858c --- /dev/null +++ b/variants/RAK811_TRACKER/ldscript.ld @@ -0,0 +1,169 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L151CBTx Device with +** 128KByte FLASH, 16KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20004000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text ALIGN(4): + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata ALIGN(4): + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/variants/RAK811_TRACKER/stm32l1xx_hal_conf.h b/variants/RAK811_TRACKER/stm32l1xx_hal_conf.h new file mode 100644 index 0000000000..4b39fbf1cb --- /dev/null +++ b/variants/RAK811_TRACKER/stm32l1xx_hal_conf.h @@ -0,0 +1,292 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_conf.h + * @author MCD Application Team + * @version 21-April-2017 + * @date V1.3.0 + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l1xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2017 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CONF_H +#define __STM32L1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/*#define HAL_COMP_MODULE_ENABLED*/ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +/*#define HAL_CRYP_MODULE_ENABLED*/ +/*#define HAL_DAC_MODULE_ENABLED*/ +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +/*#define HAL_IRDA_MODULE_ENABLED*/ +/*#define HAL_IWDG_MODULE_ENABLED*/ +/*#define HAL_LCD_MODULE_ENABLED*/ +/*#define HAL_NOR_MODULE_ENABLED*/ +/*#define HAL_OPAMP_MODULE_ENABLED*/ +/*#define HAL_PCD_MODULE_ENABLED*/ +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/*#define HAL_SD_MODULE_ENABLED*/ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED*/ +#define HAL_TIM_MODULE_ENABLED +/*#define HAL_UART_MODULE_ENABLED*/ +/*#define HAL_USART_MODULE_ENABLED*/ +/*#define HAL_WWDG_MODULE_ENABLED*/ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (12000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE (2097000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @brief Time out for LSE start up value in ms. + */ +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (0x000FU) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/*#define USE_FULL_ASSERT 1U*/ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l1xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l1xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l1xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l1xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/RAK811_TRACKER/variant.cpp b/variants/RAK811_TRACKER/variant.cpp new file mode 100644 index 0000000000..d8127e4318 --- /dev/null +++ b/variants/RAK811_TRACKER/variant.cpp @@ -0,0 +1,146 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +const PinName digitalPin[] = { + PA_0, //D0 + PA_8, //D1 + PA_9, //D2 - UART_TX + PA_10, //D3 - UART_RX + PA_12, //D4 - LED1 + PA_13, //D5 + PA_14, //D6 + PA_15, //D7 - GPS_POWER_ON_PIN + PB_2, //D8 + PB_3, //D9 + PB_4, //D10 - LED2 + PB_5, //D11 + PB_8, //D12 - I2C_SCL + PB_9, //D13 - I2C_SDA + PB_10, //D14 - GPS_UART_TX + PB_11, //D15 - GPS_UART_RX + PA_1, //D16/A0 + PA_2, //D17/A1 - ADC_VBAT + PB_12, //D18/A2 + PB_14, //D19 - LIS3DH_INT1_PIN + PB_15, //D20 - LIS3DH_INT2_PIN + PB_13, //D21 - RADIO_RESET + PH_1, //D22 - RADIO_XTAL_EN + PA_7, //D23 - RADIO_MOSI + PA_6, //D24 - RADIO_MISO + PA_5, //D25 - RADIO_SCLK + PB_0, //D26 - RADIO_NSS + PA_11, //D27 - RADIO_DIO_0 + PB_1, //D28 - RADIO_DIO_1 + PA_3, //D29 - RADIO_DIO_2 + PH_0, //D30 - RADIO_DIO_3 + PC_13, //D31 - RADIO_DIO_4 + PB_6, //D32 - RADIO_RF_CRX_RX + PB_7, //D33 - RADIO_RF_CBT_HF + PA_4 //D34 - RADIO_RF_CTX_PA +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInit; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + + /* Configure the Systick interrupt time */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /* Configure the Systick */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/RAK811_TRACKER/variant.h b/variants/RAK811_TRACKER/variant.h new file mode 100644 index 0000000000..80bf2d68a5 --- /dev/null +++ b/variants/RAK811_TRACKER/variant.h @@ -0,0 +1,179 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +enum { + PA0, //D0 - GPS_PPS_PIN + PA8, //D1 + PA9, //D2 - UART_TX + PA10, //D3 - UART_RX + PA12, //D4 - LED1 + PA13, //D5 + PA14, //D6 + PA15, //D7 - GPS_POWER_ON_PIN + PB2, //D8 + PB3, //D9 + PB4, //D10 - LED2 + PB5, //D11 + PB8, //D12 - I2C_SCL + PB9, //D13 - I2C_SDA + PB10, //D14 - GPS_UART_TX + PB11, //D15 - GPS_UART_RX + PA1, //D16/A0 + PA2, //D17/A1 - ADC_VBAT + PB12, //D18/A2 + PB14, //D19 - LIS3DH_INT1_PIN + PB15, //D20 - LIS3DH_INT2_PIN + PB13, //D21 - RADIO_RESET + PH1, //D22 - RADIO_XTAL_EN + PA7, //D23 - RADIO_MOSI + PA6, //D24 - RADIO_MISO + PA5, //D25 - RADIO_SCLK + PB0, //D26 - RADIO_NSS + PA11, //D27 - RADIO_DIO_0 + PB1, //D28 - RADIO_DIO_1 + PA3, //D29 - RADIO_DIO_2 + PH0, //D30 - RADIO_DIO_3 + PC13, //D31 - RADIO_DIO_4 + PB6, //D32 - RADIO_RF_CRX_RX + PB7, //D33 - RADIO_RF_CBT_HF + PA4, //D34 - RADIO_RF_CTX_PA + PEND +}; + +// This must be a literal with the same value as PEND +#define NUM_DIGITAL_PINS 35 +// This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 3 +#define NUM_ANALOG_FIRST 16 + +// On-board LED pin number +#define LED_BUILTIN PA12 +#define LED1 LED_BUILTIN +#define LED2 PB4 + +// SPI Definitions +#define PIN_SPI_SS PB0 +#define PIN_SPI_MOSI PA7 +#define PIN_SPI_MISO PA6 +#define PIN_SPI_SCK PA5 + +// I2C Definitions +#define PIN_WIRE_SDA PB9 +#define PIN_WIRE_SCL PB8 + +// Timer Definitions +// Do not use timer used by PWM pins when possible. See PinMap_PWM. +#define TIMER_TONE TIM10 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM2 //TODO: advanced-control timers don't work + +// UART Definitions +#define SERIAL_UART_INSTANCE 1 +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#define PIN_SERIAL_RX PA10 +#define PIN_SERIAL_TX PA9 + +// LoRa Definitions +#define RADIO_RESET PB13 +#define RADIO_XTAL_EN PH1 + +#define RADIO_MOSI PA7 +#define RADIO_MISO PA6 +#define RADIO_SCLK PA5 +#define RADIO_NSS PB0 + +#define RADIO_DIO_0 PA11 +#define RADIO_DIO_1 PB1 +#define RADIO_DIO_2 PA3 +#define RADIO_DIO_3 PH0 +#define RADIO_DIO_4 PC13 + +#define RADIO_RF_CRX_RX PB6 //CRF3 +#define RADIO_RF_CBT_HF PB7 //CRF2 HF +#define RADIO_RF_CTX_PA PA4 //CRF1 PA + +// GPS Definitions +#define GPS_PPS_PIN PA0 +#define GPS_UART USART3 +#define GPS_POWER_ON_PIN PA15 +#define GPS_UART_TX PB10 +#define GPS_UART_RX PB11 + +// MEMS (LIS3DH) +#define LIS3DH_INT1_PIN PB14 +#define LIS3DH_INT2_PIN PB15 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From a4291d8db9440da254a471d75be32bb927df64a4 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 10 Jul 2018 08:20:17 +0200 Subject: [PATCH 078/109] Added menu option to select RAM size Two version of RAK811 LoRa Tracker exist: 16Kb and 32Kb. Signed-off-by: Frederic Pillon --- boards.txt | 11 +- variants/RAK811_TRACKER/PeripheralPins.c | 2 +- variants/RAK811_TRACKER/ldscript_xba.ld | 169 +++++++++++++++++++++++ 3 files changed, 180 insertions(+), 2 deletions(-) create mode 100644 variants/RAK811_TRACKER/ldscript_xba.ld diff --git a/boards.txt b/boards.txt index 7618e33e30..5141d31f72 100644 --- a/boards.txt +++ b/boards.txt @@ -8,6 +8,7 @@ menu.usb=USB interface menu.opt=Optimize menu.upload_method=Upload method menu.flash=Flash Memory Size +menu.ram=RAM Size ################################################################################ # Nucleo 144 boards @@ -586,7 +587,6 @@ RAK.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} # RAK811_TRACKER board RAK.menu.pnum.RAK811_TRACKER=RAK811 LoRa Tracker RAK.menu.pnum.RAK811_TRACKER.upload.maximum_size=131072 -RAK.menu.pnum.RAK811_TRACKER.upload.maximum_data_size=16384 RAK.menu.pnum.RAK811_TRACKER.build.mcu=cortex-m3 RAK.menu.pnum.RAK811_TRACKER.build.board=RAK811_TRACKER RAK.menu.pnum.RAK811_TRACKER.build.series=STM32L1xx @@ -594,6 +594,15 @@ RAK.menu.pnum.RAK811_TRACKER.build.product_line=STM32L151xB RAK.menu.pnum.RAK811_TRACKER.build.variant=RAK811_TRACKER RAK.menu.pnum.RAK811_TRACKER.build.cmsis_lib_gcc=arm_cortexM3l_math +RAK.menu.ram.xB=16Kb (default) +RAK.menu.ram.xB.upload.maximum_data_size=16384 +RAK.menu.ram.xB.build.ldscript=ldscript.ld +RAK.menu.ram.xB.build.product_line=STM32L151xB +RAK.menu.ram.xBA=32Kb +RAK.menu.ram.xBA.upload.maximum_data_size=32768 +RAK.menu.ram.xBA.build.ldscript=ldscript_xba.ld +RAK.menu.ram.xBA.build.product_line=STM32L151xBA + # Upload menu RAK.menu.upload_method.serialMethod=Serial RAK.menu.upload_method.serialMethod.upload.protocol=maple_serial diff --git a/variants/RAK811_TRACKER/PeripheralPins.c b/variants/RAK811_TRACKER/PeripheralPins.c index 4762cbb81b..d2fc4bf6bd 100644 --- a/variants/RAK811_TRACKER/PeripheralPins.c +++ b/variants/RAK811_TRACKER/PeripheralPins.c @@ -26,7 +26,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* - * Automatically generated from STM32L151C(6-8-B)Tx.xml + * Automatically generated from STM32L151C(6-8-B)Tx(A).xml */ #include "Arduino.h" #include "PeripheralPins.h" diff --git a/variants/RAK811_TRACKER/ldscript_xba.ld b/variants/RAK811_TRACKER/ldscript_xba.ld new file mode 100644 index 0000000000..a9514a88cc --- /dev/null +++ b/variants/RAK811_TRACKER/ldscript_xba.ld @@ -0,0 +1,169 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L151CBTxA Device with +** 128KByte FLASH, 32KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text ALIGN(4): + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata ALIGN(4): + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + From 4919790f67495ebdc3547aa1b96ade46967a178a Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 26 Sep 2018 17:31:01 +0200 Subject: [PATCH 079/109] Fix wrong define thanks to sm32duino forum user who report this here: http://stm32duino.com/viewtopic.php?f=29&t=4159 Signed-off-by: Frederic.Pillon --- cores/arduino/HardwareSerial.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 2706ed05aa..d4157354b9 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -33,7 +33,7 @@ #if defined(HAL_UART_MODULE_ENABLED) #if defined(HAVE_HWSERIAL1) || defined(HAVE_HWSERIAL2) || defined(HAVE_HWSERIAL3) ||\ defined(HAVE_HWSERIAL4) || defined(HAVE_HWSERIAL5) || defined(HAVE_HWSERIAL6) ||\ - defined(HAVE_HWSERIAL7) || defined(HAVE_HWSERIAL8) || defined(HAVE_HWSERIAL8) ||\ + defined(HAVE_HWSERIAL7) || defined(HAVE_HWSERIAL8) || defined(HAVE_HWSERIAL9) ||\ defined(HAVE_HWSERIAL10) || defined(HAVE_HWSERIALLP1) // SerialEvent functions are weak, so when the user doesn't define them, // the linker just sets their address to 0 (which is checked below). From 8d6f69f1717d629714ab6b960e0da3a33ac3a2f0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 28 Sep 2018 11:08:52 +0200 Subject: [PATCH 080/109] Update README.md --- README.md | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index a9f49e618c..3dea51c7b7 100644 --- a/README.md +++ b/README.md @@ -3,13 +3,25 @@ [![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...master) [![Build Status](https://travis-ci.com/stm32duino/Arduino_Core_STM32.svg?branch=master)](https://travis-ci.com/stm32duino/Arduino_Core_STM32) -**Warning**: release versioning has been changed from date versioning to semantic one. See [Release Versioning change](https://github.com/stm32duino/wiki/wiki/Release-Versioning-change) - +* [Introduction](https://github.com/stm32duino/Arduino_Core_STM32#Introduction)
          * [Getting Started](https://github.com/stm32duino/Arduino_Core_STM32#getting-started)
          * [Boards available](https://github.com/stm32duino/Arduino_Core_STM32#boards-available)
          * [Troubleshooting](https://github.com/stm32duino/Arduino_Core_STM32#troubleshooting)
          * [Wiki](https://github.com/stm32duino/wiki/wiki/) +## Introduction + +This repo adds the support of STM32 MCU in Arduino IDE.
          + +This porting is based on: +* [STM32Cube MCU Packages](https://www.st.com/en/embedded-software/stm32cube-mcu-packages.html) including: + * The HAL hardware abstraction layer, enabling portability between different STM32 devices via standardized API calls + * The Low-Layer (LL) APIs, a light-weight, optimized, expert oriented set of APIs designed for both performance and runtime efficiency + * CMSIS device defintion for STM32 +* [CMSIS](https://developer.arm.com/embedded/cmsis): Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex®-M processor series and defines generic tool interfaces. It has been packaged as a module for Arduino IDE: https://github.com/stm32duino/ArduinoModule-CMSIS +* [GNU Arm Embedded Toolchain](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm): Arm Embedded GCC compiler, libraries and other GNU tools necessary for bare-metal software development on devices based on the Arm Cortex-M. Packages are provided thanks: https://github.com/stm32duino/arm-none-eabi-gcc + + ## Getting Started This repo is available as a package usable with [Arduino Boards Manager](https://www.arduino.cc/en/guide/cores). @@ -21,7 +33,9 @@ https://github.com/stm32duino/BoardManagerFiles/raw/master/STM32/package_stm_ind For full instructions on using the "**Boards Manager**", see the [Getting Started](https://github.com/stm32duino/wiki/wiki/Getting-Started) page. -For advanced user, you can use the repository: see the [Using git repository](https://github.com/stm32duino/wiki/wiki/Using-git-repository) page. +Advanced user can use the repository to benefit from the latest development. See the [Using git repository](https://github.com/stm32duino/wiki/wiki/Using-git-repository) page. + +User can add a STM32 based board following this [wiki](https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-(board)). ## Boards available ### Current release From 621d235c770621cb377decdf4ba9c3e262fc227b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 1 Oct 2018 10:02:07 +0200 Subject: [PATCH 081/109] Update README.md --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 3dea51c7b7..d97e08f4b4 100644 --- a/README.md +++ b/README.md @@ -86,6 +86,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d ### Next release * STM32F4 * [Black F407VET6](http://wiki.stm32duino.com/index.php?title=STM32F407#.22Black_VET6.22_STM32F407VET6_Variant) + * [Blue F407VET6 Mini](http://wiki.stm32duino.com/index.php?title=Vcc-gnd.com_STM32F407VET6_Mini) * STM32F7 * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) From e872a357aed81a2eb93e2f134a94e073160b5f52 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 1 Oct 2018 10:23:31 +0200 Subject: [PATCH 082/109] Update README.md --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index d97e08f4b4..1d6da38a12 100644 --- a/README.md +++ b/README.md @@ -92,6 +92,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) * [RemRam v1](https://github.com/hasenbanck/remram) + * STM32L0 + * [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) (Basic support) + * STM32L4 * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) * [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) From f2c571e127ae7d0d3c8441587b724c4a34842fe1 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 1 Oct 2018 12:22:55 +0200 Subject: [PATCH 083/109] Add keywords.txt First version of the keywords.txt. It is not exhaustive. Fix #273 Signed-off-by: Frederic.Pillon --- keywords.txt | 825 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 825 insertions(+) create mode 100644 keywords.txt diff --git a/keywords.txt b/keywords.txt new file mode 100644 index 0000000000..13b979ebea --- /dev/null +++ b/keywords.txt @@ -0,0 +1,825 @@ +# Language keywords +constexpr LITERAL1 +nullptr LITERAL1 +noexcept LITERAL1 +static_assert LITERAL1 + +# Constants +# Digital +D0 LITERAL1 +D1 LITERAL1 +D2 LITERAL1 +D3 LITERAL1 +D4 LITERAL1 +D5 LITERAL1 +D6 LITERAL1 +D7 LITERAL1 +D8 LITERAL1 +D9 LITERAL1 +D10 LITERAL1 +D11 LITERAL1 +D12 LITERAL1 +D13 LITERAL1 +D14 LITERAL1 +D15 LITERAL1 +D16 LITERAL1 +D17 LITERAL1 +D18 LITERAL1 +D19 LITERAL1 +D20 LITERAL1 +D21 LITERAL1 +D22 LITERAL1 +D23 LITERAL1 +D24 LITERAL1 +D25 LITERAL1 +D26 LITERAL1 +D27 LITERAL1 +D28 LITERAL1 +D29 LITERAL1 +D30 LITERAL1 +D31 LITERAL1 +D32 LITERAL1 +D33 LITERAL1 +D34 LITERAL1 +D35 LITERAL1 +D36 LITERAL1 +D37 LITERAL1 +D38 LITERAL1 +D39 LITERAL1 +D40 LITERAL1 +D41 LITERAL1 +D42 LITERAL1 +D43 LITERAL1 +D44 LITERAL1 +D45 LITERAL1 +D46 LITERAL1 +D47 LITERAL1 +D48 LITERAL1 +D49 LITERAL1 +D50 LITERAL1 +D51 LITERAL1 +D52 LITERAL1 +D53 LITERAL1 +D54 LITERAL1 +D55 LITERAL1 +D56 LITERAL1 +D57 LITERAL1 +D58 LITERAL1 +D59 LITERAL1 +D60 LITERAL1 +D61 LITERAL1 +D62 LITERAL1 +D63 LITERAL1 +D64 LITERAL1 +D65 LITERAL1 +D66 LITERAL1 +D67 LITERAL1 +D68 LITERAL1 +D69 LITERAL1 +D70 LITERAL1 +D71 LITERAL1 +D72 LITERAL1 +D73 LITERAL1 +D74 LITERAL1 +D75 LITERAL1 +D76 LITERAL1 +D77 LITERAL1 +D78 LITERAL1 +D79 LITERAL1 +D80 LITERAL1 +D81 LITERAL1 +D82 LITERAL1 +D83 LITERAL1 +D84 LITERAL1 +D85 LITERAL1 +D86 LITERAL1 +D87 LITERAL1 +D88 LITERAL1 +D89 LITERAL1 +D90 LITERAL1 +D91 LITERAL1 +D92 LITERAL1 +D93 LITERAL1 +D94 LITERAL1 +D95 LITERAL1 +D96 LITERAL1 +D97 LITERAL1 +D98 LITERAL1 +D99 LITERAL1 +D100 LITERAL1 +D101 LITERAL1 +D102 LITERAL1 +D103 LITERAL1 +D104 LITERAL1 +D105 LITERAL1 +D106 LITERAL1 +D107 LITERAL1 +D108 LITERAL1 +D109 LITERAL1 +D110 LITERAL1 +D111 LITERAL1 +D112 LITERAL1 +D113 LITERAL1 +D114 LITERAL1 +D115 LITERAL1 +D116 LITERAL1 +D117 LITERAL1 +D118 LITERAL1 +D119 LITERAL1 +D120 LITERAL1 +D121 LITERAL1 +D122 LITERAL1 +D123 LITERAL1 +D124 LITERAL1 +D125 LITERAL1 +D126 LITERAL1 +D127 LITERAL1 +D128 LITERAL1 +D129 LITERAL1 +D130 LITERAL1 +D131 LITERAL1 +D132 LITERAL1 +D133 LITERAL1 +D134 LITERAL1 +D135 LITERAL1 +D136 LITERAL1 +D137 LITERAL1 +D138 LITERAL1 +D139 LITERAL1 +D140 LITERAL1 +D141 LITERAL1 +D142 LITERAL1 +D143 LITERAL1 +D144 LITERAL1 +D145 LITERAL1 +D146 LITERAL1 +D147 LITERAL1 +D148 LITERAL1 +D149 LITERAL1 +D150 LITERAL1 +D151 LITERAL1 +D152 LITERAL1 +D153 LITERAL1 +D154 LITERAL1 +D155 LITERAL1 +D156 LITERAL1 +D157 LITERAL1 +D158 LITERAL1 +D159 LITERAL1 +D160 LITERAL1 +D161 LITERAL1 +D162 LITERAL1 +D163 LITERAL1 +D164 LITERAL1 +D165 LITERAL1 +D166 LITERAL1 +D167 LITERAL1 +D168 LITERAL1 +D169 LITERAL1 +D170 LITERAL1 +D171 LITERAL1 +D172 LITERAL1 +D173 LITERAL1 +D174 LITERAL1 +D175 LITERAL1 +DMAX LITERAL1 + +# Analog +A0 LITERAL1 +A1 LITERAL1 +A2 LITERAL1 +A3 LITERAL1 +A4 LITERAL1 +A5 LITERAL1 +A6 LITERAL1 +A7 LITERAL1 +A8 LITERAL1 +A9 LITERAL1 +A10 LITERAL1 +A11 LITERAL1 +A12 LITERAL1 +A13 LITERAL1 +A14 LITERAL1 +A15 LITERAL1 +A16 LITERAL1 +A17 LITERAL1 +A18 LITERAL1 +A19 LITERAL1 +A20 LITERAL1 +A21 LITERAL1 +A22 LITERAL1 +A23 LITERAL1 +PIN_A0 LITERAL1 +PIN_A1 LITERAL1 +PIN_A2 LITERAL1 +PIN_A3 LITERAL1 +PIN_A4 LITERAL1 +PIN_A5 LITERAL1 +PIN_A6 LITERAL1 +PIN_A7 LITERAL1 +PIN_A8 LITERAL1 +PIN_A9 LITERAL1 +PIN_A10 LITERAL1 +PIN_A11 LITERAL1 +PIN_A12 LITERAL1 +PIN_A13 LITERAL1 +PIN_A14 LITERAL1 +PIN_A15 LITERAL1 +PIN_A16 LITERAL1 +PIN_A17 LITERAL1 +PIN_A18 LITERAL1 +PIN_A19 LITERAL1 +PIN_A20 LITERAL1 +PIN_A21 LITERAL1 +PIN_A22 LITERAL1 +PIN_A23 LITERAL1 + +NUM_DIGITAL_PINS LITERAL1 +NUM_ANALOG_INPUTS LITERAL1 +NUM_ANALOG_FIRST LITERAL1 +MAX_ANALOG_INPUTS LITERAL1 +NOT_AN_INTERRUPT LITERAL1 + +# SPI +SS LITERAL1 +SS1 LITERAL1 +SS2 LITERAL1 +SS3 LITERAL1 +MOSI LITERAL1 +MISO LITERAL1 +SCK LITERAL1 +PIN_SPI_SS LITERAL1 +PIN_SPI_SS1 LITERAL1 +PIN_SPI_SS2 LITERAL1 +PIN_SPI_SS3 LITERAL1 +PIN_SPI_MOSI LITERAL1 +PIN_SPI_MISO LITERAL1 +PIN_SPI_SCK LITERAL1 + +# Wire +SDA LITERAL1 +SCL LITERAL1 +PIN_WIRE_SDA LITERAL1 +PIN_WIRE_SCL LITERAL1 + +# Serial +HardwareSerial KEYWORD2 +setRX KEYWORD2 +setTX KEYWORD2 +Serial4 KEYWORD1 +Serial5 KEYWORD1 +Serial6 KEYWORD1 +Serial7 KEYWORD1 +Serial8 KEYWORD1 +Serial9 KEYWORD1 +Serial10 KEYWORD1 +SerialLP1 KEYWORD1 +SERIAL_RX_BUFFER_SIZE LITERAL1 +SERIAL_TX_BUFFER_SIZE LITERAL1 +DEBUG_UART LITERAL1 +DEBUG_PINNAME_TX LITERAL1 +DEBUG_UART_BAUDRATE LITERAL1 +PIN_SERIAL_RX LITERAL1 +PIN_SERIAL_TX LITERAL1 +PIN_SERIAL1_RX LITERAL1 +PIN_SERIAL1_TX LITERAL1 +PIN_SERIAL2_RX LITERAL1 +PIN_SERIAL2_TX LITERAL1 +PIN_SERIAL3_RX LITERAL1 +PIN_SERIAL3_TX LITERAL1 +PIN_SERIAL4_RX LITERAL1 +PIN_SERIAL4_TX LITERAL1 +PIN_SERIAL5_RX LITERAL1 +PIN_SERIAL5_TX LITERAL1 +PIN_SERIAL6_RX LITERAL1 +PIN_SERIAL6_TX LITERAL1 +PIN_SERIAL7_RX LITERAL1 +PIN_SERIAL7_TX LITERAL1 +PIN_SERIAL8_RX LITERAL1 +PIN_SERIAL8_TX LITERAL1 +PIN_SERIAL9_RX LITERAL1 +PIN_SERIAL9_TX LITERAL1 +PIN_SERIAL10_RX LITERAL1 +PIN_SERIAL10_TX LITERAL1 +PIN_SERIALLP1_RX LITERAL1 +PIN_SERIALLP1_TX LITERAL1 +SERIAL_PORT_MONITOR LITERAL1 +SERIAL_PORT_HARDWARE LITERAL1 +SERIAL_7N1 LITERAL1 +SERIAL_7N2 LITERAL1 +SERIAL_6E1 LITERAL1 +SERIAL_6E2 LITERAL1 +SERIAL_6O1 LITERAL1 +SERIAL_6O2 LITERAL1 +SERIAL_8N1 LITERAL1 +SERIAL_8N2 LITERAL1 +SERIAL_7E1 LITERAL1 +SERIAL_8E1 LITERAL1 +SERIAL_7E2 LITERAL1 +SERIAL_8E2 LITERAL1 +SERIAL_7O1 LITERAL1 +SERIAL_8O1 LITERAL1 +SERIAL_7O2 LITERAL1 +SERIAL_8O2 LITERAL1 + +ADC_RESOLUTION LITERAL1 +DACC_RESOLUTION LITERAL1 +PWM_RESOLUTION LITERAL1 +PWM_FREQUENCY LITERAL1 +PWM_MAX_DUTY_CYCLE LITERAL1 +INPUT_PULLDOWN LITERAL1 +USER_BTN LITERAL1 +LED_GREEN LITERAL1 +LED_BLUE LITERAL1 +LED_RED LITERAL1 + +digitalPinToPinName KEYWORD2 +analogInputToDigitalPin KEYWORD2 +digitalPinHasI2C KEYWORD2 +digitalPinHasPWM KEYWORD2 +digitalPinHasSerial KEYWORD2 +digitalPinHasSPI KEYWORD2 +digitalPinToPort KEYWORD2 +digitalPinToBitMask KEYWORD2 +analogInPinToBit KEYWORD2 +portOutputRegister KEYWORD2 +portInputRegister KEYWORD2 +portSetRegister KEYWORD2 +portModeRegister KEYWORD2 +portConfigRegister KEYWORD2 +digitalPinIsValid KEYWORD2 +digitalPinFirstOccurence KEYWORD2 +pinIsSerial KEYWORD2 + +# Pin number +PA0 LITERAL1 +PA1 LITERAL1 +PA2 LITERAL1 +PA3 LITERAL1 +PA4 LITERAL1 +PA5 LITERAL1 +PA6 LITERAL1 +PA7 LITERAL1 +PA8 LITERAL1 +PA9 LITERAL1 +PA10 LITERAL1 +PA11 LITERAL1 +PA12 LITERAL1 +PA13 LITERAL1 +PA14 LITERAL1 +PA15 LITERAL1 +PB0 LITERAL1 +PB1 LITERAL1 +PB2 LITERAL1 +PB3 LITERAL1 +PB4 LITERAL1 +PB5 LITERAL1 +PB6 LITERAL1 +PB7 LITERAL1 +PB8 LITERAL1 +PB9 LITERAL1 +PB10 LITERAL1 +PB11 LITERAL1 +PB12 LITERAL1 +PB13 LITERAL1 +PB14 LITERAL1 +PB15 LITERAL1 +PC0 LITERAL1 +PC1 LITERAL1 +PC2 LITERAL1 +PC3 LITERAL1 +PC4 LITERAL1 +PC5 LITERAL1 +PC6 LITERAL1 +PC7 LITERAL1 +PC8 LITERAL1 +PC9 LITERAL1 +PC10 LITERAL1 +PC11 LITERAL1 +PC12 LITERAL1 +PC13 LITERAL1 +PC14 LITERAL1 +PC15 LITERAL1 +PD0 LITERAL1 +PD1 LITERAL1 +PD2 LITERAL1 +PD3 LITERAL1 +PD4 LITERAL1 +PD5 LITERAL1 +PD6 LITERAL1 +PD7 LITERAL1 +PD8 LITERAL1 +PD9 LITERAL1 +PD10 LITERAL1 +PD11 LITERAL1 +PD12 LITERAL1 +PD13 LITERAL1 +PD14 LITERAL1 +PD15 LITERAL1 +PE0 LITERAL1 +PE1 LITERAL1 +PE2 LITERAL1 +PE3 LITERAL1 +PE4 LITERAL1 +PE5 LITERAL1 +PE6 LITERAL1 +PE7 LITERAL1 +PE8 LITERAL1 +PE9 LITERAL1 +PE10 LITERAL1 +PE11 LITERAL1 +PE12 LITERAL1 +PE13 LITERAL1 +PE14 LITERAL1 +PE15 LITERAL1 +PF0 LITERAL1 +PF1 LITERAL1 +PF2 LITERAL1 +PF3 LITERAL1 +PF4 LITERAL1 +PF5 LITERAL1 +PF6 LITERAL1 +PF7 LITERAL1 +PF8 LITERAL1 +PF9 LITERAL1 +PF10 LITERAL1 +PF11 LITERAL1 +PF12 LITERAL1 +PF13 LITERAL1 +PF14 LITERAL1 +PF15 LITERAL1 +PG0 LITERAL1 +PG1 LITERAL1 +PG2 LITERAL1 +PG3 LITERAL1 +PG4 LITERAL1 +PG5 LITERAL1 +PG6 LITERAL1 +PG7 LITERAL1 +PG8 LITERAL1 +PG9 LITERAL1 +PG10 LITERAL1 +PG11 LITERAL1 +PG12 LITERAL1 +PG13 LITERAL1 +PG14 LITERAL1 +PG15 LITERAL1 +PH0 LITERAL1 +PH1 LITERAL1 +PH2 LITERAL1 +PH3 LITERAL1 +PH4 LITERAL1 +PH5 LITERAL1 +PH6 LITERAL1 +PH7 LITERAL1 +PH8 LITERAL1 +PH9 LITERAL1 +PH10 LITERAL1 +PH11 LITERAL1 +PH12 LITERAL1 +PH13 LITERAL1 +PH14 LITERAL1 +PH15 LITERAL1 +PI0 LITERAL1 +PI1 LITERAL1 +PI2 LITERAL1 +PI3 LITERAL1 +PI4 LITERAL1 +PI5 LITERAL1 +PI6 LITERAL1 +PI7 LITERAL1 +PI8 LITERAL1 +PI9 LITERAL1 +PI10 LITERAL1 +PI11 LITERAL1 +PI12 LITERAL1 +PI13 LITERAL1 +PI14 LITERAL1 +PI15 LITERAL1 +PJ0 LITERAL1 +PJ1 LITERAL1 +PJ2 LITERAL1 +PJ3 LITERAL1 +PJ4 LITERAL1 +PJ5 LITERAL1 +PJ6 LITERAL1 +PJ7 LITERAL1 +PJ8 LITERAL1 +PJ9 LITERAL1 +PJ10 LITERAL1 +PJ11 LITERAL1 +PJ12 LITERAL1 +PJ13 LITERAL1 +PJ14 LITERAL1 +PJ15 LITERAL1 +PK0 LITERAL1 +PK1 LITERAL1 +PK2 LITERAL1 +PK3 LITERAL1 +PK4 LITERAL1 +PK5 LITERAL1 +PK6 LITERAL1 +PK7 LITERAL1 +PK8 LITERAL1 +PK9 LITERAL1 +PK10 LITERAL1 +PK11 LITERAL1 +PK12 LITERAL1 +PK13 LITERAL1 +PK14 LITERAL1 +PK15 LITERAL1 + +# Pin name +PinName KEYWORD3 +NC LITERAL1 +PA_0 LITERAL1 +PA_1 LITERAL1 +PA_2 LITERAL1 +PA_3 LITERAL1 +PA_4 LITERAL1 +PA_5 LITERAL1 +PA_6 LITERAL1 +PA_7 LITERAL1 +PA_8 LITERAL1 +PA_9 LITERAL1 +PA_10 LITERAL1 +PA_11 LITERAL1 +PA_12 LITERAL1 +PA_13 LITERAL1 +PA_14 LITERAL1 +PA_15 LITERAL1 +PB_0 LITERAL1 +PB_1 LITERAL1 +PB_2 LITERAL1 +PB_3 LITERAL1 +PB_4 LITERAL1 +PB_5 LITERAL1 +PB_6 LITERAL1 +PB_7 LITERAL1 +PB_8 LITERAL1 +PB_9 LITERAL1 +PB_10 LITERAL1 +PB_11 LITERAL1 +PB_12 LITERAL1 +PB_13 LITERAL1 +PB_14 LITERAL1 +PB_15 LITERAL1 +PC_0 LITERAL1 +PC_1 LITERAL1 +PC_2 LITERAL1 +PC_3 LITERAL1 +PC_4 LITERAL1 +PC_5 LITERAL1 +PC_6 LITERAL1 +PC_7 LITERAL1 +PC_8 LITERAL1 +PC_9 LITERAL1 +PC_10 LITERAL1 +PC_11 LITERAL1 +PC_12 LITERAL1 +PC_13 LITERAL1 +PC_14 LITERAL1 +PC_15 LITERAL1 +PD_0 LITERAL1 +PD_1 LITERAL1 +PD_2 LITERAL1 +PD_3 LITERAL1 +PD_4 LITERAL1 +PD_5 LITERAL1 +PD_6 LITERAL1 +PD_7 LITERAL1 +PD_8 LITERAL1 +PD_9 LITERAL1 +PD_10 LITERAL1 +PD_11 LITERAL1 +PD_12 LITERAL1 +PD_13 LITERAL1 +PD_14 LITERAL1 +PD_15 LITERAL1 +PE_0 LITERAL1 +PE_1 LITERAL1 +PE_2 LITERAL1 +PE_3 LITERAL1 +PE_4 LITERAL1 +PE_5 LITERAL1 +PE_6 LITERAL1 +PE_7 LITERAL1 +PE_8 LITERAL1 +PE_9 LITERAL1 +PE_10 LITERAL1 +PE_11 LITERAL1 +PE_12 LITERAL1 +PE_13 LITERAL1 +PE_14 LITERAL1 +PE_15 LITERAL1 +PF_0 LITERAL1 +PF_1 LITERAL1 +PF_2 LITERAL1 +PF_3 LITERAL1 +PF_4 LITERAL1 +PF_5 LITERAL1 +PF_6 LITERAL1 +PF_7 LITERAL1 +PF_8 LITERAL1 +PF_9 LITERAL1 +PF_10 LITERAL1 +PF_11 LITERAL1 +PF_12 LITERAL1 +PF_13 LITERAL1 +PF_14 LITERAL1 +PF_15 LITERAL1 +PG_0 LITERAL1 +PG_1 LITERAL1 +PG_2 LITERAL1 +PG_3 LITERAL1 +PG_4 LITERAL1 +PG_5 LITERAL1 +PG_6 LITERAL1 +PG_7 LITERAL1 +PG_8 LITERAL1 +PG_9 LITERAL1 +PG_10 LITERAL1 +PG_11 LITERAL1 +PG_12 LITERAL1 +PG_13 LITERAL1 +PG_14 LITERAL1 +PG_15 LITERAL1 +PH_0 LITERAL1 +PH_1 LITERAL1 +PH_2 LITERAL1 +PH_3 LITERAL1 +PH_4 LITERAL1 +PH_5 LITERAL1 +PH_6 LITERAL1 +PH_7 LITERAL1 +PH_8 LITERAL1 +PH_9 LITERAL1 +PH_10 LITERAL1 +PH_11 LITERAL1 +PH_12 LITERAL1 +PH_13 LITERAL1 +PH_14 LITERAL1 +PH_15 LITERAL1 +PI_0 LITERAL1 +PI_1 LITERAL1 +PI_2 LITERAL1 +PI_3 LITERAL1 +PI_4 LITERAL1 +PI_5 LITERAL1 +PI_6 LITERAL1 +PI_7 LITERAL1 +PI_8 LITERAL1 +PI_9 LITERAL1 +PI_10 LITERAL1 +PI_11 LITERAL1 +PI_12 LITERAL1 +PI_13 LITERAL1 +PI_14 LITERAL1 +PI_15 LITERAL1 +PJ_0 LITERAL1 +PJ_1 LITERAL1 +PJ_2 LITERAL1 +PJ_3 LITERAL1 +PJ_4 LITERAL1 +PJ_5 LITERAL1 +PJ_6 LITERAL1 +PJ_7 LITERAL1 +PJ_8 LITERAL1 +PJ_9 LITERAL1 +PJ_10 LITERAL1 +PJ_11 LITERAL1 +PJ_12 LITERAL1 +PJ_13 LITERAL1 +PJ_14 LITERAL1 +PJ_15 LITERAL1 +PK_0 LITERAL1 +PK_1 LITERAL1 +PK_2 LITERAL1 +PK_3 LITERAL1 +PK_4 LITERAL1 +PK_5 LITERAL1 +PK_6 LITERAL1 +PK_7 LITERAL1 +PK_8 LITERAL1 +PK_9 LITERAL1 +PK_10 LITERAL1 +PK_11 LITERAL1 +PK_12 LITERAL1 +PK_13 LITERAL1 +PK_14 LITERAL1 +PK_15 LITERAL1 + +# Port Name +PortName KEYWORD3 +FirstPort +PortA LITERAL1 +PortB LITERAL1 +PortC LITERAL1 +PortD LITERAL1 +PortE LITERAL1 +PortF LITERAL1 +PortG LITERAL1 +PortH LITERAL1 +PortI LITERAL1 +PortJ LITERAL1 +PortK LITERAL1 +LastPort LITERAL1 + + +# STM32 +# Peripheral name +SPI1 LITERAL1 +SPI2 LITERAL1 +SPI3 LITERAL1 +SPI4 LITERAL1 +SPI5 LITERAL1 +SPI6 LITERAL1 +I2C1 LITERAL1 +I2C2 LITERAL1 +I2C3 LITERAL1 +I2C4 LITERAL1 +I2C5 LITERAL1 +I2C6 LITERAL1 +I2S1 LITERAL1 +I2S2 LITERAL1 +I2S3 LITERAL1 +TIM1 LITERAL1 +TIM2 LITERAL1 +TIM3 LITERAL1 +TIM4 LITERAL1 +TIM5 LITERAL1 +TIM6 LITERAL1 +TIM7 LITERAL1 +TIM8 LITERAL1 +TIM9 LITERAL1 +TIM10 LITERAL1 +TIM11 LITERAL1 +TIM12 LITERAL1 +TIM13 LITERAL1 +TIM14 LITERAL1 +TIM15 LITERAL1 +TIM16 LITERAL1 +TIM17 LITERAL1 +TIM18 LITERAL1 +TIM19 LITERAL1 +TIM20 LITERAL1 +TIM21 LITERAL1 +TIM22 LITERAL1 +TIM23 LITERAL1 +TIM24 LITERAL1 +USART1 LITERAL1 +USART2 LITERAL1 +USART3 LITERAL1 +UART4 LITERAL1 +USART4 LITERAL1 +UART5 LITERAL1 +USART5 LITERAL1 +USART6 LITERAL1 +USART7 LITERAL1 +UART8 LITERAL1 +UART9 LITERAL1 +UART10 LITERAL1 +LPUART1 LITERAL1 + +# Port +GPIOA_BASE LITERAL1 +GPIOB_BASE LITERAL1 +GPIOC_BASE LITERAL1 +GPIOD_BASE LITERAL1 +GPIOE_BASE LITERAL1 +GPIOF_BASE LITERAL1 +GPIOG_BASE LITERAL1 +GPIOH_BASE LITERAL1 +GPIOI_BASE LITERAL1 +GPIOJ_BASE LITERAL1 +GPIOK_BASE LITERAL1 + +GPIOA LITERAL1 +GPIOB LITERAL1 +GPIOC LITERAL1 +GPIOD LITERAL1 +GPIOE LITERAL1 +GPIOF LITERAL1 +GPIOG LITERAL1 +GPIOH LITERAL1 +GPIOI LITERAL1 +GPIOJ LITERAL1 +GPIOK LITERAL1 + +# Pin +GPIO_PIN_0 LITERAL1 +GPIO_PIN_1 LITERAL1 +GPIO_PIN_2 LITERAL1 +GPIO_PIN_3 LITERAL1 +GPIO_PIN_4 LITERAL1 +GPIO_PIN_5 LITERAL1 +GPIO_PIN_6 LITERAL1 +GPIO_PIN_7 LITERAL1 +GPIO_PIN_8 LITERAL1 +GPIO_PIN_9 LITERAL1 +GPIO_PIN_10 LITERAL1 +GPIO_PIN_11 LITERAL1 +GPIO_PIN_12 LITERAL1 +GPIO_PIN_13 LITERAL1 +GPIO_PIN_14 LITERAL1 +GPIO_PIN_15 LITERAL1 From 9830251e3d40f1c9ed5592850c99cb083445ec18 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 1 Oct 2018 14:31:02 +0200 Subject: [PATCH 084/109] Change hourAM_PM_t enum member name Add HOUR_ prefix. Require by STM32RTC library higher than 1.1.0 Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/rtc.c | 26 +++++++++++++------------- cores/arduino/stm32/rtc.h | 4 ++-- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/cores/arduino/stm32/rtc.c b/cores/arduino/stm32/rtc.c index 9b36e0da77..6f13237ea3 100644 --- a/cores/arduino/stm32/rtc.c +++ b/cores/arduino/stm32/rtc.c @@ -321,7 +321,7 @@ void RTC_init(hourFormat_t format, sourceClock_t source) RTC_SetDate(17, 1, 1, 7); /*at 0:0:0*/ - RTC_SetTime(0,0,0,0,AM); + RTC_SetTime(0,0,0,0,HOUR_AM); #if !defined(STM32F1xx) && !defined(STM32F2xx) && !defined(STM32L1xx) || defined(STM32L1_ULPH) /* Enable Direct Read of the calendar registers (not through Shadow) */ @@ -349,7 +349,7 @@ void RTC_DeInit(void) * @param minutes: 0-59 * @param seconds: 0-59 * @param subSeconds: 0-999 - * @param period: select AM or PM period in case RTC is set in 12 hours mode. Else ingored. + * @param period: select HOUR_AM or HOUR_PM period in case RTC is set in 12 hours mode. Else ingored. * @retval None */ void RTC_SetTime(uint8_t hours, uint8_t minutes, uint8_t seconds, uint32_t subSeconds, hourAM_PM_t period) @@ -358,7 +358,7 @@ void RTC_SetTime(uint8_t hours, uint8_t minutes, uint8_t seconds, uint32_t subSe /* Ignore time AM PM configuration if in 24 hours format */ if(initFormat == HOUR_FORMAT_24) { - period = AM; + period = HOUR_AM; } if((((initFormat == HOUR_FORMAT_24) && IS_RTC_HOUR24(hours)) || IS_RTC_HOUR12(hours)) @@ -367,7 +367,7 @@ void RTC_SetTime(uint8_t hours, uint8_t minutes, uint8_t seconds, uint32_t subSe RTC_TimeStruct.Minutes = minutes; RTC_TimeStruct.Seconds = seconds; #if !defined(STM32F1xx) - if(period == PM) { + if(period == HOUR_PM) { RTC_TimeStruct.TimeFormat = RTC_HOURFORMAT12_PM; } else { RTC_TimeStruct.TimeFormat = RTC_HOURFORMAT12_AM; @@ -395,7 +395,7 @@ void RTC_SetTime(uint8_t hours, uint8_t minutes, uint8_t seconds, uint32_t subSe * @param minutes: 0-59 * @param seconds: 0-59 * @param subSeconds: 0-999 (optional could be NULL) - * @param period: AM or PM period in case RTC is set in 12 hours mode (optional could be NULL). + * @param period: HOUR_AM or HOUR_PM period in case RTC is set in 12 hours mode (optional could be NULL). * @retval None */ void RTC_GetTime(uint8_t *hours, uint8_t *minutes, uint8_t *seconds, uint32_t *subSeconds, hourAM_PM_t *period) @@ -410,9 +410,9 @@ void RTC_GetTime(uint8_t *hours, uint8_t *minutes, uint8_t *seconds, uint32_t *s #if !defined(STM32F1xx) if(period != NULL) { if(RTC_TimeStruct.TimeFormat == RTC_HOURFORMAT12_PM) { - *period = PM; + *period = HOUR_PM; } else { - *period = AM; + *period = HOUR_AM; } } #if (!defined(STM32F2xx) && !defined(STM32L1xx)) || defined(STM32L1_ULPH) @@ -478,7 +478,7 @@ void RTC_GetDate(uint8_t *year, uint8_t *month, uint8_t *day, uint8_t *wday) * @param minutes: 0-59 * @param seconds: 0-59 * @param subSeconds: 0-999 - * @param period: AM or PM if in 12 hours mode else ignored. + * @param period: HOUR_AM or HOUR_PM if in 12 hours mode else ignored. * @param mask: configure alarm behavior using alarmMask_t combination. * See AN4579 Table 5 for possible values. * @retval None @@ -489,7 +489,7 @@ void RTC_StartAlarm(uint8_t day, uint8_t hours, uint8_t minutes, uint8_t seconds /* Ignore time AM PM configuration if in 24 hours format */ if(initFormat == HOUR_FORMAT_24) { - period = AM; + period = HOUR_AM; } if((((initFormat == HOUR_FORMAT_24) && IS_RTC_HOUR24(hours)) || IS_RTC_HOUR12(hours)) @@ -507,7 +507,7 @@ void RTC_StartAlarm(uint8_t day, uint8_t hours, uint8_t minutes, uint8_t seconds #else UNUSED(subSeconds); #endif /* !STM32F2xx && !STM32L1xx || STM32L1_ULPH */ - if(period == PM) { + if(period == HOUR_PM) { RTC_AlarmStructure.AlarmTime.TimeFormat = RTC_HOURFORMAT12_PM; } else { RTC_AlarmStructure.AlarmTime.TimeFormat = RTC_HOURFORMAT12_AM; @@ -567,7 +567,7 @@ void RTC_StopAlarm(void) * @param minutes: 0-59 * @param seconds: 0-59 * @param subSeconds: 0-999 (optional could be NULL) - * @param period: AM or PM (optional could be NULL) + * @param period: HOUR_AM or HOUR_PM (optional could be NULL) * @param mask: alarm behavior using alarmMask_t combination (optional could be NULL) * See AN4579 Table 5 for possible values * @retval None @@ -589,9 +589,9 @@ void RTC_GetAlarm(uint8_t *day, uint8_t *hours, uint8_t *minutes, uint8_t *secon } if(period != NULL) { if(RTC_AlarmStructure.AlarmTime.TimeFormat == RTC_HOURFORMAT12_PM) { - *period = PM; + *period = HOUR_PM; } else { - *period = AM; + *period = HOUR_AM; } } #if !defined(STM32F2xx) && !defined(STM32L1xx) || defined(STM32L1_ULPH) diff --git a/cores/arduino/stm32/rtc.h b/cores/arduino/stm32/rtc.h index 729d0344d1..8750c4218f 100644 --- a/cores/arduino/stm32/rtc.h +++ b/cores/arduino/stm32/rtc.h @@ -55,8 +55,8 @@ typedef enum { } hourFormat_t; typedef enum { - AM, - PM + HOUR_AM, + HOUR_PM } hourAM_PM_t; /* See AN4579 Table 5 for possible values */ From 3ec6c0edd37da6ac510c6bcd917bd43ccc74cdaf Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Mon, 1 Oct 2018 15:48:07 +0200 Subject: [PATCH 085/109] Use a single tab field separator in keywords.txt Each field of keywords.txt is separated by a single true tab. When you use multiple tabs it causes the field to be interpreted as empty. On Arduino IDE 1.6.5 and newer an empty KEYWORD_TOKENTYPE causes the default editor.function.style highlighting to be used (as with KEYWORD2, KEYWORD3). On Arduino IDE 1.6.4 and older it causes the keyword to not be recognized for any special highlighting. Reference: https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5:-Library-specification#keywordsFix key Signed-off-by: Frederic.Pillon --- libraries/Mouse/keywords.txt | 2 +- libraries/SPI/keywords.txt | 26 +++++++++++++------------- libraries/Wire/keywords.txt | 16 ++++++++-------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/libraries/Mouse/keywords.txt b/libraries/Mouse/keywords.txt index 258c48eeba..fcccd0d412 100644 --- a/libraries/Mouse/keywords.txt +++ b/libraries/Mouse/keywords.txt @@ -17,7 +17,7 @@ click KEYWORD2 move KEYWORD2 press KEYWORD2 release KEYWORD2 -isPressed KEYWORD2 +isPressed KEYWORD2 ####################################### # Constants (LITERAL1) diff --git a/libraries/SPI/keywords.txt b/libraries/SPI/keywords.txt index 0ef26e8a41..18701284e0 100644 --- a/libraries/SPI/keywords.txt +++ b/libraries/SPI/keywords.txt @@ -11,24 +11,24 @@ SPI KEYWORD1 ####################################### # Methods and Functions (KEYWORD2) ####################################### -begin KEYWORD2 -end KEYWORD2 -transfer KEYWORD2 +begin KEYWORD2 +end KEYWORD2 +transfer KEYWORD2 #setBitOrder KEYWORD2 -setDataMode KEYWORD2 +setDataMode KEYWORD2 setClockDivider KEYWORD2 -setMISO KEYWORD2 -setMOSI KEYWORD2 -setSCLK KEYWORD2 -setSSEL KEYWORD2 +setMISO KEYWORD2 +setMOSI KEYWORD2 +setSCLK KEYWORD2 +setSSEL KEYWORD2 ####################################### # Constants (LITERAL1) ####################################### -SPI_MODE0 LITERAL1 -SPI_MODE1 LITERAL1 -SPI_MODE2 LITERAL1 -SPI_MODE3 LITERAL1 +SPI_MODE0 LITERAL1 +SPI_MODE1 LITERAL1 +SPI_MODE2 LITERAL1 +SPI_MODE3 LITERAL1 SPI_CONTINUE LITERAL1 -SPI_LAST LITERAL1 +SPI_LAST LITERAL1 diff --git a/libraries/Wire/keywords.txt b/libraries/Wire/keywords.txt index 30040d16d3..4c8cdf5a64 100644 --- a/libraries/Wire/keywords.txt +++ b/libraries/Wire/keywords.txt @@ -10,15 +10,15 @@ # Methods and Functions (KEYWORD2) ####################################### -begin KEYWORD2 -setClock KEYWORD2 +begin KEYWORD2 +setClock KEYWORD2 beginTransmission KEYWORD2 -endTransmission KEYWORD2 -requestFrom KEYWORD2 -onReceive KEYWORD2 -onRequest KEYWORD2 -setSCL KEYWORD2 -setSDA KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +onReceive KEYWORD2 +onRequest KEYWORD2 +setSCL KEYWORD2 +setSDA KEYWORD2 ####################################### # Instances (KEYWORD2) From 956de77e85da9609353a92dd292db9a6e45277c5 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 25 Sep 2018 10:24:30 +0200 Subject: [PATCH 086/109] Fix build.flags.ldspec usage -flto options was use twice at link time. Signed-off-by: Frederic.Pillon --- boards.txt | 73 ---------------------------------------------------- platform.txt | 2 +- 2 files changed, 1 insertion(+), 74 deletions(-) diff --git a/boards.txt b/boards.txt index d8e096c444..6f7a86ec22 100644 --- a/boards.txt +++ b/boards.txt @@ -750,235 +750,162 @@ Disco.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE Nucleo_144.menu.opt.osstd=Smallest (-Os default) Nucleo_144.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_144.menu.opt.oslto.build.flags.optimize=-Os -flto -Nucleo_144.menu.opt.oslto.build.flags.ldspecs=-flto Nucleo_144.menu.opt.o1std=Fast (-O1) Nucleo_144.menu.opt.o1std.build.flags.optimize=-O1 -Nucleo_144.menu.opt.o1std.build.flags.ldspecs= Nucleo_144.menu.opt.o1lto=Fast (-O1) with LTO Nucleo_144.menu.opt.o1lto.build.flags.optimize=-O1 -flto -Nucleo_144.menu.opt.o1lto.build.flags.ldspecs=-flto Nucleo_144.menu.opt.o2std=Faster (-O2) Nucleo_144.menu.opt.o2std.build.flags.optimize=-O2 -Nucleo_144.menu.opt.o2std.build.flags.ldspecs= Nucleo_144.menu.opt.o2lto=Faster (-O2) with LTO Nucleo_144.menu.opt.o2lto.build.flags.optimize=-O2 -flto -Nucleo_144.menu.opt.o2lto.build.flags.ldspecs=-flto Nucleo_144.menu.opt.o3std=Fastest (-O3) Nucleo_144.menu.opt.o3std.build.flags.optimize=-O3 -Nucleo_144.menu.opt.o3std.build.flags.ldspecs= Nucleo_144.menu.opt.o3lto=Fastest (-O3) with LTO Nucleo_144.menu.opt.o3lto.build.flags.optimize=-O3 -flto -Nucleo_144.menu.opt.o3lto.build.flags.ldspecs=-flto Nucleo_144.menu.opt.ogstd=Debug (-g) Nucleo_144.menu.opt.ogstd.build.flags.optimize=-g -Og -Nucleo_144.menu.opt.ogstd.build.flags.ldspecs= Nucleo_64.menu.opt.osstd=Smallest (-Os default) Nucleo_64.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_64.menu.opt.oslto.build.flags.optimize=-Os -flto -Nucleo_64.menu.opt.oslto.build.flags.ldspecs=-flto Nucleo_64.menu.opt.o1std=Fast (-O1) Nucleo_64.menu.opt.o1std.build.flags.optimize=-O1 -Nucleo_64.menu.opt.o1std.build.flags.ldspecs= Nucleo_64.menu.opt.o1lto=Fast (-O1) with LTO Nucleo_64.menu.opt.o1lto.build.flags.optimize=-O1 -flto -Nucleo_64.menu.opt.o1lto.build.flags.ldspecs=-flto Nucleo_64.menu.opt.o2std=Faster (-O2) Nucleo_64.menu.opt.o2std.build.flags.optimize=-O2 -Nucleo_64.menu.opt.o2std.build.flags.ldspecs= Nucleo_64.menu.opt.o2lto=Faster (-O2) with LTO Nucleo_64.menu.opt.o2lto.build.flags.optimize=-O2 -flto -Nucleo_64.menu.opt.o2lto.build.flags.ldspecs=-flto Nucleo_64.menu.opt.o3std=Fastest (-O3) Nucleo_64.menu.opt.o3std.build.flags.optimize=-O3 -Nucleo_64.menu.opt.o3std.build.flags.ldspecs= Nucleo_64.menu.opt.o3lto=Fastest (-O3) with LTO Nucleo_64.menu.opt.o3lto.build.flags.optimize=-O3 -flto -Nucleo_64.menu.opt.o3lto.build.flags.ldspecs=-flto Nucleo_64.menu.opt.ogstd=Debug (-g) Nucleo_64.menu.opt.ogstd.build.flags.optimize=-g -Og -Nucleo_64.menu.opt.ogstd.build.flags.ldspecs= Nucleo_32.menu.opt.osstd=Smallest (-Os default) Nucleo_32.menu.opt.oslto=Smallest (-Os) with LTO Nucleo_32.menu.opt.oslto.build.flags.optimize=-Os -flto -Nucleo_32.menu.opt.oslto.build.flags.ldspecs=-flto Nucleo_32.menu.opt.o1std=Fast (-O1) Nucleo_32.menu.opt.o1std.build.flags.optimize=-O1 -Nucleo_32.menu.opt.o1std.build.flags.ldspecs= Nucleo_32.menu.opt.o1lto=Fast (-O1) with LTO Nucleo_32.menu.opt.o1lto.build.flags.optimize=-O1 -flto -Nucleo_32.menu.opt.o1lto.build.flags.ldspecs=-flto Nucleo_32.menu.opt.o2std=Faster (-O2) Nucleo_32.menu.opt.o2std.build.flags.optimize=-O2 -Nucleo_32.menu.opt.o2std.build.flags.ldspecs= Nucleo_32.menu.opt.o2lto=Faster (-O2) with LTO Nucleo_32.menu.opt.o2lto.build.flags.optimize=-O2 -flto -Nucleo_32.menu.opt.o2lto.build.flags.ldspecs=-flto Nucleo_32.menu.opt.o3std=Fastest (-O3) Nucleo_32.menu.opt.o3std.build.flags.optimize=-O3 -Nucleo_32.menu.opt.o3std.build.flags.ldspecs= Nucleo_32.menu.opt.o3lto=Fastest (-O3) with LTO Nucleo_32.menu.opt.o3lto.build.flags.optimize=-O3 -flto -Nucleo_32.menu.opt.o3lto.build.flags.ldspecs=-flto Nucleo_32.menu.opt.ogstd=Debug (-g) Nucleo_32.menu.opt.ogstd.build.flags.optimize=-g -Og -Nucleo_32.menu.opt.ogstd.build.flags.ldspecs= Disco.menu.opt.osstd=Smallest (-Os default) Disco.menu.opt.oslto=Smallest (-Os) with LTO Disco.menu.opt.oslto.build.flags.optimize=-Os -flto -Disco.menu.opt.oslto.build.flags.ldspecs=-flto Disco.menu.opt.o1std=Fast (-O1) Disco.menu.opt.o1std.build.flags.optimize=-O1 -Disco.menu.opt.o1std.build.flags.ldspecs= Disco.menu.opt.o1lto=Fast (-O1) with LTO Disco.menu.opt.o1lto.build.flags.optimize=-O1 -flto -Disco.menu.opt.o1lto.build.flags.ldspecs=-flto Disco.menu.opt.o2std=Faster (-O2) Disco.menu.opt.o2std.build.flags.optimize=-O2 -Disco.menu.opt.o2std.build.flags.ldspecs= Disco.menu.opt.o2lto=Faster (-O2) with LTO Disco.menu.opt.o2lto.build.flags.optimize=-O2 -flto -Disco.menu.opt.o2lto.build.flags.ldspecs=-flto Disco.menu.opt.o3std=Fastest (-O3) Disco.menu.opt.o3std.build.flags.optimize=-O3 -Disco.menu.opt.o3std.build.flags.ldspecs= Disco.menu.opt.o3lto=Fastest (-O3) with LTO Disco.menu.opt.o3lto.build.flags.optimize=-O3 -flto -Disco.menu.opt.o3lto.build.flags.ldspecs=-flto Disco.menu.opt.ogstd=Debug (-g) Disco.menu.opt.ogstd.build.flags.optimize=-g -Og -Disco.menu.opt.ogstd.build.flags.ldspecs= GenF103.menu.opt.osstd=Smallest (-Os default) GenF103.menu.opt.oslto=Smallest (-Os) with LTO GenF103.menu.opt.oslto.build.flags.optimize=-Os -flto -GenF103.menu.opt.oslto.build.flags.ldspecs=-flto GenF103.menu.opt.o1std=Fast (-O1) GenF103.menu.opt.o1std.build.flags.optimize=-O1 -GenF103.menu.opt.o1std.build.flags.ldspecs= GenF103.menu.opt.o1lto=Fast (-O1) with LTO GenF103.menu.opt.o1lto.build.flags.optimize=-O1 -flto -GenF103.menu.opt.o1lto.build.flags.ldspecs=-flto GenF103.menu.opt.o2std=Faster (-O2) GenF103.menu.opt.o2std.build.flags.optimize=-O2 -GenF103.menu.opt.o2std.build.flags.ldspecs= GenF103.menu.opt.o2lto=Faster (-O2) with LTO GenF103.menu.opt.o2lto.build.flags.optimize=-O2 -flto -GenF103.menu.opt.o2lto.build.flags.ldspecs=-flto GenF103.menu.opt.o3std=Fastest (-O3) GenF103.menu.opt.o3std.build.flags.optimize=-O3 -GenF103.menu.opt.o3std.build.flags.ldspecs= GenF103.menu.opt.o3lto=Fastest (-O3) with LTO GenF103.menu.opt.o3lto.build.flags.optimize=-O3 -flto -GenF103.menu.opt.o3lto.build.flags.ldspecs=-flto GenF103.menu.opt.ogstd=Debug (-g) GenF103.menu.opt.ogstd.build.flags.optimize=-g -Og -GenF103.menu.opt.ogstd.build.flags.ldspecs= GenF4.menu.opt.osstd=Smallest (-Os default) GenF4.menu.opt.osstd.build.flags.optimize=-Os -GenF4.menu.opt.osstd.build.flags.ldspecs= GenF4.menu.opt.oslto=Smallest (-Os) with LTO GenF4.menu.opt.oslto.build.flags.optimize=-Os -flto -GenF4.menu.opt.oslto.build.flags.ldspecs=-flto GenF4.menu.opt.o1std=Fast (-O1) GenF4.menu.opt.o1std.build.flags.optimize=-O1 -GenF4.menu.opt.o1std.build.flags.ldspecs= GenF4.menu.opt.o1lto=Fast (-O1) with LTO GenF4.menu.opt.o1lto.build.flags.optimize=-O1 -flto -GenF4.menu.opt.o1lto.build.flags.ldspecs=-flto GenF4.menu.opt.o2std=Faster (-O2) GenF4.menu.opt.o2std.build.flags.optimize=-O2 -GenF4.menu.opt.o2std.build.flags.ldspecs= GenF4.menu.opt.o2lto=Faster (-O2) with LTO GenF4.menu.opt.o2lto.build.flags.optimize=-O2 -flto -GenF4.menu.opt.o2lto.build.flags.ldspecs=-flto GenF4.menu.opt.o3std=Fastest (-O3) GenF4.menu.opt.o3std.build.flags.optimize=-O3 -GenF4.menu.opt.o3std.build.flags.ldspecs= GenF4.menu.opt.o3lto=Fastest (-O3) with LTO GenF4.menu.opt.o3lto.build.flags.optimize=-O3 -flto -GenF4.menu.opt.o3lto.build.flags.ldspecs=-flto GenF4.menu.opt.ogstd=Debug (-g) GenF4.menu.opt.ogstd.build.flags.optimize=-g -Og -GenF4.menu.opt.ogstd.build.flags.ldspecs= Maple.menu.opt.osstd=Smallest (-Os default) Maple.menu.opt.oslto=Smallest (-Os) with LTO Maple.menu.opt.oslto.build.flags.optimize=-Os -flto -Maple.menu.opt.oslto.build.flags.ldspecs=-flto Maple.menu.opt.o1std=Fast (-O1) Maple.menu.opt.o1std.build.flags.optimize=-O1 -Maple.menu.opt.o1std.build.flags.ldspecs= Maple.menu.opt.o1lto=Fast (-O1) with LTO Maple.menu.opt.o1lto.build.flags.optimize=-O1 -flto -Maple.menu.opt.o1lto.build.flags.ldspecs=-flto Maple.menu.opt.o2std=Faster (-O2) Maple.menu.opt.o2std.build.flags.optimize=-O2 -Maple.menu.opt.o2std.build.flags.ldspecs= Maple.menu.opt.o2lto=Faster (-O2) with LTO Maple.menu.opt.o2lto.build.flags.optimize=-O2 -flto -Maple.menu.opt.o2lto.build.flags.ldspecs=-flto Maple.menu.opt.o3std=Fastest (-O3) Maple.menu.opt.o3std.build.flags.optimize=-O3 -Maple.menu.opt.o3std.build.flags.ldspecs= Maple.menu.opt.o3lto=Fastest (-O3) with LTO Maple.menu.opt.o3lto.build.flags.optimize=-O3 -flto -Maple.menu.opt.o3lto.build.flags.ldspecs=-flto Maple.menu.opt.ogstd=Debug (-g) Maple.menu.opt.ogstd.build.flags.optimize=-g -Og -Maple.menu.opt.ogstd.build.flags.ldspecs= RAK.menu.opt.osstd=Smallest (-Os default) RAK.menu.opt.oslto=Smallest (-Os) with LTO RAK.menu.opt.oslto.build.flags.optimize=-Os -flto -RAK.menu.opt.oslto.build.flags.ldspecs=-flto RAK.menu.opt.o1std=Fast (-O1) RAK.menu.opt.o1std.build.flags.optimize=-O1 -RAK.menu.opt.o1std.build.flags.ldspecs= RAK.menu.opt.o1lto=Fast (-O1) with LTO RAK.menu.opt.o1lto.build.flags.optimize=-O1 -flto -RAK.menu.opt.o1lto.build.flags.ldspecs=-flto RAK.menu.opt.o2std=Faster (-O2) RAK.menu.opt.o2std.build.flags.optimize=-O2 -RAK.menu.opt.o2std.build.flags.ldspecs= RAK.menu.opt.o2lto=Faster (-O2) with LTO RAK.menu.opt.o2lto.build.flags.optimize=-O2 -flto -RAK.menu.opt.o2lto.build.flags.ldspecs=-flto RAK.menu.opt.o3std=Fastest (-O3) RAK.menu.opt.o3std.build.flags.optimize=-O3 -RAK.menu.opt.o3std.build.flags.ldspecs= RAK.menu.opt.o3lto=Fastest (-O3) with LTO RAK.menu.opt.o3lto.build.flags.optimize=-O3 -flto -RAK.menu.opt.o3lto.build.flags.ldspecs=-flto RAK.menu.opt.ogstd=Debug (-g) RAK.menu.opt.ogstd.build.flags.optimize=-g -Og -RAK.menu.opt.ogstd.build.flags.ldspecs= RemRam.menu.opt.osstd=Smallest (-Os default) RemRam.menu.opt.oslto=Smallest (-Os) with LTO RemRam.menu.opt.oslto.build.flags.optimize=-Os -flto -RemRam.menu.opt.oslto.build.flags.ldspecs=-flto RemRam.menu.opt.o1std=Fast (-O1) RemRam.menu.opt.o1std.build.flags.optimize=-O1 -RemRam.menu.opt.o1std.build.flags.ldspecs= RemRam.menu.opt.o1lto=Fast (-O1) with LTO RemRam.menu.opt.o1lto.build.flags.optimize=-O1 -flto -RemRam.menu.opt.o1lto.build.flags.ldspecs=-flto RemRam.menu.opt.o2std=Faster (-O2) RemRam.menu.opt.o2std.build.flags.optimize=-O2 -RemRam.menu.opt.o2std.build.flags.ldspecs= RemRam.menu.opt.o2lto=Faster (-O2) with LTO RemRam.menu.opt.o2lto.build.flags.optimize=-O2 -flto -RemRam.menu.opt.o2lto.build.flags.ldspecs=-flto RemRam.menu.opt.o3std=Fastest (-O3) RemRam.menu.opt.o3std.build.flags.optimize=-O3 -RemRam.menu.opt.o3std.build.flags.ldspecs= RemRam.menu.opt.o3lto=Fastest (-O3) with LTO RemRam.menu.opt.o3lto.build.flags.optimize=-O3 -flto -RemRam.menu.opt.o3lto.build.flags.ldspecs=-flto RemRam.menu.opt.ogstd=Debug (-g) RemRam.menu.opt.ogstd.build.flags.optimize=-g -Og -RemRam.menu.opt.ogstd.build.flags.ldspecs= diff --git a/platform.txt b/platform.txt index 01ac507e35..4ae5f95864 100644 --- a/platform.txt +++ b/platform.txt @@ -46,7 +46,7 @@ compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc, compiler.elf2bin.flags=-O binary compiler.elf2hex.flags=-O ihex -compiler.ldflags={build.flags.ldspecs} +compiler.ldflags= compiler.size.cmd=arm-none-eabi-size compiler.define=-DARDUINO= From 1220b4a9fbfdb7e287cf4c2d0d0f3cdcfb89f205 Mon Sep 17 00:00:00 2001 From: ppescher Date: Mon, 24 Sep 2018 14:51:22 +0200 Subject: [PATCH 087/109] Add menu options for C RunTime library Mainly to support floating point format strings in printf/scanf functions and their variants. Default settings uses Newlib Nano without floating point support (as before). One can add floating point support for Printf only, Scanf only or both, or just use the standard one. Signed-off-by: ppescher --- boards.txt | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++ platform.txt | 6 ++-- 2 files changed, 95 insertions(+), 3 deletions(-) diff --git a/boards.txt b/boards.txt index 6f7a86ec22..1c01b489fc 100644 --- a/boards.txt +++ b/boards.txt @@ -6,6 +6,7 @@ menu.xserial=Serial interface menu.usb=USB interface menu.opt=Optimize +menu.rtlib=C Runtime Library menu.upload_method=Upload method menu.flash=Flash Memory Size menu.ram=RAM Size @@ -909,3 +910,94 @@ RemRam.menu.opt.o3lto=Fastest (-O3) with LTO RemRam.menu.opt.o3lto.build.flags.optimize=-O3 -flto RemRam.menu.opt.ogstd=Debug (-g) RemRam.menu.opt.ogstd.build.flags.optimize=-g -Og + +# C Runtime Library +Nucleo_144.menu.rtlib.nano=Newlib Nano (default) +Nucleo_144.menu.rtlib.nanofp=Newlib Nano + Float Printf +Nucleo_144.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +Nucleo_144.menu.rtlib.nanofs=Newlib Nano + Float Scanf +Nucleo_144.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +Nucleo_144.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +Nucleo_144.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +Nucleo_144.menu.rtlib.full=Newlib Standard +Nucleo_144.menu.rtlib.full.build.flags.ldspecs= + +Nucleo_64.menu.rtlib.nano=Newlib Nano (default) +Nucleo_64.menu.rtlib.nanofp=Newlib Nano + Float Printf +Nucleo_64.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +Nucleo_64.menu.rtlib.nanofs=Newlib Nano + Float Scanf +Nucleo_64.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +Nucleo_64.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +Nucleo_64.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +Nucleo_64.menu.rtlib.full=Newlib Standard +Nucleo_64.menu.rtlib.full.build.flags.ldspecs= + +Nucleo_32.menu.rtlib.nano=Newlib Nano (default) +Nucleo_32.menu.rtlib.nanofp=Newlib Nano + Float Printf +Nucleo_32.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +Nucleo_32.menu.rtlib.nanofs=Newlib Nano + Float Scanf +Nucleo_32.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +Nucleo_32.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +Nucleo_32.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +Nucleo_32.menu.rtlib.full=Newlib Standard +Nucleo_32.menu.rtlib.full.build.flags.ldspecs= + +Disco.menu.rtlib.nano=Newlib Nano (default) +Disco.menu.rtlib.nanofp=Newlib Nano + Float Printf +Disco.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +Disco.menu.rtlib.nanofs=Newlib Nano + Float Scanf +Disco.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +Disco.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +Disco.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +Disco.menu.rtlib.full=Newlib Standard +Disco.menu.rtlib.full.build.flags.ldspecs= + +GenF103.menu.rtlib.nano=Newlib Nano (default) +GenF103.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenF103.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenF103.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenF103.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenF103.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenF103.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenF103.menu.rtlib.full=Newlib Standard +GenF103.menu.rtlib.full.build.flags.ldspecs= + +GenF4.menu.rtlib.nano=Newlib Nano (default) +GenF4.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenF4.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenF4.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenF4.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenF4.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenF4.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenF4.menu.rtlib.full=Newlib Standard +GenF4.menu.rtlib.full.build.flags.ldspecs= + +Maple.menu.rtlib.nano=Newlib Nano (default) +Maple.menu.rtlib.nanofp=Newlib Nano + Float Printf +Maple.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +Maple.menu.rtlib.nanofs=Newlib Nano + Float Scanf +Maple.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +Maple.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +Maple.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +Maple.menu.rtlib.full=Newlib Standard +Maple.menu.rtlib.full.build.flags.ldspecs= + +RAK.menu.rtlib.nano=Newlib Nano (default) +RAK.menu.rtlib.nanofp=Newlib Nano + Float Printf +RAK.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +RAK.menu.rtlib.nanofs=Newlib Nano + Float Scanf +RAK.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +RAK.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +RAK.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +RAK.menu.rtlib.full=Newlib Standard +RAK.menu.rtlib.full.build.flags.ldspecs= + +RemRam.menu.rtlib.nano=Newlib Nano (default) +RemRam.menu.rtlib.nanofp=Newlib Nano + Float Printf +RemRam.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +RemRam.menu.rtlib.nanofs=Newlib Nano + Float Scanf +RemRam.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +RemRam.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +RemRam.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +RemRam.menu.rtlib.full=Newlib Standard +RemRam.menu.rtlib.full.build.flags.ldspecs= diff --git a/platform.txt b/platform.txt index 4ae5f95864..4260277745 100644 --- a/platform.txt +++ b/platform.txt @@ -33,7 +33,7 @@ compiler.extra_flags=-mcpu={build.mcu} -mthumb "@{build.opt.path}" compiler.S.flags={compiler.extra_flags} -c -x assembler-with-cpp {compiler.stm.extra_include} -compiler.c.flags={compiler.extra_flags} -c {build.flags.optimize} {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -Dprintf=iprintf -MMD {compiler.stm.extra_include} +compiler.c.flags={compiler.extra_flags} -c {build.flags.optimize} {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -MMD {compiler.stm.extra_include} compiler.cpp.flags={compiler.extra_flags} -c {build.flags.optimize} {compiler.warning_flags} -std={compiler.cpp.std} -ffunction-sections -fdata-sections -nostdlib -fno-threadsafe-statics --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -MMD {compiler.stm.extra_include} @@ -82,7 +82,7 @@ build.info.flags=-D{build.series} -DARDUINO={runtime.ide.version} -DARDUINO_{bui build.xSerial=-DHAL_UART_MODULE_ENABLED build.enable_usb= build.flags.optimize=-Os -build.flags.ldspecs= +build.flags.ldspecs=--specs=nano.specs # Pre and post build hooks build.opt.name=build_opt.h @@ -110,7 +110,7 @@ recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} {build.i recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" ## Combine gc-sections, archives, and objects -recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} {compiler.ldflags} {compiler.arm.cmsis.ldflags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--start-group {object_files} -Wl,--whole-archive "{archive_file_path}" -Wl,--no-whole-archive -lc -Wl,--end-group -lm -lgcc -lstdc++ --specs=nano.specs +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} {compiler.ldflags} {compiler.arm.cmsis.ldflags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--start-group {object_files} -Wl,--whole-archive "{archive_file_path}" -Wl,--no-whole-archive -lc -Wl,--end-group -lm -lgcc -lstdc++ ## Create output (.bin file) recipe.objcopy.bin.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.elf2bin.flags} {compiler.elf2bin.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.bin" From 45a0dcfb01f987493c8b4c30a0486a27f47f975b Mon Sep 17 00:00:00 2001 From: zoomx Date: Mon, 1 Oct 2018 18:03:14 +0200 Subject: [PATCH 088/109] Added NUCLEO_L073RZ support (#343) Added NUCLEO_L073RZ support --- boards.txt | 13 + variants/NUCLEO_L073RZ/PeripheralPins.c | 287 ++++++++++++++++++ variants/NUCLEO_L073RZ/PinNamesVar.h | 25 ++ variants/NUCLEO_L073RZ/ldscript.ld | 153 ++++++++++ variants/NUCLEO_L073RZ/stm32l0xx_hal_conf.h | 312 ++++++++++++++++++++ variants/NUCLEO_L073RZ/variant.cpp | 165 +++++++++++ variants/NUCLEO_L073RZ/variant.h | 173 +++++++++++ 7 files changed, 1128 insertions(+) create mode 100644 variants/NUCLEO_L073RZ/PeripheralPins.c create mode 100644 variants/NUCLEO_L073RZ/PinNamesVar.h create mode 100644 variants/NUCLEO_L073RZ/ldscript.ld create mode 100644 variants/NUCLEO_L073RZ/stm32l0xx_hal_conf.h create mode 100644 variants/NUCLEO_L073RZ/variant.cpp create mode 100644 variants/NUCLEO_L073RZ/variant.h diff --git a/boards.txt b/boards.txt index d8e096c444..6bd930e61f 100644 --- a/boards.txt +++ b/boards.txt @@ -250,6 +250,19 @@ Nucleo_64.menu.pnum.NUCLEO_L053R8.build.variant=NUCLEO_L053R8 Nucleo_64.menu.pnum.NUCLEO_L053R8.build.cmsis_lib_gcc=arm_cortexM0l_math Nucleo_64.menu.pnum.NUCLEO_L053R8.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +# NUCLEO_L073RZ board +# Support: Serial1 (USART1 on PA10, PA9) +Nucleo_64.menu.pnum.NUCLEO_L073RZ=Nucleo L073RZ +Nucleo_64.menu.pnum.NUCLEO_L073RZ.node=NODE_L073RZ +Nucleo_64.menu.pnum.NUCLEO_L073RZ.upload.maximum_size=196608 +Nucleo_64.menu.pnum.NUCLEO_L073RZ.upload.maximum_data_size=20480 +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.board=NUCLEO_L073RZ +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.series=STM32L0xx +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.product_line=STM32L073xx +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.variant=NUCLEO_L073RZ +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.cmsis_lib_gcc=arm_cortexM0l_math +Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 # NUCLEO_L152RE board # Support: Serial1 (USART1 on PA10, PA9) and Serial2 (UART4 on PC11, PC10) Nucleo_64.menu.pnum.NUCLEO_L152RE=Nucleo L152RE diff --git a/variants/NUCLEO_L073RZ/PeripheralPins.c b/variants/NUCLEO_L073RZ/PeripheralPins.c new file mode 100644 index 0000000000..e520c0904e --- /dev/null +++ b/variants/NUCLEO_L073RZ/PeripheralPins.c @@ -0,0 +1,287 @@ +/* + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * Automatically generated from STM32L073R(B-Z)Tx.xml + */ +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Note: Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC_IN10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC_IN11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC_IN12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PC_1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, + {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, + {PC_0, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** PWM *** + +#ifdef HAL_TIM_MODULE_ENABLED +const PinMap PinMap_PWM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1 + {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1 + {PB_14, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1 + {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {NC, NP, 0} +}; +#endif + +//*** SERIAL *** + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_TX[] = { + {PA_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_14, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PB_3, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PC_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PC_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PC_10, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PC_12, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)}, + {NC, NP, 0} +}; +/* +const PinMap PinMap_UART_TX[] = { + {PA_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_14, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PB_3, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PC_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PC_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PC_10, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PC_12, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)}, + {NC, NP, 0} +}; + + +*/ +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RX[] = { + {PA_1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PB_4, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PC_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PC_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PC_11, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PD_2, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_15, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_5, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PB_14, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PD_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, + {PB_7, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +//*** No CAN_RD *** + +//*** No CAN_TD *** + +//*** ETHERNET *** + +//*** No Ethernet *** + +//*** QUADSPI *** + +//*** No QUADSPI *** diff --git a/variants/NUCLEO_L073RZ/PinNamesVar.h b/variants/NUCLEO_L073RZ/PinNamesVar.h new file mode 100644 index 0000000000..0b7fa5cc33 --- /dev/null +++ b/variants/NUCLEO_L073RZ/PinNamesVar.h @@ -0,0 +1,25 @@ + /* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif diff --git a/variants/NUCLEO_L073RZ/ldscript.ld b/variants/NUCLEO_L073RZ/ldscript.ld new file mode 100644 index 0000000000..8f792887d3 --- /dev/null +++ b/variants/NUCLEO_L073RZ/ldscript.ld @@ -0,0 +1,153 @@ +/* +***************************************************************************** +** +** File : ldscript.ld +** +** Abstract : Linker script for STM32 Device +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +***************************************************************************** +*/ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20005000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 192K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/NUCLEO_L073RZ/stm32l0xx_hal_conf.h b/variants/NUCLEO_L073RZ/stm32l0xx_hal_conf.h new file mode 100644 index 0000000000..2dd135ddcc --- /dev/null +++ b/variants/NUCLEO_L073RZ/stm32l0xx_hal_conf.h @@ -0,0 +1,312 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

          © COPYRIGHT(c) 2018 STMicroelectronics

          + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_CONF_H +#define __STM32L0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/*#define HAL_COMP_MODULE_ENABLED*/ +/*#define HAL_CRC_MODULE_ENABLED*/ +/*#define HAL_CRYP_MODULE_ENABLED*/ +#define HAL_DAC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +/*#define HAL_FIREWALL_MODULE_ENABLED*/ +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED*/ +#define HAL_IWDG_MODULE_ENABLED +/*#define HAL_LCD_MODULE_ENABLED*/ +/*#define HAL_LPTIM_MODULE_ENABLED*/ +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED*/ +#define HAL_RTC_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +/*#define HAL_TSC_MODULE_ENABLED*/ +/*#define HAL_UART_MODULE_ENABLED*/ +/*#define HAL_USART_MODULE_ENABLED*/ +/*#define HAL_IRDA_MODULE_ENABLED*/ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +/*#define HAL_SMBUS_MODULE_ENABLED*/ +/*#define HAL_WWDG_MODULE_ENABLED*/ +#define HAL_CORTEX_MODULE_ENABLED +/*#define HAL_PCD_MODULE_ENABLED*/ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @brief Time out for LSE start up value in ms. + */ +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define PREREAD_ENABLE 0U +#define BUFFER_CACHE_DISABLE 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l0xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l0xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32l0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l0xx_hal_rtc.h" + +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_L073RZ/variant.cpp b/variants/NUCLEO_L073RZ/variant.cpp new file mode 100644 index 0000000000..92e6b20638 --- /dev/null +++ b/variants/NUCLEO_L073RZ/variant.cpp @@ -0,0 +1,165 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "variant.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Pin number +const PinName digitalPin[] = { + PA_3, //D0 + PA_2, //D1 + PA_10, //D2 + PB_3, //D3 + PB_5, //D4 + PB_4, //D5 + PB_10, //D6 + PA_8, //D7 + PA_9, //D8 + PC_7, //D9 + PB_6, //D10 - PWM is not supported by D10 as no timer on PB_6 + PA_7, //D11 + PA_6, //D12 + PA_5, //D13 + PB_9, //D14 + PB_8, //D15 +// ST Morpho +// CN7 Left Side + PC_10, //D16 + PC_12, //D17 + NC, //D18 - BOOT0 + PA_13, //D19 - SWD + PA_14, //D20 - SWD + PA_15, //D21 + PB_7, //D22 + PC_13, //D23 + PC_14, //D24 + PC_15, //D25 + PH_0, //D26 + PH_1, //D27 + PC_2, //D28 + PC_3, //D29 +// CN7 Right Side + PC_11, //D30 + PD_2, //D31 +// CN10 Left Side + PC_9, //D32 +// CN10 Right side + PC_8, //D33 + PC_6, //D34 + PC_5, //D35 + PA_12, //D36 + PA_11, //D37 + PB_12, //D38 + PB_11, //D39 + PB_2, //D40 + PB_1, //D41 + PB_15, //D42 + PB_14, //D43 + PB_13, //D44 + PC_4, //D45 + PA_0, //D46/A0 + PA_1, //D47/A1 + PA_4, //D48/A2 + PB_0, //D49/A3 + PC_1, //D50/A4 - SB56 ON SB51 ON on the board + PC_0, //D51/A5 + // Duplicated pins in order to be aligned with PinMap_ADC + PA_7, //D52/A6 = D11 + PA_6, //D53/A7 = D12 + PC_2, //D54/A8 = D28 + PC_3, //D55/A9 = D29 + PC_5, //D56/A10 = D35 + PC_4 //D57/A11 = D45 +}; + +#ifdef __cplusplus +} +#endif + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + _Error_Handler(__FILE__, __LINE__); + } + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + _Error_Handler(__FILE__, __LINE__); + } + + /* Configure the Systick interrupt time */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + + /* Configure the Systick */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); +} + +#ifdef __cplusplus +} +#endif diff --git a/variants/NUCLEO_L073RZ/variant.h b/variants/NUCLEO_L073RZ/variant.h new file mode 100644 index 0000000000..603c40c0aa --- /dev/null +++ b/variants/NUCLEO_L073RZ/variant.h @@ -0,0 +1,173 @@ +/* + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef _VARIANT_ARDUINO_STM32_ +#define _VARIANT_ARDUINO_STM32_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ +extern const PinName digitalPin[]; + +// Enum defining pin names to match digital pin number --> Dx +enum { + PA3, //D0 + PA2, //D1 + PA10, //D2 + PB3, //D3 + PB5, //D4 + PB4, //D5 + PB10, //D6 + PA8, //D7 + PA9, //D8 + PC7, //D9 + PB6, //D10 - PWM is not supported by D10 as no timer on PB6 + PA7, //D11 + PA6, //D12 + PA5, //D13 + PB9, //D14 + PB8, //D15 +// ST Morpho +// CN7 Left Side + PC10, //D16 + PC12, //D17 + NC_1, //D18 - BOOT0 + PA13, //D19 - SWD + PA14, //D20 - SWD + PA15, //D21 + PB7, //D22 + PC13, //D23 + PC14, //D24 + PC15, //D25 + PH0, //D26 + PH1, //D27 + PC2, //D28 + PC3, //D29 +// CN7 Right Side + PC11, //D30 + PD2, //D31 +// CN10 Left Side + PC9, //D32 +// CN10 Right side + PC8, //D33 + PC6, //D34 + PC5, //D35 + PA12, //D36 + PA11, //D37 + PB12, //D38 + PB11, //D39 + PB2, //D40 + PB1, //D41 + PB15, //D42 + PB14, //D43 + PB13, //D44 + PC4, //D45 + PA0, //D46/A0 + PA1, //D47/A1 + PA4, //D48/A2 + PB0, //D49/A3 + PC1, //D50/A4 - SB56 ON SB51 ON on the board! + PC0, //D51/A5 + // Duplicated pins in order to be aligned with PinMap_ADC + PA7_2,//D52/A6 = D11 + PA6_2,//D53/A7 = D12 + PC2_2,//D54/A8 = D28 + PC3_2,//D55/A9 = D29 + PC5_2,//D56/A10 = D35 + PC4_2,//D57/A11 = D45 + PEND +}; + +// This must be a literal with the same value as PEND +#define NUM_DIGITAL_PINS 58 + +// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS +#define NUM_ANALOG_INPUTS 12 +#define NUM_ANALOG_FIRST 46 + +// On-board LED pin number +#define LED_BUILTIN 13 +#define LED_GREEN LED_BUILTIN + +// On-board user button +#define USER_BTN PC13 + +// Timer Definitions +//Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c +#define TIMER_TONE TIM3 + +// Do not use basic timer: OC is required +#define TIMER_SERVO TIM3 //TODO: advanced-control timers don't work + +// UART Definitions +#define SERIAL_UART_INSTANCE 2 //ex: 2 for Serial2 (USART2) + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#define PIN_SERIAL_RX 0 +#define PIN_SERIAL_TX 1 + +#ifdef __cplusplus +} // extern "C" +#endif +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +// These serial port names are intended to allow libraries and architecture-neutral +// sketches to automatically default to the correct port name for a particular type +// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, +// the first hardware serial port whose RX/TX pins are not dedicated to another use. +// +// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor +// +// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial +// +// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library +// +// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. +// +// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX +// pins are NOT connected to anything by default. +#define SERIAL_PORT_MONITOR Serial +#define SERIAL_PORT_HARDWARE Serial +#endif + +#endif /* _VARIANT_ARDUINO_STM32_ */ From 650f9e9f8bafd9627f23db44fe510095d7e60a1e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 1 Oct 2018 18:09:18 +0200 Subject: [PATCH 089/109] Update README.md --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 1d6da38a12..c63572fe5f 100644 --- a/README.md +++ b/README.md @@ -93,6 +93,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d * [RemRam v1](https://github.com/hasenbanck/remram) * STM32L0 + * [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) * [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) (Basic support) * STM32L4 From 1baed55e36fe5932c82cd583070cc2a4b0b61ce3 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 2 Oct 2018 10:29:03 +0200 Subject: [PATCH 090/109] Fix std::abs() usage Call of overloaded 'abs(unsigned int&)' is ambiguous See https://gcc.gnu.org/gcc-6/porting_to.html#overloaded-abs Signed-off-by: Frederic.Pillon --- libraries/CapacitiveSensor-0.5.1/CapacitiveSensor.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libraries/CapacitiveSensor-0.5.1/CapacitiveSensor.cpp b/libraries/CapacitiveSensor-0.5.1/CapacitiveSensor.cpp index 18128e322e..fe84960b3c 100644 --- a/libraries/CapacitiveSensor-0.5.1/CapacitiveSensor.cpp +++ b/libraries/CapacitiveSensor-0.5.1/CapacitiveSensor.cpp @@ -61,7 +61,8 @@ long CapacitiveSensor::capacitiveSensor(uint8_t samples) // only calibrate if time is greater than CS_AutocaL_Millis and total is less than 10% of baseline // this is an attempt to keep from calibrating when the sensor is seeing a "touched" signal - if ( (millis() - lastCal > CS_AutocaL_Millis) && abs(total - leastTotal) < (int)(.10 * (float)leastTotal) ) { + if ( (millis() - lastCal > CS_AutocaL_Millis) && + abs((signed long)total - (signed long)leastTotal) < (int)(.10 * (float)leastTotal) ) { // Serial.println(); // debugging // Serial.println("auto-calibrate"); From 41f92b2ac98a05874a65a3dc4f77bf4f7c1cfab7 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 2 Oct 2018 11:25:56 +0200 Subject: [PATCH 091/109] Enable FPU Single Precision (SP) for Nucleo-F303K8 Signed-off-by: Frederic.Pillon --- boards.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.txt b/boards.txt index 94eaf0ca5e..9dd40c9f13 100644 --- a/boards.txt +++ b/boards.txt @@ -345,7 +345,7 @@ Nucleo_32.menu.pnum.NUCLEO_F303K8=Nucleo F303K8 Nucleo_32.menu.pnum.NUCLEO_F303K8.node=NODE_F303K8 Nucleo_32.menu.pnum.NUCLEO_F303K8.upload.maximum_size=65536 Nucleo_32.menu.pnum.NUCLEO_F303K8.upload.maximum_data_size=12288 -Nucleo_32.menu.pnum.NUCLEO_F303K8.build.mcu=cortex-m4 +Nucleo_32.menu.pnum.NUCLEO_F303K8.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard Nucleo_32.menu.pnum.NUCLEO_F303K8.build.board=NUCLEO_F303K8 Nucleo_32.menu.pnum.NUCLEO_F303K8.build.series=STM32F3xx Nucleo_32.menu.pnum.NUCLEO_F303K8.build.product_line=STM32F303x8 From 156d9d9c1bc025db59babce890747eecbc189d20 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 3 Oct 2018 08:55:38 +0200 Subject: [PATCH 092/109] Rename debug to core_debug to avoid issue Several libraries provides debug.h or debug function __DEBUG define has been renamed CORE_DEBUG Signed-off-by: Frederic.Pillon --- cores/arduino/{debug.h => core_debug.h} | 15 ++++++++------- cores/arduino/stm32/spi_com.c | 8 ++++---- cores/arduino/stm32/stm32_def.c | 4 ++-- cores/arduino/stm32/timer.c | 8 ++++---- cores/arduino/stm32/twi.c | 8 ++++---- cores/arduino/stm32/uart.c | 6 +++--- 6 files changed, 25 insertions(+), 24 deletions(-) rename cores/arduino/{debug.h => core_debug.h} (71%) diff --git a/cores/arduino/debug.h b/cores/arduino/core_debug.h similarity index 71% rename from cores/arduino/debug.h rename to cores/arduino/core_debug.h index 88d447b84e..5d0b9b9fe3 100644 --- a/cores/arduino/debug.h +++ b/cores/arduino/core_debug.h @@ -1,8 +1,9 @@ -#ifndef _DEBUG_H -#ifdef __DEBUG +#ifndef _CORE_DEBUG_H +#define _CORE_DEBUG_H +#ifdef CORE_DEBUG #include #include -#endif /* __DEBUG */ +#endif /* CORE_DEBUG */ #ifdef __cplusplus extern "C" { @@ -15,19 +16,19 @@ extern "C" { * the code, use a lot of stack. An alternative, will be to implement a tiny * and limited functionality implementation of printf. */ -static inline void debug(const char *format, ...) { -#ifdef __DEBUG +static inline void core_debug(const char *format, ...) { +#ifdef CORE_DEBUG va_list args; va_start(args, format); vfprintf(stderr, format, args); va_end(args); #else (void)(format); -#endif /* __DEBUG */ +#endif /* CORE_DEBUG */ } #ifdef __cplusplus } #endif -#endif /* _DEBUG_H */ +#endif /* _CORE_DEBUG_H */ diff --git a/cores/arduino/stm32/spi_com.c b/cores/arduino/stm32/spi_com.c index 8b51fe0bb4..9a5f41521f 100644 --- a/cores/arduino/stm32/spi_com.c +++ b/cores/arduino/stm32/spi_com.c @@ -46,7 +46,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ -#include "debug.h" +#include "core_debug.h" #include "stm32_def.h" #include "spi_com.h" #include "PinAF_STM32F1.h" @@ -150,7 +150,7 @@ uint32_t spi_getClkFreqInst(SPI_TypeDef * spi_inst) break; #endif default: - debug("CLK: SPI instance not set"); + core_debug("CLK: SPI instance not set"); break; } } @@ -204,7 +204,7 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) /* Pins MOSI/MISO/SCLK must not be NP. ssel can be NP. */ if(spi_mosi == NP || spi_miso == NP || spi_sclk == NP) { - debug("ERROR: at least one SPI pin has no peripheral\n"); + core_debug("ERROR: at least one SPI pin has no peripheral\n"); return; } @@ -215,7 +215,7 @@ void spi_init(spi_t *obj, uint32_t speed, spi_mode_e mode, uint8_t msb) // Are all pins connected to the same SPI instance? if(obj->spi == NP) { - debug("ERROR: SPI pins mismatch\n"); + core_debug("ERROR: SPI pins mismatch\n"); return; } diff --git a/cores/arduino/stm32/stm32_def.c b/cores/arduino/stm32/stm32_def.c index b94cbdc6ec..4fb3dc1ccf 100644 --- a/cores/arduino/stm32/stm32_def.c +++ b/cores/arduino/stm32/stm32_def.c @@ -1,5 +1,5 @@ #include "stm32_def.h" -#include "debug.h" +#include "core_debug.h" #ifdef __cplusplus extern "C" { @@ -12,7 +12,7 @@ extern "C" { */ WEAK void _Error_Handler(const char * msg, int val) { /* User can add his own implementation to report the HAL error return state */ - debug("Error: %s (%i)\n", msg, val); + core_debug("Error: %s (%i)\n", msg, val); while(1) { } } diff --git a/cores/arduino/stm32/timer.c b/cores/arduino/stm32/timer.c index 656f4d9e32..6905b5846a 100644 --- a/cores/arduino/stm32/timer.c +++ b/cores/arduino/stm32/timer.c @@ -46,7 +46,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ -#include "debug.h" +#include "core_debug.h" #include "timer.h" #include "board.h" @@ -545,7 +545,7 @@ uint32_t getTimerIrq(TIM_TypeDef* tim) #endif break; default: - debug("TIM: Unknown timer IRQn"); + core_debug("TIM: Unknown timer IRQn"); break; } } @@ -653,7 +653,7 @@ uint8_t getTimerClkSrc(TIM_TypeDef* tim) clkSrc = 2; break; default: - debug("TIM: Unknown timer instance"); + core_debug("TIM: Unknown timer instance"); break; } } @@ -687,7 +687,7 @@ uint32_t getTimerClkFreq(TIM_TypeDef* tim) #endif default: case 0: - debug("TIM: Unknown clock source"); + core_debug("TIM: Unknown clock source"); break; } /* When TIMPRE bit of the RCC_DCKCFGR register is reset, diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index 6133582778..2c3ad39804 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -47,7 +47,7 @@ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ -#include "debug.h" +#include "core_debug.h" #include "stm32_def.h" #include "twi.h" #include "PinAF_STM32F1.h" @@ -167,14 +167,14 @@ void i2c_custom_init(i2c_t *obj, i2c_timing_e timing, uint32_t addressingMode, u //Pins SDA/SCL must not be NP if(i2c_sda == NP || i2c_scl == NP) { - debug("ERROR: at least one I2C pin has no peripheral\n"); + core_debug("ERROR: at least one I2C pin has no peripheral\n"); return; } obj->i2c = pinmap_merge_peripheral(i2c_sda, i2c_scl); if(obj->i2c == NP) { - debug("ERROR: I2C pins mismatch\n"); + core_debug("ERROR: I2C pins mismatch\n"); return; } @@ -597,7 +597,7 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) if(obj->slaveRxNbData < I2C_TXRX_BUFFER_SIZE) { obj->slaveRxNbData++; } else { - debug("ERROR: I2C Slave RX overflow\n"); + core_debug("ERROR: I2C Slave RX overflow\n"); } /* Restart interrupt mode for next Byte */ if(obj->slaveMode == SLAVE_MODE_RECEIVE) { diff --git a/cores/arduino/stm32/uart.c b/cores/arduino/stm32/uart.c index 1be5325797..81401788f7 100644 --- a/cores/arduino/stm32/uart.c +++ b/cores/arduino/stm32/uart.c @@ -33,7 +33,7 @@ * ****************************************************************************** */ -#include "debug.h" +#include "core_debug.h" #include "uart.h" #include "Arduino.h" #include "PinAF_STM32F1.h" @@ -102,7 +102,7 @@ void uart_init(serial_t *obj) /* Pins Rx/Tx must not be NP */ if(uart_rx == NP || uart_tx == NP) { - debug("ERROR: at least one UART pin has no peripheral\n"); + core_debug("ERROR: at least one UART pin has no peripheral\n"); return; } @@ -113,7 +113,7 @@ void uart_init(serial_t *obj) obj->uart = pinmap_merge_peripheral(uart_tx, uart_rx); if(obj->uart == NP) { - debug("ERROR: U(S)ART pins mismatch\n"); + core_debug("ERROR: U(S)ART pins mismatch\n"); return; } From 19eaae61e63975cb8094aa40ba1c5bdaf772d5d4 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 2 Oct 2018 10:18:44 +0200 Subject: [PATCH 093/109] Update CI configuration Signed-off-by: Frederic.Pillon --- CI/build/conf/cores_config.json | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index bad2f09d6f..e0bb1925fa 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -41,6 +41,7 @@ "NUCLEO_L031K6", "NUCLEO_L432KC", "NUCLEO_F303K8", + "BLUE_F407VE_Mini", "BLUEPILL_F103C8", "MAPLEMINI_F103CB", "RAK811_TRACKER", @@ -77,23 +78,32 @@ "pattern": "X_NUCLEO_IDB05A1_HelloWorld.ino", "applicable": false, "boards": [ - "NUCLEO_L031K6", "NUCLEO_L432KC", "NUCLEO_F303K8", + "BLUE_F407VE_Mini", "BLUEPILL_F103C8", - "MAPLEMINI_F103CB", - "RAK811_TRACKER" + "MAPLEMINI_F103CB" ] }, { - "pattern": "X_NUCLEO_IKA01A1_HelloWorld.ino|X_NUCLEO_IHM02A1_HelloWorld.ino", + "pattern": "X_NUCLEO_|FP_Examples", "applicable": false, - "boards": [ "RAK811_TRACKER" ] + "boards": [ "NUCLEO_L031K6", "RAK811_TRACKER", "REMRAM_V1" ] }, { "pattern": "StringComparisonOperators.ino", "applicable": false, - "boards": [ "REMRAM_V1" ] + "boards": [ "RAK811_TRACKER", "REMRAM_V1" ] + }, + { + "pattern": "ADXL3xx.ino", + "applicable": false, + "boards": [ "RAK811_TRACKER" ] + }, + { + "pattern": "SerialLoop.ino", + "applicable": false, + "boards": [ "NUCLEO_L031K6" ] } ] }, From e971088c14af729ac330a29ed760e8bee71c48ab Mon Sep 17 00:00:00 2001 From: Nils Hasenbanck Date: Thu, 4 Oct 2018 16:29:26 +0200 Subject: [PATCH 094/109] Change variant RemRam for final design I had to make some backward incompatible changes: * Remove the KILL_PIN * Change SS_SD to SS_SDLCD for external SD card * Added SS_SD for on-board SD card reader Since the only development boards are in my possession, this breaking change shouldn't affect anybody. Going forward the board in version 1 is considered feature complete and won't change in a backward incompatible way. --- variants/REMRAM_V1/variant.cpp | 6 ++++-- variants/REMRAM_V1/variant.h | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/variants/REMRAM_V1/variant.cpp b/variants/REMRAM_V1/variant.cpp index 1debb48b81..d20948f01c 100644 --- a/variants/REMRAM_V1/variant.cpp +++ b/variants/REMRAM_V1/variant.cpp @@ -55,7 +55,7 @@ extern "C" PE_1, // D8 - EXT_D5 // SPI - PB_2, // D9 - SS_SD + PB_2, // D9 - SS_SDLCD PC_4, // D10 - SS_E PA_7, // D11 - MOSI PA_6, // D12 - MISO @@ -120,7 +120,9 @@ extern "C" PC_14, // D54 - BTN_EN1 PC_15, // D55 - BTN_EN2 PC_13, // D56 - SD_CARD_DET - PE_6, // D57 - KILL_PIN + + // SD Card Reader + PE_7, // D57 - SS_SD // Endstops PB_12, // D58 - X_MIN diff --git a/variants/REMRAM_V1/variant.h b/variants/REMRAM_V1/variant.h index 14feeae82a..38c5a53b6e 100644 --- a/variants/REMRAM_V1/variant.h +++ b/variants/REMRAM_V1/variant.h @@ -65,7 +65,7 @@ extern "C" PE1, // D8 - EXT_D5 // SPI - PB2, // D9 - SS_SD + PB2, // D9 - SS_SDLCD PC4, // D10 - SS_E PA7, // D11 - MOSI PA6, // D12 - MISO @@ -130,7 +130,9 @@ extern "C" PC14, // D54 - BTN_EN1 PC15, // D55 - BTN_EN2 PC13, // D56 - SD_CARD_DET - PE6, // D57 - KILL_PIN + + // SD Card Reader + PE7, // D57 - SS_SD // Endstops PB12, // D58 - X_MIN From c3d12c670ce457bf8e096e205ff28ba58bf31c30 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 9 Oct 2018 10:00:23 +0200 Subject: [PATCH 095/109] Allow use of a custom startup file Syntax in the board.txt: xxx.build.startup_file=-DCUSTOM_STARTUP_FILE Example to use a custom startup file for Nucleo_L476RG: Nucleo_64.menu.pnum.NUCLEO_L476RG.build.startup_file=-DCUSTOM_STARTUP_FILE Then add a "*.S" file in the "variant/NUCLEO_L476RG/" folder Important note: extension must be '.S' not '.s' CUSTOM_STARTUP_FILE could also be defined thanks the build_opt.h. CMSIS_STARTUP_FILE could now be overridden using the build_opt.h, ex: -DCMSIS_STARTUP_FILE=\"startup_stm32l476xx.s\" Signed-off-by: Frederic.Pillon --- cores/arduino/stm32/startup_stm32yyxx.S | 3 ++- cores/arduino/stm32/stm32_def_build.h | 6 +++++- platform.txt | 3 ++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/cores/arduino/stm32/startup_stm32yyxx.S b/cores/arduino/stm32/startup_stm32yyxx.S index 77f9a2b1c5..8572083cdd 100644 --- a/cores/arduino/stm32/startup_stm32yyxx.S +++ b/cores/arduino/stm32/startup_stm32yyxx.S @@ -1,4 +1,5 @@ #include "stm32_def_build.h" +#if defined(CMSIS_STARTUP_FILE) #include CMSIS_STARTUP_FILE - +#endif diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index d131d85361..5b2709fb4b 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -1,6 +1,7 @@ #ifndef _STM32_DEF_BUILD_ #define _STM32_DEF_BUILD_ +#if !defined(CMSIS_STARTUP_FILE) && !defined(CUSTOM_STARTUP_FILE) #if defined(STM32F030x6) #define CMSIS_STARTUP_FILE "startup_stm32f030x6.s" #elif defined(STM32F030x8) @@ -296,4 +297,7 @@ #else #error UNKNOWN CHIP #endif -#endif //_STM32_DEF_BUILD_ +#else +#warning "No CMSIS startup file defined, custom one should be used" +#endif /* !CMSIS_STARTUP_FILE && !CUSTOM_STARTUP_FILE */ +#endif /* _STM32_DEF_BUILD_ */ diff --git a/platform.txt b/platform.txt index 4260277745..a09134bf16 100644 --- a/platform.txt +++ b/platform.txt @@ -59,7 +59,7 @@ compiler.c.extra_flags= compiler.c.elf.extra_flags= compiler.cpp.extra_flags= compiler.cpp.std=gnu++14 -compiler.S.extra_flags= +compiler.S.extra_flags={build.startup_file} compiler.ar.extra_flags= compiler.elf2bin.extra_flags= compiler.elf2hex.extra_flags= @@ -81,6 +81,7 @@ build.info.flags=-D{build.series} -DARDUINO={runtime.ide.version} -DARDUINO_{bui # Defaults config build.xSerial=-DHAL_UART_MODULE_ENABLED build.enable_usb= +build.startup_file= build.flags.optimize=-Os build.flags.ldspecs=--specs=nano.specs From 6f9963c025eb0b0d364f9f707d97bd4ebfafbc5b Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Fri, 12 Oct 2018 09:37:10 +0200 Subject: [PATCH 096/109] Fix warning in twi.c (I2C) --- cores/arduino/stm32/twi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cores/arduino/stm32/twi.c b/cores/arduino/stm32/twi.c index 2c3ad39804..44c8e9fc34 100644 --- a/cores/arduino/stm32/twi.c +++ b/cores/arduino/stm32/twi.c @@ -548,14 +548,14 @@ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, ui if(obj->i2c_onSlaveTransmit != NULL) { obj->i2c_onSlaveTransmit(); } - HAL_I2C_Slave_Sequential_Transmit_IT(hi2c, obj->i2cTxRxBuffer, + HAL_I2C_Slave_Sequential_Transmit_IT(hi2c, (uint8_t *) obj->i2cTxRxBuffer, obj->i2cTxRxBufferSize, I2C_LAST_FRAME); } else { obj->slaveRxNbData = 0; obj->slaveMode = SLAVE_MODE_RECEIVE; /* We don't know in advance how many bytes will be sent by master so * we'll fetch one by one until master ends the sequence */ - HAL_I2C_Slave_Sequential_Receive_IT(hi2c, &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), + HAL_I2C_Slave_Sequential_Receive_IT(hi2c, (uint8_t *) &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), 1, I2C_NEXT_FRAME); } } @@ -576,7 +576,7 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) if((obj->i2c_onSlaveReceive != NULL) && (obj->slaveMode == SLAVE_MODE_RECEIVE)) { if(obj->slaveRxNbData != 0) { - obj->i2c_onSlaveReceive(obj->i2cTxRxBuffer, obj->slaveRxNbData); + obj->i2c_onSlaveReceive((uint8_t *) obj->i2cTxRxBuffer, obj->slaveRxNbData); } } obj->slaveMode = SLAVE_MODE_LISTEN; @@ -601,7 +601,7 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) } /* Restart interrupt mode for next Byte */ if(obj->slaveMode == SLAVE_MODE_RECEIVE) { - HAL_I2C_Slave_Sequential_Receive_IT(hi2c, &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), + HAL_I2C_Slave_Sequential_Receive_IT(hi2c, (uint8_t *) &(obj->i2cTxRxBuffer[obj->slaveRxNbData]), 1, I2C_NEXT_FRAME); } } From 6bb57a8d4eb3c22b8324e24087d6d457b5a17d37 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 28 Sep 2018 14:12:58 +0200 Subject: [PATCH 097/109] Rename syscall file Signed-off-by: Frederic.Pillon --- cores/arduino/{syscalls_stm32.c => syscalls.c} | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) rename cores/arduino/{syscalls_stm32.c => syscalls.c} (92%) diff --git a/cores/arduino/syscalls_stm32.c b/cores/arduino/syscalls.c similarity index 92% rename from cores/arduino/syscalls_stm32.c rename to cores/arduino/syscalls.c index 2631b78b30..bdf970ad18 100644 --- a/cores/arduino/syscalls_stm32.c +++ b/cores/arduino/syscalls.c @@ -29,13 +29,8 @@ register char * stack_ptr asm("sp"); caddr_t _sbrk( int incr ) { extern char _end; /* Defined by the linker */ - static char *heap_end = NULL ; - char *prev_heap_end ; - - if ( heap_end == NULL ) { - heap_end = &_end ; - } - prev_heap_end = heap_end; + static char *heap_end = &_end ; + char *prev_heap_end = heap_end; if (heap_end + incr > stack_ptr) { /* Heap and stack collision */ From e257ad5ced37a173aff89aa33494975297fe8d87 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 28 Sep 2018 14:13:22 +0200 Subject: [PATCH 098/109] Fix possible issue with realloc usage Signed-off-by: Frederic.Pillon --- libraries/Wire/src/Wire.cpp | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index d6ed2becb2..cfafbf1870 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -435,8 +435,13 @@ void TwoWire::allocateRxBuffer(size_t length) if(rxBufferAllocated < length) { // By default we allocate BUFFER_LENGTH bytes. It is the min size of the buffer. if(length < BUFFER_LENGTH) { length = BUFFER_LENGTH; } - rxBuffer = (uint8_t *)realloc(rxBuffer, length * sizeof(uint8_t)); - rxBufferAllocated = (rxBuffer != nullptr) ? length: 0; + uint8_t *tmp = (uint8_t *)realloc(rxBuffer, length * sizeof(uint8_t)); + if(tmp != nullptr) { + rxBuffer = tmp; + rxBufferAllocated = length; + } else { + _Error_Handler("No enough memory! (%i)\n", length); + } } } @@ -445,8 +450,13 @@ inline void TwoWire::allocateTxBuffer(size_t length) if(txBufferAllocated < length) { // By default we allocate BUFFER_LENGTH bytes. It is the min size of the buffer. if(length < BUFFER_LENGTH) { length = BUFFER_LENGTH; } - txBuffer = (uint8_t *)realloc(txBuffer, length * sizeof(uint8_t)); - txBufferAllocated = (txBuffer != nullptr) ? length: 0; + uint8_t *tmp = (uint8_t *)realloc(txBuffer, length * sizeof(uint8_t)); + if(tmp != nullptr) { + txBuffer = tmp; + txBufferAllocated = length; + } else { + _Error_Handler("No enough memory! (%i)\n", length); + } } } From 8cef68d73855db9733b76d1f5a06cc5b8fae94f8 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 3 Oct 2018 15:25:18 +0200 Subject: [PATCH 099/109] Define _sbrk as weak This will allow to user to override the default behavior. Signed-off-by: Frederic.Pillon --- cores/arduino/syscalls.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cores/arduino/syscalls.c b/cores/arduino/syscalls.c index bdf970ad18..d8003466a6 100644 --- a/cores/arduino/syscalls.c +++ b/cores/arduino/syscalls.c @@ -27,6 +27,7 @@ extern size_t uart_debug_write(uint8_t *data, uint32_t size); register char * stack_ptr asm("sp"); +__attribute__((weak)) caddr_t _sbrk( int incr ) { extern char _end; /* Defined by the linker */ static char *heap_end = &_end ; From b25ccca571fc29504cbff09aa9c96953a8825f25 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 3 Oct 2018 15:14:17 +0200 Subject: [PATCH 100/109] Avoid user heap to override the minimum stack size Minimum stack size is defined in linker script: _Min_Stack_Size = 0x400;; /* required amount of stack */ If more stack is requested, then user have to ensure that heap and stack can fit in the SRAM. Fix #307 Signed-off-by: Frederic.Pillon --- cores/arduino/syscalls.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/cores/arduino/syscalls.c b/cores/arduino/syscalls.c index d8003466a6..975135e9e7 100644 --- a/cores/arduino/syscalls.c +++ b/cores/arduino/syscalls.c @@ -29,6 +29,8 @@ register char * stack_ptr asm("sp"); __attribute__((weak)) caddr_t _sbrk( int incr ) { + extern char _estack; /* Defined in the linker script */ + extern char _Min_Stack_Size; /* Defined in the linker script */ extern char _end; /* Defined by the linker */ static char *heap_end = &_end ; char *prev_heap_end = heap_end; @@ -38,6 +40,11 @@ caddr_t _sbrk( int incr ) { errno = ENOMEM; return (caddr_t) -1; } + /* Ensure to keep minimun stack size defined in the linker script */ + if (heap_end + incr >= (char*)(&_estack - &_Min_Stack_Size)) { + errno = ENOMEM; + return (caddr_t) -1; + } heap_end += incr ; return (caddr_t) prev_heap_end ; From 12bc1c2321a2c85ab81328704f0d64c2625d8dfa Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 4 Oct 2018 10:20:03 +0200 Subject: [PATCH 101/109] [Nucleo-L432KC] Provide full SRAM access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit STM32L432xx SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2000 C000, offering a contiguous address space with the SRAM1 (16 Kbyte aliased by bit band Signed-off-by: Frederic.Pillon --- variants/NUCLEO_L432KC/ldscript.ld | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/variants/NUCLEO_L432KC/ldscript.ld b/variants/NUCLEO_L432KC/ldscript.ld index 407bbb90a5..4280cfd517 100644 --- a/variants/NUCLEO_L432KC/ldscript.ld +++ b/variants/NUCLEO_L432KC/ldscript.ld @@ -33,7 +33,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ -_estack = 0x2000c000; /* end of RAM */ +_estack = 0x20010000; /* end of RAM */ /* Generate a link error if heap and stack don't fit into RAM */ _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ @@ -41,9 +41,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ MEMORY { -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K -SRAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 16K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K } /* Define output sections */ @@ -58,7 +57,7 @@ SECTIONS } >FLASH /* The program code and other data goes into FLASH */ - .text ALIGN(8): + .text : { . = ALIGN(8); *(.text) /* .text sections (code) */ @@ -140,25 +139,6 @@ SECTIONS _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH - _sisram2 = LOADADDR(.sram2); - - /* CCM-RAM section - * - * IMPORTANT NOTE! - * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. - */ - .sram2 : - { - . = ALIGN(8); - _ssram2 = .; /* create a global symbol at sram2 start */ - *(.sram2) - *(.sram2*) - - . = ALIGN(8); - _esram2 = .; /* create a global symbol at sram2 end */ - } >SRAM2 AT> FLASH - /* Uninitialized data section */ . = ALIGN(4); From c3e2de671f87ce6cb8bba58c157ceb2fde676fad Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Thu, 4 Oct 2018 10:32:17 +0200 Subject: [PATCH 102/109] [Nucleo-L476RG] Fix available SRAM size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit STM32L476xx SRAM is split into two blocks: • 96 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). Only the SRAM1 is managed. One enhancement could be done to use SRAM1 for the heap and SRAM2 for the stack. (Refer to MBED) Signed-off-by: Frederic.Pillon --- boards.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.txt b/boards.txt index 9dd40c9f13..4daf7fc1e7 100644 --- a/boards.txt +++ b/boards.txt @@ -282,7 +282,7 @@ Nucleo_64.menu.pnum.NUCLEO_L152RE.build.cmsis_lib_gcc=arm_cortexM3l_math Nucleo_64.menu.pnum.NUCLEO_L476RG=Nucleo L476RG Nucleo_64.menu.pnum.NUCLEO_L476RG.node=NODE_L476RG Nucleo_64.menu.pnum.NUCLEO_L476RG.upload.maximum_size=1048576 -Nucleo_64.menu.pnum.NUCLEO_L476RG.upload.maximum_data_size=131072 +Nucleo_64.menu.pnum.NUCLEO_L476RG.upload.maximum_data_size=98304 Nucleo_64.menu.pnum.NUCLEO_L476RG.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard Nucleo_64.menu.pnum.NUCLEO_L476RG.build.board=NUCLEO_L476RG Nucleo_64.menu.pnum.NUCLEO_L476RG.build.series=STM32L4xx From 14b4dd89534aad11de11ed48931e0807888ccdde Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 9 Oct 2018 08:23:28 +0200 Subject: [PATCH 103/109] Use CMSIS function to get SP Signed-off-by: Frederic.Pillon --- cores/arduino/syscalls.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/cores/arduino/syscalls.c b/cores/arduino/syscalls.c index 975135e9e7..c545eb6f34 100644 --- a/cores/arduino/syscalls.c +++ b/cores/arduino/syscalls.c @@ -5,6 +5,7 @@ * */ +#include "stm32_def.h" #if defined ( __GNUC__ ) /* GCC CS3 */ #include #endif @@ -25,8 +26,6 @@ extern size_t uart_debug_write(uint8_t *data, uint32_t size); #define UNUSED(x) x ## _UNUSED #endif -register char * stack_ptr asm("sp"); - __attribute__((weak)) caddr_t _sbrk( int incr ) { extern char _estack; /* Defined in the linker script */ @@ -35,7 +34,7 @@ caddr_t _sbrk( int incr ) { static char *heap_end = &_end ; char *prev_heap_end = heap_end; - if (heap_end + incr > stack_ptr) { + if (heap_end + incr > (char *)__get_MSP()) { /* Heap and stack collision */ errno = ENOMEM; return (caddr_t) -1; From 20dc15290a9b4c13d9ef5e2f0991a77d3ae331f4 Mon Sep 17 00:00:00 2001 From: Venelin Efremov Date: Sun, 26 Aug 2018 14:43:26 -0700 Subject: [PATCH 104/109] Use define instead of enum for pins in variant.h Remove PEND as no more relevant Remove duplicated pins which is not required anymore as PEND removed Signed-off-by: Venelin Efremov --- cores/arduino/pins_arduino.h | 3 - variants/BLACK_F407VE/variant.h | 153 +++++++------- variants/BLUEPILL_F103C8/variant.h | 75 ++++--- variants/BLUE_F407VE_Mini/variant.h | 212 +++++++++---------- variants/DISCO_F030R8/variant.h | 138 ++++++------- variants/DISCO_F100RB/variant.h | 118 +++++------ variants/DISCO_F407VG/variant.h | 177 ++++++++-------- variants/DISCO_F746NG/variant.h | 59 +++--- variants/DISCO_L072CZ_LRWAN1/variant.h | 90 ++++----- variants/DISCO_L475VG_IOT/variant.h | 168 +++++++-------- variants/MAPLEMINI_F103CB/variant.h | 86 ++++---- variants/NUCLEO_F030R8/variant.h | 124 ++++++------ variants/NUCLEO_F091RC/variant.h | 118 +++++------ variants/NUCLEO_F103RB/variant.h | 130 ++++++------ variants/NUCLEO_F207ZG/variant.h | 191 ++++++++---------- variants/NUCLEO_F302R8/variant.h | 118 +++++------ variants/NUCLEO_F303K8/variant.h | 53 +++-- variants/NUCLEO_F303RE/variant.h | 120 +++++------ variants/NUCLEO_F401RE/variant.h | 119 +++++------ variants/NUCLEO_F411RE/variant.h | 119 +++++------ variants/NUCLEO_F429ZI/variant.h | 192 +++++++++--------- variants/NUCLEO_F446RE/variant.h | 120 +++++------ variants/NUCLEO_F767ZI/variant.h | 192 +++++++++--------- variants/NUCLEO_L031K6/variant.h | 51 +++-- variants/NUCLEO_L053R8/variant.h | 118 +++++------ variants/NUCLEO_L073RZ/variant.h | 119 +++++------ variants/NUCLEO_L152RE/variant.h | 123 +++++------ variants/NUCLEO_L432KC/variant.h | 53 +++-- variants/NUCLEO_L476RG/variant.h | 118 +++++------ variants/NUCLEO_L496ZG/variant.h | 269 ++++++++++++------------- variants/NUCLEO_L4R5ZI/variant.h | 261 ++++++++++++------------ variants/RAK811_TRACKER/variant.h | 77 ++++--- variants/REMRAM_V1/variant.h | 204 +++++++++---------- variants/board_template/variant.h | 33 ++- 34 files changed, 1994 insertions(+), 2307 deletions(-) diff --git a/cores/arduino/pins_arduino.h b/cores/arduino/pins_arduino.h index cf28def2a2..b13b9c36e0 100644 --- a/cores/arduino/pins_arduino.h +++ b/cores/arduino/pins_arduino.h @@ -23,9 +23,6 @@ // Avoid PortName issue _Static_assert(LastPort <= 0x0F, "PortName must be less than 16"); -// Avoid pins number misalignment -_Static_assert(NUM_DIGITAL_PINS==PEND, "NUM_DIGITAL_PINS and PEND differ!"); - // Arduino digital pins alias // GPIO port (A to K) * 16 pins: 176 enum { diff --git a/variants/BLACK_F407VE/variant.h b/variants/BLACK_F407VE/variant.h index 6b7fabb4b3..0f4bb05bf0 100644 --- a/variants/BLACK_F407VE/variant.h +++ b/variants/BLACK_F407VE/variant.h @@ -44,80 +44,85 @@ extern "C"{ * Pins *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; - -enum { - // Left Side - //Ext //Int - //5V //5V - //5V //5V - //3V3 //3V3 - //3V3 //3V3 - //GND //GND - PE2, PE3, // D0, D1 - PE4, PE5, // PE_4: BUT K0, PE_5: BUT K1 - PE6, PC13, - PC0, PC1, - PC2, PC3, - //VREF- //VREF+ - PA0, PA1, // D10, D11 PA_0(WK_UP): BUT K_UP) - PA2, PA3, - PA4, PA5, - PA6, PA7, // PA_6: LED D2, PA_7: LED D3 (active LOW) - PC4, PC5, - PB0, PB1, // D20, D21 - PE7, PE8, - PE9, PE10, - PE11, PE12, - PE13, PE14, - PE15, PB10, // D30, D31 - PB11, PB12, - PB13, PB14, - // Right Side - //Int //Ext - //3V3 //3V3 - //3V3 //3V3 - //BOOT0 //BOOT1 - //GND //GND - //GND //GND - PE1, PE0, - PB9, PB8, - PB7, PB6, // D40, D41 - PB5, PB3, - PD7, PD6, - PD5, PD4, - PD3, PD2, - PD1, PD0, // D50, D51 - PC12, PC11, - PC10, PA15, - PA12, PA11, // PA_11: USB_DM, PA_12: USB_DP - PA10, PA9, - PA8, PC9, // D60, D61 - PC8, PC7, - PC6, PD15, - PD14, PD13, - PD12, PD11, - PD10, PD9, // D70, D71 - PD8, PB15, - PB4, - // Analog pins - PA0_A, // D75 - PA1_A, - PA2_A, - PA3_A, - PA4_A, - PA5_A, // D80 - PB0_A, - PB1_A, - PC0_A, - PC1_A, - PC2_A, - PC3_A, - PC4_A, - PC5_A, - PEND -}; - -// This must be a literal with the same value as PEND +// Left Side +#define PE2 0 +#define PE3 1 +#define PE4 2 // BUT K0 +#define PE5 3 // BUT K1 +#define PE6 4 +#define PC13 5 +#define PC0 6 // A8 +#define PC1 7 // A9 +#define PC2 8 // A10 +#define PC3 9 // A11 +#define PA0 10 // A0/WK_UP: BUT K_UP +#define PA1 11 // A1 +#define PA2 12 // A2 +#define PA3 13 // A3 +#define PA4 14 // A4 +#define PA5 15 // A5 +#define PA6 16 // LED D2 +#define PA7 17 // LED D3 (active LOW) +#define PC4 18 // A12 +#define PC5 19 // A13 +#define PB0 20 // A6 +#define PB1 21 // A7 +#define PE7 22 +#define PE8 23 +#define PE9 24 +#define PE10 25 +#define PE11 26 +#define PE12 27 +#define PE13 28 +#define PE14 29 +#define PE15 30 +#define PB10 31 +#define PB11 32 +#define PB12 33 +#define PB13 34 +#define PB14 35 +// Right Side +#define PE1 36 +#define PE0 37 +#define PB9 38 +#define PB8 39 +#define PB7 40 +#define PB6 41 +#define PB5 42 +#define PB3 43 +#define PD7 44 +#define PD6 45 +#define PD5 46 +#define PD4 47 +#define PD3 48 +#define PD2 49 +#define PD1 50 +#define PD0 51 +#define PC12 52 +#define PC11 53 +#define PC10 54 +#define PA15 55 +#define PA12 56 // USB_DP +#define PA11 57 // USB_DM +#define PA10 58 +#define PA9 59 +#define PA8 60 +#define PC9 61 +#define PC8 62 +#define PC7 63 +#define PC6 64 +#define PD15 65 +#define PD14 66 +#define PD13 67 +#define PD12 68 +#define PD11 69 +#define PD10 70 +#define PD9 71 +#define PD8 72 +#define PB15 73 +#define PB4 74 + +// This must be a literal #define NUM_DIGITAL_PINS 89 // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 diff --git a/variants/BLUEPILL_F103C8/variant.h b/variants/BLUEPILL_F103C8/variant.h index 9abe752a0c..ed24c56705 100644 --- a/variants/BLUEPILL_F103C8/variant.h +++ b/variants/BLUEPILL_F103C8/variant.h @@ -44,50 +44,47 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { // USB connector on the top, MCU side // Left Side - PB9, //D0 - PB8, //D1 - PB7, //D2 - PB6, //D3 - PB5, //D4 - PB4, //D5 - PB3, //D6 - PA15, //D7 - PA12, //D8 - USB DP - PA11, //D9 - USB DM - PA10, //D10 - PA9, //D11 - PA8, //D12 - PB15, //D13 - PB14, //D14 - PB13, //D15 - PB12, //D16 +#define PB9 0 +#define PB8 1 +#define PB7 2 +#define PB6 3 +#define PB5 4 +#define PB4 5 +#define PB3 6 +#define PA15 7 +#define PA12 8 // USB DP +#define PA11 9 // USB DM +#define PA10 10 +#define PA9 11 +#define PA8 12 +#define PB15 13 +#define PB14 14 +#define PB13 15 +#define PB12 16 // Right side - PC13, //D17 - LED - PC14, //D18 - PC15, //D19 - PA0, //D20/A0 - PA1, //D21/A1 - PA2, //D22/A2 - PA3, //D23/A3 - PA4, //D24/A4 - PA5, //D25/A5 - PA6, //D26/A6 - PA7, //D27/A7 - PB0, //D28/A8 - PB1, //D29/A9 - PB10, //D30 - PB11, //D31 +#define PC13 17 // LED +#define PC14 18 +#define PC15 19 +#define PA0 20 // A0 +#define PA1 21 // A1 +#define PA2 22 // A2 +#define PA3 23 // A3 +#define PA4 24 // A4 +#define PA5 25 // A5 +#define PA6 26 // A6 +#define PA7 27 // A7 +#define PB0 28 // A8 +#define PB1 29 // A9 +#define PB10 30 +#define PB11 31 // Other - PB2, //D32 - BOOT1 - PA13, //D33 - SWDI0 - PA14, //D34 - SWCLK - PEND -}; +#define PB2 32 // BOOT1 +#define PA13 33 // SWDI0 +#define PA14 34 // SWCLK -// This must be a literal with the same value as PEND +// This must be a literal #define NUM_DIGITAL_PINS 35 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 10 diff --git a/variants/BLUE_F407VE_Mini/variant.h b/variants/BLUE_F407VE_Mini/variant.h index d018e24543..cea8978e78 100644 --- a/variants/BLUE_F407VE_Mini/variant.h +++ b/variants/BLUE_F407VE_Mini/variant.h @@ -44,121 +44,103 @@ extern "C"{ * Pins *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; - -enum { -//External (left to right) - //GND - //VBAT - //5V - PE0, //D0 - PE2, - PE4, - PE6, - PC14, //OSC32_IN - PC0, - PC2, - PA0, - PA1, - PA4, - PA6, //D10 - PC4, - PB0, - PB2, - PE8, - PE9, - PE11, - PE13, - PE15, - PB11, - PB13, //D20 - PB15, - PD9, - PD11, - PD13, - PD15, - PC6, - PC8, - PC9, - PA9, - PA11, //D30 - USB_DM - PA13, - PA15, - PC11, - PC12, - PD1, - PD3, - PD5, - PD7, - PB4, - PB6, //D40 - PB8, - //GND - //3V3 - //GND -//Internal (left to right) - //GND - //3V3 - //5V - PE1, - PE3, - PE5, - PC13, - PC15, //OSC32_OUT - PC1, - PC3, - PA2, - PA3, //D50 - PA5, - PA7, - PC5, - PB1, - PE7, - PE10, - PE12, - PE14, - PB10, - PB12, //D60 - PB14, - PD8, - PD10, - PD12, - PD14, - PC7, - PA8, - PA10, - PA12, //USB_DP - PA14, //D70 - PC10, - PD0, - PD2, - PD4, - PD6, - PB3, - PB5, - PB7, - PB9, //D79 - LED - //GND - //3V3 - //GND - // Analog pins - PA0_A, //D80 - PA1_A, - PA2_A, - PA3_A, - PA4_A, - PA5_A, - PB0_A, - PB1_A, - PC0_A, - PC1_A, - PC2_A, //D90 - PC3_A, - PC4_A, - PC5_A, - PEND -}; - -// This must be a literal with the same value as PEND +// External (left to right) +// GND +// VBAT +// 5V +#define PE0 0 +#define PE2 1 +#define PE4 2 +#define PE6 3 +#define PC14 4 // OSC32_IN +#define PC0 5 // A8 +#define PC2 6 // A10 +#define PA0 7 // A0 +#define PA1 8 // A1 +#define PA4 9 // A4 +#define PA6 10 +#define PC4 11 // A12 +#define PB0 12 // A6 +#define PB2 13 +#define PE8 14 +#define PE9 15 +#define PE11 16 +#define PE13 17 +#define PE15 18 +#define PB11 19 +#define PB13 20 +#define PB15 21 +#define PD9 22 +#define PD11 23 +#define PD13 24 +#define PD15 25 +#define PC6 26 +#define PC8 27 +#define PC9 28 +#define PA9 29 +#define PA11 30 // USB_DM +#define PA13 31 +#define PA15 32 +#define PC11 33 +#define PC12 34 +#define PD1 35 +#define PD3 36 +#define PD5 37 +#define PD7 38 +#define PB4 39 +#define PB6 40 +#define PB8 41 +// GND +// 3V3 +// GND +// Internal (left to right) +// GND +// 3V3 +// 5V +#define PE1 42 +#define PE3 43 +#define PE5 44 +#define PC13 45 +#define PC15 46 // OSC32_OUT +#define PC1 47 // A9 +#define PC3 48 // A11 +#define PA2 49 // A2 +#define PA3 50 // A3 +#define PA5 51 // A5 +#define PA7 52 +#define PC5 53 // A13 +#define PB1 54 // A7 +#define PE7 55 +#define PE10 56 +#define PE12 57 +#define PE14 58 +#define PB10 59 +#define PB12 60 +#define PB14 61 +#define PD8 62 +#define PD10 63 +#define PD12 64 +#define PD14 65 +#define PC7 66 +#define PA8 67 +#define PA10 68 +#define PA12 69 // USB_DP +#define PA14 70 +#define PC10 71 +#define PD0 72 +#define PD2 73 +#define PD4 74 +#define PD6 75 +#define PB3 76 +#define PB5 77 +#define PB7 78 +#define PB9 79 // LED + +// GND +// 3V3 +// GND + +// This must be a literal #define NUM_DIGITAL_PINS 94 // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 diff --git a/variants/DISCO_F030R8/variant.h b/variants/DISCO_F030R8/variant.h index 54362354d3..c78b0421a6 100644 --- a/variants/DISCO_F030R8/variant.h +++ b/variants/DISCO_F030R8/variant.h @@ -46,85 +46,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - //P1 connector Right side (bottom view) - PC13, //D0 - PC14, //D1 - PC15, //D2 - PF0, //D3 - PF1, //D4 - PC0, //D5 - PC1, //D6 - PC2, //D7 - PC3, //D8 - PA0, //D9 - USER_BTN - PA1, //D10 - PA2, //D11 - PA3, //D12 - PF4, //D13 - PF5, //D14 - PA4, //D15 - PA5, //D16 - PA6, //D17 - PA7, //D18 - PC4, //D19 - PC5, //D20 - PB0, //D21 - PB1, //D22 - PB2, //D23 - PB10, //D24 - PB11, //D25 - PB12, //D26 - //P2 connector Left side (bottom view) - PB9, //D27 - PB8, //D28 - PB7, //D29 - PB6, //D30 - PB5, //D31 - PB4, //D32 - PB3, //D33 - PD2, //D34 - PC12, //D35 - PC11, //D36 - PC10, //D37 - PA15, //D38 - PA14, //D39 - PF7, //D40 - PF6, //D41 - PA13, //D42 - PA12, //D43 - PA11, //D44 - PA10, //D45 - PA9, //D46 - PA8, //D47 - PC9, //D48 - LED_GREEN (LD3) - PC8, //D49 - LED_BLUE (LD4) - PC7, //D50 - PC6, //D51 - PB15, //D52 - PB14, //D53 - PB13, //D54 - // Duplicated pins in order to be aligned with PinMap_ADC - PC_0_A, //D55/A0 = D5 - PC_1_A, //D56/A1 = D6 - PC_2_A, //D57/A2 = D7 - PC_3_A, //D58/A3 = D8 - PA_0_A, //D59/A4 = D9 - PA_1_A, //D60/A5 = D10 - PA_2_A, //D61/A6 = D11 - PA_3_A, //D62/A7 = D12 - PA_4_A, //D63/A8 = D15 - PA_5_A, //D64/A9 = D16 - PA_6_A, //D65/A10 = D17 - PA_7_A, //D66/A11 = D18 - PC_4_A, //D67/A12 = D19 - PC_5_A, //D68/A13 = D20 - PB_0_A, //D69/A14 = D21 - PB_1_A, //D70/A15 = D22 - PEND -}; - -// This must be a literal with the same value as PEND +// P1 connector Right side (bottom view) +#define PC13 0 +#define PC14 1 +#define PC15 2 +#define PF0 3 +#define PF1 4 +#define PC0 5 // A0 +#define PC1 6 // A1 +#define PC2 7 // A2 +#define PC3 8 // A3 +#define PA0 9 // A4/USER_BTN +#define PA1 10 // A5 +#define PA2 11 // A6 +#define PA3 12 // A7 +#define PF4 13 +#define PF5 14 +#define PA4 15 // A8 +#define PA5 16 // A9 +#define PA6 17 // A10 +#define PA7 18 // A11 +#define PC4 19 // A12 +#define PC5 20 // A13 +#define PB0 21 // A14 +#define PB1 22 // A15 +#define PB2 23 +#define PB10 24 +#define PB11 25 +#define PB12 26 +// P2 connector Left side (bottom view) +#define PB9 27 +#define PB8 28 +#define PB7 29 +#define PB6 30 +#define PB5 31 +#define PB4 32 +#define PB3 33 +#define PD2 34 +#define PC12 35 +#define PC11 36 +#define PC10 37 +#define PA15 38 +#define PA14 39 +#define PF7 40 +#define PF6 41 +#define PA13 42 +#define PA12 43 +#define PA11 44 +#define PA10 45 +#define PA9 46 +#define PA8 47 +#define PC9 48 // LED_GREEN (LD3) +#define PC8 49 // LED_BLUE (LD4) +#define PC7 50 +#define PC6 51 +#define PB15 52 +#define PB14 53 +#define PB13 54 + +// This must be a literal #define NUM_DIGITAL_PINS 71 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 16 diff --git a/variants/DISCO_F100RB/variant.h b/variants/DISCO_F100RB/variant.h index f241b3b9c1..2ffa455b9f 100644 --- a/variants/DISCO_F100RB/variant.h +++ b/variants/DISCO_F100RB/variant.h @@ -33,78 +33,58 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { // P1 connector - PC13, //D0 - PC0, //D1 - PC1, //D2 - PC2, //D3 - PC3, //D4 - PA0, //D5 - User button - PA1, //D6 - PA2, //D7 - PA3, //D8 - PA4, //D9 - PA5, //D10 - PA6, //D11 - PA7, //D12 - PC4, //D13 - PC5, //D14 - PB0, //D15 - PB1, //D16 - PB2, //D17 +#define PC13 0 +#define PC0 1 // A0 +#define PC1 2 // A1 +#define PC2 3 // A2 +#define PC3 4 // A3 +#define PA0 5 // A4/User button +#define PA1 6 // A5 +#define PA2 7 // A6 +#define PA3 8 // A7 +#define PA4 9 // A8 +#define PA5 10 // A9 +#define PA6 11 // A10 +#define PA7 12 // A11 +#define PC4 13 // A12 +#define PC5 14 // A13 +#define PB0 15 // A14 +#define PB1 16 // A15 +#define PB2 17 // P2 connector - PC6, //D18 - PC7, //D19 - PC8, //D20 - LED blue - PC9, //D21 - LED green - PA8, //D22 - PA9, //D23 - PA10, //D24 - PA11, //D25 - PA12, //D26 - PA13, //D27 - PA14, //D28 - PA15, //D29 - PC10, //D30 - PC11, //D31 - PC12, //D32 - PD2, //D33 - PB3, //D34 - PB4, //D35 - PB5, //D36 - I2C SCL - PB6, //D37 - I2C SDA - PB7, //D38 - PB8, //D39 - PB9, //D40 +#define PC6 18 +#define PC7 19 +#define PC8 20 // LED blue +#define PC9 21 // LED green +#define PA8 22 +#define PA9 23 +#define PA10 24 +#define PA11 25 +#define PA12 26 +#define PA13 27 +#define PA14 28 +#define PA15 29 +#define PC10 30 +#define PC11 31 +#define PC12 32 +#define PD2 33 +#define PB3 34 +#define PB4 35 +#define PB5 36 // I2C SCL +#define PB6 37 // I2C SDA +#define PB7 38 +#define PB8 39 +#define PB9 40 // P3 connector - PB10, //D41 - PB11, //D42 - PB12, //D43 - SPI SS - PB13, //D44 - SPI SCLK - PB14, //D45 - SPI MISO - PB15, //D46 - SPI MOSI - // Duplicated pins in order to be aligned with PinMap_ADC - PC0_2,//D47/A0 = D0 - PC1_2,//D48/A1 = D1 - PC2_2,//D49/A2 = D2 - PC3_2,//D50/A3 = D3 - PA0_2,//D51/A4 = D4 - PA1_2,//D52/A5 = D5 - PA2_2,//D53/A6 = D6 - PA3_2,//D54/A7 = D7 - PA4_2,//D55/A8 = D8 - PA5_2,//D56/A9 = D9 - PA6_2,//D57/A10 = D10 - PA7_2,//D58/A11 = D11 - PC4_2,//D59/A12 = D12 - PC5_2,//D60/A13 = D13 - PB0_2,//D61/A14 = D14 - PB1_2,//D62/A15 = D15 - PEND -}; - -// This must be a literal with the same value as PEND +#define PB10 41 +#define PB11 42 +#define PB12 43 // SPI SS +#define PB13 44 // SPI SCLK +#define PB14 45 // SPI MISO +#define PB15 46 // SPI MOSI + +// This must be a literal #define NUM_DIGITAL_PINS 63 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 16 diff --git a/variants/DISCO_F407VG/variant.h b/variants/DISCO_F407VG/variant.h index cf5b13dfd9..9cfb747fd6 100644 --- a/variants/DISCO_F407VG/variant.h +++ b/variants/DISCO_F407VG/variant.h @@ -33,104 +33,91 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { //P1 connector Right side - PC0, //D0 - PC2, //D1 - PA0, //D2 - PA2, //D3 - PA4, //D4 - PA6, //D5 - PC4, //D6 - PB0, //D7 - PB2, //D8 - PE8, //D9 - PE10, //D10 - PE12, //D11 - PE14, //D12 - PB10, //D13 - PB12, //D14 - PB14, //D15 - PD8, //D16 - PD10, //D17 - PD12, //D18 - PD14, //D19 +#define PC0 0 +#define PC2 1 // A0 +#define PA0 2 +#define PA2 3 +#define PA4 4 +#define PA6 5 +#define PC4 6 // A1 +#define PB0 7 // A2 +#define PB2 8 +#define PE8 9 +#define PE10 10 +#define PE12 11 +#define PE14 12 +#define PB10 13 +#define PB12 14 +#define PB14 15 +#define PD8 16 +#define PD10 17 +#define PD12 18 +#define PD14 19 //P2 connector Left side - PH0, //D20 - PC14, //D21 - PE6, //D22 - PE4, //D23 - PE2, //D24 - PE0, //D25 - PB8, //D26 - PB6, //D27 - PB4, //D28 - PD7, //D29 - PD5, //D30 - PD3, //D31 - PD1, //D32 - PC12, //D33 - PC10, //D34 - PA10, //D35 - PA8, //D36 - PC8, //D37 - PC6, //D38 +#define PH0 20 +#define PC14 21 +#define PE6 22 +#define PE4 23 +#define PE2 24 +#define PE0 25 +#define PB8 26 +#define PB6 27 +#define PB4 28 +#define PD7 29 +#define PD5 30 +#define PD3 31 +#define PD1 32 +#define PC12 33 +#define PC10 34 +#define PA10 35 +#define PA8 36 +#define PC8 37 +#define PC6 38 //P1 Connector Left Side - PC1, //D39 - PC3, //D40 - PA1, //D41 - PA3, //D42 - PA5, //D43 - PA7, //D44 - PC5, //D45 - PB1, //D46 - PE7, //D47 - PE9, //D48 - PE11, //D49 - PE13, //D50 - PE15, //D51 - PB11, //D52 - PB13, //D53 - PB15, //D54 - PD9, //D55 - PD11, //D56 - PD13, //D57 - PD15, //D58 +#define PC1 39 // A3 +#define PC3 40 // A4 +#define PA1 41 // A5 +#define PA3 42 +#define PA5 43 +#define PA7 44 +#define PC5 45 // A6 +#define PB1 46 // A7 +#define PE7 47 +#define PE9 48 +#define PE11 49 +#define PE13 50 +#define PE15 51 +#define PB11 52 +#define PB13 53 +#define PB15 54 +#define PD9 55 +#define PD11 56 +#define PD13 57 +#define PD15 58 //P2 connector Right side - PH1, //D59 - PC15, //D60 - PC13, //D61 - PE5, //D62 - PE3, //D63 - PE1, //D64 - PB9, //D65 - PB7, //D66 - PB5, //D67 - PB3, //D68 - PD6, //D69 - PD4, //D70 - PD2, //D71 - PD0, //D72 - PC11, //D73 - PA15, //D74 - PA13, //D75 - PA9, //D76 - PC9, //D77 - PC7, //D78 -//Duplicated to have A0-A5 as F407 do not have Uno like connector -// and to be aligned with PinMap_ADC - PC2_2,//D79/A0 = D1 - PC4_2,//D80/A1 = D6 - PB0_2,//D81/A2 = D7 - PC1_2,//D82/A3 = D39 - PC3_2,//D83/A4 = D40 - PA1_2,//D84/A5 = D41 - PC5_2,//D85/A6 = D45 - PB1_2,//D86/A7 = D46 - PEND -}; - -// This must be a literal with the same value as PEND +#define PH1 59 +#define PC15 60 +#define PC13 61 +#define PE5 62 +#define PE3 63 +#define PE1 64 +#define PB9 65 +#define PB7 66 +#define PB5 67 +#define PB3 68 +#define PD6 69 +#define PD4 70 +#define PD2 71 +#define PD0 72 +#define PC11 73 +#define PA15 74 +#define PA13 75 +#define PA9 76 +#define PC9 77 +#define PC7 78 + +// This must be a literal #define NUM_DIGITAL_PINS 87 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 8 @@ -193,7 +180,7 @@ enum { // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX // pins are NOT connected to anything by default. #define SERIAL_PORT_MONITOR Serial // Require connections for ST-LINK VCP on U2 pin 12 and 13. - // See UM §6.1.3 ST-LINK/V2-A VCP configuration) + // See UM §6.1.3 ST-LINK/V2-A VCP configuration) #define SERIAL_PORT_HARDWARE_OPEN Serial #endif diff --git a/variants/DISCO_F746NG/variant.h b/variants/DISCO_F746NG/variant.h index 55684879ce..2556b92f0b 100644 --- a/variants/DISCO_F746NG/variant.h +++ b/variants/DISCO_F746NG/variant.h @@ -33,37 +33,34 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PC7, //D0 - PC6, //D1 - PG6, //D2 - PB4, //D3 - PG7, //D4 - PI0, //D5 - PH6, //D6 - PI3, //D7 - PI2, //D8 - PA15, //D9 - PA8, //D10 - PB15, //D11 - PB14, //D12 - PI1, //D13 - PB9, //D14 - PB8, //D15 - PA0, //D16/A0 - PF10, //D17/A1 - PF9, //D18/A2 - PF8, //D19/A3 - PF7, //D20/A4 - PF6, //D21/A5 - PI11, //D22 User btn - PB7, //D23 ST-Link Rx - PA9, //D24 ST-Link Tx - PC13, //D25 SD detect - PEND -}; - -// This must be a literal with the same value as PEND +#define PC7 0 +#define PC6 1 +#define PG6 2 +#define PB4 3 +#define PG7 4 +#define PI0 5 +#define PH6 6 +#define PI3 7 +#define PI2 8 +#define PA15 9 +#define PA8 10 +#define PB15 11 +#define PB14 12 +#define PI1 13 +#define PB9 14 +#define PB8 15 +#define PA0 16 // A0 +#define PF10 17 // A1 +#define PF9 18 // A2 +#define PF8 19 // A3 +#define PF7 20 // A4 +#define PF6 21 // A5 +#define PI11 22 // User btn +#define PB7 23 // ST-Link Rx +#define PA9 24 // ST-Link Tx +#define PC13 25 // SD detect + +// This must be a literal #define NUM_DIGITAL_PINS 26 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 6 diff --git a/variants/DISCO_L072CZ_LRWAN1/variant.h b/variants/DISCO_L072CZ_LRWAN1/variant.h index 4c88cb69ad..1b59bd4a7b 100644 --- a/variants/DISCO_L072CZ_LRWAN1/variant.h +++ b/variants/DISCO_L072CZ_LRWAN1/variant.h @@ -33,55 +33,51 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB13, //D3 - PB5, //D4 - PB7, //D5 - PB2, //D6 - PA8, //D7 - PA9, //D8 - PB12, //D9 - PB6, //D10 - PB15, //D11 - PB14, //D12 - PB13_2, //D13 - default SB2 is closed - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB13 3 +#define PB5 4 +#define PB7 5 +#define PB2 6 +#define PA8 7 +#define PA9 8 +#define PB12 9 +#define PB6 10 +#define PB15 11 +#define PB14 12 +// 13 is PB13 (3) as default SB2 is closed +#define PB9 14 // A4 - requires closing solder bridge SB11 +#define PB8 15 // A5 - requires closing solder bridge SB12 // Connector CN2 - NC_1, //D16 - BOOT0 - PA13, //D17 - SWD - PA14, //D18 - SWD - PH1, //D19 - PH0, //D20 +// 16 is NC - BOOT0 +#define PA13 17 // SWD +#define PA14 18 // SWD +#define PH1 19 +#define PH0 20 // Connector CN3 - PA1, //D21 - PC2, //D22 - PC1, //D23 - PA12, //D24 - PA11, //D25 - PA0, //D26/A0 - PA0_2,//D27/A1 - alias for A0 - requires closing solder bridge SB7 - PA4, //D28/A2 - RADIO_DIO_5_PORT - PA4_2,//D29/A3 - alias for A2 - requires closing solder bridge SB8 - PB9_2,//D30/A4 - requires closing solder bridge SB11 - PB8_2,//D31/A5 - requires closing solder bridge SB12 - PA5, //D32/A6 - RADIO_DIO_4_PORT - PC0, //D33 - RADIO_RESET_PORT - PA7, //D34 - RADIO_MOSI_PORT - PA6, //D35 - RADIO_MISO_PORT - PB3, //D36 - RADIO_SCLK_PORT - PA15, //D37 - RADIO_NSS_PORT - PB4, //D38 - RADIO_DIO_0_PORT - PB1, //D39 - RADIO_DIO_1_PORT - PB0, //D40 - RADIO_DIO_2_PORT - PC13, //D41 - RADIO_DIO_3_PORT - PEND -}; - -// This must be a literal with the same value as PEND +#define PA1 21 +#define PC2 22 +#define PC1 23 +#define PA12 24 +#define PA11 25 +#define PA0 26 // A0/A1 +// 27 is A1 an alias for A0 - requires closing solder bridge SB7 +#define PA4 28 // A2/A3 - RADIO_DIO_5_PORT +// 29 is A3 an alias for A2 - requires closing solder bridge SB8 +// 30 is A4 - requires closing solder bridge SB11 +// 31 is A5 - requires closing solder bridge SB12 +#define PA5 32 // A6 - RADIO_DIO_4_PORT +#define PC0 33 // RADIO_RESET_PORT +#define PA7 34 // RADIO_MOSI_PORT +#define PA6 35 // RADIO_MISO_PORT +#define PB3 36 // RADIO_SCLK_PORT +#define PA15 37 // RADIO_NSS_PORT +#define PB4 38 // RADIO_DIO_0_PORT +#define PB1 39 // RADIO_DIO_1_PORT +#define PB0 40 // RADIO_DIO_2_PORT + +// This must be a literal #define NUM_DIGITAL_PINS 42 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 7 diff --git a/variants/DISCO_L475VG_IOT/variant.h b/variants/DISCO_L475VG_IOT/variant.h index 0367dfaa6e..b219dc1a8f 100644 --- a/variants/DISCO_L475VG_IOT/variant.h +++ b/variants/DISCO_L475VG_IOT/variant.h @@ -33,105 +33,91 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { // CN3 connector - PA1, //D0 - UART4_RX - PA0, //D1 - UART4_TX - PD14, //D2 - PB0, //D3 - PWM - PA3, //D4 - PB4, //D5 - PWM - PB1, //D6 - PWM - PA4, //D7 +#define PA1 0 // A6/UART4_RX +#define PA0 1 // A7/UART4_TX +#define PD14 2 +#define PB0 3 // A8/PWM +#define PA3 4 // A9 +#define PB4 5 // PWM +#define PB1 6 // A10/PWM +#define PA4 7 // A11 // CN1 connector - PB2, //D8 - PA15, //D9 - PWM - PA2, //D10 - SPI_SSN/PWM - PA7, //D11 - SPI1_MOSI/PWM - PA6, //D12 - SPI1_MISO - PA5, //D13 - SPI1_SCK/LED1 - PB9, //D14 - I2C1_SDA - PB8, //D15 - I2C1_SCL +#define PB2 8 +#define PA15 9 // PWM +#define PA2 10 // A12/SPI_SSN/PWM +#define PA7 11 // A13/SPI1_MOSI/PWM +#define PA6 12 // A14/SPI1_MISO +#define PA5 13 // A15/SPI1_SCK/LED1 +#define PB9 14 // I2C1_SDA +#define PB8 15 // I2C1_SCL // Not on connector - PB14, //D16 - LED2 - PC13, //D17 - USER_BTN +#define PB14 16 // LED2 +#define PC13 17 // USER_BTN // ST-LINK - PB6, //D18 - ST-LINK-UART1_TX - PB7, //D19 - ST-LINK-UART1_RX +#define PB6 18 // ST-LINK-UART1_TX +#define PB7 19 // ST-LINK-UART1_RX // CN9 USB OTG FS connector - PA9, //D20 - USB_OTG_FS_VBUS - PA10, //D21 - USB_OTG_FS_ID - PA11, //D22 - USB_OTG_FS_DM - PA12, //D23 - USB_OTG_FS_DP - PD12, //D24 - USB_OTG_FS_PWR_EN - PE3, //D25 - USB_OTG_OVRCR_EXTI3 +#define PA9 20 // USB_OTG_FS_VBUS +#define PA10 21 // USB_OTG_FS_ID +#define PA11 22 // USB_OTG_FS_DM +#define PA12 23 // USB_OTG_FS_DP +#define PD12 24 // USB_OTG_FS_PWR_EN +#define PE3 25 // USB_OTG_OVRCR_EXTI3 // CN10 PMOD connector - PD0, //D26 - PMOD-RESET - PD1, //D27 - PMOD-SPI2_SCK - PD2, //D28 - PMOD-IRQ_EXTI2 - PD3, //D29 - PMOD-UART2_CTS/SPI2_MISO - PD4, //D30 - PMOD-UART2_RTS/SPI2_MOSI - PD5, //D31 - PMOD-UART2_TX/SPI2_CSN - PD6, //D32 - PMOD-UART2_RX +#define PD0 26 // PMOD-RESET +#define PD1 27 // PMOD-SPI2_SCK +#define PD2 28 // PMOD-IRQ_EXTI2 +#define PD3 29 // PMOD-UART2_CTS/SPI2_MISO +#define PD4 30 // PMOD-UART2_RTS/SPI2_MOSI +#define PD5 31 // PMOD-UART2_TX/SPI2_CSN +#define PD6 32 // PMOD-UART2_RX // Sensors / modules pins - PA8, //D33 - SPBTLE-RF-RST - PB5, //D34 - SPSGRF-915-SPI3_CSN - PB10, //D35 - INTERNAL-I2C2_SCL - PB11, //D36 - INTERNAL-I2C2_SDA - PB12, //D37 - ISM43362-BOOT0 - PB13, //D38 - ISM43362-WAKEUP - PB15, //D39 - SPSGRF-915-SDN - PC6, //D40 - VL53L0X_XSHUT - PC7, //D41 - VL53L0X_GPIO1_EXTI7 - PC8, //D42 - LIS3MDL_DRDY_EXTI8 - PC9, //D43 - LED3 (WIFI) & LED4 (BLE) - PC10, //D44 - INTERNAL-SPI3_SCK - PC11, //D45 - INTERNAL-SPI3_MISO - PC12, //D46 - INTERNAL-SPI3_MOSI - PD7, //D47 - STSAFE-A100-RESET - PD8, //D48 - INTERNAL-UART3_TX - PD9, //D49 - INTERNAL-UART3_RX - PD10, //D50 - LPS22HB_INT_DRDY_EXTI10 - PD11, //D51 - LSM6DSL_INT1_EXTI11 - PD13, //D52 - SPBTLE-RF-SPI3_CSN - PD15, //D53 - HTS221_DRDY_EXTI15 - PE0, //D54 - ISM43362-SPI3_CSN - PE1, //D55 - ISM43362-DRDY_EXTI1 - PE2, //D56 - M24SR64-Y-RF_DISABLE - PE4, //D57 - M24SR64-Y-GPO - PE5, //D58 - SPSGRF-915-GPIO3_EXTI5 - PE6, //D59 - SPBTLE-RF-IRQ_EXTI6 - PE7, //D60 - DFSDM1_DATIN2 - PE8, //D61 - ISM43362-RST - PE9, //D62 - DFSDM1_CKOUT - PE10, //D63 - QUADSPI_CLK - PE11, //D64 - QUADSPI_NCS - PE12, //D65 - QUADSPI_BK1_IO0 - PE13, //D66 - QUADSPI_BK1_IO1 - PE14, //D67 - QUADSPI_BK1_IO2 - PE15, //D68 - QUADSPI_BK1_IO3 +#define PA8 33 // SPBTLE-RF-RST +#define PB5 34 // SPSGRF-915-SPI3_CSN +#define PB10 35 // INTERNAL-I2C2_SCL +#define PB11 36 // INTERNAL-I2C2_SDA +#define PB12 37 // ISM43362-BOOT0 +#define PB13 38 // ISM43362-WAKEUP +#define PB15 39 // SPSGRF-915-SDN +#define PC6 40 // VL53L0X_XSHUT +#define PC7 41 // VL53L0X_GPIO1_EXTI7 +#define PC8 42 // LIS3MDL_DRDY_EXTI8 +#define PC9 43 // LED3 (WIFI) & LED4 (BLE) +#define PC10 44 // INTERNAL-SPI3_SCK +#define PC11 45 // INTERNAL-SPI3_MISO +#define PC12 46 // INTERNAL-SPI3_MOSI +#define PD7 47 // STSAFE-A100-RESET +#define PD8 48 // INTERNAL-UART3_TX +#define PD9 49 // INTERNAL-UART3_RX +#define PD10 50 // LPS22HB_INT_DRDY_EXTI10 +#define PD11 51 // LSM6DSL_INT1_EXTI11 +#define PD13 52 // SPBTLE-RF-SPI3_CSN +#define PD15 53 // HTS221_DRDY_EXTI15 +#define PE0 54 // ISM43362-SPI3_CSN +#define PE1 55 // ISM43362-DRDY_EXTI1 +#define PE2 56 // M24SR64-Y-RF_DISABLE +#define PE4 57 // M24SR64-Y-GPO +#define PE5 58 // SPSGRF-915-GPIO3_EXTI5 +#define PE6 59 // SPBTLE-RF-IRQ_EXTI6 +#define PE7 60 // DFSDM1_DATIN2 +#define PE8 61 // ISM43362-RST +#define PE9 62 // DFSDM1_CKOUT +#define PE10 63 // QUADSPI_CLK +#define PE11 64 // QUADSPI_NCS +#define PE12 65 // QUADSPI_BK1_IO0 +#define PE13 66 // QUADSPI_BK1_IO1 +#define PE14 67 // QUADSPI_BK1_IO2 +#define PE15 68 // QUADSPI_BK1_IO3 // CN4 connector - PC5, //D69/A0 - PC4, //D70/A1 - PC3, //D71/A2 - PC2, //D72/A3 - PC1, //D73/A4 - PC0, //D74/A5 -// Duplicated pins in order to be aligned with PinMap_ADC - PA1_2, //D75/A6 - PA0_2, //D76/A7 - PB0_2, //D77/A8 - PA3_2, //D78/A9 - PB1_2, //D79/A10 - PA4_2, //D80/A11 - PA2_2, //D81/A12 - PA7_2, //D82/A13 - PA6_2, //D83/A14 - PA5_2, //D84/A15 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC5 69 // A0 +#define PC4 70 // A1 +#define PC3 71 // A2 +#define PC2 72 // A3 +#define PC1 73 // A4 +#define PC0 74 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 85 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 16 diff --git a/variants/MAPLEMINI_F103CB/variant.h b/variants/MAPLEMINI_F103CB/variant.h index 4b808b365d..6e7df51de9 100644 --- a/variants/MAPLEMINI_F103CB/variant.h +++ b/variants/MAPLEMINI_F103CB/variant.h @@ -44,60 +44,46 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { // Right side - PB11, //D0 - PB10, //D1 - PB2, //D2 - PB0, //D3 - PA7, //D4 - PA6, //D5 - PA5, //D6 - PA4, //D7 - PA3, //D8 - PA2, //D9 - PA1, //D10 - PA0, //D11 - PC15, //D12 - PC14, //D13 - PC13, //D14 +#define PB11 0 +#define PB10 1 +#define PB2 2 +#define PB0 3 // A0 +#define PA7 4 // A1 +#define PA6 5 // A2 +#define PA5 6 // A3 +#define PA4 7 // A4 +#define PA3 8 // A5 +#define PA2 9 // A6 +#define PA1 10 // A7 +#define PA0 11 // A8 +#define PC15 12 +#define PC14 13 +#define PC13 14 // Left side - PB7, //D15 - PB6, //D16 - PB5, //D17 - PB4, //D18 - PB3, //D19 - PA15, //D20 - PA14, //D21 - SWCLK - PA13, //D22 - SWDI0 - PA12, //D23 - USB DP - PA11, //D24 - USB DM - PA10, //D25 - PA9, //D26 - PA8, //D27 - PB15, //D28 - PB14, //D29 - PB13, //D30 - PB12, //D31 +#define PB7 15 +#define PB6 16 +#define PB5 17 +#define PB4 18 +#define PB3 19 +#define PA15 20 +#define PA14 21 // SWCLK +#define PA13 22 // SWDI0 +#define PA12 23 // USB DP +#define PA11 24 // USB DM +#define PA10 25 +#define PA9 26 +#define PA8 27 +#define PB15 28 +#define PB14 29 +#define PB13 30 +#define PB12 31 // Other - PB8, //D32 - BOOT0 - User buttons - PB1, //D33 - LED - PB9, //D34 - USB DISC -// Duplicated pins to avoid issue with analogRead -// A0 have to be greater than NUM_ANALOG_INPUTS - PB0_2,//D35/A0 = D3 - PA7_2,//D36/A1 = D4 - PA6_2,//D37/A2 = D5 - PA5_2,//D38/A3 = D6 - PA4_2,//D39/A4 = D7 - PA3_2,//D40/A5 = D8 - PA2_2,//D41/A6 = D9 - PA1_2,//D42/A7 = D10 - PA0_2,//D43/A8 = D11 - PEND -}; +#define PB8 32 // BOOT0 - User buttons +#define PB1 33 // LED +#define PB9 34 // USB DISC -// This must be a literal with the same value as PEND +// This must be a literal #define NUM_DIGITAL_PINS 44 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 9 diff --git a/variants/NUCLEO_F030R8/variant.h b/variants/NUCLEO_F030R8/variant.h index d13db669df..2d67814e7e 100644 --- a/variants/NUCLEO_F030R8/variant.h +++ b/variants/NUCLEO_F030R8/variant.h @@ -33,78 +33,68 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - no PWM - PB5, //D4 - PB4, //D5 - PB10, //D6 - no PWM - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 // no PWM +#define PB5 4 +#define PB4 5 +#define PB10 6 // no PWM +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - PF6, //D18 - PF7, //D19 - PA13, //D20 - SWD - PA14, //D21 - SWD - PA15, //D22 - PB7, //D23 - PC13, //D24 - PC14, //D25 - PC15, //D26 - PF0, //D27 - PF1, //D28 - PC2, //D29 - PC3, //D30 +#define PC10 16 +#define PC12 17 +#define PF6 18 +#define PF7 19 +#define PA13 20 // SWD +#define PA14 21 // SWD +#define PA15 22 +#define PB7 23 +#define PC13 24 +#define PC14 25 +#define PC15 26 +#define PF0 27 +#define PF1 28 +#define PC2 29 // A8 +#define PC3 30 // A9 // CN7 Right Side - PC11, //D31 - PD2, //D32 +#define PC11 31 +#define PD2 32 // CN10 Left Side - PC9, //D33 +#define PC9 33 // CN10 Right side - PC8, //D34 - PC6, //D35 - PC5, //D36 - PA12, //D37 - PA11, //D38 - PB12, //D39 - PB11, //D40 - PB2, //D41 - PB1, //D42 - PB15, //D43 - PB14, //D44 - PB13, //D45 - PC4, //D46 - PF5, //D47 - PF4, //D48 - PA0, //D49/A0 - PA1, //D50/A1 - PA4, //D51/A2 - PB0, //D52/A3 - PC1, //D53/A4 - PC0, //D54/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D55/A6 = D11 - PA6_2,//D56/A7 = D12 - PC2_2,//D57/A8 = D29 - PC3_2,//D58/A9 = D30 - PC5_2,//D59/A10 = D36 - PC4_2,//D60/A11 = D46 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 34 +#define PC6 35 +#define PC5 36 // A10 +#define PA12 37 +#define PA11 38 +#define PB12 39 +#define PB11 40 +#define PB2 41 +#define PB1 42 +#define PB15 43 +#define PB14 44 +#define PB13 45 +#define PC4 46 // A11 +#define PF5 47 +#define PF4 48 +#define PA0 49 // A0 +#define PA1 50 // A1 +#define PA4 51 // A2 +#define PB0 52 // A3 +#define PC1 53 // A4 +#define PC0 54 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 61 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 12 diff --git a/variants/NUCLEO_F091RC/variant.h b/variants/NUCLEO_F091RC/variant.h index daf438de0d..6ff4ef0e98 100644 --- a/variants/NUCLEO_F091RC/variant.h +++ b/variants/NUCLEO_F091RC/variant.h @@ -33,75 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - PF11, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PF0, //D26 - PF1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +#define PF11 18 // BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PF0 26 +#define PF1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PC4_2,//D57/A11 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A11 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 58 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 12 diff --git a/variants/NUCLEO_F103RB/variant.h b/variants/NUCLEO_F103RB/variant.h index 2d8d8ec7d8..40ca87280f 100644 --- a/variants/NUCLEO_F103RB/variant.h +++ b/variants/NUCLEO_F103RB/variant.h @@ -33,77 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - LED - PB9, //D14 - PB8, //D15 - // ST Morpho - // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PD0, //D26 - PD1, //D27 - PC2, //D28 - PC3, //D29 - // CN7 Right Side - PC11, //D30 - PD2, //D31 - // CN10 Left Side - PC9, //D32 - // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PA5_2,//D54/A8 = D13 - PC2_2,//D55/A9 = D28 - PC3_2,//D56/A10 = D29 - PB1_2,//D57/A11 = D41 - PC4_2,//D58/A12 = D45 - PC5_2,//D59/A13 = D35 - PEND -}; - -// This must be a literal with the same value as PEND +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 // A8 - LED +#define PB9 14 +#define PB8 15 +// ST Morpho +// CN7 Left Side +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PD0 26 +#define PD1 27 +#define PC2 28 // A9 +#define PC3 29 // A10 +// CN7 Right Side +#define PC11 30 +#define PD2 31 +// CN10 Left Side +#define PC9 32 +// CN10 Right side +#define PC8 33 +#define PC6 34 +#define PC5 35 // A13 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 // A11 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A12 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 60 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 diff --git a/variants/NUCLEO_F207ZG/variant.h b/variants/NUCLEO_F207ZG/variant.h index 2ce4ea92d4..8a509791d0 100644 --- a/variants/NUCLEO_F207ZG/variant.h +++ b/variants/NUCLEO_F207ZG/variant.h @@ -45,109 +45,96 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -// Enum defining Arduino style alias for digital pin number --> Dx -enum { - PG9, //D0 - PG14, //D1 - PF15, //D2 - PE13, //D3 - PF14, //D4 - PE11, //D5 - PE9, //D6 - PF13, //D7 - PF12, //D8 - PD15, //D9 - PD14, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 - PC6, //D16 - PB15, //D17 - PB13, //D18 - PB12, //D19 - PA15, //D20 - PC7, //D21 - PB5, //D22 - PB3, //D23 - PA4, //D24 - PB4, //D25 - PB6, //D26 - PB2, //D27 - PD13, //D28 - PD12, //D29 - PD11, //D30 - PE2, //D31 - PA0, //D32 - PB0, //D33 - LED1 - PE0, //D34 - PB11, //D35 - PB10, //D36 - PE15, //D37 - PE14, //D38 - PE12, //D39 - PE10, //D40 - PE7, //D41 - PE8, //D42 - PC8, //D43 - PC9, //D44 - PC10, //D45 - PC11, //D46 - PC12, //D47 - PD2, //D48 - PG2, //D49 - PG3, //D50 - PD7, //D51 - PD6, //D52 - PD5, //D53 - PD4, //D54 - PD3, //D55 - PE2_2,//D56 - PE4, //D57 - PE5, //D58 - PE6, //D59 - PE3, //D60 - PF8, //D61 - PF7, //D62 - PF9, //D63 - PG1, //D64 - PG0, //D65 - PD1, //D66 - PD0, //D67 - PF0, //D68 - PF1, //D69 - PF2, //D70 - PA7_2,//D71 - NC_1, //D72 - PB7, //D73 - LED_BLUE - PB14, //D74 - LED_RED - PC13, //D75 - USER_BTN - PD9, //D76 - Serial Rx - PD8, //D77 - Serial Tx - PA3, //D78/A0 - PC0, //D79/A1 - PC3, //D80/A2 - PF3, //D81/A3 - PF5, //D82/A4 - PF10, //D83/A5 - PB1, //D84/A6 - PC2, //D85/A7 - PF4, //D86/A8 - PF6, //D87/A9 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_3,//D88/A10 = D11/D71 - PA6_2,//D89/A11 = D12 - PA5_2,//D90/A12 = D13 - PA4_2,//D91/A13 = D24 - PA0_2,//D92/A14 = D32 - PF8_2,//D93/A15 = D61 - PF7_2,//D94/A16 = D62 - PF9_2,//D95/A17 = D63 - PEND -}; +#define PG9 0 +#define PG14 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 +#define PA7 11 // A10 +#define PA6 12 // A11 +#define PA5 13 // A12 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 24 // A13 +#define PB4 25 +#define PB6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 32 // A14 +#define PB0 33 // LED1 +#define PE0 34 +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE14 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG2 49 +#define PG3 50 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 // A15 +#define PF7 62 // A16 +#define PF9 63 // A17 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +// 71 is PA7 (11) +// 72 is NC +#define PB7 73 // LED_BLUE +#define PB14 74 // LED_RED +#define PC13 75 // USER_BTN +#define PD9 76 // Serial Rx +#define PD8 77 // Serial Tx +#define PA3 78 // A0 +#define PC0 79 // A1 +#define PC3 80 // A2 +#define PF3 81 // A3 +#define PF5 82 // A4 +#define PF10 83 // A5 +#define PB1 84 // A6 +#define PC2 85 // A7 +#define PF4 86 // A8 +#define PF6 87 // A9 -// This must be a literal with the same value as PEND +// This must be a literal #define NUM_DIGITAL_PINS 96 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 18 diff --git a/variants/NUCLEO_F302R8/variant.h b/variants/NUCLEO_F302R8/variant.h index 5398ee58b3..9e6fb281d3 100644 --- a/variants/NUCLEO_F302R8/variant.h +++ b/variants/NUCLEO_F302R8/variant.h @@ -33,75 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PB15,//D11 - PB14,//D12 - PB13,//D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PB15 11 +#define PB14 12 +#define PB13 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - PF11, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PF0, //D26 - PF1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +#define PF11 18 // BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PF0 26 +#define PF1 27 +#define PC2 28 // A6 +#define PC3 29 // A7 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PA7, //D42 - PA6, //D43 - PA5, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PC2_2,//D52/A6 = D28 - PC3_2,//D53/A7 = D29 - PB11_2,//D54/A8 = D39 - PB1_2,//D55/A9 = D41 - PA7_2,//D56/A10 = D42 - PA6_2,//D57/A11 = D43 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 // A8 +#define PB2 40 +#define PB1 41 // A9 +#define PA7 42 // A10 +#define PA6 43 // A11 +#define PA5 44 +#define PC4 45 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 58 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 12 diff --git a/variants/NUCLEO_F303K8/variant.h b/variants/NUCLEO_F303K8/variant.h index 2883f93896..1e4e754add 100644 --- a/variants/NUCLEO_F303K8/variant.h +++ b/variants/NUCLEO_F303K8/variant.h @@ -33,34 +33,31 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA10, //D0 - PA9, //D1 - PA12, //D2 - PB0, //D3 - PB7, //D4 - PB6, //D5 - PB1, //D6 - PF0, //D7 - PF1, //D8 - PA8, //D9 - PA11, //D10 - PB5, //D11 - PB4, //D12 - PB3, //D13 - LED - PA0, //D14/A0 - PA1, //D15/A1 - PA3, //D16/A2 - PA4, //D17/A3 - PA5, //D18/A4 - if SB18 ON (default) connected to PB7 - PA6, //D19/A5 - if SB16 ON (default) connected to PB6 - PA7, //D20/A6 - PA2, //D21/A7 - STLink Tx - PA15, //D22 - STLink Rx - PEND -}; - -// This must be a literal with the same value as PEND +#define PA10 0 +#define PA9 1 +#define PA12 2 +#define PB0 3 +#define PB7 4 +#define PB6 5 +#define PB1 6 +#define PF0 7 +#define PF1 8 +#define PA8 9 +#define PA11 10 +#define PB5 11 +#define PB4 12 +#define PB3 13 // LED +#define PA0 14 // A0 +#define PA1 15 // A1 +#define PA3 16 // A2 +#define PA4 17 // A3 +#define PA5 18 // A4 - if SB18 ON (default) connected to PB7 +#define PA6 19 // A5 - if SB16 ON (default) connected to PB6 +#define PA7 20 // A6 +#define PA2 21 // A7 - STLink Tx +#define PA15 22 // STLink Rx + +// This must be a literal #define NUM_DIGITAL_PINS 23 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 7 diff --git a/variants/NUCLEO_F303RE/variant.h b/variants/NUCLEO_F303RE/variant.h index 0893ba18ea..2857d8366c 100644 --- a/variants/NUCLEO_F303RE/variant.h +++ b/variants/NUCLEO_F303RE/variant.h @@ -33,77 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - PF11, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PF0, //D26 - PF1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +#define PF11 18 // BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PF0 26 +#define PF1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2, //D52/A6 = D11 - PA6_2, //D53/A7 = D12 - PC2_2, //D54/A8 = D28 - PC3_2, //D55/A9 = D29 - PC5_2, //D56/A10 = D35 - PB11_2,//D57/A11 = D39 - PB2_2, //D58/A12 = D40 - PC4_2, //D59/A13 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 // A11 +#define PB2 40 // A12 +#define PB1 41 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A13 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 60 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 diff --git a/variants/NUCLEO_F401RE/variant.h b/variants/NUCLEO_F401RE/variant.h index deabf2e9ec..3eedccd053 100644 --- a/variants/NUCLEO_F401RE/variant.h +++ b/variants/NUCLEO_F401RE/variant.h @@ -33,76 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PB1_2,//D57/A11 = D41 - PC4_2,//D58/A12 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 // A11 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A12 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 59 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 13 diff --git a/variants/NUCLEO_F411RE/variant.h b/variants/NUCLEO_F411RE/variant.h index 4ec64f2f47..ab14462621 100644 --- a/variants/NUCLEO_F411RE/variant.h +++ b/variants/NUCLEO_F411RE/variant.h @@ -33,76 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMapADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PB1_2,//D57/A11 = D41 - PC4_2,//D58/A12 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 // A11 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A12 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 59 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 13 diff --git a/variants/NUCLEO_F429ZI/variant.h b/variants/NUCLEO_F429ZI/variant.h index 14686e6031..dd8790ffb0 100644 --- a/variants/NUCLEO_F429ZI/variant.h +++ b/variants/NUCLEO_F429ZI/variant.h @@ -33,108 +33,96 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PG9, //D0 - PG14, //D1 - PF15, //D2 - PE13, //D3 - PF14, //D4 - PE11, //D5 - PE9, //D6 - PF13, //D7 - PF12, //D8 - PD15, //D9 - PD14, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 - PC6, //D16 - PB15, //D17 - PB13, //D18 - PB12, //D19 - PA15, //D20 - PC7, //D21 - PB5, //D22 - PB3, //D23 - PA4, //D24 - PB4, //D25 - PB6, //D26 - PB2, //D27 - PD13, //D28 - PD12, //D29 - PD11, //D30 - PE2, //D31 - PA0, //D32 - PB0, //D33 - LEDGREEN - PE0, //D34 - PB11, //D35 - PB10, //D36 - PE15, //D37 - PE14, //D38 - PE12, //D39 - PE10, //D40 - PE7, //D41 - PE8, //D42 - PC8, //D43 - PC9, //D44 - PC10, //D45 - PC11, //D46 - PC12, //D47 - PD2, //D48 - PG2, //D49 - PG3, //D50 - PD7, //D51 - PD6, //D52 - PD5, //D53 - PD4, //D54 - PD3, //D55 - PE2_2,//D56 - PE4, //D57 - PE5, //D58 - PE6, //D59 - PE3, //D60 - PF8, //D61 - PF7, //D62 - PF9, //D63 - PG1, //D64 - PG0, //D65 - PD1, //D66 - PD0, //D67 - PF0, //D68 - PF1, //D69 - PF2, //D70 - PA7_2,//D71 - NC_1, //D72 - PB7, //D73 - LEDBLUE - PB14, //D74 - LEDRED - PC13, //D75 - USERBTN - PD9, //D76 - Serial Rx - PD8, //D77 - Serial Tx - PA3, //D78/A0 - PC0, //D79/A1 - PC3, //D80/A2 - PF3, //D81/A3 - PF5, //D82/A4 - PF10, //D83/A5 - PB1, //D84/A6 - PC2, //D85/A7 - PF4, //D86/A8 - PF6, //D87/A9 - // Duplicated pins in order to be aligned with PinMapADC - PA7_3, //D88/A10 = D11 - PA6_2, //D89/A11 = D12 - PA5_2, //D90/A12 = D13 - PA4_2, //D91/A13 = D24 - PA0_2, //D92/A14 = D32 - PF8_2, //D93/A15 = D61 - PF7_2, //D94/A16 = D62 - PF9_2, //D95/A17 = D63 - PEND -}; - -// This must be a literal with the same value as PEND +#define PG9 0 +#define PG14 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 +#define PA7 11 // A10 +#define PA6 12 // A11 +#define PA5 13 // A12 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 24 // A13 +#define PB4 25 +#define PB6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 32 // A14 +#define PB0 33 // LED_GREEN +#define PE0 34 +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE14 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG2 49 +#define PG3 50 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 // A15 +#define PF7 62 // A16 +#define PF9 63 // A17 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +// 71 is PA7 (11) +// 72 is NC +#define PB7 73 // LED_BLUE +#define PB14 74 // LED_RED +#define PC13 75 // USER_BTN +#define PD9 76 // Serial Rx +#define PD8 77 // Serial Tx +#define PA3 78 // A0 +#define PC0 79 // A1 +#define PC3 80 // A2 +#define PF3 81 // A3 +#define PF5 82 // A4 +#define PF10 83 // A5 +#define PB1 84 // A6 +#define PC2 85 // A7 +#define PF4 86 // A8 +#define PF6 87 // A9 + +// This must be a literal #define NUM_DIGITAL_PINS 96 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 18 diff --git a/variants/NUCLEO_F446RE/variant.h b/variants/NUCLEO_F446RE/variant.h index 3977feab20..de7b9a0ac4 100644 --- a/variants/NUCLEO_F446RE/variant.h +++ b/variants/NUCLEO_F446RE/variant.h @@ -33,77 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - LD2 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 // A8 - LD2 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - USER_BTN - PC14, //D24 - NC by default SB49 opened - PC15, //D25 - NC by default SB48 opened - PH0, //D26 - NC by default SB55 opened - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 // USER_BTN +#define PC14 24 // NC by default SB49 opened +#define PC15 25 // NC by default SB48 opened +#define PH0 26 // NC by default SB55 opened +#define PH1 27 +#define PC2 28 // A9 +#define PC3 29 // A10 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - NC_2, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMapADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PA5_2,//D54/A8 = D13 - PC2_2,//D55/A9 = D28 - PC3_2,//D56/A10 = D29 - PC5_2,//D57/A11 = D35 - PB1_2,//D58/A12 = D41 - PC4_2,//D59/A13 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A11 +#define PA12 36 +#define PA11 37 +#define PB12 38 +// 39 is NC +#define PB2 40 +#define PB1 41 // A12 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A13 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 60 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 14 diff --git a/variants/NUCLEO_F767ZI/variant.h b/variants/NUCLEO_F767ZI/variant.h index e5537dce51..640ce73abb 100644 --- a/variants/NUCLEO_F767ZI/variant.h +++ b/variants/NUCLEO_F767ZI/variant.h @@ -33,108 +33,96 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PG9, //D0 - PG14, //D1 - PF15, //D2 - PE13, //D3 - PF14, //D4 - PE11, //D5 - PE9, //D6 - PF13, //D7 - PF12, //D8 - PD15, //D9 - PD14, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 - PC6, //D16 - PB15, //D17 - PB13, //D18 - PB12, //D19 - PA15, //D20 - PC7, //D21 - PB5, //D22 - PB3, //D23 - PA4, //D24 - PB4, //D25 - PB6, //D26 - PB2, //D27 - PD13, //D28 - PD12, //D29 - PD11, //D30 - PE2, //D31 - PA0, //D32 - PB0, //D33 - LED_GREEN - PE0, //D34 - PB11, //D35 - PB10, //D36 - PE15, //D37 - PE14, //D38 - PE12, //D39 - PE10, //D40 - PE7, //D41 - PE8, //D42 - PC8, //D43 - PC9, //D44 - PC10, //D45 - PC11, //D46 - PC12, //D47 - PD2, //D48 - PG2, //D49 - PG3, //D50 - PD7, //D51 - PD6, //D52 - PD5, //D53 - PD4, //D54 - PD3, //D55 - PE2_2,//D56 - PE4, //D57 - PE5, //D58 - PE6, //D59 - PE3, //D60 - PF8, //D61 - PF7, //D62 - PF9, //D63 - PG1, //D64 - PG0, //D65 - PD1, //D66 - PD0, //D67 - PF0, //D68 - PF1, //D69 - PF2, //D70 - PA7_2,//D71 - NC_1, //D72 - PB7, //D73 - LED_BLUE - PB14, //D74 - LED_RED - PC13, //D75 - USER_BTN - PD9, //D76 - Serial Rx - PD8, //D77 - Serial Tx - PA3, //D78/A0 - PC0, //D79/A1 - PC3, //D80/A2 - PF3, //D81/A3 - PF5, //D82/A4 - PF10, //D83/A5 - PB1, //D84/A6 - PC2, //D85/A7 - PF4, //D86/A8 - PF6, //D87/A9 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_3, //D88/A10 = D11 - PA6_2, //D89/A11 = D12 - PA5_2, //D90/A12 = D13 - PA4_2, //D91/A13 = D24 - PA0_2, //D92/A14 = D32 - PF8_2, //D93/A15 = D61 - PF7_2, //D94/A16 = D62 - PF9_2, //D95/A17 = D63 - PEND -}; - -// This must be a literal with the same value as PEND +#define PG9 0 +#define PG14 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 // A10 +#define PA7 11 // A11 +#define PA6 12 // A12 +#define PA5 13 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 24 // A13 +#define PB4 25 +#define PB6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 32 // A14 +#define PB0 33 // LED_GREEN +#define PE0 34 +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE14 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG2 49 +#define PG3 50 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 // A15 +#define PF7 62 // A16 +#define PF9 63 // A17 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +// 71 is PA7 (11) +// 72 is NC +#define PB7 73 // LED_BLUE +#define PB14 74 // LED_RED +#define PC13 75 // USER_BTN +#define PD9 76 // Serial Rx +#define PD8 77 // Serial Tx +#define PA3 78 // A0 +#define PC0 79 // A1 +#define PC3 80 // A2 +#define PF3 81 // A3 +#define PF5 82 // A4 +#define PF10 83 // A5 +#define PB1 84 // A6 +#define PC2 85 // A7 +#define PF4 86 // A8 +#define PF6 87 // A9 + +// This must be a literal #define NUM_DIGITAL_PINS 96 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 18 diff --git a/variants/NUCLEO_L031K6/variant.h b/variants/NUCLEO_L031K6/variant.h index 57f6f3ec7b..e5621079d2 100644 --- a/variants/NUCLEO_L031K6/variant.h +++ b/variants/NUCLEO_L031K6/variant.h @@ -45,34 +45,31 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA10, //D0 - PA9, //D1 - PA12, //D2 - PB0, //D3 - PB7, //D4 - PB6, //D5 - PB1, //D6 - PC14, //D7 - PC15, //D8 - PA8, //D9 - PA11, //D10 - PB5, //D11 - PB4, //D12 - PB3, //D13 - LED - PA0, //D14/A0 - PA1, //D15/A1 - PA3, //D16/A2 - PA4, //D17/A3 - PA5, //D18/A4 - PA6, //D19/A5 - PA7, //D20/A6 - PA2, //D21/A7 - STLink Tx - PA15, //D22 - STLink Rx - PEND -}; +#define PA10 0 +#define PA9 1 +#define PA12 2 +#define PB0 3 +#define PB7 4 +#define PB6 5 +#define PB1 6 +#define PC14 7 +#define PC15 8 +#define PA8 9 +#define PA11 10 +#define PB5 11 +#define PB4 12 +#define PB3 13 // LED +#define PA0 14 // A0 +#define PA1 15 // A1 +#define PA3 16 // A2 +#define PA4 17 // A3 +#define PA5 18 // A4 +#define PA6 19 // A5 +#define PA7 20 // A6 +#define PA2 21 // A7 - STLink Tx +#define PA15 22 // STLink Rx -// This must be a literal with the same value as PEND +// This must be a literal #define NUM_DIGITAL_PINS 23 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 7 diff --git a/variants/NUCLEO_L053R8/variant.h b/variants/NUCLEO_L053R8/variant.h index ca8fb40caa..c431880241 100644 --- a/variants/NUCLEO_L053R8/variant.h +++ b/variants/NUCLEO_L053R8/variant.h @@ -33,75 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PC4_2,//D57/A11 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A11 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 58 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 12 diff --git a/variants/NUCLEO_L073RZ/variant.h b/variants/NUCLEO_L073RZ/variant.h index 603c40c0aa..9b3e44d4e9 100644 --- a/variants/NUCLEO_L073RZ/variant.h +++ b/variants/NUCLEO_L073RZ/variant.h @@ -45,76 +45,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -// Enum defining pin names to match digital pin number --> Dx -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PWM is not supported by D10 as no timer on PB6 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 // PWM is not supported by D10 as no timer on PB6 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - SB56 ON SB51 ON on the board! - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PC4_2,//D57/A11 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A11 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 - SB56 ON SB51 ON on the board! +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 58 // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS diff --git a/variants/NUCLEO_L152RE/variant.h b/variants/NUCLEO_L152RE/variant.h index 99590cbd09..7347174de7 100644 --- a/variants/NUCLEO_L152RE/variant.h +++ b/variants/NUCLEO_L152RE/variant.h @@ -33,80 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PB12_2,//D57/A11 = D38 - PB1_2,//D58/A12 = D41 - PB15_2,//D59/A13 = D42 - PB14_2,//D60/A14 = D43 - PB13_2,//D61/A15 = D44 - PC4_2, //D62/A16 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 // A11 +#define PB11 39 +#define PB2 40 +#define PB1 41 // A12 +#define PB15 42 // A13 +#define PB14 43 // A14 +#define PB13 44 // A15 +#define PC4 45 // A16 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 63 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 17 diff --git a/variants/NUCLEO_L432KC/variant.h b/variants/NUCLEO_L432KC/variant.h index 58e8df1013..c56ec05958 100644 --- a/variants/NUCLEO_L432KC/variant.h +++ b/variants/NUCLEO_L432KC/variant.h @@ -33,34 +33,31 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA10, //D0 - PA9, //D1 - PA12, //D2 - PB0, //D3 - PB7, //D4 - PB6, //D5 - PB1, //D6 - PC14, //D7 - PC15, //D8 - PA8, //D9 - PA11, //D10 - PB5, //D11 - PB4, //D12 - PB3, //D13 - LED - PA0, //D14/A0 - PA1, //D15/A1 - PA3, //D16/A2 - PA4, //D17/A3 - PA5, //D18/A4 - PA6, //D19/A5 - PA7, //D20/A6 - PA2, //D21/A7 - STLink Tx - PA15, //D22 - STLink Rx - PEND -}; - -// This must be a literal with the same value as PEND +#define PA10 0 +#define PA9 1 +#define PA12 2 +#define PB0 3 +#define PB7 4 +#define PB6 5 +#define PB1 6 +#define PC14 7 +#define PC15 8 +#define PA8 9 +#define PA11 10 +#define PB5 11 +#define PB4 12 +#define PB3 13 // LED +#define PA0 14 // A0 +#define PA1 15 // A1 +#define PA3 16 // A2 +#define PA4 17 // A3 +#define PA5 18 // A4 +#define PA6 19 // A5 +#define PA7 20 // A6 +#define PA2 21 // A7 - STLink Tx +#define PA15 22 // STLink Rx + +// This must be a literal #define NUM_DIGITAL_PINS 23 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 7 diff --git a/variants/NUCLEO_L476RG/variant.h b/variants/NUCLEO_L476RG/variant.h index 06100e2d24..09f5bfa02a 100644 --- a/variants/NUCLEO_L476RG/variant.h +++ b/variants/NUCLEO_L476RG/variant.h @@ -33,75 +33,65 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA3, //D0 - PA2, //D1 - PA10, //D2 - PB3, //D3 - PB5, //D4 - PB4, //D5 - PB10, //D6 - PA8, //D7 - PA9, //D8 - PC7, //D9 - PB6, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - LED - PB9, //D14 - PB8, //D15 +#define PA3 0 +#define PA2 1 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 11 // A6 +#define PA6 12 // A7 +#define PA5 13 // LED +#define PB9 14 +#define PB8 15 // ST Morpho // CN7 Left Side - PC10, //D16 - PC12, //D17 - NC_1, //D18 - BOOT0 - PA13, //D19 - SWD - PA14, //D20 - SWD - PA15, //D21 - PB7, //D22 - PC13, //D23 - PC14, //D24 - PC15, //D25 - PH0, //D26 - PH1, //D27 - PC2, //D28 - PC3, //D29 +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 28 // A8 +#define PC3 29 // A9 // CN7 Right Side - PC11, //D30 - PD2, //D31 +#define PC11 30 +#define PD2 31 // CN10 Left Side - PC9, //D32 +#define PC9 32 // CN10 Right side - PC8, //D33 - PC6, //D34 - PC5, //D35 - PA12, //D36 - PA11, //D37 - PB12, //D38 - PB11, //D39 - PB2, //D40 - PB1, //D41 - PB15, //D42 - PB14, //D43 - PB13, //D44 - PC4, //D45 - PA0, //D46/A0 - PA1, //D47/A1 - PA4, //D48/A2 - PB0, //D49/A3 - PC1, //D50/A4 - PC0, //D51/A5 - // Duplicated pins in order to be aligned with PinMap_ADC - PA7_2,//D52/A6 = D11 - PA6_2,//D53/A7 = D12 - PC2_2,//D54/A8 = D28 - PC3_2,//D55/A9 = D29 - PC5_2,//D56/A10 = D35 - PC4_2,//D57/A11 = D45 - PEND -}; - -// This must be a literal with the same value as PEND +#define PC8 33 +#define PC6 34 +#define PC5 35 // A10 +#define PA12 36 +#define PA11 37 +#define PB12 38 +#define PB11 39 +#define PB2 40 +#define PB1 41 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 45 // A11 +#define PA0 46 // A0 +#define PA1 47 // A1 +#define PA4 48 // A2 +#define PB0 49 // A3 +#define PC1 50 // A4 +#define PC0 51 // A5 + +// This must be a literal #define NUM_DIGITAL_PINS 58 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 12 diff --git a/variants/NUCLEO_L496ZG/variant.h b/variants/NUCLEO_L496ZG/variant.h index 5d0f1c0c88..b50a74d93d 100644 --- a/variants/NUCLEO_L496ZG/variant.h +++ b/variants/NUCLEO_L496ZG/variant.h @@ -47,154 +47,137 @@ extern const PinName digitalPin[]; // Match Table 11. NUCLEO-L496ZG, NUCLEO-L496ZG-P pin assignments // from UM2179 STM32 Nucleo-144 board -enum { - PD9, //D0 - PD8, //D1 - PF15, //D2 - PE13, //D3 - PF14, //D4 - PE11, //D5 - PE9, //D6 - PF13, //D7 - PF12, //D8 - PD15, //D9 - PD14, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 - PC6, //D16 - PB15, //D17 - PB13, //D18 - PB12, //D19 - PA4, //D20 - PB4, //D21 - PB5, //D22 - PB3, //D23 - PA4_2,//D24 - PB4_2,//D25 - PA2, //D26 - PB10, //D27 - PE15, //D28 - PB0, //D29 - PE12, //D30 - PE14, //D31 - PA0, //D32 - PB0_2,//D33 - PE0, //D34 +#define PD9 0 +#define PD8 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 +#define PA7 11 // A11 +#define PA6 12 // A12 +#define PA5 13 // A13 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA4 20 // A14 +#define PB4 21 +#define PB5 22 +#define PB3 23 +// 24 is PA4 (20) +// 25 is PB4 (21) +#define PA2 26 // A15 +#define PB10 27 +#define PE15 28 +#define PB0 29 // A16 +#define PE12 30 +#define PE14 31 +#define PA0 32 // A17 +// 32 is PB0 (29) +#define PE0 34 #ifdef ARDUINO_NUCLEO_L496ZG - PB11, //D35 -#else - NC_1, //D35 +#define PB11 35 +//else 35 is NC #endif - PB10_2,//D36 - PE15_2,//D37 - PE14_2,//D38 - PE12_2,//D39 - PE10, //D40 - PE7, //D41 - PE8, //D42 - PC8, //D43 - PC9, //D44 - PC10, //D45 - PC11, //D46 - PC12, //D47 - PD2, //D48 - PF3, //D49 - PF5, //D50 - PD7, //D51 - PD6, //D52 - PD5, //D53 - PD4, //D54 - PD3, //D55 - PE2, //D56 - PE4, //D57 - PE5, //D58 - PE6, //D59 - PE3, //D60 - PF8, //D61 - PF7, //D62 - PF9, //D63 - PG1, //D64 - PG0, //D65 - PD1, //D66 - PD0, //D67 - PF0, //D68 - PF1, //D69 - PF2, //D70 - PB6, //D71 - PB2, //D72 +// 36 is PB10 (27) +// 37 is PE15 (28) +// 38 is PE14 (31) +// 39 is PE12 (30) +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PF3 49 // A18 +#define PF5 50 // A19 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +#define PE2 56 +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 // A20 +#define PF7 62 // A21 +#define PF9 63 // A22 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +#define PB6 71 +#define PB2 72 // ST Morpho - PA8, //D73 - PA9, //D74 - PA10, //D75 - PA11, //D76 - PA12, //D77 - PA15, //D78 - PB7, //D79 - LEDBLUE - PB14, //D80 - LEDRED - PC7, //D81 - LEDGREEN - PC13, //D82 - USERBTN - PC14, //D83 - PC15, //D84 - PD10, //D85 - PD11, //D86 - PD12, //D87 - PD13, //D88 - PE1, //D89 - PF10, //D90 - PF11, //D91 - PG2, //D92 - PG3, //D93 - PG4, //D94 - PG5, //D95 - PG6, //D96 - PG7, //D97 - Serial Tx - PG8, //D98 - Serial Rx - PG9, //D99 - PG10, //D100 - PG11, //D101 - PG12, //D102 - PG13, //D103 - PG14, //D104 - PH0, //D105 - PH1, //D106 - // Analog pins - PA3, //D107/A0 - PC0, //D108/A1 - PC3, //D109/A2 - PC1, //D110/A3 - PC4, //D111/A4 - PC5, //D112/A5 - PB1, //D113/A6 - PC2, //D114/A7 - PA1, //D115/A8 - PF4, //D116/A9 - PF6, //D117/A10 - // Duplicated pins in order to be aligned with PinMapADC - PA7_3, //D118/A11 = D11 - PA6_2, //D119/A12 = D12 - PA5_2, //D120/A13 = D13 - PA4_3, //D121/A14 = D20 - PA2_2, //D122/A15 = D26 - PB0_3, //D123/A16 = D29 - PA0_2, //D124/A17 = D32 - PF3_2, //D125/A18 = D49 - PF5_2, //D126/A19 = D50 - PF8_2, //D127/A20 = D61 - PF7_2, //D128/A21 = D62 - PF9_2, //D129/A22 = D63 - PF10_2,//D130/A23 = D91 +#define PA8 73 +#define PA9 74 +#define PA10 75 +#define PA11 76 +#define PA12 77 +#define PA15 78 +#define PB7 79 // LED_BLUE +#define PB14 80 // LED_RED +#define PC7 81 // LED_GREEN +#define PC13 82 // USER_BTN +#define PC14 83 +#define PC15 84 +#define PD10 85 +#define PD11 86 +#define PD12 87 +#define PD13 88 +#define PE1 89 +#define PF10 90 // A23 +#define PF11 91 +#define PG2 92 +#define PG3 93 +#define PG4 94 +#define PG5 95 +#define PG6 96 +#define PG7 97 // Serial Tx +#define PG8 98 // Serial Rx +#define PG9 99 +#define PG10 100 +#define PG11 101 +#define PG12 102 +#define PG13 103 +#define PG14 104 +#define PH0 105 +#define PH1 106 +// Analog pins +#define PA3 107 // A0 +#define PC0 108 // A1 +#define PC3 109 // A2 +#define PC1 110 // A3 +#define PC4 111 // A4 +#define PC5 112 // A5 +#define PB1 113 // A6 +#define PC2 114 // A7 +#define PA1 115 // A8 +#define PF4 116 // A9 +#define PF6 117 // A10 +// 118 to 130 reserved fot A11 to A23 #ifdef ARDUINO_NUCLEO_L496ZG - PG15, //D131 +#define PG15 131 #endif - // PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. - // If ST-LINK part is not cut, it is not recommended to use them as I/O pins. -//PA13, //D132 -//PA14, //D133 - PEND -}; +// PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. +// If ST-LINK part is not cut, it is not recommended to use them as I/O pins. +//#define PA13 132 +//#define PA14 133 // This must be a literal with the same value as PEND #ifdef ARDUINO_NUCLEO_L496ZG diff --git a/variants/NUCLEO_L4R5ZI/variant.h b/variants/NUCLEO_L4R5ZI/variant.h index db2be985c3..75841ff503 100644 --- a/variants/NUCLEO_L4R5ZI/variant.h +++ b/variants/NUCLEO_L4R5ZI/variant.h @@ -47,148 +47,137 @@ extern const PinName digitalPin[]; // Match Table 11. NUCLEO-L4R5ZI, NUCLEO-L4R5ZI-P pin assignments // from UM2179 STM32 Nucleo-144 board -enum { - PD9, //D0 - PD8, //D1 - PF15, //D2 - PE13, //D3 - PF14, //D4 - PE11, //D5 - PE9, //D6 - PF13, //D7 - PF12, //D8 - PD15, //D9 - PD14, //D10 - PA7, //D11 - PA6, //D12 - PA5, //D13 - PB9, //D14 - PB8, //D15 - PC6, //D16 - PB15, //D17 - PB13, //D18 - PB12, //D19 - PA4, //D20 - PB4, //D21 - PB5, //D22 - PB3, //D23 - PA4_2,//D24 - PB4_2,//D25 - PA2, //D26 - PB10, //D27 - PE15, //D28 - PB0, //D29 - PE12, //D30 - PE14, //D31 - PA0, //D32 - PB0_2,//D33 - PE0, //D34 +#define PD9 0 +#define PD8 1 +#define PF15 2 +#define PE13 3 +#define PF14 4 +#define PE11 5 +#define PE9 6 +#define PF13 7 +#define PF12 8 +#define PD15 9 +#define PD14 10 +#define PA7 11 // A9 +#define PA6 12 // A10 +#define PA5 13 // A11 +#define PB9 14 +#define PB8 15 +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA4 20 // A12 +#define PB4 21 +#define PB5 22 +#define PB3 23 +// 24 is PA4 (20) +// 25 is PB4 (21) +#define PA2 26 // A13 +#define PB10 27 +#define PE15 28 +#define PB0 29 // A14 +#define PE12 30 +#define PE14 31 +#define PA0 32 // A15 +// 32 is PB0 (29) +#define PE0 34 #ifdef ARDUINO_NUCLEO_L4R5ZI - PB11, //D35 -#else - NC_1, //D35 +#define PB11 35 +// else 35 is NC #endif - PB10_2,//D36 - PE15_2,//D37 - PE14_2,//D38 - PE12_2,//D39 - PE10, //D40 - PE7, //D41 - PE8, //D42 - PC8, //D43 - PC9, //D44 - PC10, //D45 - PC11, //D46 - PC12, //D47 - PD2, //D48 - PF3, //D49 - PF5, //D50 - PD7, //D51 - PD6, //D52 - PD5, //D53 - PD4, //D54 - PD3, //D55 - PE2, //D56 - PE4, //D57 - PE5, //D58 - PE6, //D59 - PE3, //D60 - PF8, //D61 - PF7, //D62 - PF9, //D63 - PG1, //D64 - PG0, //D65 - PD1, //D66 - PD0, //D67 - PF0, //D68 - PF1, //D69 - PF2, //D70 - PB6, //D71 - PB2, //D72 +// 36 is PB10 (27) +// 37 is PE15 (28) +// 38 is PE14 (31) +// 39 is PE12 (30) +#define PE10 40 +#define PE7 41 +#define PE8 42 +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PF3 49 +#define PF5 50 +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +#define PE2 56 +#define PE4 57 +#define PE5 58 +#define PE6 59 +#define PE3 60 +#define PF8 61 +#define PF7 62 +#define PF9 63 +#define PG1 64 +#define PG0 65 +#define PD1 66 +#define PD0 67 +#define PF0 68 +#define PF1 69 +#define PF2 70 +#define PB6 71 +#define PB2 72 // ST Morpho - PA8, //D73 - PA9, //D74 - PA10, //D75 - PA11, //D76 - PA12, //D77 - PA15, //D78 - PB7, //D79 - LEDBLUE - PB14, //D80 - LEDRED - PC7, //D81 - LEDGREEN - PC13, //D82 - USERBTN - PC14, //D83 - PC15, //D84 - PD10, //D85 - PD11, //D86 - PD12, //D87 - PD13, //D88 - PE1, //D89 - PF10, //D90 - PF11, //D91 - PG2, //D92 - PG3, //D93 - PG4, //D94 - PG5, //D95 - PG6, //D96 - PG7, //D97 - Serial Tx - PG8, //D98 - Serial Rx - PG9, //D99 - PG10, //D100 - PG11, //D101 - PG12, //D102 - PG13, //D103 - PG14, //D104 - PH0, //D105 - PH1, //D106 - // Analog pins - PA3, //D107/A0 - PC0, //D108/A1 - PC3, //D109/A2 - PC1, //D110/A3 - PC4, //D111/A4 - PC5, //D112/A5 - PB1, //D113/A6 - PC2, //D114/A7 - PA1, //D115/A8 - // Duplicated pins in order to be aligned with PinMapADC - PA7_3, //D116/A9 = D11 - PA6_2, //D117/A10 = D12 - PA5_2, //D118/A11 = D13 - PA4_3, //D119/A12 = D20 - PA2_2, //D120/A13 = D26 - PB0_3, //D121/A14 = D29 - PA0_2, //D122/A15 = D32 +#define PA8 73 +#define PA9 74 +#define PA10 75 +#define PA11 76 +#define PA12 77 +#define PA15 78 +#define PB7 79 // LED_BLUE +#define PB14 80 // LED_RED +#define PC7 81 // LED_GREEN +#define PC13 82 // USER_BTN +#define PC14 83 +#define PC15 84 +#define PD10 85 +#define PD11 86 +#define PD12 87 +#define PD13 88 +#define PE1 89 +#define PF10 90 +#define PF11 91 +#define PG2 92 +#define PG3 93 +#define PG4 94 +#define PG5 95 +#define PG6 96 +#define PG7 97 // Serial Tx +#define PG8 98 // Serial Rx +#define PG9 99 +#define PG10 100 +#define PG11 101 +#define PG12 102 +#define PG13 103 +#define PG14 104 +#define PH0 105 +#define PH1 106 +// Analog pins +#define PA3 107 // A0 +#define PC0 108 // A1 +#define PC3 109 // A2 +#define PC1 110 // A3 +#define PC4 111 // A4 +#define PC5 112 // A5 +#define PB1 113 // A6 +#define PC2 114 // A7 +#define PA1 115 // A8 +// 116 to 122 reserved fot A9 to A15 #ifdef ARDUINO_NUCLEO_L4R5ZI - PG15, //D123 +#define PG15 123 #endif - // PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. - // If ST-LINK part is not cut, it is not recommended to use them as I/O pins. -//PA13, //D124 -//PA14, //D125 - PEND -}; +// PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. +// If ST-LINK part is not cut, it is not recommended to use them as I/O pins. +//#define PA13 124 +//#define PA14 125 -// This must be a literal with the same value as PEND +// This must be a literal #ifdef ARDUINO_NUCLEO_L4R5ZI #define NUM_DIGITAL_PINS 124 #else diff --git a/variants/RAK811_TRACKER/variant.h b/variants/RAK811_TRACKER/variant.h index 80bf2d68a5..199cbabcef 100644 --- a/variants/RAK811_TRACKER/variant.h +++ b/variants/RAK811_TRACKER/variant.h @@ -45,46 +45,43 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -enum { - PA0, //D0 - GPS_PPS_PIN - PA8, //D1 - PA9, //D2 - UART_TX - PA10, //D3 - UART_RX - PA12, //D4 - LED1 - PA13, //D5 - PA14, //D6 - PA15, //D7 - GPS_POWER_ON_PIN - PB2, //D8 - PB3, //D9 - PB4, //D10 - LED2 - PB5, //D11 - PB8, //D12 - I2C_SCL - PB9, //D13 - I2C_SDA - PB10, //D14 - GPS_UART_TX - PB11, //D15 - GPS_UART_RX - PA1, //D16/A0 - PA2, //D17/A1 - ADC_VBAT - PB12, //D18/A2 - PB14, //D19 - LIS3DH_INT1_PIN - PB15, //D20 - LIS3DH_INT2_PIN - PB13, //D21 - RADIO_RESET - PH1, //D22 - RADIO_XTAL_EN - PA7, //D23 - RADIO_MOSI - PA6, //D24 - RADIO_MISO - PA5, //D25 - RADIO_SCLK - PB0, //D26 - RADIO_NSS - PA11, //D27 - RADIO_DIO_0 - PB1, //D28 - RADIO_DIO_1 - PA3, //D29 - RADIO_DIO_2 - PH0, //D30 - RADIO_DIO_3 - PC13, //D31 - RADIO_DIO_4 - PB6, //D32 - RADIO_RF_CRX_RX - PB7, //D33 - RADIO_RF_CBT_HF - PA4, //D34 - RADIO_RF_CTX_PA - PEND -}; - -// This must be a literal with the same value as PEND +#define PA0 0 // GPS_PPS_PIN +#define PA8 1 +#define PA9 2 // UART_TX +#define PA10 3 // UART_RX +#define PA12 4 // LED1 +#define PA13 5 +#define PA14 6 +#define PA15 7 // GPS_POWER_ON_PIN +#define PB2 8 +#define PB3 9 +#define PB4 10 // LED2 +#define PB5 11 +#define PB8 12 // I2C_SCL +#define PB9 13 // I2C_SDA +#define PB10 14 // GPS_UART_TX +#define PB11 15 // GPS_UART_RX +#define PA1 16 // A0 +#define PA2 17 // A1 - ADC_VBAT +#define PB12 18 // A2 +#define PB14 19 // LIS3DH_INT1_PIN +#define PB15 20 // LIS3DH_INT2_PIN +#define PB13 21 // RADIO_RESET +#define PH1 22 // RADIO_XTAL_EN +#define PA7 23 // RADIO_MOSI +#define PA6 24 // RADIO_MISO +#define PA5 25 // RADIO_SCLK +#define PB0 26 // RADIO_NSS +#define PA11 27 // RADIO_DIO_0 +#define PB1 28 // RADIO_DIO_1 +#define PA3 29 // RADIO_DIO_2 +#define PH0 30 // RADIO_DIO_3 +#define PC13 31 // RADIO_DIO_4 +#define PB6 32 // RADIO_RF_CRX_RX +#define PB7 33 // RADIO_RF_CBT_HF +#define PA4 34 // RADIO_RF_CTX_PA + +// This must be a literal #define NUM_DIGITAL_PINS 35 // This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS #define NUM_ANALOG_INPUTS 3 diff --git a/variants/REMRAM_V1/variant.h b/variants/REMRAM_V1/variant.h index 38c5a53b6e..018ed996fc 100644 --- a/variants/REMRAM_V1/variant.h +++ b/variants/REMRAM_V1/variant.h @@ -46,111 +46,105 @@ extern "C" *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; - // Enum defining pin names to match digital pin number --> Dx - enum - { - // USART - PA10, // D0 - RX - PA9, // D1 - TX - - // SWD - PA14, // D2 - SWCLK - PA13, // D3 - SWDIO - - // EXT3 - PE5, // D4 - EXT_D1 - PE4, // D5 - EXT_D2 - PE3, // D6 - EXT_D3 - PE2, // D7 - EXT_D4 - PE1, // D8 - EXT_D5 - - // SPI - PB2, // D9 - SS_SDLCD - PC4, // D10 - SS_E - PA7, // D11 - MOSI - PA6, // D12 - MISO - PA5, // D13 - SCK - PB1, // D14 - SS_X - PB0, // D15 - SS_Y - PC5, // D16 - SS_Z - - // I2C - PB6, // D17 - SCL - PB7, // D18 - SDA - - // USB - PA12, // D19 - DD+ - PA11, // D20 - DD- - - // LED - PD0, // D21 - STATUS_LED - - // PWM - // TIM2 - PA15, // D22 - X_STEP - PB3, // D23 - Y_STEP - PB10, // D24 - Z_STEP - PB11, // D25 - E_STEP - // TIM3 - PB5, // D26 - PWM_EXT1 - PB4, // D27 - PWM_EXT2 - PC8, // D28 - PWM_EXT3 - PC9, // D29 - PWM_EXT4 - // TIM5 - PA0, // D30 - PWM_FAN1 - PA1, // D31 - PWM_BED - PA2, // D32 - PWM_FAN2 - PA3, // D33 - PWM_HEAT - - // Stepper - PC12, // D34 - X_EN - PC10, // D35 - X_DIR - PC11, // D36 - X_DIAG - PD4, // D37 - Y_EN - PD6, // D38 - Y_DIR - PD5, // D39 - Y_DIAG - PE15, // D40 - Z_EN - PE13, // D41 - Z_DIR - PE14, // D42 - Z_DIAG - PE11, // D43 - E_EN - PE10, // D44 - E_DIR - PE12, // D45 - E_DIAG - - // EXT3 - PC6, // D46 - LCD_BEEPER - PC7, // D47 - BTN_ENC - PD14, // D48 - LCD_EN - PD15, // D49 - LCD_RS - PD13, // D50 - LCD_D4 - PD12, // D51 - LCD_D5 - PD11, // D52 - LCD_D6 - PD10, // D53 - LCD_D7 - - // EXT2 - PC14, // D54 - BTN_EN1 - PC15, // D55 - BTN_EN2 - PC13, // D56 - SD_CARD_DET - - // SD Card Reader - PE7, // D57 - SS_SD - - // Endstops - PB12, // D58 - X_MIN - PB13, // D59 - X_MAX - PB14, // D60 - Y_MIN - PB15, // D61 - Y_MAX - PD8, // D62 - Z_MIN - PD9, // D63 - Z_MAX - - // ADC - PC0, // D64 - THERM_1 - PC1, // D65 - THERM_2 - PC2, // D66 - THERM_3 - PA4, // D67 - FAN_SPEED1 - PC3, // D68 - FAN_SPEED2 - - PEND - }; +// USART +#define PA10 0 // RX +#define PA9 1 // TX + +// SWD +#define PA14 2 // SWCLK +#define PA13 3 // SWDIO + +// EXT3 +#define PE5 4 // EXT_D1 +#define PE4 5 // EXT_D2 +#define PE3 6 // EXT_D3 +#define PE2 7 // EXT_D4 +#define PE1 8 // EXT_D5 + +// SPI +#define PB2 9 // SS_SDLCD +#define PC4 10 // SS_E +#define PA7 11 // MOSI +#define PA6 12 // MISO +#define PA5 13 // SCK +#define PB1 14 // SS_X +#define PB0 15 // SS_Y +#define PC5 16 // SS_Z + +// I2C +#define PB6 17 // SCL +#define PB7 18 // SDA + +// USB +#define PA12 19 // DD+ +#define PA11 20 // DD// + +// LED +#define PD0 21 // STATUS_LED + +// PWM +// TIM2 +#define PA15 22 // X_STEP +#define PB3 23 // Y_STEP +#define PB10 24 // Z_STEP +#define PB11 25 // E_STEP +// TIM3 +#define PB5 26 // PWM_EXT1 +#define PB4 27 // PWM_EXT2 +#define PC8 28 // PWM_EXT3 +#define PC9 29 // PWM_EXT4 +// TIM5 +#define PA0 30 // PWM_FAN1 +#define PA1 31 // PWM_BED +#define PA2 32 // PWM_FAN2 +#define PA3 33 // PWM_HEAT + +// Stepper +#define PC12 34 // X_EN +#define PC10 35 // X_DIR +#define PC11 36 // X_DIAG +#define PD4 37 // Y_EN +#define PD6 38 // Y_DIR +#define PD5 39 // Y_DIAG +#define PE15 40 // Z_EN +#define PE13 41 // Z_DIR +#define PE14 42 // Z_DIAG +#define PE11 43 // E_EN +#define PE10 44 // E_DIR +#define PE12 45 // E_DIAG + +// EXT3 +#define PC6 46 // LCD_BEEPER +#define PC7 47 // BTN_ENC +#define PD14 48 // LCD_EN +#define PD15 49 // LCD_RS +#define PD13 50 // LCD_D4 +#define PD12 51 // LCD_D5 +#define PD11 52 // LCD_D6 +#define PD10 53 // LCD_D7 + +// EXT2 +#define PC14 54 // BTN_EN1 +#define PC15 55 // BTN_EN2 +#define PC13 56 // SD_CARD_DET + +// SD Card Reader +#define PE7 57 // SS_SD + +// Endstops +#define PB12 58 // X_MIN +#define PB13 59 // X_MAX +#define PB14 60 // Y_MIN +#define PB15 61 // Y_MAX +#define PD8 62 // Z_MIN +#define PD9 63 // Z_MAX + +// ADC +#define PC0 64 // THERM_1 +#define PC1 65 // THERM_2 +#define PC2 66 // THERM_3 +#define PA4 67 // FAN_SPEED1 +#define PC3 68 // FAN_SPEED2 // PIN definition #define NUM_DIGITAL_PINS 69 diff --git a/variants/board_template/variant.h b/variants/board_template/variant.h index 6a6e5e7d17..49cd4a6298 100644 --- a/variants/board_template/variant.h +++ b/variants/board_template/variant.h @@ -45,19 +45,30 @@ extern "C"{ *----------------------------------------------------------------------------*/ extern const PinName digitalPin[]; -// Enum defining pin names to match digital pin number --> Dx +// Define pin names to match digital pin number --> Dx +// It could be used with preprocessor tests (e.g. #if PXn == 3) +// so an enum will not work. // !!! -// !!! Copy the digitalPin[] array in variant.cpp +// !!! Copy the digitalPin[] array from the variant.cpp // !!! and remove all '_': PX_n --> PXn -// !!! For NC, suffix by _x where x is the number of NC: -// !!! NC_1, NC_2,... -// !!! For duplicated pin name, suffix by _x where x is the number of pin: -// !!! PA7, PA7_2, PA7_3,... -enum { - PEND -}; - -// This must be a literal with the same value as PEND +// !!! For NC, comment the line to warn x pin number is NC +// !!! // x is NC +// !!! For duplicated pin name, comment the line to warn x pin number +// !!! is PXn which is already defined with y pin number +// !!! // x is PXn (y) +// !!! Ex: +// !!! ... +// !!! #define PA4 20 // A14 +// !!! #define PB4 21 +// !!! #define PB5 22 +// !!! #define PB3 23 +// !!! // 24 is PA4 (20) +// !!! // 25 is PB4 (21)// #define PXn x +// !!! #define PA2 26 // A15 +// !!! ... +//#define PXn x + +// This must be a literal // It is used with preprocessor tests (e.g. #if NUM_DIGITAL_PINS > 3) // so an enum will not work. #define NUM_DIGITAL_PINS 0 From 099819b948a6535f59a8f1f95258889258ab41dc Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Fri, 19 Oct 2018 08:14:41 +0200 Subject: [PATCH 105/109] Update CI core configuration Signed-off-by: Frederic.Pillon --- CI/build/conf/cores_config.json | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index e0bb1925fa..e73ab23b75 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -64,7 +64,7 @@ "boards": [ "DISCO_F746NG", "BLACK_F407VE", "BLUE_F407VE_Mini" ] }, { - "pattern": "Ethernet/", + "pattern": "Ethernet/|STM32FreeRTOS", "applicable": false, "boards": [ "NUCLEO_L031K6" ] }, @@ -85,6 +85,16 @@ "MAPLEMINI_F103CB" ] }, + { + "pattern": "X_NUCLEO_NFC03A1_HelloWorld.ino", + "applicable": false, + "boards": [ + "DISCO_F030R8", + "DISCO_F100RB", + "NUCLEO_F030R8", + "NUCLEO_L053R8" + ] + }, { "pattern": "X_NUCLEO_|FP_Examples", "applicable": false, @@ -101,7 +111,7 @@ "boards": [ "RAK811_TRACKER" ] }, { - "pattern": "SerialLoop.ino", + "pattern": "SerialLoop.ino|Tests_basic_functions.ino", "applicable": false, "boards": [ "NUCLEO_L031K6" ] } From af1449510414a9743fa8634834c4141037dbab39 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 30 Oct 2018 15:18:29 +0100 Subject: [PATCH 106/109] Update README.md --- README.md | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index c63572fe5f..430173d930 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # Arduino core support for STM32 based boards [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...master) +[![GitHub commits](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/1.3.0.svg)](https://github.com/stm32duino/Arduino_Core_STM32/compare/1.3.0...1.4.0) [![Build Status](https://travis-ci.com/stm32duino/Arduino_Core_STM32.svg?branch=master)](https://travis-ci.com/stm32duino/Arduino_Core_STM32) * [Introduction](https://github.com/stm32duino/Arduino_Core_STM32#Introduction)
          @@ -59,6 +59,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d * [Nucleo F303RE](http://www.st.com/en/evaluation-tools/nucleo-f303re.html) * STM32F4 + * [Black F407VET6](http://wiki.stm32duino.com/index.php?title=STM32F407#.22Black_VET6.22_STM32F407VET6_Variant) + * [Blue F407VET6 Mini](http://wiki.stm32duino.com/index.php?title=Vcc-gnd.com_STM32F407VET6_Mini) * [Nucleo F401RE](http://www.st.com/en/evaluation-tools/nucleo-f401re.html) * [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) * [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) @@ -66,12 +68,16 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d * [STM32F407G-DISC1](http://www.st.com/en/evaluation-tools/stm32f4discovery.html) * STM32F7 + * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) + * [RemRam v1](https://github.com/hasenbanck/remram) * [STM32F746G-DISCOVERY](http://www.st.com/en/evaluation-tools/32f746gdiscovery.html) * STM32L0 * [Nucleo L031K6](http://www.st.com/en/evaluation-tools/nucleo-l031k6.html) * [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) + * [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) * [B-L072Z-LRWAN1](http://www.st.com/en/evaluation-tools/b-l072z-lrwan1.html) + * [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) (Basic support) * STM32L1 * [Nucleo L152RE](http://www.st.com/en/evaluation-tools/nucleo-l152re.html) @@ -81,25 +87,11 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d * [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) * [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) * [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) - * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) - -### Next release - * STM32F4 - * [Black F407VET6](http://wiki.stm32duino.com/index.php?title=STM32F407#.22Black_VET6.22_STM32F407VET6_Variant) - * [Blue F407VET6 Mini](http://wiki.stm32duino.com/index.php?title=Vcc-gnd.com_STM32F407VET6_Mini) - - * STM32F7 - * [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) - * [RemRam v1](https://github.com/hasenbanck/remram) - - * STM32L0 - * [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) - * [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) (Basic support) - - * STM32L4 * [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) * [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) + * [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) +### Next release ## Troubleshooting From d9870f91d22aeccdba25faf681f6557e11aa4c53 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 31 Oct 2018 13:52:41 +0100 Subject: [PATCH 107/109] [Nucleo L432KC] Fix pin mapping D7/D8 was inverted, moreover add a comment to specify they are not connected by default. SB6 and SB8 need to be closed to connect them to the CN3 connector. Signed-off-by: Frederic.Pillon --- variants/NUCLEO_L432KC/variant.cpp | 4 ++-- variants/NUCLEO_L432KC/variant.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/variants/NUCLEO_L432KC/variant.cpp b/variants/NUCLEO_L432KC/variant.cpp index 6f927bf319..f4c4f320ad 100644 --- a/variants/NUCLEO_L432KC/variant.cpp +++ b/variants/NUCLEO_L432KC/variant.cpp @@ -31,8 +31,8 @@ const PinName digitalPin[] = { PB_7, //D4 PB_6, //D5 PB_1, //D6 - PC_14, //D7 - PC_15, //D8 + PC15, //D7 - By default, SB8 open PF1/PC15 not connected to D7 + PC14, //D8 - By default, SB6 open PF0/PC14 not connected to D8 PA_8, //D9 PA_11, //D10 PB_5, //D11 diff --git a/variants/NUCLEO_L432KC/variant.h b/variants/NUCLEO_L432KC/variant.h index c56ec05958..a6c486611e 100644 --- a/variants/NUCLEO_L432KC/variant.h +++ b/variants/NUCLEO_L432KC/variant.h @@ -40,8 +40,8 @@ extern const PinName digitalPin[]; #define PB7 4 #define PB6 5 #define PB1 6 -#define PC14 7 -#define PC15 8 +#define PC15 7 // By default, SB8 open PF1/PC15 not connected to D7 +#define PC14 8 // By default, SB6 open PF0/PC14 not connected to D8 #define PA8 9 #define PA11 10 #define PB5 11 From 6069da10750597ab7d1ce372e2b3178801b5f784 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 31 Oct 2018 16:03:04 +0100 Subject: [PATCH 108/109] [Nucleo L073RZ] Fix pin mapping Signed-off-by: Frederic.Pillon --- variants/NUCLEO_L073RZ/PeripheralPins.c | 46 +++++++------------------ 1 file changed, 13 insertions(+), 33 deletions(-) diff --git a/variants/NUCLEO_L073RZ/PeripheralPins.c b/variants/NUCLEO_L073RZ/PeripheralPins.c index e520c0904e..9af6ff1ab3 100644 --- a/variants/NUCLEO_L073RZ/PeripheralPins.c +++ b/variants/NUCLEO_L073RZ/PeripheralPins.c @@ -107,29 +107,29 @@ const PinMap PinMap_PWM[] = { {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_2, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 +// {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 {PA_3, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1 - {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1 +// {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 {PA_7, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2 {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 {PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_4, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1 - {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM3, 2, 0)}, // TIM3_CH2 +// {PB_4, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1 +// {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM3, 2, 0)}, // TIM3_CH2 {PB_5, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2 {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 {PB_13, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1 {PB_14, TIM21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2 {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1 - {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_6, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1 +// {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 {PC_7, TIM22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2 {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 @@ -142,48 +142,28 @@ const PinMap PinMap_PWM[] = { #ifdef HAL_UART_MODULE_ENABLED const PinMap PinMap_UART_TX[] = { {PA_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, +// {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_14, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, +// {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_3, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PC_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PC_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, +// {PC_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {PC_10, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, {PC_12, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)}, {NC, NP, 0} }; -/* -const PinMap PinMap_UART_TX[] = { - {PA_0, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PA_14, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PB_3, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, - {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, - {PC_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PC_4, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PC_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, - {PC_10, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PC_12, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)}, - {NC, NP, 0} -}; - - -*/ #endif #ifdef HAL_UART_MODULE_ENABLED const PinMap PinMap_UART_RX[] = { {PA_1, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, +// {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, @@ -194,7 +174,7 @@ const PinMap PinMap_UART_RX[] = { {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PC_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PC_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PC_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, +// {PC_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {PC_11, USART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, {PD_2, USART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, {NC, NP, 0} From 0a826c37d92db6b8f9e6b58c40788efeb86d2519 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Wed, 31 Oct 2018 18:03:11 +0100 Subject: [PATCH 109/109] [Nucleo L432KC] Fix wrong typo Signed-off-by: Frederic.Pillon --- variants/NUCLEO_L432KC/variant.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/NUCLEO_L432KC/variant.cpp b/variants/NUCLEO_L432KC/variant.cpp index f4c4f320ad..051e05b672 100644 --- a/variants/NUCLEO_L432KC/variant.cpp +++ b/variants/NUCLEO_L432KC/variant.cpp @@ -31,8 +31,8 @@ const PinName digitalPin[] = { PB_7, //D4 PB_6, //D5 PB_1, //D6 - PC15, //D7 - By default, SB8 open PF1/PC15 not connected to D7 - PC14, //D8 - By default, SB6 open PF0/PC14 not connected to D8 + PC_15, //D7 - By default, SB8 open PF1/PC15 not connected to D7 + PC_14, //D8 - By default, SB6 open PF0/PC14 not connected to D8 PA_8, //D9 PA_11, //D10 PB_5, //D11