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| 1 | +/** |
| 2 | + ****************************************************************************** |
| 3 | + * @file stm32f7xx_hal.h |
| 4 | + * @author MCD Application Team |
| 5 | + * @version V1.2.2 |
| 6 | + * @date 14-April-2017 |
| 7 | + * @brief This file contains all the functions prototypes for the HAL |
| 8 | + * module driver. |
| 9 | + ****************************************************************************** |
| 10 | + * @attention |
| 11 | + * |
| 12 | + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| 13 | + * |
| 14 | + * Redistribution and use in source and binary forms, with or without modification, |
| 15 | + * are permitted provided that the following conditions are met: |
| 16 | + * 1. Redistributions of source code must retain the above copyright notice, |
| 17 | + * this list of conditions and the following disclaimer. |
| 18 | + * 2. Redistributions in binary form must reproduce the above copyright notice, |
| 19 | + * this list of conditions and the following disclaimer in the documentation |
| 20 | + * and/or other materials provided with the distribution. |
| 21 | + * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| 22 | + * may be used to endorse or promote products derived from this software |
| 23 | + * without specific prior written permission. |
| 24 | + * |
| 25 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 26 | + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 27 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 28 | + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| 29 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 30 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 31 | + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 32 | + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 33 | + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 34 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | + * |
| 36 | + ****************************************************************************** |
| 37 | + */ |
| 38 | + |
| 39 | +/* Define to prevent recursive inclusion -------------------------------------*/ |
| 40 | +#ifndef __STM32F7xx_HAL_H |
| 41 | +#define __STM32F7xx_HAL_H |
| 42 | + |
| 43 | +#ifdef __cplusplus |
| 44 | + extern "C" { |
| 45 | +#endif |
| 46 | + |
| 47 | +/* Includes ------------------------------------------------------------------*/ |
| 48 | +#include "stm32f7xx_hal_conf.h" |
| 49 | + |
| 50 | +/** @addtogroup STM32F7xx_HAL_Driver |
| 51 | + * @{ |
| 52 | + */ |
| 53 | + |
| 54 | +/** @addtogroup HAL |
| 55 | + * @{ |
| 56 | + */ |
| 57 | + |
| 58 | +/* Exported types ------------------------------------------------------------*/ |
| 59 | +/* Exported constants --------------------------------------------------------*/ |
| 60 | +/** @defgroup HAL_Exported_Constants HAL Exported Constants |
| 61 | + * @{ |
| 62 | + */ |
| 63 | + |
| 64 | +/** @defgroup SYSCFG_BootMode Boot Mode |
| 65 | + * @{ |
| 66 | + */ |
| 67 | +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) |
| 68 | +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT |
| 69 | +/** |
| 70 | + * @} |
| 71 | + */ |
| 72 | + |
| 73 | +/** |
| 74 | + * @} |
| 75 | + */ |
| 76 | + |
| 77 | +/* Exported macro ------------------------------------------------------------*/ |
| 78 | +/** @defgroup HAL_Exported_Macros HAL Exported Macros |
| 79 | + * @{ |
| 80 | + */ |
| 81 | + |
| 82 | +/** @brief Freeze/Unfreeze Peripherals in Debug mode |
| 83 | + */ |
| 84 | +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| 85 | +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| 86 | +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| 87 | +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| 88 | +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| 89 | +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| 90 | +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| 91 | +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| 92 | +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| 93 | +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) |
| 94 | +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| 95 | +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| 96 | +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| 97 | +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| 98 | +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| 99 | +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| 100 | +#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) |
| 101 | +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
| 102 | +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) |
| 103 | +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| 104 | +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| 105 | +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) |
| 106 | +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) |
| 107 | +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) |
| 108 | + |
| 109 | +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| 110 | +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| 111 | +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| 112 | +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| 113 | +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| 114 | +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| 115 | +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| 116 | +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| 117 | +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| 118 | +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) |
| 119 | +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| 120 | +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| 121 | +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| 122 | +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| 123 | +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| 124 | +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| 125 | +#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) |
| 126 | +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
| 127 | +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) |
| 128 | +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| 129 | +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| 130 | +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) |
| 131 | +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) |
| 132 | +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) |
| 133 | + |
| 134 | + |
| 135 | +/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 |
| 136 | + */ |
| 137 | +#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) |
| 138 | + |
| 139 | + |
| 140 | +/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 |
| 141 | + */ |
| 142 | +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ |
| 143 | + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ |
| 144 | + }while(0); |
| 145 | +/** |
| 146 | + * @brief Return the memory boot mapping as configured by user. |
| 147 | + * @retval The boot mode as configured by user. The returned value can be one |
| 148 | + * of the following values: |
| 149 | + * @arg @ref SYSCFG_MEM_BOOT_ADD0 |
| 150 | + * @arg @ref SYSCFG_MEM_BOOT_ADD1 |
| 151 | + */ |
| 152 | +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) |
| 153 | + |
| 154 | +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
| 155 | +/** @brief SYSCFG Break Cortex-M7 Lockup lock. |
| 156 | + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. |
| 157 | + * @note The selected configuration is locked and can be unlocked only by system reset. |
| 158 | + */ |
| 159 | +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) |
| 160 | + |
| 161 | +/** @brief SYSCFG Break PVD lock. |
| 162 | + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. |
| 163 | + * @note The selected configuration is locked and can be unlocked only by system reset. |
| 164 | + */ |
| 165 | +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) |
| 166 | +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| 167 | + |
| 168 | +/** |
| 169 | + * @} |
| 170 | + */ |
| 171 | + |
| 172 | +/* Exported functions --------------------------------------------------------*/ |
| 173 | +/** @addtogroup HAL_Exported_Functions |
| 174 | + * @{ |
| 175 | + */ |
| 176 | +/** @addtogroup HAL_Exported_Functions_Group1 |
| 177 | + * @{ |
| 178 | + */ |
| 179 | +/* Initialization and de-initialization functions ******************************/ |
| 180 | +HAL_StatusTypeDef HAL_Init(void); |
| 181 | +HAL_StatusTypeDef HAL_DeInit(void); |
| 182 | +void HAL_MspInit(void); |
| 183 | +void HAL_MspDeInit(void); |
| 184 | +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| 185 | +/** |
| 186 | + * @} |
| 187 | + */ |
| 188 | + |
| 189 | +/** @addtogroup HAL_Exported_Functions_Group2 |
| 190 | + * @{ |
| 191 | + */ |
| 192 | +/* Peripheral Control functions ************************************************/ |
| 193 | +void HAL_IncTick(void); |
| 194 | +void HAL_Delay(__IO uint32_t Delay); |
| 195 | +uint32_t HAL_GetTick(void); |
| 196 | +void HAL_SuspendTick(void); |
| 197 | +void HAL_ResumeTick(void); |
| 198 | +uint32_t HAL_GetHalVersion(void); |
| 199 | +uint32_t HAL_GetREVID(void); |
| 200 | +uint32_t HAL_GetDEVID(void); |
| 201 | +void HAL_DBGMCU_EnableDBGSleepMode(void); |
| 202 | +void HAL_DBGMCU_DisableDBGSleepMode(void); |
| 203 | +void HAL_DBGMCU_EnableDBGStopMode(void); |
| 204 | +void HAL_DBGMCU_DisableDBGStopMode(void); |
| 205 | +void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| 206 | +void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| 207 | +void HAL_EnableCompensationCell(void); |
| 208 | +void HAL_DisableCompensationCell(void); |
| 209 | +void HAL_EnableFMCMemorySwapping(void); |
| 210 | +void HAL_DisableFMCMemorySwapping(void); |
| 211 | +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
| 212 | +void HAL_EnableMemorySwappingBank(void); |
| 213 | +void HAL_DisableMemorySwappingBank(void); |
| 214 | +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| 215 | +/** |
| 216 | + * @} |
| 217 | + */ |
| 218 | + |
| 219 | +/** |
| 220 | + * @} |
| 221 | + */ |
| 222 | +/* Private types -------------------------------------------------------------*/ |
| 223 | +/* Private variables ---------------------------------------------------------*/ |
| 224 | +/** @defgroup HAL_Private_Variables HAL Private Variables |
| 225 | + * @{ |
| 226 | + */ |
| 227 | +/** |
| 228 | + * @} |
| 229 | + */ |
| 230 | +/* Private constants ---------------------------------------------------------*/ |
| 231 | +/** @defgroup HAL_Private_Constants HAL Private Constants |
| 232 | + * @{ |
| 233 | + */ |
| 234 | +/** |
| 235 | + * @} |
| 236 | + */ |
| 237 | +/* Private macros ------------------------------------------------------------*/ |
| 238 | +/* Private functions ---------------------------------------------------------*/ |
| 239 | +/** |
| 240 | + * @} |
| 241 | + */ |
| 242 | + |
| 243 | +/** |
| 244 | + * @} |
| 245 | + */ |
| 246 | + |
| 247 | +#ifdef __cplusplus |
| 248 | +} |
| 249 | +#endif |
| 250 | + |
| 251 | +#endif /* __STM32F7xx_HAL_H */ |
| 252 | + |
| 253 | +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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