Update PAC stm32l4 to v0.15.1

Author: jspngh

Cargo.toml

@@ -23,7 +23,7 @@ edition = "2018"
 [dependencies]
 cortex-m = "0.7"
 nb = "0.1.1"
-stm32l4 = "0.14.0"
+stm32l4 = "0.15.1"
 embedded-dma = "0.1"
 bxcan = ">=0.4, <0.7"
 fugit = "0.3.5"

src/pwm.rs

@@ -370,7 +370,7 @@ macro_rules! pwm_channels {
 
                 #[inline(always)]
                 fn get_duty(&self) -> Self::Duty {
-                    unsafe { (*$TIMX::ptr()).$ccrX.read().$ccr().bits() }
+                    unsafe { (*$TIMX::ptr()).$ccrX().read().$ccr().bits() }
                 }
 
                 #[inline(always)]
@@ -380,7 +380,7 @@ macro_rules! pwm_channels {
 
                 #[inline(always)]
                 fn set_duty(&mut self, duty: Self::Duty) {
-                    unsafe { (*$TIMX::ptr()).$ccrX.write(|w| w.$ccr().bits(duty)) }
+                    unsafe { (*$TIMX::ptr()).$ccrX().write(|w| w.$ccr().bits(duty)) }
                 }
             }
         )+

src/rtc.rs

@@ -271,7 +271,7 @@ impl Rtc {
                 rtc_registers::clear_alarm_a_flag(rtc);
                 while !rtc_registers::is_alarm_a_accessible(rtc) {}
 
-                rtc.alrmar.modify(|_, w| unsafe {
+                rtc.alrmar().modify(|_, w| unsafe {
                     w.dt()
                         .bits(dt)
                         .du()
@@ -307,7 +307,7 @@ impl Rtc {
                 rtc_registers::clear_alarm_b_flag(rtc);
                 while !rtc_registers::is_alarm_b_accessible(rtc) {}
 
-                rtc.alrmbr.modify(|_, w| unsafe {
+                rtc.alrmbr().modify(|_, w| unsafe {
                     w.dt()
                         .bits(dt)
                         .du()

src/tsc.rs

@@ -267,7 +267,7 @@ impl<SPIN> Tsc<SPIN> {
     /// Reads the tsc group 2 count register
     /// WARNING, just returns the contents of the register! No validation of the correct pin
     pub fn read_unchecked(&self) -> u16 {
-        self.tsc.iog2cr.read().cnt().bits()
+        self.tsc.iog2cr().read().cnt().bits()
     }
 
     /// Is the tsc performing an aquisition

src/watchdog.rs

@@ -27,34 +27,7 @@ impl IndependentWatchdog {
 
     /// Debug independent watchdog stopped when core is halted
     pub fn stop_on_debug(&self, dbgmcu: &DBGMCU, stop: bool) {
-        #[cfg(any(
-            feature = "stm32l431",
-            feature = "stm32l451",
-            feature = "stm32l471",
-            feature = "stm32l412",
-            feature = "stm32l422",
-            feature = "stm32l432",
-            feature = "stm32l442",
-            feature = "stm32l452",
-            feature = "stm32l462",
-            feature = "stm32l433",
-            feature = "stm32l443",
-        ))]
         dbgmcu.apb1fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
-        #[cfg(not(any(
-            feature = "stm32l431",
-            feature = "stm32l451",
-            feature = "stm32l471",
-            feature = "stm32l412",
-            feature = "stm32l422",
-            feature = "stm32l432",
-            feature = "stm32l442",
-            feature = "stm32l452",
-            feature = "stm32l462",
-            feature = "stm32l433",
-            feature = "stm32l443",
-        )))]
-        dbgmcu.apb1_fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
     }
 
     /// Sets the watchdog timer timout period. Max: 32768 ms