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LogicalStep_Lab3_top.sta.rpt
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TimeQuest Timing Analyzer report for LogicalStep_Lab3_top
Tue Mar 06 18:43:59 2018
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Fmax Summary
6. Setup Summary
7. Hold Summary
8. Recovery Summary
9. Removal Summary
10. Minimum Pulse Width Summary
11. Metastability Summary
12. Board Trace Model Assignments
13. Input Transition Times
14. Signal Integrity Metrics (Slow 1200mv 85c Model)
15. Setup Transfers
16. Hold Transfers
17. Report TCCS
18. Report RSKM
19. Unconstrained Paths Summary
20. Clock Status Summary
21. Unconstrained Input Ports
22. Unconstrained Output Ports
23. Unconstrained Input Ports
24. Unconstrained Output Ports
25. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Timing Analyzer ; TimeQuest ;
; Revision Name ; LogicalStep_Lab3_top ;
; Device Family ; MAX 10 ;
; Device Name ; 10M08SAE144C8G ;
; Timing Models ; Final ;
; Delay Model ; Slow 1200mV 85C Model ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
; clkin_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clkin_50 } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------+
; Fmax Summary ;
+------------+-----------------+------------+---------------------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+---------------------------------------------------------------+
; 379.08 MHz ; 250.0 MHz ; clkin_50 ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+-----------------------------------+
; Setup Summary ;
+----------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------+--------+---------------+
; clkin_50 ; -1.638 ; -12.869 ;
+----------+--------+---------------+
+----------------------------------+
; Hold Summary ;
+----------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------+-------+---------------+
; clkin_50 ; 0.379 ; 0.000 ;
+----------+-------+---------------+
--------------------
; Recovery Summary ;
--------------------
No paths to report.
-------------------
; Removal Summary ;
-------------------
No paths to report.
+-----------------------------------+
; Minimum Pulse Width Summary ;
+----------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------+--------+---------------+
; clkin_50 ; -3.000 ; -19.357 ;
+----------+--------+---------------+
-------------------------
; Metastability Summary ;
-------------------------
No synchronizer chains to report.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; leds[0] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[1] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[2] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[3] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[4] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[5] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[6] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; leds[7] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[0] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[1] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[2] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[3] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[4] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[5] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_data[6] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_char1 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; seg7_char2 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+--------------------------------------------------------------------------+
; Input Transition Times ;
+--------------+-----------------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+-----------------------+-----------------+-----------------+
; pb[3] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; pb[0] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; pb[1] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; pb[2] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[7] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[6] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[2] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[3] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[5] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[4] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[0] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sw[1] ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; clkin_50 ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; ~ALTERA_TMS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
; ~ALTERA_TCK~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
; ~ALTERA_TDI~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
+--------------+-----------------------+-----------------+-----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; leds[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; leds[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; leds[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.08 V ; 2.3e-06 V ; 0.15 V ; 0.118 V ; 1.03e-08 s ; 1.07e-08 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.08 V ; 2.3e-06 V ; 0.15 V ; 0.118 V ; 1.03e-08 s ; 1.07e-08 s ; Yes ; Yes ;
; leds[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; leds[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; leds[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; leds[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; leds[7] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; seg7_data[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.08 V ; 2.3e-06 V ; 0.15 V ; 0.118 V ; 1.03e-08 s ; 1.07e-08 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.08 V ; 2.3e-06 V ; 0.15 V ; 0.118 V ; 1.03e-08 s ; 1.07e-08 s ; Yes ; Yes ;
; seg7_data[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; seg7_data[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; seg7_data[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; seg7_data[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; seg7_data[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; seg7_data[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; seg7_char1 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; seg7_char2 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ; 3.08 V ; 1.3e-06 V ; 3.15 V ; -0.0682 V ; 0.279 V ; 0.237 V ; 4.81e-10 s ; 6.4e-10 s ; Yes ; No ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clkin_50 ; clkin_50 ; 66 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clkin_50 ; clkin_50 ; 66 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 11 ; 11 ;
; Unconstrained Input Port Paths ; 100 ; 100 ;
; Unconstrained Output Ports ; 16 ; 16 ;
; Unconstrained Output Port Paths ; 109 ; 109 ;
+---------------------------------+-------+------+
+------------------------------------------+
; Clock Status Summary ;
+----------+----------+------+-------------+
; Target ; Clock ; Type ; Status ;
+----------+----------+------+-------------+
; clkin_50 ; clkin_50 ; Base ; Constrained ;
+----------+----------+------+-------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; pb[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pb[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pb[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; leds[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_char1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_char2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; pb[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pb[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; pb[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sw[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+--------------+---------------------------------------------------------------------------------------+
; leds[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; leds[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_char1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_char2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; seg7_data[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Tue Mar 06 18:43:57 2018
Info: Command: quartus_sta LogicalStep_Lab3 -c LogicalStep_Lab3_top
Info: qsta_default_script.tcl version: #3
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'LogicalStep_Lab3_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name clkin_50 clkin_50
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -1.638
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.638 -12.869 clkin_50
Info (332146): Worst-case hold slack is 0.379
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.379 0.000 clkin_50
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -3.000 -19.357 clkin_50
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 610 megabytes
Info: Processing ended: Tue Mar 06 18:43:59 2018
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02