optimization to speed up the execution

[ligang-github]

We just finished an optimized version of the iverilog: https://github.com/pytec8800/pint_iverilog
Instead of using the original vvp execution flow which is based on interpreter virtual machine, we compile simulation into the optimized event-based execution C codes. This will take some extra time to compile, while greatly speed up the simulation execution. For some design like video codec cores, it could run 20-100x faster in x86 cpu. Run time is also a few times faster than commercial simulator for many test cases based on our prior test records.

Please try it out and any suggestion is welcome! We continue to improve the performance.

[pytec8800]

The following is the performance test data for some cases:

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cases	icarus verilog(s)	pls_cpu(s)	cpu vs icarus
rv10_8224	809.88	8.50	95.28
vp6_1236	1066.06	8.40	126.91
rv8_8241	985.84	9.40	104.88
h263_2	536.25	3.16	169.70
sorenson_39	680.58	5.11	133.19
vc1_1538	730.53	4.67	156.43
h264_7173	1129.83	9.78	115.52
divx_6605	3059.13	26.90	113.72
mpeg4_3503	3552.36	36.10	98.40
avs_3537	5089.63	67.72	75.16
h264_10350	67839.14	4872.92	13.92
faa_tests_1k	364.49	7.42	49.12
test_pf_one_point	5686.31	78.73	72.23
mem_test_b_64K	7075.38	110.86	63.82
maxpool_2x2	68096.03	1581.14	43.07