DTACK Issue

[plowcat]

On the schematic DTACK is Pin 1 on the GAL where as in the PLD file its is Pin 23. Since it is an output it can't be on Pin 1.

I noticed this after assembling a board with 3 SRAM chips and testing in an ACE with a Sharp 1 MB expansion on the internal memory expansion header. I worked around the issue by cutting the link on the "1 MB" jumper and adding a wire between the middle pad of the jumper and Pin 1 of the GAL. I tested with a program found somewhere called "mtest.r" which passed.

I also felt that the GAL was getting warm from driving DTACK as push-pull rather than open drain so I added an open drain buffer. It is maybe less warm, but I don't have a way to measure well. It worked with and without the buffer so this may not be an issue. I think using the tri-state outputs on the GAL should be able get the same effect.

[rapiqui]

On the schematic DTACK is Pin 1 on the GAL where as in the PLD file its is Pin 23. Since it is an output it can't be on Pin 1.

I noticed this after assembling a board with 3 SRAM chips and testing in an ACE with a Sharp 1 MB expansion on the internal memory expansion header. I worked around the issue by cutting the link on the "1 MB" jumper and adding a wire between the middle pad of the jumper and Pin 1 of the GAL. I tested with a program found somewhere called "mtest.r" which passed.

I also felt that the GAL was getting warm from driving DTACK as push-pull rather than open drain so I added an open drain buffer. It is maybe less warm, but I don't have a way to measure well. It worked with and without the buffer so this may not be an issue. I think using the tri-state outputs on the GAL should be able get the same effect.

Hi,

I assume then there might be an error on the current GAL routing and that fix you applied would be required if using 4 SRAM chips?
As I mentioned on another issue I had no success with my built unit and I was blaming the GAL speed, but perhaps the problem is caused by this.

Thanks

[ArcadeKing]

Thanks for posting this fix.
Looking at the PLD via WinCUPL Pin 1 (DTACK) isn't fused to anything internally anyway so tying it to MSK or NDTACK as its called in the PLD shouldn't do any damage.
GAL's tend to run hot normally. I've had my Galspanic installed for 2 days and the GAL is warm to the touch.

[tdaede]

Driving DTACK push-pull is likely to prevent other expansion cards from working that are installed alongside the RAM expansion. (It seems that this is currently accidentally being avoided by the DTACK line not being driven at all).

[badass-boss]

Any updates on this issue? What is the final solution for this then? Anyone cares to update the design?

[carlosbragatto]

There is an "unofficial" fix by ArcadeKing (same guy as above) and the gerbers are available on Aussie Arcade, as well as his updated GAL file:

https://www.aussiearcade.com/topic/101533-sharp-x68000-repair/

I'd like to see the project back here in two ways:

1. the full kicad project so we could edit (I'd make larger "finger holes" to make it easier to pull the board from the slot)
2. I'd love to see the GAL being able to start the memory at 1MB rather than 2MB, which would be great for owners of the CZ-600, Ace and Pro machines not having to pay LOADS of money for the 1MB card required to expand the X68000 before using any slot-based RAM card.

[badass-boss]

I guess the original creator is no longer interested ¯_(ツ)_/¯ Shame

Also has anyone fully reverse engineered this design:
http://retropc.net/gimons/marsx/index.html

It uses a low power 8MB SRAM (AS6C6416 I think) with voltage translators which should be way more affordable if you want to go up by 8MB right away and this seems to make much more sense. What I want to change here is convert it to a standard removable card just like the card here in question

[carlosbragatto]

@badass-boss not sure if you seen a modern board like Edu Arana's Etarikashikoshi, which is an 8MB + MIDI all in one card, it has only a single RAM chip, and an Altera FPGA, so it might be even easier to make, but the code is of course, proprietary.

MarsX is a great idea as it doesn't use a slot, but it's not easily removable...

[stas2k]

1. the full kicad project so we could edit (I'd make larger "finger holes" to make it easier to pull the board from the slot)

Send changes as MR and I will merge.

2. I'd love to see the GAL being able to start the memory at 1MB rather than 2MB, which would be great for owners of the CZ-600, Ace and Pro machines not having to pay LOADS of money for the 1MB card required to expand the X68000 before using any slot-based RAM card.

This is also possible with a GAL bitstream change, but even easier is to design a separate RAM board to go into that specialized slot. It already provides all the right control signals to drive a DRAM chip. You just need to find one which can handle the 5V. If it has more RAM than needed, just ground the unused pins.

I have implemented the required changes to make the board behave correctly on DTACK, just need to spin some and test it out. Basically it needs a pinout change and a bitstream change.

[stas2k]

I guess the original creator is no longer interested ¯_(ツ)_/¯ Shame

I got what I wanted out of the project - learned 68000 interfacing, got started in programmable logic, and expanded RAM in my X68000. If someone is still fresh and willing to help, MRs are welcome.

I will fix the current issue, and do a production run of the boards, as I still have some spare SRAM chips left.

[badass-boss]

@badass-boss not sure if you seen a modern board like Edu Arana's Etarikashikoshi, which is an 8MB + MIDI all in one card, it has only a single RAM chip, and an Altera FPGA, so it might be even easier to make, but the code is of course, proprietary.

MarsX is a great idea as it doesn't use a slot, but it's not easily removable...

Yes but since this is github I'm interested in building one, not buying one

I'm more interested in reverse engineering that Marsx 8MB RAM card and as far as I can tell it should be easy to do because it is just a 8MB SRAM 3V chip so the signals need to be translated between 3V and 5V and then connected to X68000, that's it. Also what is the purpose of those PLD chips on both of these cards? Are they supposed to configure memory starting address? But why, I thought all expansion RAM cards are supposed to start from $200000?? In this instance there is no need to implement any programmable chip on board at all and it can be reduced to just 74 chips, all it needs is a NOR gate and XOR gate which can reduce costs even further and there is no need to go through the hassle of programming anything

Anyway good to hear there will be some official updates over here

[stas2k]

In this instance there is no need to implement any programmable chip on board at all and it can be reduced to just 74 chips,

You can do it with this SRAM-based setup, but not with the other, older boards. They all used DRAM, and require quite a bit of logic to refresh and multiplex data/address buses.