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hal-fengMichaelZhuxx
hal-feng
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MichaelZhuxx
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media/starfive: use clock and reset api
Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
1 parent 016794a commit 45d1740

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17 files changed

+630
-214
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17 files changed

+630
-214
lines changed

‎arch/riscv/boot/dts/starfive/jh7100-common.dtsi‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#include <dt-bindings/gpio/gpio.h>
1010
#include <dt-bindings/leds/common.h>
1111
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
12-
#include <dt-bindings/starfive_fb.h>
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1413
/ {
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aliases {

‎arch/riscv/boot/dts/starfive/jh7100.dtsi‎

Lines changed: 94 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,10 @@
88
#include "starfive_vic7100_clk.dtsi"
99
#include <dt-bindings/clock/starfive-jh7100.h>
1010
#include <dt-bindings/clock/starfive-jh7100-audio.h>
11+
#include <dt-bindings/clock/starfive-jh7100-isp.h>
1112
#include <dt-bindings/reset/starfive-jh7100.h>
1213
#include <dt-bindings/reset/starfive-jh7100-audio.h>
14+
#include <dt-bindings/reset/starfive-jh7100-isp.h>
1315
#include <dt-bindings/starfive_fb.h>
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/ {
@@ -397,6 +399,21 @@
397399
interrupts = <98>;
398400
};
399401

402+
ispclk: clock-controller@19810000 {
403+
compatible = "starfive,jh7100-ispclk";
404+
reg = <0x0 0x19810000 0x0 0x10000>;
405+
clocks = <&clkgen JH7100_CLK_VIN_SRC>,
406+
<&clkgen JH7100_CLK_ISPSLV_AXI>;
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clock-names = "vin_src", "ispslv_axi";
408+
#clock-cells = <1>;
409+
};
410+
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isprst: reset-controller@19820000 {
412+
compatible = "starfive,jh7100-isprst";
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reg = <0x0 0x19820000 0x0 0x10000>;
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#reset-cells = <1>;
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};
416+
400417
vin_sysctl: vin_sysctl@19800000 {
401418
compatible = "starfive,stf-vin";
402419
reg = <0x0 0x19800000 0x0 0x10000>,
@@ -421,56 +438,83 @@
421438
<&clkgen JH7100_CLK_ISP1_AXI>,
422439
<&clkgen JH7100_CLK_ISP1NOC_AXI>,
423440
<&clkgen JH7100_CLK_VIN_AXI>,
424-
<&clkgen JH7100_CLK_VINNOC_AXI>;
425-
// <&clkgen JH7100_CLK_CSI2RX_APB>,
426-
// <&clkgen JH7100_CLK_MIPI_RX0_PXL_0>,
427-
// <&clkgen JH7100_CLK_MIPI_RX0_PXL_1>,
428-
// <&clkgen JH7100_CLK_MIPI_RX0_PXL_2>,
429-
// <&clkgen JH7100_CLK_MIPI_RX0_PXL_3>,
430-
// <&clkgen JH7100_CLK_MIPI_RX0_SYS>,
431-
// <&clkgen JH7100_CLK_MIPI_RX1_PXL_0>,
432-
// <&clkgen JH7100_CLK_MIPI_RX1_PXL_1>,
433-
// <&clkgen JH7100_CLK_MIPI_RX1_PXL_2>,
434-
// <&clkgen JH7100_CLK_MIPI_RX1_PXL_3>,
435-
// <&clkgen JH7100_CLK_MIPI_RX1_SYS>,
436-
// <&clkgen JH7100_CLK_DPHY_CFGCLK>,
437-
// <&clkgen JH7100_CLK_DPHY_REFCLK>,
438-
// <&clkgen JH7100_CLK_DPHY_TXCLKESC>,
439-
// <&clkgen JH7100_CLK_ISP0_CTRL>,
440-
// <&clkgen JH7100_CLK_ISP0_2X_CTRL>,
441-
// <&clkgen JH7100_CLK_ISP0_MIPI_CTRL>,
442-
// <&clkgen JH7100_CLK_ISP1_CTRL>,
443-
// <&clkgen JH7100_CLK_ISP1_2X_CTRL>,
444-
// <&clkgen JH7100_CLK_ISP1_MIPI_CTRL>;
445-
446-
clock-names = "vin_src",
447-
"isp0_axi",
448-
"isp0noc_axi",
449-
"ispslv_axi",
450-
"isp1_axi",
451-
"isp1noc_axi",
452-
"vin_axi",
453-
"vinnoc_axi";
454-
// "csi2rx_apb_clk",
455-
// "mipirx0_pixel0",
456-
// "mipirx0_pixel1",
457-
// "mipirx0_pixel2",
458-
// "mipirx0_pixel3",
459-
// "mipirx0_sys",
460-
// "mipirx1_pixel0",
461-
// "mipirx1_pixel1",
462-
// "mipirx1_pixel2",
463-
// "mipirx1_pixel3",
464-
// "mipirx1_sys",
465-
// "csidphy_cfgclk",
466-
// "csidphy_regclk",
467-
// "csidphy_txclkesc",
468-
// "isp0_ctrl",
469-
// "isp0_2x_ctrl",
470-
// "isp0_mipi_ctrl",
471-
// "isp1_ctrl",
472-
// "isp1_2x_ctrl",
473-
// "isp1_mipi_ctrl";
441+
<&clkgen JH7100_CLK_VINNOC_AXI>,
442+
<&ispclk JH7100_ISPCLK_DPHY_CFGCLK>,
443+
<&ispclk JH7100_ISPCLK_DPHY_REFCLK>,
444+
<&ispclk JH7100_ISPCLK_DPHY_TXCLKESC>,
445+
<&ispclk JH7100_ISPCLK_MIPI_RX0_PXL>,
446+
<&ispclk JH7100_ISPCLK_MIPI_RX1_PXL>,
447+
<&ispclk JH7100_ISPCLK_MIPI_RX0_PXL_0>,
448+
<&ispclk JH7100_ISPCLK_MIPI_RX0_PXL_1>,
449+
<&ispclk JH7100_ISPCLK_MIPI_RX0_PXL_2>,
450+
<&ispclk JH7100_ISPCLK_MIPI_RX0_PXL_3>,
451+
<&ispclk JH7100_ISPCLK_MIPI_RX0_SYS>,
452+
<&ispclk JH7100_ISPCLK_MIPI_RX1_PXL_0>,
453+
<&ispclk JH7100_ISPCLK_MIPI_RX1_PXL_1>,
454+
<&ispclk JH7100_ISPCLK_MIPI_RX1_PXL_2>,
455+
<&ispclk JH7100_ISPCLK_MIPI_RX1_PXL_3>,
456+
<&ispclk JH7100_ISPCLK_MIPI_RX1_SYS>,
457+
<&ispclk JH7100_ISPCLK_ISP0>,
458+
<&ispclk JH7100_ISPCLK_ISP0_2X>,
459+
<&ispclk JH7100_ISPCLK_ISP0_MIPI>,
460+
<&ispclk JH7100_ISPCLK_ISP1>,
461+
<&ispclk JH7100_ISPCLK_ISP1_2X>,
462+
<&ispclk JH7100_ISPCLK_ISP1_MIPI>,
463+
<&ispclk JH7100_ISPCLK_DOM4_APB>,
464+
<&ispclk JH7100_ISPCLK_CSI2RX_APB>,
465+
<&ispclk JH7100_ISPCLK_VIN_AXI_WR>,
466+
<&ispclk JH7100_ISPCLK_VIN_AXI_RD>,
467+
<&ispclk JH7100_ISPCLK_C_ISP0>,
468+
<&ispclk JH7100_ISPCLK_C_ISP1>;
469+
470+
clock-names = "vin_src", "isp0_axi", "isp0noc_axi", "ispslv_axi",
471+
"isp1_axi", "isp1noc_axi", "vin_axi", "vinnoc_axi",
472+
"dphy_cfgclk", "dphy_refclk", "dphy_txclkesc", "mipi_rx0_pxl",
473+
"mipi_rx1_pxl", "mipi_rx0_pxl_0", "mipi_rx0_pxl_1", "mipi_rx0_pxl_2",
474+
"mipi_rx0_pxl_3", "mipi_rx0_sys", "mipi_rx1_pxl_0", "mipi_rx1_pxl_1",
475+
"mipi_rx1_pxl_2", "mipi_rx1_pxl_3", "mipi_rx1_sys", "isp0",
476+
"isp0_2x", "isp0_mipi", "isp1", "isp1_2x",
477+
"isp1_mipi", "dom4_apb", "csi2rx_apb", "vin_axi_wr",
478+
"vin_axi_rd", "c_isp0", "c_isp1";
479+
480+
resets = <&rstgen JH7100_RSTN_VIN_SRC>,
481+
<&rstgen JH7100_RSTN_ISPSLV_AXI>,
482+
<&rstgen JH7100_RSTN_VIN_AXI>,
483+
<&rstgen JH7100_RSTN_VINNOC_AXI>,
484+
<&rstgen JH7100_RSTN_ISP0_AXI>,
485+
<&rstgen JH7100_RSTN_ISP0NOC_AXI>,
486+
<&rstgen JH7100_RSTN_ISP1_AXI>,
487+
<&rstgen JH7100_RSTN_ISP1NOC_AXI>,
488+
<&isprst JH7100_ISPRSTN_SYS_CLK>,
489+
<&isprst JH7100_ISPRSTN_PCLK>,
490+
<&isprst JH7100_ISPRSTN_SYS_CLK_1>,
491+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF0>,
492+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF1>,
493+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF2>,
494+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF3>,
495+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF10>,
496+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF11>,
497+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF12>,
498+
<&isprst JH7100_ISPRSTN_PIXEL_CLK_IF13>,
499+
<&isprst JH7100_ISPRST_ISP_0>,
500+
<&isprst JH7100_ISPRST_ISP_1>,
501+
<&isprst JH7100_ISPRST_P_AXIRD>,
502+
<&isprst JH7100_ISPRST_P_AXIWR>,
503+
<&isprst JH7100_ISPRST_P_ISP0>,
504+
<&isprst JH7100_ISPRST_P_ISP1>,
505+
<&isprst JH7100_ISPRST_DPHY_HW_RSTN>,
506+
<&isprst JH7100_ISPRST_DPHY_RST09_ALWY_ON>,
507+
<&isprst JH7100_ISPRST_C_ISP0>,
508+
<&isprst JH7100_ISPRST_C_ISP1>;
509+
510+
reset-names = "vin_src", "ispslv_axi", "vin_axi", "vinnoc_axi",
511+
"isp0_axi", "isp0noc_axi", "isp1_axi", "isp1noc_axi",
512+
"sys_clk", "pclk", "sys_clk_1", "pixel_clk_if0",
513+
"pixel_clk_if1", "pixel_clk_if2", "pixel_clk_if3", "pixel_clk_if10",
514+
"pixel_clk_if11", "pixel_clk_if12", "pixel_clk_if13", "isp_0",
515+
"isp_1", "p_axird", "p_axiwr", "p_isp0",
516+
"p_isp1", "dphy_hw_rstn", "dphy_rst09_alwy_on", "c_isp0",
517+
"c_isp1";
474518

475519
ports {
476520
#address-cells = <1>;

‎arch/riscv/boot/dts/starfive/starfive_vic7100_clk.dtsi‎

Lines changed: 0 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -1,33 +1,4 @@
11
/ {
2-
hfclk: hfclk {
3-
#clock-cells = <0>;
4-
compatible = "fixed-clock";
5-
clock-frequency = <25000000>;
6-
clock-output-names = "hfclk";
7-
};
8-
rtcclk: rtcclk {
9-
#clock-cells = <0>;
10-
compatible = "fixed-clock";
11-
clock-frequency = <6250000>;
12-
clock-output-names = "rtcclk";
13-
};
14-
axiclk: axiclk {
15-
#clock-cells = <0>;
16-
compatible = "fixed-clock";
17-
clock-frequency = <500000000>;
18-
clock-output-names = "axiclk";
19-
};
20-
21-
ahb0clk: ahb0clk {
22-
#clock-cells = <0>;
23-
compatible = "fixed-clock";
24-
clock-frequency = <250000000>;
25-
};
26-
ahb2clk: ahb2clk {
27-
#clock-cells = <0>;
28-
compatible = "fixed-clock";
29-
clock-frequency = <125000000>;
30-
};
312
apb1clk: apb1clk {
323
#clock-cells = <0>;
334
compatible = "fixed-clock";
@@ -38,63 +9,11 @@
389
compatible = "fixed-clock";
3910
clock-frequency = <125000000>;
4011
};
41-
jpuclk: jpuclk {
42-
#clock-cells = <0>;
43-
compatible = "fixed-clock";
44-
clock-frequency = <333333333>;
45-
};
46-
vpuclk: vpuclk {
47-
#clock-cells = <0>;
48-
compatible = "fixed-clock";
49-
clock-frequency = <400000000>;
50-
};
51-
gmacclk: gmacclk {
52-
#clock-cells = <0>;
53-
compatible = "fixed-clock";
54-
clock-frequency = <25000000>;
55-
};
56-
qspi_clk: qspi-clk@0 {
57-
#clock-cells = <0>;
58-
compatible = "fixed-clock";
59-
clock-frequency = <50000000>;
60-
};
6112
uartclk: uartclk {
6213
#clock-cells = <0>;
6314
compatible = "fixed-clock";
6415
clock-frequency = <100000000>;
6516
};
66-
hs_uartclk: hs_uartclk {
67-
#clock-cells = <0>;
68-
compatible = "fixed-clock";
69-
clock-frequency = <74250000>;
70-
};
71-
dwmmc_biuclk: dwmmc_biuclk {
72-
#clock-cells = <0>;
73-
compatible = "fixed-clock";
74-
clock-frequency = <100000000>;
75-
};
76-
/*
77-
dwmmc_ciuclk: dwmmc_ciuclk {
78-
#clock-cells = <0>;
79-
compatible = "fixed-clock";
80-
clock-frequency = <100000000>;
81-
};
82-
*/
83-
pwmclk: pwmclk {
84-
#clock-cells = <0>;
85-
compatible = "fixed-clock";
86-
clock-frequency = <125000000>;
87-
};
88-
spiclk: spiclk {
89-
#clock-cells = <0>;
90-
compatible = "fixed-clock";
91-
clock-frequency = <50000000>;
92-
};
93-
audioclk: audioclk {
94-
#clock-cells = <0>;
95-
compatible = "fixed-clock";
96-
clock-frequency = <12288000>;
97-
};
9817
clk_ext_camera: clk-ext-camera {
9918
#clock-cells = <0>;
10019
compatible = "fixed-clock";

‎drivers/clk/starfive/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -14,3 +14,10 @@ config CLK_STARFIVE_JH7100_AUDIO
1414
default SOC_STARFIVE
1515
help
1616
Say yes here to support the audio clocks on the StarFive JH7100 SoC.
17+
18+
config CLK_STARFIVE_JH7100_ISP
19+
tristate "StarFive JH7100 isp clock support"
20+
depends on CLK_STARFIVE_JH7100
21+
default SOC_STARFIVE
22+
help
23+
Say yes here to support the isp clocks on the StarFive JH7100 SoC.

‎drivers/clk/starfive/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -2,3 +2,4 @@
22
# StarFive Clock
33
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
44
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
5+
obj-$(CONFIG_CLK_STARFIVE_JH7100_ISP) += clk-starfive-jh7100-isp.o

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