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wm8350-regulator.c
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/*
* wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood
* linux@wolfsonmicro.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
/* Microamps */
static const int isink_cur[] = {
4,
5,
6,
7,
8,
10,
11,
14,
16,
19,
23,
27,
32,
39,
46,
54,
65,
77,
92,
109,
130,
154,
183,
218,
259,
308,
367,
436,
518,
616,
733,
872,
1037,
1233,
1466,
1744,
2073,
2466,
2933,
3487,
4147,
4932,
5865,
6975,
8294,
9864,
11730,
13949,
16589,
19728,
23460,
27899,
33178,
39455,
46920,
55798,
66355,
78910,
93840,
111596,
132710,
157820,
187681,
223191
};
static int get_isink_val(int min_uA, int max_uA, u16 *setting)
{
int i;
for (i = ARRAY_SIZE(isink_cur) - 1; i >= 0; i--) {
if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
*setting = i;
return 0;
}
}
return -EINVAL;
}
static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
{
if (val < 16)
return (val * 50) + 900;
else
return ((val - 16) * 100) + 1800;
}
static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
{
if (mV < 1800)
return (mV - 900) / 50;
else
return ((mV - 1800) / 100) + 16;
}
static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
{
return (val * 25) + 850;
}
static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
{
return (mV - 850) / 25;
}
static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
int max_uA)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int isink = rdev_get_id(rdev);
u16 val, setting;
int ret;
ret = get_isink_val(min_uA, max_uA, &setting);
if (ret != 0)
return ret;
switch (isink) {
case WM8350_ISINK_A:
val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
~WM8350_CS1_ISEL_MASK;
wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
val | setting);
break;
case WM8350_ISINK_B:
val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
~WM8350_CS1_ISEL_MASK;
wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
val | setting);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_isink_get_current(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int isink = rdev_get_id(rdev);
u16 val;
switch (isink) {
case WM8350_ISINK_A:
val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
WM8350_CS1_ISEL_MASK;
break;
case WM8350_ISINK_B:
val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
WM8350_CS1_ISEL_MASK;
break;
default:
return 0;
}
return (isink_cur[val] + 50) / 100;
}
/* turn on ISINK followed by DCDC */
static int wm8350_isink_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int isink = rdev_get_id(rdev);
switch (isink) {
case WM8350_ISINK_A:
switch (wm8350->pmic.isink_A_dcdc) {
case WM8350_DCDC_2:
case WM8350_DCDC_5:
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
WM8350_CS1_ENA);
wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
WM8350_CS1_DRIVE);
wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
1 << (wm8350->pmic.isink_A_dcdc -
WM8350_DCDC_1));
break;
default:
return -EINVAL;
}
break;
case WM8350_ISINK_B:
switch (wm8350->pmic.isink_B_dcdc) {
case WM8350_DCDC_2:
case WM8350_DCDC_5:
wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
WM8350_CS2_ENA);
wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
WM8350_CS2_DRIVE);
wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
1 << (wm8350->pmic.isink_B_dcdc -
WM8350_DCDC_1));
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_isink_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int isink = rdev_get_id(rdev);
switch (isink) {
case WM8350_ISINK_A:
switch (wm8350->pmic.isink_A_dcdc) {
case WM8350_DCDC_2:
case WM8350_DCDC_5:
wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
1 << (wm8350->pmic.isink_A_dcdc -
WM8350_DCDC_1));
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
WM8350_CS1_ENA);
break;
default:
return -EINVAL;
}
break;
case WM8350_ISINK_B:
switch (wm8350->pmic.isink_B_dcdc) {
case WM8350_DCDC_2:
case WM8350_DCDC_5:
wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
1 << (wm8350->pmic.isink_B_dcdc -
WM8350_DCDC_1));
wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
WM8350_CS2_ENA);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int isink = rdev_get_id(rdev);
switch (isink) {
case WM8350_ISINK_A:
return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
0x8000;
case WM8350_ISINK_B:
return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
0x8000;
}
return -EINVAL;
}
int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
u16 drive)
{
switch (isink) {
case WM8350_ISINK_A:
wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
(mode ? WM8350_CS1_FLASH_MODE : 0) |
(trigger ? WM8350_CS1_TRIGSRC : 0) |
duration | on_ramp | off_ramp | drive);
break;
case WM8350_ISINK_B:
wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
(mode ? WM8350_CS2_FLASH_MODE : 0) |
(trigger ? WM8350_CS2_TRIGSRC : 0) |
duration | on_ramp | off_ramp | drive);
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
int max_uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, dcdc = rdev_get_id(rdev), mV,
min_mV = min_uV / 1000, max_mV = max_uV / 1000;
u16 val;
if (min_mV < 850 || min_mV > 4025)
return -EINVAL;
if (max_mV < 850 || max_mV > 4025)
return -EINVAL;
/* step size is 25mV */
mV = (min_mV - 826) / 25;
if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_CONTROL;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_CONTROL;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_CONTROL;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_CONTROL;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg, val | mV);
return 0;
}
static int wm8350_dcdc_get_voltage(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_CONTROL;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_CONTROL;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_CONTROL;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_CONTROL;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK;
return wm8350_dcdc_val_to_mvolts(val) * 1000;
}
static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
u16 val;
dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
if (mV && (mV < 850 || mV > 4025)) {
dev_err(wm8350->dev,
"DCDC%d suspend voltage %d mV out of range\n",
dcdc, mV);
return -EINVAL;
}
if (mV == 0)
mV = 850;
switch (dcdc) {
case WM8350_DCDC_1:
volt_reg = WM8350_DCDC1_LOW_POWER;
break;
case WM8350_DCDC_3:
volt_reg = WM8350_DCDC3_LOW_POWER;
break;
case WM8350_DCDC_4:
volt_reg = WM8350_DCDC4_LOW_POWER;
break;
case WM8350_DCDC_6:
volt_reg = WM8350_DCDC6_LOW_POWER;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
/* all DCDCs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg,
val | wm8350_dcdc_mvolts_to_val(mV));
return 0;
}
static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_1:
val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
wm8350->pmic.dcdc1_hib_mode);
break;
case WM8350_DCDC_3:
val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
wm8350->pmic.dcdc3_hib_mode);
break;
case WM8350_DCDC_4:
val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
wm8350->pmic.dcdc4_hib_mode);
break;
case WM8350_DCDC_6:
val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
& ~WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
wm8350->pmic.dcdc6_hib_mode);
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
return 0;
}
static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_1:
val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
WM8350_DCDC_HIB_MODE_DIS);
break;
case WM8350_DCDC_3:
val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
WM8350_DCDC_HIB_MODE_DIS);
break;
case WM8350_DCDC_4:
val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
WM8350_DCDC_HIB_MODE_DIS);
break;
case WM8350_DCDC_6:
val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
WM8350_DCDC_HIB_MODE_DIS);
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
return 0;
}
static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_2:
val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
& ~WM8350_DC2_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
WM8350_DC2_HIB_MODE_ACTIVE);
break;
case WM8350_DCDC_5:
val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
& ~WM8350_DC2_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
WM8350_DC5_HIB_MODE_ACTIVE);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
switch (dcdc) {
case WM8350_DCDC_2:
val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
& ~WM8350_DC2_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
WM8350_DC2_HIB_MODE_DISABLE);
break;
case WM8350_DCDC_5:
val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
& ~WM8350_DC2_HIB_MODE_MASK;
wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
WM8350_DC2_HIB_MODE_DISABLE);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
unsigned int mode)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 *hib_mode;
switch (dcdc) {
case WM8350_DCDC_1:
hib_mode = &wm8350->pmic.dcdc1_hib_mode;
break;
case WM8350_DCDC_3:
hib_mode = &wm8350->pmic.dcdc3_hib_mode;
break;
case WM8350_DCDC_4:
hib_mode = &wm8350->pmic.dcdc4_hib_mode;
break;
case WM8350_DCDC_6:
hib_mode = &wm8350->pmic.dcdc6_hib_mode;
break;
case WM8350_DCDC_2:
case WM8350_DCDC_5:
default:
return -EINVAL;
}
switch (mode) {
case REGULATOR_MODE_NORMAL:
*hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
break;
case REGULATOR_MODE_IDLE:
*hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
break;
case REGULATOR_MODE_STANDBY:
*hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
u16 val;
dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
if (mV < 900 || mV > 3300) {
dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
ldo, mV);
return -EINVAL;
}
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_LOW_POWER;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_LOW_POWER;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_LOW_POWER;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_LOW_POWER;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg,
val | wm8350_ldo_mvolts_to_val(mV));
return 0;
}
static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, ldo = rdev_get_id(rdev);
u16 val;
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_LOW_POWER;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_LOW_POWER;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_LOW_POWER;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_LOW_POWER;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
wm8350_reg_write(wm8350, volt_reg, val);
return 0;
}
static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, ldo = rdev_get_id(rdev);
u16 val;
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_LOW_POWER;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_LOW_POWER;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_LOW_POWER;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_LOW_POWER;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
wm8350_reg_write(wm8350, volt_reg, WM8350_LDO1_HIB_MODE_DIS);
return 0;
}
static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
int max_uV)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
max_mV = max_uV / 1000;
u16 val;
if (min_mV < 900 || min_mV > 3300)
return -EINVAL;
if (max_mV < 900 || max_mV > 3300)
return -EINVAL;
if (min_mV < 1800) {
/* step size is 50mV < 1800mV */
mV = (min_mV - 851) / 50;
if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
} else {
/* step size is 100mV > 1800mV */
mV = ((min_mV - 1701) / 100) + 16;
if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
return -EINVAL;
BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
}
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_CONTROL;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_CONTROL;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_CONTROL;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_CONTROL;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
wm8350_reg_write(wm8350, volt_reg, val | mV);
return 0;
}
static int wm8350_ldo_get_voltage(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int volt_reg, ldo = rdev_get_id(rdev);
u16 val;
switch (ldo) {
case WM8350_LDO_1:
volt_reg = WM8350_LDO1_CONTROL;
break;
case WM8350_LDO_2:
volt_reg = WM8350_LDO2_CONTROL;
break;
case WM8350_LDO_3:
volt_reg = WM8350_LDO3_CONTROL;
break;
case WM8350_LDO_4:
volt_reg = WM8350_LDO4_CONTROL;
break;
default:
return -EINVAL;
}
/* all LDOs have same mV bits */
val = wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK;
return wm8350_ldo_val_to_mvolts(val) * 1000;
}
int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
u16 stop, u16 fault)
{
int slot_reg;
u16 val;
dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
__func__, dcdc, start, stop);
/* slot valid ? */
if (start > 15 || stop > 15)
return -EINVAL;
switch (dcdc) {
case WM8350_DCDC_1:
slot_reg = WM8350_DCDC1_TIMEOUTS;
break;
case WM8350_DCDC_2:
slot_reg = WM8350_DCDC2_TIMEOUTS;
break;
case WM8350_DCDC_3:
slot_reg = WM8350_DCDC3_TIMEOUTS;
break;
case WM8350_DCDC_4:
slot_reg = WM8350_DCDC4_TIMEOUTS;
break;
case WM8350_DCDC_5:
slot_reg = WM8350_DCDC5_TIMEOUTS;
break;
case WM8350_DCDC_6:
slot_reg = WM8350_DCDC6_TIMEOUTS;
break;
default:
return -EINVAL;
}
val = wm8350_reg_read(wm8350, slot_reg) &
~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
WM8350_DC1_ERRACT_MASK);
wm8350_reg_write(wm8350, slot_reg,
val | (start << WM8350_DC1_ENSLOT_SHIFT) |
(stop << WM8350_DC1_SDSLOT_SHIFT) |
(fault << WM8350_DC1_ERRACT_SHIFT));
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
{
int slot_reg;
u16 val;
dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
__func__, ldo, start, stop);
/* slot valid ? */
if (start > 15 || stop > 15)
return -EINVAL;
switch (ldo) {
case WM8350_LDO_1:
slot_reg = WM8350_LDO1_TIMEOUTS;
break;
case WM8350_LDO_2:
slot_reg = WM8350_LDO2_TIMEOUTS;
break;
case WM8350_LDO_3:
slot_reg = WM8350_LDO3_TIMEOUTS;
break;
case WM8350_LDO_4:
slot_reg = WM8350_LDO4_TIMEOUTS;
break;
default:
return -EINVAL;
}
val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
u16 ilim, u16 ramp, u16 feedback)
{
u16 val;
dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
mode ? "normal" : "boost", ilim ? "low" : "normal");
switch (dcdc) {
case WM8350_DCDC_2:
val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
& ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
(mode << WM8350_DC2_MODE_SHIFT) |
(ilim << WM8350_DC2_ILIM_SHIFT) |
(ramp << WM8350_DC2_RMP_SHIFT) |
(feedback << WM8350_DC2_FBSRC_SHIFT));
break;
case WM8350_DCDC_5:
val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
& ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
(mode << WM8350_DC5_MODE_SHIFT) |
(ilim << WM8350_DC5_ILIM_SHIFT) |
(ramp << WM8350_DC5_RMP_SHIFT) |
(feedback << WM8350_DC5_FBSRC_SHIFT));
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
static int wm8350_dcdc_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 shift;
if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
return -EINVAL;
shift = dcdc - WM8350_DCDC_1;
wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
return 0;
}
static int wm8350_dcdc_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 shift;
if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
return -EINVAL;
shift = dcdc - WM8350_DCDC_1;
wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
return 0;
}
static int wm8350_ldo_enable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int ldo = rdev_get_id(rdev);
u16 shift;
if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
return -EINVAL;
shift = (ldo - WM8350_LDO_1) + 8;
wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
return 0;
}
static int wm8350_ldo_disable(struct regulator_dev *rdev)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int ldo = rdev_get_id(rdev);
u16 shift;
if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
return -EINVAL;
shift = (ldo - WM8350_LDO_1) + 8;
wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
return 0;
}
static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
{
int reg = 0, ret;
switch (dcdc) {
case WM8350_DCDC_1:
reg = WM8350_DCDC1_FORCE_PWM;
break;
case WM8350_DCDC_3:
reg = WM8350_DCDC3_FORCE_PWM;
break;
case WM8350_DCDC_4:
reg = WM8350_DCDC4_FORCE_PWM;
break;
case WM8350_DCDC_6:
reg = WM8350_DCDC6_FORCE_PWM;
break;
default:
return -EINVAL;
}
if (enable)
ret = wm8350_set_bits(wm8350, reg,
WM8350_DCDC1_FORCE_PWM_ENA);
else
ret = wm8350_clear_bits(wm8350, reg,
WM8350_DCDC1_FORCE_PWM_ENA);
return ret;
}
static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
{
struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
int dcdc = rdev_get_id(rdev);
u16 val;
if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
return -EINVAL;
if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
return -EINVAL;
val = 1 << (dcdc - WM8350_DCDC_1);
switch (mode) {
case REGULATOR_MODE_FAST: