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PPC: dbdma: Move defines into header file
We usually keep struct and constant definitions in header files. Move them there to stay consistent and to make access to fields easier. Signed-off-by: Alexander Graf <agraf@suse.de>
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+118
-117
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‎hw/misc/macio/mac_dbdma.c

-117
Original file line numberDiff line numberDiff line change
@@ -54,123 +54,6 @@
5454
/*
5555
*/
5656

57-
/*
58-
* DBDMA control/status registers. All little-endian.
59-
*/
60-
61-
#define DBDMA_CONTROL 0x00
62-
#define DBDMA_STATUS 0x01
63-
#define DBDMA_CMDPTR_HI 0x02
64-
#define DBDMA_CMDPTR_LO 0x03
65-
#define DBDMA_INTR_SEL 0x04
66-
#define DBDMA_BRANCH_SEL 0x05
67-
#define DBDMA_WAIT_SEL 0x06
68-
#define DBDMA_XFER_MODE 0x07
69-
#define DBDMA_DATA2PTR_HI 0x08
70-
#define DBDMA_DATA2PTR_LO 0x09
71-
#define DBDMA_RES1 0x0A
72-
#define DBDMA_ADDRESS_HI 0x0B
73-
#define DBDMA_BRANCH_ADDR_HI 0x0C
74-
#define DBDMA_RES2 0x0D
75-
#define DBDMA_RES3 0x0E
76-
#define DBDMA_RES4 0x0F
77-
78-
#define DBDMA_REGS 16
79-
#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
80-
81-
#define DBDMA_CHANNEL_SHIFT 7
82-
#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
83-
84-
#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
85-
86-
/* Bits in control and status registers */
87-
88-
#define RUN 0x8000
89-
#define PAUSE 0x4000
90-
#define FLUSH 0x2000
91-
#define WAKE 0x1000
92-
#define DEAD 0x0800
93-
#define ACTIVE 0x0400
94-
#define BT 0x0100
95-
#define DEVSTAT 0x00ff
96-
97-
/*
98-
* DBDMA command structure. These fields are all little-endian!
99-
*/
100-
101-
typedef struct dbdma_cmd {
102-
uint16_t req_count; /* requested byte transfer count */
103-
uint16_t command; /* command word (has bit-fields) */
104-
uint32_t phy_addr; /* physical data address */
105-
uint32_t cmd_dep; /* command-dependent field */
106-
uint16_t res_count; /* residual count after completion */
107-
uint16_t xfer_status; /* transfer status */
108-
} dbdma_cmd;
109-
110-
/* DBDMA command values in command field */
111-
112-
#define COMMAND_MASK 0xf000
113-
#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
114-
#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
115-
#define INPUT_MORE 0x2000 /* transfer stream data to memory */
116-
#define INPUT_LAST 0x3000 /* ditto, expect end marker */
117-
#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
118-
#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
119-
#define DBDMA_NOP 0x6000 /* do nothing */
120-
#define DBDMA_STOP 0x7000 /* suspend processing */
121-
122-
/* Key values in command field */
123-
124-
#define KEY_MASK 0x0700
125-
#define KEY_STREAM0 0x0000 /* usual data stream */
126-
#define KEY_STREAM1 0x0100 /* control/status stream */
127-
#define KEY_STREAM2 0x0200 /* device-dependent stream */
128-
#define KEY_STREAM3 0x0300 /* device-dependent stream */
129-
#define KEY_STREAM4 0x0400 /* reserved */
130-
#define KEY_REGS 0x0500 /* device register space */
131-
#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
132-
#define KEY_DEVICE 0x0700 /* device memory-mapped space */
133-
134-
/* Interrupt control values in command field */
135-
136-
#define INTR_MASK 0x0030
137-
#define INTR_NEVER 0x0000 /* don't interrupt */
138-
#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
139-
#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
140-
#define INTR_ALWAYS 0x0030 /* always interrupt */
141-
142-
/* Branch control values in command field */
143-
144-
#define BR_MASK 0x000c
145-
#define BR_NEVER 0x0000 /* don't branch */
146-
#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
147-
#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
148-
#define BR_ALWAYS 0x000c /* always branch */
149-
150-
/* Wait control values in command field */
151-
152-
#define WAIT_MASK 0x0003
153-
#define WAIT_NEVER 0x0000 /* don't wait */
154-
#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
155-
#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
156-
#define WAIT_ALWAYS 0x0003 /* always wait */
157-
158-
typedef struct DBDMA_channel {
159-
int channel;
160-
uint32_t regs[DBDMA_REGS];
161-
qemu_irq irq;
162-
DBDMA_io io;
163-
DBDMA_rw rw;
164-
DBDMA_flush flush;
165-
dbdma_cmd current;
166-
int processing;
167-
} DBDMA_channel;
168-
169-
typedef struct {
170-
MemoryRegion mem;
171-
DBDMA_channel channels[DBDMA_CHANNELS];
172-
} DBDMAState;
173-
17457
#ifdef DEBUG_DBDMA
17558
static void dump_dbdma_cmd(dbdma_cmd *cmd)
17659
{

‎include/hw/ppc/mac_dbdma.h

+118
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,124 @@ struct DBDMA_io {
3939
DBDMA_end dma_end;
4040
};
4141

42+
/*
43+
* DBDMA control/status registers. All little-endian.
44+
*/
45+
46+
#define DBDMA_CONTROL 0x00
47+
#define DBDMA_STATUS 0x01
48+
#define DBDMA_CMDPTR_HI 0x02
49+
#define DBDMA_CMDPTR_LO 0x03
50+
#define DBDMA_INTR_SEL 0x04
51+
#define DBDMA_BRANCH_SEL 0x05
52+
#define DBDMA_WAIT_SEL 0x06
53+
#define DBDMA_XFER_MODE 0x07
54+
#define DBDMA_DATA2PTR_HI 0x08
55+
#define DBDMA_DATA2PTR_LO 0x09
56+
#define DBDMA_RES1 0x0A
57+
#define DBDMA_ADDRESS_HI 0x0B
58+
#define DBDMA_BRANCH_ADDR_HI 0x0C
59+
#define DBDMA_RES2 0x0D
60+
#define DBDMA_RES3 0x0E
61+
#define DBDMA_RES4 0x0F
62+
63+
#define DBDMA_REGS 16
64+
#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
65+
66+
#define DBDMA_CHANNEL_SHIFT 7
67+
#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
68+
69+
#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
70+
71+
/* Bits in control and status registers */
72+
73+
#define RUN 0x8000
74+
#define PAUSE 0x4000
75+
#define FLUSH 0x2000
76+
#define WAKE 0x1000
77+
#define DEAD 0x0800
78+
#define ACTIVE 0x0400
79+
#define BT 0x0100
80+
#define DEVSTAT 0x00ff
81+
82+
/*
83+
* DBDMA command structure. These fields are all little-endian!
84+
*/
85+
86+
typedef struct dbdma_cmd {
87+
uint16_t req_count; /* requested byte transfer count */
88+
uint16_t command; /* command word (has bit-fields) */
89+
uint32_t phy_addr; /* physical data address */
90+
uint32_t cmd_dep; /* command-dependent field */
91+
uint16_t res_count; /* residual count after completion */
92+
uint16_t xfer_status; /* transfer status */
93+
} dbdma_cmd;
94+
95+
/* DBDMA command values in command field */
96+
97+
#define COMMAND_MASK 0xf000
98+
#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
99+
#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
100+
#define INPUT_MORE 0x2000 /* transfer stream data to memory */
101+
#define INPUT_LAST 0x3000 /* ditto, expect end marker */
102+
#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
103+
#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
104+
#define DBDMA_NOP 0x6000 /* do nothing */
105+
#define DBDMA_STOP 0x7000 /* suspend processing */
106+
107+
/* Key values in command field */
108+
109+
#define KEY_MASK 0x0700
110+
#define KEY_STREAM0 0x0000 /* usual data stream */
111+
#define KEY_STREAM1 0x0100 /* control/status stream */
112+
#define KEY_STREAM2 0x0200 /* device-dependent stream */
113+
#define KEY_STREAM3 0x0300 /* device-dependent stream */
114+
#define KEY_STREAM4 0x0400 /* reserved */
115+
#define KEY_REGS 0x0500 /* device register space */
116+
#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
117+
#define KEY_DEVICE 0x0700 /* device memory-mapped space */
118+
119+
/* Interrupt control values in command field */
120+
121+
#define INTR_MASK 0x0030
122+
#define INTR_NEVER 0x0000 /* don't interrupt */
123+
#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
124+
#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
125+
#define INTR_ALWAYS 0x0030 /* always interrupt */
126+
127+
/* Branch control values in command field */
128+
129+
#define BR_MASK 0x000c
130+
#define BR_NEVER 0x0000 /* don't branch */
131+
#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
132+
#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
133+
#define BR_ALWAYS 0x000c /* always branch */
134+
135+
/* Wait control values in command field */
136+
137+
#define WAIT_MASK 0x0003
138+
#define WAIT_NEVER 0x0000 /* don't wait */
139+
#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
140+
#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
141+
#define WAIT_ALWAYS 0x0003 /* always wait */
142+
143+
typedef struct DBDMA_channel {
144+
int channel;
145+
uint32_t regs[DBDMA_REGS];
146+
qemu_irq irq;
147+
DBDMA_io io;
148+
DBDMA_rw rw;
149+
DBDMA_flush flush;
150+
dbdma_cmd current;
151+
int processing;
152+
} DBDMA_channel;
153+
154+
typedef struct {
155+
MemoryRegion mem;
156+
DBDMA_channel channels[DBDMA_CHANNELS];
157+
} DBDMAState;
158+
159+
/* Externally callable functions */
42160

43161
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
44162
DBDMA_rw rw, DBDMA_flush flush,

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