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@taichi-ishitani

Taichi Ishitani

taichi-ishitani
Kanagawa, Japan

I'm developing OSS for digital circuit engineers. My works are listed below.

  • RgGen
    • Code generation tool for CSR (Configuration and Status Register)
  • TNoC
    • NoC (Network on Chip) implementation written in SystemVerilog
  • tvip-axi
    • UVM based AMBA AXI4 VIP
  • tvip-apb
    • UVM based AMBA APB VIP

Featured work

  1. rggen/rggen

    Code generation tool for control and status registers

    Ruby 329
  2. rggen/rggen-core

    RgGen Core Library

    Ruby 3
  3. rggen/rggen-plugin-template

    Project template for RgGen plugin

    Ruby 3
  4. taichi-ishitani/tnoc

    Network on Chip Implementation written in SytemVerilog

    SystemVerilog 157
  5. SystemVerilog 362
  6. taichi-ishitani/tue

    Useful UVM extensions

    SystemVerilog 20

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Thank you ! I will enjoy a cup of coffee at coding ☕️