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Merge remote-tracking branch 'adafruit/3.x' into merge_3x
2 parents 0015db1 + af7a0ee commit e527495

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2 files changed

+21
-8
lines changed

2 files changed

+21
-8
lines changed

ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -385,15 +385,15 @@
385385

386386
// <i> Select the clock source for DAC.
387387
#ifndef CONF_GCLK_DAC_SRC
388-
#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK1_Val
388+
#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
389389
#endif
390390

391391
/**
392392
* \def CONF_GCLK_DAC_FREQUENCY
393393
* \brief DAC's Clock frequency
394394
*/
395395
#ifndef CONF_GCLK_DAC_FREQUENCY
396-
#define CONF_GCLK_DAC_FREQUENCY 320000
396+
#define CONF_GCLK_DAC_FREQUENCY 48000000
397397
#endif
398398

399399
// <y> USB Clock Source

ports/atmel-samd/common-hal/audioio/AudioOut.c

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -110,13 +110,14 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
110110
_pm_enable_bus_clock(PM_BUS_APBC, DAC);
111111
#endif
112112

113-
// SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3.
114-
// SAMD51: This clock should be <= 350kHz, per datasheet table 37-6.
113+
// SAMD51: This clock should be <= 12 MHz, per datasheet section 47.6.3.
114+
// SAMD21: This clock is 48mhz despite the datasheet saying it must only be <= 350kHz, per
115+
// datasheet table 37-6. It's incorrect because the max output rate is 350ksps and is only
116+
// achieved when the GCLK is more than 8mhz.
115117
_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
116118

117-
118-
DAC->CTRLA.bit.SWRST = 1;
119-
while (DAC->CTRLA.bit.SWRST == 1) {}
119+
DAC->CTRLA.bit.SWRST = 1;
120+
while (DAC->CTRLA.bit.SWRST == 1) {}
120121

121122
bool channel0_enabled = true;
122123
#ifdef SAMD51
@@ -127,9 +128,11 @@ void common_hal_audioio_audioout_construct(audioio_audioout_obj_t* self,
127128
if (channel0_enabled) {
128129
#ifdef SAMD21
129130
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI;
131+
// We disable the voltage pump because we always run at 3.3v.
130132
DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC |
131133
DAC_CTRLB_LEFTADJ |
132-
DAC_CTRLB_EOEN;
134+
DAC_CTRLB_EOEN |
135+
DAC_CTRLB_VPD;
133136
#endif
134137
#ifdef SAMD51
135138
DAC->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
@@ -283,6 +286,16 @@ void common_hal_audioio_audioout_play(audioio_audioout_obj_t* self,
283286
common_hal_audioio_audioout_stop(self);
284287
}
285288
audio_dma_result result = AUDIO_DMA_OK;
289+
uint32_t sample_rate = audiosample_sample_rate(sample);
290+
#ifdef SAMD21
291+
uint32_t max_sample_rate = 350000;
292+
#endif
293+
#ifdef SAMD51
294+
uint32_t max_sample_rate = 1000000;
295+
#endif
296+
if (sample_rate > max_sample_rate) {
297+
mp_raise_ValueError_varg("Sample rate too high. It must be less than %d", max_sample_rate);
298+
}
286299
#ifdef SAMD21
287300
result = audio_dma_setup_playback(&self->left_dma, sample, loop, true, 0,
288301
false /* output unsigned */,

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