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Commits on Feb 28, 2020

• Create IDT_VC6E---RegProgGuide_MAU_20180830_Clock_Registers.pdf

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  committed
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• Update README.md

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  authored
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Commits on Feb 27, 2020

• Updates README

  

  Elias Santistevan

  committed
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Commits on Feb 14, 2020

• Removes buzzard labels, moves datasheet

  

  Elias Santistevan

  committed
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Commits on Jan 17, 2020

• Replaces previous panel due to the Panelizer changing the DRC

  

  Elias Santistevan

  committed
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• Puts the aforementioned production files in the right folder.

  

  Elias Santistevan

  committed
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• Adds Production Files for a 6x7 Panel

  

  Elias Santistevan

  committed
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• Adds more info to schematic, removes old production files and unnecessary README's

  

  Elias Santistevan

  committed
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• Replace "SEL" silk - not sure where it went.

  

  Elias Santistevan

  committed
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• Rotates Ferrite bead,

  

  Elias Santistevan

  committed
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Commits on Jan 16, 2020

• Fixes air wires, adds clock generator to eagle library, removes buzzard label folder

  

  Elias Santistevan

  committed
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• Fixes "SEL" text, adds second ground pour for clock lines isolate only, fixes power shorting through ferrite and resistor

  

  Elias Santistevan

  committed
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Commits on Jan 15, 2020

• Checks DRC and fixes errors

  

  Elias Santistevan

  committed
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• Improves ground plane pour, adds some more vias, updates packages of clock and crystal

  

  Elias Santistevan

  committed
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Commits on Jan 14, 2020

• Updates board with select jumper to enable select mode and fixes labels

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  Elias Santistevan

  committed
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Commits on Dec 16, 2019

• Radical change to design

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  Elias Santistevan

  committed
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Commits on Sep 30, 2019

• Moves SCL silk back to its' pin

  

  Elias Santistevan

  committed
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• Updates crystal footprint, and fixes routing

  

  Elias Santistevan

  committed
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Commits on Sep 26, 2019

• Update ferrite bead

  

  Elias Santistevan

  committed
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Commits on Sep 19, 2019

• Adds new production files for update design with different DRC

  

  Elias Santistevan

  committed
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• Changes DRC to SparkFun Tight to ensure that JLCPCB could do it - parts were adjusted accordingly

  

  Elias Santistevan

  committed
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• Panelizes NEO-M9N and cams gerbers

  

  Elias Santistevan

  committed
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• Adds default address to schematic, moves design to 0,0 , updates right angle qwiic connector with value

  

  Elias Santistevan

  committed
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Commits on Sep 17, 2019

• Updates crystal and 12pF parts

  

  Elias Santistevan

  committed
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• Updates README with all but description

  

  Elias Santistevan

  committed
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• Enlarges the silk on the bottom side labeling the clocks

  

  Elias Santistevan

  committed
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Commits on Sep 16, 2019

• Moves I2C header to align with bottom header

  

  Elias Santistevan

  committed
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• Removes screw terminals in place of PTH header (with additional ground through holes)

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  Elias Santistevan

  committed
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• Removes pulling SEL_I2CB line from ground, and instead leaves it floating

  

  Elias Santistevan

  committed
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• Minor adjustments to schematic

  

  Elias Santistevan

  committed
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Commits on Sep 13, 2019

• Adjusts via for better ground pour

  

  Elias Santistevan

  committed
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• Adds silk to jumpers and adds smaller diameter through holes for clock signals

  

  Elias Santistevan

  committed
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Commits on Sep 12, 2019

• Adds a few (probably) unnecessary stitching vias

  

  Elias Santistevan

  committed
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• Adds silk, so much silk

  

  Elias Santistevan

  committed
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• Routes board

  

  Elias Santistevan

  committed
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