GitHub - soltanloo/DirectMappedCache: A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran.

soltanloo / DirectMappedCache Public

A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran.

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.gitignore		.gitignore
Cache.v		Cache.v
CacheDataMemory.v		CacheDataMemory.v
Controller.v		Controller.v
Datapath.v		Datapath.v
DirectMappedDataCache.v		DirectMappedDataCache.v
MainMemory.v		MainMemory.v
TB.v		TB.v
TagMemory.v		TagMemory.v
VMemory.v		VMemory.v