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Simplify, styling & spelling
1 parent e9a3a5e commit 4ba5052

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5 files changed

+73
-76
lines changed

5 files changed

+73
-76
lines changed

examples/tcp_stm32f407.rs

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
use core::env;
55

66
extern crate panic_itm;
7-
use cortex_m::iprintln;
7+
use cortex_m::{iprintln, iprint};
88

99
use cortex_m_rt::entry;
1010
use embedded_hal::digital::v2::OutputPin;
@@ -90,7 +90,7 @@ fn main() -> ! {
9090
let mut itm = cp.ITM;
9191
let stim0 = &mut itm.stim[0];
9292

93-
iprintln!(stim0,
93+
iprintln!(stim0,
9494
"Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
9595

9696
// Get IP address from args
@@ -132,34 +132,38 @@ fn main() -> ! {
132132
spisel.set_low().unwrap();
133133
// Create SPI1 for HAL
134134
let spi_eth_port = Spi::spi1(
135-
spi1, (spi1_sck, spi1_miso, spi1_mosi),
136-
enc424j600::spi::interfaces::SPI_MODE,
135+
spi1, (spi1_sck, spi1_miso, spi1_mosi),
136+
enc424j600::spi::interfaces::SPI_MODE,
137137
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
138138
clocks);
139139
let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
140140
// Init
141141
match spi_eth.init_dev(&mut delay) {
142142
Ok(_) => {
143-
iprintln!(stim0, "Ethernet initialised.")
143+
iprintln!(stim0, "Ethernet initialized")
144144
}
145145
Err(_) => {
146-
panic!("Ethernet initialisation Failed!")
146+
panic!("Ethernet initialization failed!")
147147
}
148148
}
149149

150150
// Setup SysTick
151151
// Reference to stm32-eth:examples/ip.rs
152152
timer_setup(delay.free(), clocks);
153-
iprintln!(stim0, "Timer initialised.");
153+
iprintln!(stim0, "Timer initialized");
154154

155155
// Read MAC
156156
let mut eth_mac_addr: [u8; 6] = [0; 6];
157157
spi_eth.read_from_mac(&mut eth_mac_addr);
158-
iprintln!(stim0,
159-
"MAC Address = {:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x}",
160-
eth_mac_addr[0], eth_mac_addr[1],
161-
eth_mac_addr[2], eth_mac_addr[3],
162-
eth_mac_addr[4], eth_mac_addr[5]);
158+
for i in 0..6 {
159+
let byte = eth_mac_addr[i];
160+
match i {
161+
0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
162+
1..=4 => iprint!(stim0, "{:02x}-", byte),
163+
5 => iprint!(stim0, "{:02x}\n", byte),
164+
_ => ()
165+
};
166+
}
163167

164168
// Init Rx/Tx buffers
165169
spi_eth.init_rxbuf();
@@ -199,10 +203,9 @@ fn main() -> ! {
199203
let mut socket_set = SocketSet::new(&mut socket_set_entries[..]);
200204
let echo_handle = socket_set.add(echo_socket);
201205
let greet_handle = socket_set.add(greet_socket);
202-
iprintln!(stim0,
203-
"TCP sockets will listen at {}", ip_addr);
206+
iprintln!(stim0, "TCP sockets will listen at {}", ip_addr);
204207

205-
// Copied / modified from:
208+
// Copied / modified from:
206209
// smoltcp:examples/loopback.rs, examples/server.rs;
207210
// stm32-eth:examples/ip.rs,
208211
// git.m-labs.hk/M-Labs/tnetplug
@@ -220,13 +223,13 @@ fn main() -> ! {
220223
{
221224
let mut socket = socket_set.get::<TcpSocket>(echo_handle);
222225
if !socket.is_open() {
223-
iprintln!(stim0,
226+
iprintln!(stim0,
224227
"[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
225228
socket.listen(1234).unwrap();
226229
socket.set_timeout(Some(Duration::from_millis(10000)));
227230
}
228231
if socket.can_recv() {
229-
iprintln!(stim0,
232+
iprintln!(stim0,
230233
"[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
231234
(buffer.len(), str::from_utf8(buffer).unwrap())
232235
}));
@@ -236,7 +239,7 @@ fn main() -> ! {
236239
{
237240
let mut socket = socket_set.get::<TcpSocket>(greet_handle);
238241
if !socket.is_open() {
239-
iprintln!(stim0,
242+
iprintln!(stim0,
240243
"[{}] Listening to port 4321 for greeting, \
241244
please connect to the port", instant);
242245
socket.listen(4321).unwrap();
@@ -245,13 +248,10 @@ fn main() -> ! {
245248
if socket.can_send() {
246249
let greeting = "Welcome to the server demo for STM32-F407!";
247250
write!(socket, "{}\n", greeting).unwrap();
248-
iprintln!(stim0,
251+
iprintln!(stim0,
249252
"[{}] Greeting sent, socket closed", instant);
250253
socket.close();
251254
}
252255
}
253-
254256
}
255-
256-
unreachable!()
257257
}

examples/tx_stm32f407.rs

Lines changed: 30 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#![no_main]
33

44
extern crate panic_itm;
5-
use cortex_m::iprintln;
5+
use cortex_m::{iprintln, iprint};
66

77
use cortex_m_rt::entry;
88
use embedded_hal::digital::v2::OutputPin;
@@ -39,7 +39,7 @@ fn main() -> ! {
3939
let mut itm = cp.ITM;
4040
let stim0 = &mut itm.stim[0];
4141

42-
iprintln!(stim0,
42+
iprintln!(stim0,
4343
"Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
4444

4545
// NIC100 / ENC424J600 Set-up
@@ -57,33 +57,33 @@ fn main() -> ! {
5757
spisel.set_low().unwrap();
5858
// Create SPI1 for HAL
5959
let spi_eth_port = Spi::spi1(
60-
spi1, (spi1_sck, spi1_miso, spi1_mosi),
60+
spi1, (spi1_sck, spi1_miso, spi1_mosi),
6161
enc424j600::spi::interfaces::SPI_MODE,
6262
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
6363
clocks);
6464
let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
6565
// Init
6666
match spi_eth.init_dev(&mut delay) {
6767
Ok(_) => {
68-
iprintln!(stim0, "Ethernet initialised.")
68+
iprintln!(stim0, "Ethernet initialized")
6969
}
7070
Err(_) => {
71-
panic!("Ethernet initialisation Failed!")
71+
panic!("Ethernet initialization failed!")
7272
}
7373
}
7474

7575
// Read MAC
7676
let mut eth_mac_addr: [u8; 6] = [0; 6];
7777
spi_eth.read_from_mac(&mut eth_mac_addr);
78-
iprintln!(stim0,
79-
"MAC Address = {:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x}",
80-
eth_mac_addr[0], eth_mac_addr[1],
81-
eth_mac_addr[2], eth_mac_addr[3],
82-
eth_mac_addr[4], eth_mac_addr[5]);
83-
// Set to promiscuous mode
84-
spi_eth.set_promiscuous();
85-
iprintln!(stim0,
86-
"Promiscuous Mode ON");
78+
for i in 0..6 {
79+
let byte = eth_mac_addr[i];
80+
match i {
81+
0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
82+
1..=4 => iprint!(stim0, "{:02x}-", byte),
83+
5 => iprint!(stim0, "{:02x}\n", byte),
84+
_ => ()
85+
};
86+
}
8787

8888
// Init Rx/Tx buffers
8989
spi_eth.init_rxbuf();
@@ -102,26 +102,23 @@ fn main() -> ! {
102102
loop {
103103
let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
104104
eth_tx_packet.update_frame(&eth_tx_dat, 64);
105-
iprintln!(stim0,
106-
"Sending packet (len={:}): \
107-
dest={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
108-
src={:02x}-{:02x}-{:02x}-{:02x}-{:02x}-{:02x} \
109-
data={:02x}{:02x}{:02x}{:02x} {:02x}{:02x}{:02x}{:02x} ...",
110-
eth_tx_packet.get_frame_length(),
111-
eth_tx_packet.get_frame_byte(0), eth_tx_packet.get_frame_byte(1), eth_tx_packet.get_frame_byte(2),
112-
eth_tx_packet.get_frame_byte(3), eth_tx_packet.get_frame_byte(4), eth_tx_packet.get_frame_byte(5),
113-
eth_tx_packet.get_frame_byte(6), eth_tx_packet.get_frame_byte(7), eth_tx_packet.get_frame_byte(8),
114-
eth_tx_packet.get_frame_byte(9), eth_tx_packet.get_frame_byte(10), eth_tx_packet.get_frame_byte(11),
115-
eth_tx_packet.get_frame_byte(12), eth_tx_packet.get_frame_byte(13),
116-
eth_tx_packet.get_frame_byte(14), eth_tx_packet.get_frame_byte(15),
117-
eth_tx_packet.get_frame_byte(16), eth_tx_packet.get_frame_byte(17),
118-
eth_tx_packet.get_frame_byte(18), eth_tx_packet.get_frame_byte(19)
119-
);
105+
iprint!(stim0,
106+
"Sending packet (len={:}): ", eth_tx_packet.get_frame_length());
107+
for i in 0..20 {
108+
let byte = eth_tx_packet.get_frame_byte(i);
109+
match i {
110+
0 => iprint!(stim0, "dest={:02x}-", byte),
111+
6 => iprint!(stim0, "src={:02x}-", byte),
112+
12 => iprint!(stim0, "data={:02x}", byte),
113+
1..=4 | 7..=10 => iprint!(stim0, "{:02x}-", byte),
114+
13..=14 | 16..=18 => iprint!(stim0, "{:02x}", byte),
115+
5 | 11 | 15 => iprint!(stim0, "{:02x} ", byte),
116+
19 => iprint!(stim0, "{:02x} ...\n", byte),
117+
_ => ()
118+
};
119+
}
120120
spi_eth.send_raw_packet(&eth_tx_packet);
121-
iprintln!(stim0,
122-
"Packet sent");
121+
iprintln!(stim0, "Packet sent");
123122
delay.delay_ms(100_u32);
124123
}
125-
126-
unreachable!()
127124
}

src/lib.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -40,14 +40,14 @@ impl From<spi::SpiPortError> for EthControllerError {
4040
}
4141

4242
/// Ethernet controller using SPI interface
43-
pub struct SpiEth<SPI: Transfer<u8>,
43+
pub struct SpiEth<SPI: Transfer<u8>,
4444
NSS: OutputPin> {
4545
spi_port: spi::SpiPort<SPI, NSS>,
4646
rx_buf: rx::RxBuffer,
4747
tx_buf: tx::TxBuffer
4848
}
4949

50-
impl <SPI: Transfer<u8>,
50+
impl <SPI: Transfer<u8>,
5151
NSS: OutputPin> SpiEth<SPI, NSS> {
5252
pub fn new(spi: SPI, nss: NSS) -> Self {
5353
SpiEth {
@@ -58,14 +58,14 @@ impl <SPI: Transfer<u8>,
5858
}
5959
}
6060

61-
impl <'c, SPI: Transfer<u8>,
61+
impl <'c, SPI: Transfer<u8>,
6262
NSS: OutputPin> EthController<'c> for SpiEth<SPI, NSS> {
6363
fn init_dev(&mut self, delay: &mut dyn DelayUs<u16>) -> Result<(), EthControllerError> {
6464
// Write 0x1234 to EUDAST
6565
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
6666
// Verify that EUDAST is 0x1234
6767
let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
68-
if eudast != 0x1234 {
68+
if eudast != 0x1234 {
6969
return Err(EthControllerError::GeneralError)
7070
}
7171
// Poll CLKRDY (ESTAT<12>) to check if it is set
@@ -80,7 +80,7 @@ impl <'c, SPI: Transfer<u8>,
8080
delay.delay_us(25_u16);
8181
// Verify that EUDAST is 0x0000
8282
eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
83-
if eudast != 0x0000 {
83+
if eudast != 0x0000 {
8484
return Err(EthControllerError::GeneralError)
8585
}
8686
// Wait for 256us
@@ -110,7 +110,7 @@ impl <'c, SPI: Transfer<u8>,
110110
/// Receive the next packet and return it
111111
/// Set is_poll to true for returning until PKTIF is set;
112112
/// Set is_poll to false for returning Err when PKTIF is not set
113-
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
113+
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
114114
// Poll PKTIF (EIR<4>) to check if it is set
115115
loop {
116116
let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
@@ -156,7 +156,7 @@ impl <'c, SPI: Transfer<u8>,
156156
// Set EGPWRPT pointer to next_addr
157157
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
158158
// Copy packet data to SRAM Buffer
159-
// 1-byte Opcode is included
159+
// 1-byte Opcode is included
160160
let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
161161
packet.write_frame_to(&mut txdat_buf[1..]);
162162
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
@@ -175,15 +175,15 @@ impl <'c, SPI: Transfer<u8>,
175175
// TODO: Read ETXSTAT to understand Ethernet transmission status
176176
// (See: Register 9-2, ENC424J600 Data Sheet)
177177
// Update TX buffer start address
178-
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
178+
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
179179
tx::GPBUFEN_DEFAULT);
180180
Ok(())
181181
}
182182

183183
/// Set controller to Promiscuous Mode
184184
fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
185-
// From Section 10.12, ENC424J600 Data Sheet:
186-
// "To accept all incoming frames regardless of content (Promiscuous mode),
185+
// From Section 10.12, ENC424J600 Data Sheet:
186+
// "To accept all incoming frames regardless of content (Promiscuous mode),
187187
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
188188
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
189189
self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;

src/spi.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ pub mod addrs {
5151

5252
/// Struct for SPI I/O interface on ENC424J600
5353
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
54-
pub struct SpiPort<SPI: Transfer<u8>,
54+
pub struct SpiPort<SPI: Transfer<u8>,
5555
NSS: OutputPin> {
5656
spi: SPI,
5757
nss: NSS,
@@ -62,14 +62,14 @@ pub enum SpiPortError {
6262
}
6363

6464
#[allow(unused_must_use)]
65-
impl <SPI: Transfer<u8>,
65+
impl <SPI: Transfer<u8>,
6666
NSS: OutputPin> SpiPort<SPI, NSS> {
6767
// TODO: return as Result()
6868
pub fn new(spi: SPI, mut nss: NSS) -> Self {
6969
nss.set_high();
70-
70+
7171
SpiPort {
72-
spi,
72+
spi,
7373
nss
7474
}
7575
}
@@ -88,15 +88,15 @@ impl <SPI: Transfer<u8>,
8888
}
8989

9090
// Currently requires manual slicing (buf[1..]) for the data read back
91-
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
91+
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
9292
-> Result<(), SpiPortError> {
9393
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
9494
Ok(r_valid)
9595
}
9696

9797
// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
9898
// TODO: Maybe better naming?
99-
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
99+
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
100100
-> Result<(), SpiPortError> {
101101
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
102102
Ok(w_valid)
@@ -118,7 +118,7 @@ impl <SPI: Transfer<u8>,
118118
// TODO: Generalise transfer functions
119119
// TODO: (Make data read/write as reference to array)
120120
// Currently requires 1-byte addr, read/write data is only 1-byte
121-
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
121+
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
122122
-> Result<u8, SpiPortError> {
123123
// Enable chip select
124124
self.nss.set_low();
@@ -144,11 +144,11 @@ impl <SPI: Transfer<u8>,
144144
}
145145

146146
// TODO: Generalise transfer functions
147-
// Currently does NOT accept addr, read data is N-byte long
147+
// Currently does NOT accept addr, read data is N-byte long
148148
// Returns a reference to the data returned
149149
// Note: buf must be at least (data_length + 1)-byte long
150150
// TODO: Check and raise error for array size < (data_length + 1)
151-
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
151+
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
152152
-> Result<(), SpiPortError> {
153153
// Enable chip select
154154
self.nss.set_low();
@@ -171,7 +171,7 @@ impl <SPI: Transfer<u8>,
171171

172172
// Note: buf[0] is currently reserved for opcode to overwrite
173173
// TODO: Actual data should start from buf[0], not buf[1]
174-
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
174+
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
175175
-> Result<(), SpiPortError> {
176176
// Enable chip select
177177
self.nss.set_low();

src/tx.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ impl TxBuffer {
3636
pub fn get_next_addr(& self) -> u16{
3737
self.next_addr
3838
}
39-
39+
4040
pub fn set_tail_addr(&mut self, addr: u16) {
4141
self.tail_addr = addr;
4242
}

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