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Achievement: QuickdrawAchievement: Pull Sharkx2Achievement: YOLO

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skudlur/README.md

Hello there 👋

My name is Suhas Kudlur Viswanath and I am an avid enthusiast of open Instruction Set Architectures like RISC-V. I mainly develop RTL for processors using the RISC-V ISA, some more RTL for accelerators and interconnects. I used to work as a Hardware Engineer at Arithmic Labs working on the research and development of an accelerator on FPGA. At present, I am a Master's By Research candidate at The University of Edinburgh, School of Informatics. I have been awarded the Huawei Research Grant.

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  1. diablo diablo Public

    diablo is an Out-Of-Order 64-bit RISC-V processor.

    SystemVerilog 15 4

  2. cayde cayde Public

    cayde is 32-bit RISC-V core written in SystemVerilog

    SystemVerilog 7 8

  3. waveplot waveplot Public

    waveplot is a VCD waveform generator for the terminal.

    Rust 4 2

  4. RISCulator RISCulator Public

    RISCulator is a RISC-V emulator.

    Rust 10

  5. CFT CFT Public

    Circuit Fault Tester: This tool will process a netlist and the faults in the netlist.

    Rust 1

  6. rv-decoder rv-decoder Public

    RISC-V Decoder library for Rust

    Rust 3 1