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[RISC-V] Implement On Stack Replacement #1

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Merged
merged 31 commits into from
Dec 7, 2023
Merged

[RISC-V] Implement On Stack Replacement #1

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2803037
[RISC-V] Set OSR root frames reg for large offset
sirntar Nov 28, 2023
4eaddc1
[RISC-V] Enable OSR feature in cmake
sirntar Nov 28, 2023
bff6fe5
[RISC-V] Add config info about QuickJitForLoops
sirntar Nov 28, 2023
43b5a49
[RISC-V] Add osr ifdef directives to codegencommon
sirntar Nov 28, 2023
42c1b20
[RISC-V] Redesign FuncletFrameInfoDsc for OSR
sirntar Nov 29, 2023
c32d8a8
[RISC-V] Correct some assembly comments
sirntar Nov 29, 2023
fbd338a
[RISC-V] Rebuild genFuncletProlog for OSR
sirntar Nov 30, 2023
405bdab
[RISC-V] Add some documentation in coments
sirntar Dec 1, 2023
d2fb93b
[RISC-V] Fix potential issue for 0 calee-save regs
sirntar Dec 1, 2023
b799803
[RISC-V] Rebuild OSR epilog
sirntar Dec 1, 2023
53a6dc1
[RISC-V] Rebuild genCaptureFuncletPrologEpilogInfo for OSR
sirntar Dec 1, 2023
b306acb
[RISC-V] Add OSR support in genSetPSPSym
sirntar Dec 1, 2023
9ad6889
[RISC-V] Cosmetic changes in genSetRegToConst
sirntar Dec 1, 2023
3ad737d
[RISC-V] Add coment to genCodeForCpObj
sirntar Dec 1, 2023
f05be9c
[RISC-V] Cleanup in genCodeForCompare for OSR
sirntar Dec 1, 2023
1e13920
[RISC-V] Improve some SP/FP delta manimulations
sirntar Dec 1, 2023
058aadc
[RISC-V] Add OSR support to genSetGSSecurityCookie
sirntar Dec 1, 2023
4e0823e
[RISC-V] Implement genPushCalleeSavedRegisters for OSR
sirntar Dec 4, 2023
65324eb
[RISC-V] Implement genPopCalleeSavedRegisters for OSR
sirntar Dec 5, 2023
e2d6fd9
[RISC-V] Update vars for OSR in Compiler
sirntar Dec 5, 2023
05b50f2
[RISC-V] Update gcInfoBlockHdrSave for OSR
sirntar Dec 5, 2023
cba3bf6
[RISC-V] Enable TC_OnStackReplacement
sirntar Dec 5, 2023
9079076
[RISC-V] Correct compiler OSR vars
sirntar Dec 5, 2023
a940ddd
[RISC-V] Fix codegen definition
sirntar Dec 5, 2023
bf3dca9
[RISC-V] Correct spelling of SPtoCallerSPdelta
sirntar Dec 5, 2023
1c002d4
[RISC-V] Add missing semicolon
sirntar Dec 5, 2023
99a5d05
[RISC-V] Fix IsOSR is not a pointer member
sirntar Dec 5, 2023
5423fa9
[RISC-V] Fix OSR errors
sirntar Dec 5, 2023
1092662
[RISC-V] A little correction and cleanup
sirntar Dec 6, 2023
d6d8f4c
[RISC-V] Add some docs and small optimization changes
sirntar Dec 7, 2023
e6116dc
[RISC-V] Remove space before genCaptureFuncletPrologEpilogInfo
sirntar Dec 7, 2023
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4 changes: 2 additions & 2 deletions src/coreclr/clrdefinitions.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -184,9 +184,9 @@ endif(FEATURE_ENABLE_NO_ADDRESS_SPACE_RANDOMIZATION)
add_definitions(-DFEATURE_SVR_GC)
add_definitions(-DFEATURE_SYMDIFF)
add_compile_definitions(FEATURE_TIERED_COMPILATION)
if (CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
if (CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
add_compile_definitions(FEATURE_ON_STACK_REPLACEMENT)
endif (CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
endif (CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
add_compile_definitions(FEATURE_PGO)
if (CLR_CMAKE_TARGET_WIN32)
add_definitions(-DFEATURE_TYPEEQUIVALENCE)
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/inc/clrconfigvalues.h
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Expand Up @@ -570,11 +570,11 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_HillClimbing_GainExponent,
#endif // _DEBUG
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_TieredCompilation, W("TieredCompilation"), 1, "Enables tiered compilation")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_TC_QuickJit, W("TC_QuickJit"), 1, "For methods that would be jitted, enable using quick JIT when appropriate.")
#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
RETAIL_CONFIG_DWORD_INFO(UNSUPPORTED_TC_QuickJitForLoops, W("TC_QuickJitForLoops"), 1, "When quick JIT is enabled, quick JIT may also be used for methods that contain loops.")
#else // !(defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64))
#else // !(defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)) || defined(TARGET_RISCV64)
RETAIL_CONFIG_DWORD_INFO(UNSUPPORTED_TC_QuickJitForLoops, W("TC_QuickJitForLoops"), 0, "When quick JIT is enabled, quick JIT may also be used for methods that contain loops.")
#endif // defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#endif // defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_TC_AggressiveTiering, W("TC_AggressiveTiering"), 0, "Transition through tiers aggressively.")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_TC_CallCountThreshold, W("TC_CallCountThreshold"), TC_CallCountThreshold, "Number of times a method must be called in tier 0 after which it is promoted to the next tier.")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_TC_CallCountingDelayMs, W("TC_CallCountingDelayMs"), TC_CallCountingDelayMs, "A perpetual delay in milliseconds that is applied to call counting in tier 0 and jitting at higher tiers, while there is startup-like activity.")
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/codegen.h
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Original file line number Diff line number Diff line change
Expand Up @@ -262,7 +262,7 @@ class CodeGen final : public CodeGenInterface
void genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbered, RegState* regState);
#endif
void genEnregisterIncomingStackArgs();
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
void genEnregisterOSRArgsAndLocals(regNumber initReg, bool* pInitRegZeroed);
#else
void genEnregisterOSRArgsAndLocals();
Expand Down Expand Up @@ -447,11 +447,11 @@ class CodeGen final : public CodeGenInterface
regMaskTP fiSaveRegs; // Set of callee-saved registers saved in the funclet prolog (includes RA)
int fiFunction_CallerSP_to_FP_delta; // Delta between caller SP and the frame pointer in the parent function
// (negative)
int fiSP_to_FPRA_save_delta; // FP/RA register save offset from SP (positive)
int fiSP_to_CalleeSaved_delta; // CalleeSaved register save offset from SP (positive)
int fiCalleeSavedPadding; // CalleeSaved offset padding (positive)
int fiSP_to_PSP_slot_delta; // PSP slot offset from SP (positive)
int fiCallerSP_to_PSP_slot_delta; // PSP slot offset from Caller SP (negative)
int fiFrameType; // Funclet frame types are numbered. See genFuncletProlog() for details.
int fiSpDelta1; // Stack pointer delta 1 (negative)
int fiSpDelta; // Stack pointer delta (negative)
};

FuncletFrameInfoDsc genFuncletInfo;
Expand Down
30 changes: 21 additions & 9 deletions src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4732,7 +4732,7 @@ void CodeGen::genZeroInitFrame(int untrLclHi, int untrLclLo, regNumber initReg,
// initReg -- scratch register to use if needed
// pInitRegZeroed -- [IN,OUT] if init reg is zero (on entry/exit)
//
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
void CodeGen::genEnregisterOSRArgsAndLocals(regNumber initReg, bool* pInitRegZeroed)
#else
void CodeGen::genEnregisterOSRArgsAndLocals()
Expand Down Expand Up @@ -4873,7 +4873,7 @@ void CodeGen::genEnregisterOSRArgsAndLocals()

GetEmitter()->emitIns_R_AR(ins_Load(lclTyp), size, varDsc->GetRegNum(), genFramePointerReg(), offset);

#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)

// Patchpoint offset is from top of Tier0 frame
//
Expand Down Expand Up @@ -4905,7 +4905,7 @@ void CodeGen::genEnregisterOSRArgsAndLocals()

genInstrWithConstant(ins_Load(lclTyp), size, varDsc->GetRegNum(), genFramePointerReg(), offset, initReg);
*pInitRegZeroed = false;
#endif
#endif // TARGET_ARM64 || TARGET_LOONGARCH64 || TARGET_RISCV64
}
}

Expand Down Expand Up @@ -5512,7 +5512,7 @@ void CodeGen::genFnProlog()
psiBegProlog();
}

#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
// For arm64 OSR, emit a "phantom prolog" to account for the actions taken
// in the tier0 frame that impact FP and SP on entry to the OSR method.
//
Expand All @@ -5527,7 +5527,7 @@ void CodeGen::genFnProlog()
// SP is tier0 method's SP.
compiler->unwindAllocStack(tier0FrameSize);
}
#endif // defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#endif // defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)

#ifdef DEBUG

Expand Down Expand Up @@ -5857,13 +5857,25 @@ void CodeGen::genFnProlog()
{
initReg = REG_SCRATCH;
}
#elif defined(TARGET_RISCV64)
// For RISC-V64 OSR root frames, we may need a scratch register for large
// offset addresses. Use a register that won't be allocated.
if (isRoot && compiler->opts.IsOSR())
{
initReg = REG_SCRATCH; // REG_T0
}
#endif

#ifndef TARGET_LOONGARCH64
#if !defined(TARGET_LOONGARCH64) && !defined(TARGET_RISCV64)
// For LoongArch64's OSR root frames, we may need a scratch register for large
// offset addresses. But this does not conflict with the REG_PINVOKE_FRAME.
//
// RISC-V64's OSR root frames are similar to LoongArch64's. In this case
// REG_SCRATCH also shouldn't conflict with REG_PINVOKE_FRAME, even if
// technically they are the same register - REG_T0.
//
noway_assert(!compiler->compMethodRequiresPInvokeFrame() || (initReg != REG_PINVOKE_FRAME));
#endif
#endif // !TARGET_LOONGARCH64 && !TARGET_RISCV64

#if defined(TARGET_AMD64)
// If we are a varargs call, in order to set up the arguments correctly this
Expand Down Expand Up @@ -6174,7 +6186,7 @@ void CodeGen::genFnProlog()
// Otherwise we'll do some of these fetches twice.
//
CLANG_FORMAT_COMMENT_ANCHOR;
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
genEnregisterOSRArgsAndLocals(initReg, &initRegZeroed);
#else
genEnregisterOSRArgsAndLocals();
Expand Down Expand Up @@ -6226,7 +6238,7 @@ void CodeGen::genFnProlog()
assignIncomingRegisterArgs(&floatRegState);
#else
assignIncomingRegisterArgs(&intRegState);
#endif
#endif // TARGET_ARM64 || TARGET_LOONGARCH64 || TARGET_RISCV64

#endif // TARGET_LOONGARCH64 || TARGET_RISCV64

Expand Down
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