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base repository: simd-everywhere/simde-no-tests
base: v0.8.4-rc1
head repository: simd-everywhere/simde-no-tests
compare: 0faa907b2
- 16 commits
- 24 files changed
- 8 contributors
Commits on Feb 3, 2025
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Commits on Feb 10, 2025
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Commits on Feb 14, 2025
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x86 sse2,avx2 loongarch impl: let compiler to generate instructions b…
…ased on imm8 On loongarch, for example simde_mm_srai_epi16, GCC will generate a vsrai.h instruction for '>>' operator if the imm8 is a real immediate const value, otherwise it will generate two instructions vsral.h and vreplgr2vr.h. But for clang it always generates two instructions. So don't use intrinsics directly, instead let the compiler itself to generate instructions based on imm8, which will save one instruction for GCC at least. Same for below: simde_mm_srai_epi32 simde_mm_slli_epi[16/32/64] simde_mm_srli_epi[16/32/64] simde_mm256_slli_epi[16/32/64] simde_mm256_srai_epi[16/32] simde_mm256_srli_epi[16/32/64]
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x86 avx for loongarch: use vfcmp_clt to save one instruction in `_mm_…
…cmp_{sd,ss}` and `_mm256_cmp_pd`
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Commits on Feb 26, 2025
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riscv64: Enable V feature when both zve64d and zvl128b are present (#…
…1284) Co-authored-by: Juhung Li <jhlee755@andestech.com>
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neon riscv64: Enable RVV segment load/store only when we have `__risc…
…v_zvlsseg` flag. (#1285) Co-authored-by: Juhung Li <jhlee755@andestech.com> Co-authored-by: Michael R. Crusoe <1330696+mr-c@users.noreply.github.com>
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Commits on Feb 27, 2025
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Commits on Mar 13, 2025
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Commits on Jun 30, 2025
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arm64 gcc FRINT: skip native call on GCC
GCC through 15.1 at least, require that `-march=armv8.5-a` even when /proc/cpuinfo lists "frint" and `-march=native` is used
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Avoid undefined behaviour with signed integer multiplication (#1296)
Fixes #1295 . Co-authored-by: Michael R. Crusoe <1330696+mr-c@users.noreply.github.com>
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Commits on Jul 2, 2025
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Commits on Jul 7, 2025
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Commits on Jul 27, 2025
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