bitfield and cv maps working better

Author: siddacious

.gitignore

@@ -1,4 +1,5 @@
 __pycache__
+.vscode
 .idea
 .*.sw*
 *.code-workspace

as7341_map.pypickle

@@ -11,7 +11,7 @@ class Transaction:
     """A class representing a complete read or write transaction between an I2C Master and a slave device with addressable registers"""
     end_time: float
     #is_multibyte_read: bool
-    is_write: bool
+    write: bool
     start_time: float
     _last_addr_frame: int
     data: bytearray
@@ -22,7 +22,7 @@ def __init__(self, start_time):
         self.end_time = None
         self.register_address = None
         self.data = bytearray()
-        self.write = True 
+        self.write = None
 
         # we would know this if prev start was a read and len(data) >1
         # this means it is likely reading from a data register, right? Unless registers are muilti-byte (config). This would matter if reads were auto incrementing and we
@@ -47,6 +47,8 @@ class I2CRegisterTransactions(HighLevelAnalyzer):
     # json_register_map_path = StringSetting(label='Register map (JSON)')
     # csv_register_map_path = StringSetting(label='Register map (CSV)')
     pickled_register_map_path = StringSetting(label='Register map (Python Pickle)')
+    log_file_path = StringSetting(label='Log file path')
+
 
 #    # List of settings that a user can set for this High Level Analyzer.
 #     my_string_setting = StringSetting()
@@ -83,12 +85,13 @@ def __init__(self):
 
     def _init_decoder(self):
         if self.pickled_register_map_path and os.path.exists(self.pickled_register_map_path):
-            self.decoder = RegisterDecoder(pickled_map_path=self.pickled_register_map_path)
+            self.decoder = RegisterDecoder(pickled_map_path=self.pickled_register_map_path, log_path=self.log_file_path)
         # CSV support here
 
     def process_transaction(self):
         # This doesn't need to be in here?
         self.current_transaction.register_address = self.current_transaction.data.pop(0)
+        self.current_transaction.write = self.address_is_write
         # we can also set the type here
         transaction_string = self.decoder.decode_transaction(self.current_transaction)
 

i2c_transactions.py

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c6b5f736ab5d5780cc6118b966f8ebdc6173d3f5e84473540baadbed92fcb3d5
+size 8641

logic_captures/ard_led_working.sal

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:36afbb028f7bbbe1f8af155fd76c0fbb602e04eb1a36e23dff1acdfae53225b4
+size 65721

logic_captures/ard_spectral_working.sal

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:4b5e64af0959a3b2c15b3269f582b4bd866fc7c6f7c50f660c309a1345726868
+size 98731

logic_captures/cp_bulk_spectral_main.sal

@@ -1,26 +1,47 @@
 BITFIELD,DEFAULT,ACCESS,DESC,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
-WEN,0,RW,Wait Enable.,,,,,,,,,,,,,,,,,
-SP_EN,0,RW,Spectral Measurement Enable.,Spectral Measurement Enabled,Spectral Measurement Disabled,,,,,,,,,,,,,,,
-PON,0,RW,Power ON.,AS7341 disabled,AS7341 enabled,,,,,,,,,,,,,,,
-LED_SEL,0,RW,LED control.,External LED not controlled by AS7341,Register LED controls LED connected to pin LDR,,,,,,,,,,,,,,,
-INT_SEL,0,RW,,,Sync signal applied on output pin INT,,,,,,,,,,,,,,,
-INT_MODE,0,RW,Ambient light sensing mode:,"SPM mode (spectral measurement, normal mode)",SYNS mode,2: reserved,3: SYND mode,,,,,,,,,,,,,
-GPIO_INV,0,RW,GPIO Invert., GPIO output normal,GPIO output is inverted.,,,,,,,,,,,,,,,
-GPIO_IN_EN,0,RW,GPIO Input Enable.,,GPIO pin accepts a non-floating input.,,,,,,,,,,,,,,,
-GPIO_OUT,1,RW,GPIO Output.,GPIO DIR IN,GPIO DIR OUT,,,,,,,,,,,,,,,
-GPIO_IN,0,R,GPIO Input.,GPIO LOW,GPIO HIGH,,,,,,,,,,,,,,,
-LED_ACT,0,RW,LED control.,External LED connected to pin LDR off,External LED connected to pin LDR on,,,,,,,,,,,,,,,
-LED_DRIVE,000 0100,RW,LED driving strength.,000 0004mA,000 0006mA,000 0018mA,000 00110mA,000 01012mA,,,,,,,,,,,,
-ASIEN,0,RW,Spectral and Flicker Detect Saturation Interrupt Enable.,,Permits saturation interrupts to be generated,,,,,,,,,,,,,,,
-SP_IEN,0,RW,Spectral Interrupt Enable.,,"Permits interrupts to be generated, subject to the spectral thresholds and persistence filter. Bit is mirrored in the ENABLE register.",,,,,,,,,,,,,,,
-SP_MAN_AZ,0,RW,Spectral Engine Manual Autozero.,,Starts a manual autozero of the spectral engines.,,,,,,,,,,,,,,,
-FIFO_CLR,0,RW,FIFO Buffer Clear.,,"Clears all FIFO data, FINT, FIFO_OV, and FIFO_LVL.",,,,,,,,,,,,,,,
-FD_GAIN,9,R/W,,0.5x,1x,2x,4x,8x,16x,32x,64x,128x,256x,1512x,,,,,,
-AGAIN,9,RW,Spectral engine gain setting.,0.5x,1x,2x,4x,8x,16x,32x,64x,128x,256x,512x,,,,,,
-SP_TH_CH,0,RW,,CH0,CH1,CH2,CH3,CH4,,,,,,,,,,,,
-READY,0,R,,Spectral measurement status is busy,Spectral measurement status is ready,,,,,,,,,,,,,,,
-REG_BANK,0,RW,Register Bank Access,Register access to register 0x80 and above,Register access to register 0x60 to 0x74,,,,,,,,,,,,,,,
-SMUX_CMD,2,RW,SMUX command.,ROM code initialization of SMUX,Read SMUX configuration to RAM from SMUX chain,Write SMUX configuration from RAM to SMUX chain,"3 Reserved, do not use",,,,,,,,,,,,,
-SIEN_FD,0,RW,,System Interrupt Flicker Detection.,,,,,,,,,,,,,,,,
-SIEN_SMUX,0,RW,,,SMUX CMD Complete INT ENABLED,,,,,,,,,,,,,,,
-APERS,0,RW,,Every spectral cycle generates an,1,2,3,5,10,,,,,,,,,,,
+WEN,0,RW,Wait Enable,Disabled,Enabled,,,,,,,,,,,,,,,
+SMUXEN,0,CL,SMUX Command,Completed,Started  ,,,,,,,,,,,,,,,
+SP_EN,0,RW,Spectral Measurement ,Disabled,Enabled,,,,,,,,,,,,,,,
+PON,0,RW,Power enable,Disabled,Enabled,,,,,,,,,,,,,,,
+LED_SEL,0,RW,LED control,Disabled,Enabled,,,,,,,,,,,,,,,
+INT_SEL,0,RW,Sync signal on INT Pin,Disabled,Enabled,,,,,,,,,,,,,,,
+INT_MODE,0,RW,Ambient light sensing mode,SPM mode,SYNS mode,Reserved,SYND mode,,,,,,,,,,,,,
+GPIO_INV,0,RW,GPIO Invert, GPIO output normal,GPIO output is inverted.,,,,,,,,,,,,,,,
+GPIO_IN_EN,0,RW,GPIO Input Enable,Disabled,Enabled,,,,,,,,,,,,,,,
+GPIO_OUT,1,RW,GPIO Output,GPIO DIR IN,GPIO DIR OUT,,,,,,,,,,,,,,,
+GPIO_IN,0,R,GPIO Input,LOW,HIGH,,,,,,,,,,,,,,,
+LED_ACT,0,RW,LED control,External LED connected to pin LDR off,External LED connected to pin LDR on,,,,,,,,,,,,,,,
+LED_DRIVE,4,RW,LED driving strength.,4mA,6mA,18mA,000 00110mA,000 01012mA,,,,,,,,,,,,
+ASIEN,0,RW,Saturation Interrupt Enable,Disabled,Enabled,,,,,,,,,,,,,,,
+SP_IEN,0,RW,Spectral Interrupt Enable,Disabled,Enabled,,,,,,,,,,,,,,,,
+SP_MAN_AZ,0,RW,Spectral Engine Manual Autozero,,Starts a manual autozero of the spectral engines.,,,,,,,,,,,,,,,
+FIFO_CLR,0,RW,FIFO Buffer Clear,,Cleared,,,,,,,,,,,,,,,
+FD_GAIN,9,R/W,Flicker Detection Gain,0.5x,1x,2x,4x,8x,16x,32x,64x,128x,256x,512x,,,,,,
+AGAIN,9,RW,Spectral engine gain,0.5x,1x,2x,4x,8x,16x,32x,64x,128x,256x,512x,,,,,,
+SP_TH_CH,0,RW,Spectral Threshold Channel,CH0,CH1,CH2,CH3,CH4,,,,,,,,,,,,
+READY,0,R,Spectral measurement statu,Busy,Ready,,,,,,,,,,,,,,,
+REG_BANK,0,RW,Register Bank Access,Registers 0x80 and above,Registers 0x60 to 0x74,,,,,,,,,,,,,,,
+SMUX_CMD,2,RW,SMUX Command,ROM code initialization of SMUX,Read SMUX configuration to RAM from SMUX chain,Write SMUX configuration from RAM to SMUX chain,Reserved  ,,,,,,,,,,,,,
+SIEN_FD,0,RW,Flicker Detection INT Enable,Disabled, Enabled,,,,,,,,,,,,,,,
+SIEN_SMUX,0,RW,SMUX CMD Completion INT Enable,Disabled,Enabled,,,,,,,,,,,,,,,
+APERS,0,RW,Spectral Interrupt Persistence,Every spectral cycle generates an,1,2,3,5,10,,,,,,,,,,,
+APERS,0,RW,SMUX Setting,Every spectral cycle generates an,1,2,3,5,10,,,,,,,,,,,
+F1L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F1R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F2L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F2R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F3L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F3R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F4L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F4R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F5L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F5R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F6L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F6R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F7L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F7R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F8L,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F8R,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+CL,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+CR,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,
+F,0,RW,SMUX Output, Ground,ADC1,ADC2,ADC3,ADC4,ADC5 (Flicker), Reserved,,,,,,,,,,

maps/as7341_cv.csv

@@ -0,0 +1,94 @@
+ADDR (HEX),ADDR (DEC.),REGISTER NAME,SERIAL I/F,BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+0x60,96,ASTATUS,,ASAT_STATUS,,,,AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0]
+0x61,97,CH0_DATA_L ,,CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0]
+0x62,98,CH0_DATA_H,,CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0]
+0x63,99,ITIME_L,,ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0],ITIME_L [7:0]
+0x64,100,ITIME_M,,ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0],ITIME_M [7:0]
+0x65,101,ITIME_H,,ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0],ITIME_H [7:0]
+0x66,102,CH1_DATA_L,,CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0]
+0x67,103,CH1_DATA_H,,CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0]
+0x68,104,CH2_DATA_L,,CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0]
+0x69,105,CH2_DATA_H,,CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0]
+0x6A,106,CH3_DATA_L,,CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0]
+0x6B,107,CH3_DATA_H,,CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0]
+0x6C,108,CH4_DATA_L,,CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0]
+0x6D,109,CH4_DATA_H,,CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0]
+0x6E,110,CH5_DATA_L,,CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0]
+0x6F,111,CH5_DATA_H,,CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0]
+0x70,112,CONFIG,,,,,,LED_SEL,INT_SEL,INT_MODE[1:0],INT_MODE[1:0]
+0x71,113,STAT,,,,,,,,WAIT_SYNC,READY
+0x72,114,EDGE,,SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0],SYNC_EDGE [7:0]
+0x73,115,GPIO,,,,,,,,PD_GPIO,PD_INT
+0x74,116,LED,,LED_ACT,LED_DRIVE [6:0],LED_DRIVE [6:0],LED_DRIVE [6:0],LED_DRIVE [6:0],LED_DRIVE [6:0],LED_DRIVE [6:0],LED_DRIVE [6:0]
+0x80,128,ENABLE,,FDEN,,,SMUXEN, WEN,,SP_EN,PON
+0x81,129,ATIME,,ATIME [7:0],ATIME [7:0],ATIME [7:0],ATIME [7:0],ATIME [7:0],ATIME [7:0],ATIME [7:0],ATIME [7:0]
+0x83,131,WTIME,,WTIME [7:0],WTIME [7:0],WTIME [7:0],WTIME [7:0],WTIME [7:0],WTIME [7:0],WTIME [7:0],WTIME [7:0]
+0x84,132,SP_LOW_TH_L,,SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0],SP_TH_L_LSB [7:0]
+0x85,133,SP_LOW_TH_H,,SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0],SP_TH_L_MSB [7:0]
+0x86,134,SP_HIGH_TH_L,,SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0],SP_TH_H_LSB [7:0]
+0x87,135,SP_HIGH_TH_H,,SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0],SP_TH_H_MSB [7:0]
+0x90,144,AUXID,,AUXID [7:0],AUXID [7:0],AUXID [7:0],AUXID [7:0],AUXID [7:0],AUXID [7:0],AUXID [7:0],AUXID [7:0]
+0x91,145,REVID,,REVID [7:0],REVID [7:0],REVID [7:0],REVID [7:0],REVID [7:0],REVID [7:0],REVID [7:0],REVID [7:0]
+0x92,146,ID,,ID [7:0],ID [7:0],ID [7:0],ID [7:0],ID [7:0],ID [7:0],ID [7:0],ID [7:0]
+0x93,147,STATUS,,ASAT,,,AINT,,FINT,CINT,SINT
+0x94,148,ASTATUS,,ASAT_STATUS,,,,AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0]
+0x95,149,CH0_DATA_L,,CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0]
+0x96,150,CH0_DATA_H,,CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0]
+0x97,151,CH1_DATA_L,,CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0],CH1_DATA_L [7:0]
+0x98,152,CH1_DATA_H,,CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0],CH1_DATA_H [7:0]
+0x99,153,CH2_DATA_L,,CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0],CH2_DATA_L [7:0]
+0x9A,154,CH2_DATA_H,,CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0],CH2_DATA_H [7:0]
+0x9B,155,CH3_DATA_L,,CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0],CH3_DATA_L [7:0]
+0x9C,156,CH3_DATA_H,,CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0],CH3_DATA_H [7:0]
+0x9D,157,CH4_DATA_L,,CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0],CH4_DATA_L [7:0]
+0x9E,158,CH4_DATA_H,,CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0],CH4_DATA_H [7:0]
+0x9F,159,CH5_DATA_L,,CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0],CH5_DATA_L [7:0]
+0xA0,160,CH5_DATA_H,,CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0],CH5_DATA_H [7:0]
+0xA3,163,STATUS 2,,,AVALID,,ASAT_DIG,ASAT_ ANA,,FDSAT_ANA,FDSAT_DIG
+0xA4,164,STATUS 3,,,,INT_SP_H,INT_SP_L,,,,
+0xA6,166,STATUS 5,,,,,,SINT_FD,,,
+0xA7,167,STATUS 6,,FIFO_OV,,OVTEMP,FD_TRIG,,SP_TRIG,SAI_ACT,INT_BUSY
+0xA9,169,CFG 0,,,,LOW_POWER,,REG_BANK,WLONG,,
+0xAA,170,CFG 1,,,,,,AGAIN[4:0],AGAIN[4:0],AGAIN[4:0],AGAIN[4:0]
+0xAC,172,CFG 3,,,,,SAI,,,,
+0xAF,175,CFG 6,,,,,SMUX_CMD[4:3],SMUX_CMD[4:3],,,
+0xB1,177,CFG 8,,FIFO_TH [7:6],FIFO_TH [7:6],,,FD_AGC,SP_AGC,,
+0xB2,178,CFG 9,,,SIEN_FD,,SIEN_SMUX,,,,
+0xB3,179,CFG 10,,AGC_H [7:6],AGC_L[7:6],,,,,FD_PERS [2:0],FD_PERS [2:0]
+0xB5,181,CFG 12,,,,,,,,SP_TH_CH [2:0],SP_TH_CH [2:0]
+0xBD,189,PERS,,,,,,APERS [3:0],APERS [3:0],APERS [3:0],APERS [3:0]
+0xBE,190,GPIO 2,,,,,,GPIO_INV,GPIO_IN,GPIO_OUT,GPIO_IN
+0xCA,202,ASTEP_L,,,,,ASTEP [7:0],,,,
+0xCB,203,ASTEP_H,,,,,ASTEP [15:8],,,,
+0xCF,207,AGC_GAIN_MAX,,AGC_FD_GAIN_MAX [7:4],AGC_FD_GAIN_MAX [7:4],AGC_FD_GAIN_MAX [7:4],AGC_FD_GAIN_MAX [7:4],AGC_AGAIN_MAX [3:0],AGC_AGAIN_MAX [3:0],AGC_AGAIN_MAX [3:0],AGC_AGAIN_MAX [3:0]
+0xD6,214,AZ_CONFIG,,,,,AT_NTH_ITERATION [7:0],,,,
+0xD8,216,FD_TIME 1,,,,,FD_TIME [7:0],,,,
+0xDA,218,FD_TIME 2,,FD_GAIN [7:3],,,,,FD_TIME [10:8],,
+0xD7,215,FD_CFG0,,FD_FIFO,FD_SAMPLES[6:5] *,FD_SAMPLES[6:5] *,,,,,
+0xDB,219,FD_STATUS,,,,FD_VALID,FD_SAT,FD_120HZ_VALID,FD_100Hz_VALID,FD_120Hz,FD_100Hz
+0xF9,249,INTENAB,,ASIEN,,,SP_IEN,,FIEN,CIEN,SIEN
+0xFA,250,CONTROL,,,,,,,AZ_SP_MAN,FIFO_CLR,CLEAR_SAI_ACT
+0xFC,252,FIFO_MAP,,FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1],ASTATUS
+0xFD,253,FIFO_LVL,,FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0],FIFO_LVL [7:0]
+0xFE,254,FDATA_L,,FDATA [7:0],FDATA [7:0],FDATA [7:0],FDATA [7:0],FDATA [7:0],FDATA [7:0],FDATA [7:0],FDATA [7:0]
+0xFF,255,FDATA_H,,FDATA [15:8],FDATA [15:8],FDATA [15:8],FDATA [15:8],FDATA [15:8],FDATA [15:8],FDATA [15:8],FDATA [15:8]

maps/as7341_cv.csv.compare

@@ -1,8 +1,4 @@
 ADDR (HEX),ADDR (DEC.),REGISTER NAME,SERIAL I/F,BIT7,BIT6,BIT5,BIT4,BIT3,BIT2,BIT1,BIT0
-8,8,REF_P_XL,R/W,REFL[7:0],REFL[7:0],REFL[7:0],REFL[7:0],REFL[7:0],REFL[7:0],REFL[7:0],REFL[7:0]
-9,9,REF_P_L,R/W,REFL[15:8],REFL[15:8],REFL[15:8],REFL[15:8],REFL[15:8],REFL[15:8],REFL[15:8],REFL[15:8]
-0A,10,REF_P_H,R/W,REFL[23:16],REFL[23:16],REFL[23:16],REFL[23:16],REFL[23:16],REFL[23:16],REFL[23:16],REFL[23:16]
-10,16,RES_CONF,R/W,,,,,AVGT1,AVGT0,AVGP1,AVGP0
 0x60,96,ASTATUS,,ASAT_STATUS,,,,AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0],AGAIN_STATUS [3:0]
 0x61,97,CH0_DATA_L ,,CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0],CH0_DATA_L [7:0]
 0x62,98,CH0_DATA_H,,CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0],CH0_DATA_H [7:0]