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Commits on Dec 15, 2021

• Rewritten arst conditions in cdc_strobe.sv

  pConst

  committed
  36f89f2

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Commits on Nov 18, 2021

• Added batch update script for your git repos

  pConst

  committed
  b91f6ad

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Commits on Nov 9, 2021

• Added recursive build script

  pConst

  committed
  937edbe

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• Quartus demands to split if conditions

  pConst

  committed
  29df4d5

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Commits on Nov 3, 2021

• Added Intel HLS scripts and boilerplate

  pConst

  committed
  2499f3a

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Commits on Nov 1, 2021

• Added Vivado quick project template

  pConst

  committed
  6c5ef36

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• Added testbench template

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  committed
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Commits on Oct 28, 2021

• Added more cleaning scripts

  pConst

  committed
  a80efe1

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• Added typical .gitignore-files for FPGA projects

  pConst

  committed
  39490ae

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• Added cleaning scripts

  pConst

  committed
  9203d17

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Commits on Oct 18, 2021

• Added scripts for back-annotate and git-merge

  pConst

  committed
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Commits on Sep 13, 2021

• SImplified reverse_vector.sv code

  pConst

  committed
  bcc548f

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Commits on Sep 11, 2021

• Updated cdc_strobe. Used gray counter under the hood

  pConst

  committed
  0e19b10

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Commits on Aug 18, 2021

• Added Vivado initialization code

  pConst

  committed
  261e056

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Commits on Aug 9, 2021

• Added exporting script for Vivado

  

  Konstantin Pavlov

  committed
  871c924

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Commits on Jul 29, 2021

• Updated version autoincrement script for Quartus

  

  Konstantin Pavlov

  committed
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Commits on Jul 28, 2021

• Added SMA and tb

  pConst

  committed
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Commits on Jul 18, 2021

• Added universal block RAM fifo

  pConst

  committed
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Commits on Jul 9, 2021

• Added soft_latch module and testbench

  pConst

  committed
  1efbd7c

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Commits on Jul 7, 2021

• Update README.md

  pConst

  authored
  d262582

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Commits on Jul 6, 2021

• Updated lifo module to support FWFT and normal modes

  pConst

  committed
  2845a2a

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Commits on Jul 5, 2021

• Added single clock fifo modules (two variants)

  pConst

  committed
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Commits on Jun 11, 2021

• Added synchronizer modules

  pConst

  committed
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Commits on Jun 3, 2021

• Added Vivado-specific scripts

  pConst

  committed
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Commits on May 27, 2021

• Added Modelsim cleaning script

  pConst

  committed
  48e9dde

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Commits on Apr 12, 2021

• Updated Quartus Makefile and the reference project

  pConst

  committed
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Commits on Feb 5, 2021

• Test project for iterative compilation Quartus projects

  pConst

  committed
  111dbc6

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• Added fast counter sources

  pConst

  committed
  3619810

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• Added Quartus Makefile. Customizable and gives faster compilation

  pConst

  committed
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Commits on Jan 27, 2021

• Added SV version of UART receiver

  pConst

  committed
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Commits on Jan 26, 2021

• Rewriting UART modules to SystemVerilog

  pConst

  committed
  536a8b8

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• Minor code style update

  pConst

  committed
  b4b191c

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• Moved all bencmarks to the separate directory

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  committed
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Commits on Dec 22, 2020

• Update README.md

  pConst

  authored
  1b84472

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Commits on Dec 18, 2020

• Added UART-like shifters for for simple synchronous messaging inside the FPGA or between FPGAs

  pConst

  committed
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