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aquynhaquynh
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directly update cs_insn from MCInst interface to avoid multiple memcpy()
1 parent 7566a2d commit 5329a6f

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7 files changed

+96
-116
lines changed

7 files changed

+96
-116
lines changed

‎MCInst.c

-5
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,6 @@ void MCInst_Init(cs_struct *handle, MCInst *inst)
1818
break;
1919
case CS_ARCH_X86:
2020
inst->size = 0;
21-
inst->flat_insn.x86.op_count = 0;
22-
if (handle->detail) {
23-
memset(inst->flat_insn.x86.prefix, 0, sizeof(inst->flat_insn.x86.prefix));
24-
memset(inst->flat_insn.x86.operands, 0, sizeof(inst->flat_insn.x86.operands));
25-
}
2621
break;
2722
}
2823
}

‎MCInst.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -143,9 +143,8 @@ struct MCInst {
143143
unsigned Opcode;
144144
MCOperand Operands[34];
145145
unsigned size; // number of operands
146-
cs_insn_flat flat_insn; // insn to be exposed to public
146+
cs_insn *flat_insn; // insn to be exposed to public
147147
unsigned OpcodePub;
148-
int insn_size; // instruction size
149148
uint64_t address; // address of this insn
150149
cs_struct *csh; // save the main csh
151150
uint8_t x86_imm_size; // save immediate size to print immediate properly

‎arch/X86/X86ATTInstPrinter.c

+29-29
Original file line numberDiff line numberDiff line change
@@ -275,17 +275,17 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
275275
}
276276

277277
if (MI->csh->detail) {
278-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
279-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = X86_REG_INVALID;
280-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = X86_REG_INVALID;
281-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = 1;
282-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
278+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
279+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
280+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
281+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
282+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
283283
}
284284

285285
if (MCOperand_isImm(DispSpec)) {
286286
int64_t imm = MCOperand_getImm(DispSpec);
287287
if (MI->csh->detail)
288-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
288+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
289289
if (imm < 0) {
290290
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
291291
} else {
@@ -299,7 +299,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
299299
SStream_concat0(O, markup(">"));
300300

301301
if (MI->csh->detail)
302-
MI->flat_insn.x86.op_count++;
302+
MI->flat_insn->detail->x86.op_count++;
303303
}
304304

305305
static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O)
@@ -332,7 +332,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
332332
{
333333
MCOperand *Op = MCInst_getOperand(MI, OpNo);
334334
if (MCOperand_isImm(Op)) {
335-
int64_t imm = MCOperand_getImm(Op) + MI->insn_size + MI->address;
335+
int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address;
336336
if (imm < 0) {
337337
if (imm < -HEX_THRESHOLD)
338338
SStream_concat(O, "-0x%"PRIx64, -imm);
@@ -349,9 +349,9 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
349349
SStream_concat(O, "%"PRIu64, imm);
350350
}
351351
if (MI->csh->detail) {
352-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
353-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
354-
MI->flat_insn.x86.op_count++;
352+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
353+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
354+
MI->flat_insn->detail->x86.op_count++;
355355
}
356356
}
357357
}
@@ -362,9 +362,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
362362
if (MCOperand_isReg(Op)) {
363363
printRegName(O, MCOperand_getReg(Op));
364364
if (MI->csh->detail) {
365-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_REG;
366-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].reg = MCOperand_getReg(Op);
367-
MI->flat_insn.x86.op_count++;
365+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
366+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = MCOperand_getReg(Op);
367+
MI->flat_insn->detail->x86.op_count++;
368368
}
369369
} else if (MCOperand_isImm(Op)) {
370370
// Print X86 immediates as signed values.
@@ -381,9 +381,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
381381
SStream_concat(O, "%s$-%"PRIu64"%s", markup("<imm:"), -imm, markup(">"));
382382
}
383383
if (MI->csh->detail) {
384-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
385-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
386-
MI->flat_insn.x86.op_count++;
384+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
385+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
386+
MI->flat_insn->detail->x86.op_count++;
387387
}
388388
}
389389
}
@@ -420,11 +420,11 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
420420
uint64_t ScaleVal;
421421

422422
if (MI->csh->detail) {
423-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
424-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
425-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
426-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = 1;
427-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
423+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
424+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = MCOperand_getReg(BaseReg);
425+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = MCOperand_getReg(IndexReg);
426+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
427+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
428428
}
429429

430430
SStream_concat0(O, markup("<mem:"));
@@ -438,7 +438,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
438438
if (MCOperand_isImm(DispSpec)) {
439439
int64_t DispVal = MCOperand_getImm(DispSpec);
440440
if (MI->csh->detail)
441-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal;
441+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
442442
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
443443
if (DispVal < 0) {
444444
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
@@ -462,7 +462,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
462462
_printOperand(MI, Op+2, O);
463463
ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
464464
if (MI->csh->detail)
465-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
465+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal;
466466
if (ScaleVal != 1) {
467467
SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">"));
468468
}
@@ -473,7 +473,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
473473
SStream_concat0(O, markup(">"));
474474

475475
if (MI->csh->detail)
476-
MI->flat_insn.x86.op_count++;
476+
MI->flat_insn->detail->x86.op_count++;
477477
}
478478

479479
#include "X86InstPrinter.h"
@@ -514,10 +514,10 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
514514
// add register operand
515515
for (i = 0;; i++) {
516516
// find the first empty slot to put it there
517-
if (MI->flat_insn.x86.operands[i].type == 0) {
518-
MI->flat_insn.x86.operands[i].type = X86_OP_REG;
519-
MI->flat_insn.x86.operands[i].reg = reg;
520-
MI->flat_insn.x86.op_count++;
517+
if (MI->flat_insn->detail->x86.operands[i].type == 0) {
518+
MI->flat_insn->detail->x86.operands[i].type = X86_OP_REG;
519+
MI->flat_insn->detail->x86.operands[i].reg = reg;
520+
MI->flat_insn->detail->x86.op_count++;
521521
break;
522522
}
523523
}

‎arch/X86/X86Disassembler.c

+17-17
Original file line numberDiff line numberDiff line change
@@ -660,35 +660,35 @@ static int reader(const struct reader_info *info, uint8_t *byte, uint64_t addres
660660
}
661661

662662
// copy x86 detail information from internal structure to public structure
663-
static void update_pub_insn(cs_insn_flat *pub, InternalInstruction *inter, uint8_t *prefixes)
663+
static void update_pub_insn(cs_insn *pub, InternalInstruction *inter, uint8_t *prefixes)
664664
{
665665
prefixes[0] = inter->prefix0;
666666
prefixes[1] = inter->prefix1;
667667
prefixes[2] = inter->prefix2;
668668
prefixes[3] = inter->prefix3;
669669

670-
pub->x86.segment = x86_map_segment(inter->segmentOverride);
670+
pub->detail->x86.segment = x86_map_segment(inter->segmentOverride);
671671

672672
if (inter->vectorExtensionType > 0)
673-
memcpy(pub->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->x86.opcode));
673+
memcpy(pub->detail->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->detail->x86.opcode));
674674
else {
675-
pub->x86.opcode[0] = inter->opcode;
676-
pub->x86.opcode[1] = inter->twoByteEscape;
677-
pub->x86.opcode[2] = inter->threeByteEscape;
675+
pub->detail->x86.opcode[0] = inter->opcode;
676+
pub->detail->x86.opcode[1] = inter->twoByteEscape;
677+
pub->detail->x86.opcode[2] = inter->threeByteEscape;
678678
}
679679

680-
pub->x86.op_size = inter->operandSize;
681-
pub->x86.addr_size = inter->addressSize;
682-
pub->x86.disp_size = inter->displacementSize;
683-
pub->x86.imm_size = inter->immediateSize;
680+
pub->detail->x86.op_size = inter->operandSize;
681+
pub->detail->x86.addr_size = inter->addressSize;
682+
pub->detail->x86.disp_size = inter->displacementSize;
683+
pub->detail->x86.imm_size = inter->immediateSize;
684684

685-
pub->x86.modrm = inter->orgModRM;
686-
pub->x86.sib = inter->sib;
687-
pub->x86.disp = inter->displacement;
685+
pub->detail->x86.modrm = inter->orgModRM;
686+
pub->detail->x86.sib = inter->sib;
687+
pub->detail->x86.disp = inter->displacement;
688688

689-
pub->x86.sib_index = x86_map_sib_index(inter->sibIndex);
690-
pub->x86.sib_scale = inter->sibScale;
691-
pub->x86.sib_base = x86_map_sib_base(inter->sibBase);
689+
pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex);
690+
pub->detail->x86.sib_scale = inter->sibScale;
691+
pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase);
692692
}
693693

694694
#define offsetof(st, member) __builtin_offsetof(st, member)
@@ -734,7 +734,7 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
734734
result = (!translateInstruction(instr, &insn)) ? true : false;
735735
if (result) {
736736
if (handle->detail)
737-
update_pub_insn(&instr->flat_insn, &insn, instr->x86_prefix);
737+
update_pub_insn(instr->flat_insn, &insn, instr->x86_prefix);
738738
else {
739739
// copy all prefixes
740740
instr->x86_prefix[0] = insn.prefix0;

‎arch/X86/X86IntelInstPrinter.c

+29-29
Original file line numberDiff line numberDiff line change
@@ -291,11 +291,11 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
291291
MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
292292

293293
if (MI->csh->detail) {
294-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
295-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = X86_REG_INVALID;
296-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = X86_REG_INVALID;
297-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = 1;
298-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
294+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
295+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
296+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
297+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
298+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
299299
}
300300

301301
// If this has a segment register, print it.
@@ -309,7 +309,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
309309
if (MCOperand_isImm(DispSpec)) {
310310
int64_t imm = MCOperand_getImm(DispSpec);
311311
if (MI->csh->detail)
312-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm;
312+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
313313
if (imm < 0) {
314314
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
315315
} else {
@@ -323,7 +323,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
323323
SStream_concat0(O, "]");
324324

325325
if (MI->csh->detail)
326-
MI->flat_insn.x86.op_count++;
326+
MI->flat_insn->detail->x86.op_count++;
327327
}
328328

329329
static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O)
@@ -374,11 +374,11 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
374374
reg = X86_insn_reg(MCInst_getOpcode(MI));
375375
if (reg) {
376376
// shift all the ops right to leave 1st slot for this new register op
377-
memmove(&(MI->flat_insn.x86.operands[1]), &(MI->flat_insn.x86.operands[0]),
378-
sizeof(MI->flat_insn.x86.operands[0]) * (ARR_SIZE(MI->flat_insn.x86.operands) - 1));
379-
MI->flat_insn.x86.operands[0].type = X86_OP_REG;
380-
MI->flat_insn.x86.operands[0].reg = reg;
381-
MI->flat_insn.x86.op_count++;
377+
memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]),
378+
sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1));
379+
MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG;
380+
MI->flat_insn->detail->x86.operands[0].reg = reg;
381+
MI->flat_insn->detail->x86.op_count++;
382382
}
383383

384384
}
@@ -390,7 +390,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
390390
{
391391
MCOperand *Op = MCInst_getOperand(MI, OpNo);
392392
if (MCOperand_isImm(Op)) {
393-
int64_t imm = MCOperand_getImm(Op) + MI->insn_size + MI->address;
393+
int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address;
394394
if (imm < 0) {
395395
if (imm < -HEX_THRESHOLD)
396396
SStream_concat(O, "-0x%"PRIx64, -imm);
@@ -407,9 +407,9 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
407407
SStream_concat(O, "%"PRIu64, imm);
408408
}
409409
if (MI->csh->detail) {
410-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
411-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
412-
MI->flat_insn.x86.op_count++;
410+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
411+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
412+
MI->flat_insn->detail->x86.op_count++;
413413
}
414414
}
415415
}
@@ -426,9 +426,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
426426
if (MCOperand_isReg(Op)) {
427427
printRegName(O, MCOperand_getReg(Op));
428428
if (MI->csh->detail) {
429-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_REG;
430-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].reg = MCOperand_getReg(Op);
431-
MI->flat_insn.x86.op_count++;
429+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
430+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = MCOperand_getReg(Op);
431+
MI->flat_insn->detail->x86.op_count++;
432432
}
433433
} else if (MCOperand_isImm(Op)) {
434434
int64_t imm = MCOperand_getImm(Op);
@@ -445,9 +445,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
445445
}
446446

447447
if (MI->csh->detail) {
448-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM;
449-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].imm = imm;
450-
MI->flat_insn.x86.op_count++;
448+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
449+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
450+
MI->flat_insn->detail->x86.op_count++;
451451
}
452452
}
453453
}
@@ -485,11 +485,11 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
485485
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
486486

487487
if (MI->csh->detail) {
488-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
489-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
490-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
491-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
492-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
488+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
489+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = MCOperand_getReg(BaseReg);
490+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = MCOperand_getReg(IndexReg);
491+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal;
492+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
493493
}
494494

495495
// If this has a segment register, print it.
@@ -519,7 +519,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
519519
} else {
520520
int64_t DispVal = MCOperand_getImm(DispSpec);
521521
if (MI->csh->detail)
522-
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal;
522+
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
523523
if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) {
524524
if (NeedPlus) {
525525
SStream_concat0(O, " + ");
@@ -539,7 +539,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
539539
SStream_concat0(O, "]");
540540

541541
if (MI->csh->detail)
542-
MI->flat_insn.x86.op_count++;
542+
MI->flat_insn->detail->x86.op_count++;
543543
}
544544

545545
#define PRINT_ALIAS_INSTR

‎arch/X86/X86Mapping.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -41984,7 +41984,7 @@ bool X86_lockrep(MCInst *MI, SStream *O)
4198441984

4198541985
// copy normalized prefix[] back to x86.prefix[]
4198641986
if (MI->csh->detail)
41987-
memcpy(MI->flat_insn.x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix));
41987+
memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix));
4198841988

4198941989
return res;
4199041990
}

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