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Sebastien Sikora
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Revised folder structure and moved demos to separate folder.
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‎demos_src/1_bit_register_demo.cpp

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#include "c_core.h" // Core simulator functionality
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#include "devices.h" // One_Bit_Register Device
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation sim("test_sim", verbose);
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// Add a 4-bit counter device.
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sim.AddComponent(new One_Bit_Register(&sim, "test_reg", monitor_on, {{"clr", true}, {"load", false}, {"d_in", false}}));
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim.Stabilise();
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// Add a Clock and connect it to the clk input on the register.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim.AddClock("clock_0", {false, true}, monitor_on);
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sim.ClockConnect("clock_0", "test_reg", "clk");
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// Add Probes connected to the clk, load and clear inputs of the register and one to it's data output.
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sim.AddProbe("reg_clk_input", "test_sim:test_reg", {"clk"}, "clock_0");
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sim.AddProbe("reg_clr_input", "test_sim:test_reg", {"clr"}, "clock_0");
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sim.AddProbe("reg_load_input", "test_sim:test_reg", {"load"}, "clock_0");
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sim.AddProbe("reg_data_output", "test_sim:test_reg", {"d_out"}, "clock_0");
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//sim.ChildSet("test_reg", "d_in", false);
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//sim.ChildSet("test_reg", "clr", true);
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//sim.ChildSet("test_reg", "load", false);
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sim.Run(3, true, verbose, false);
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sim.ChildSet("test_reg", "d_in", true);
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sim.ChildSet("test_reg", "load", true);
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sim.ChildSet("test_reg", "clr", false);
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sim.Run(2, false, verbose, false);
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sim.ChildSet("test_reg", "d_in", false);
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sim.ChildSet("test_reg", "load", false);
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sim.Run(4, false, verbose, false);
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sim.ChildSet("test_reg", "clr", true);
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sim.Run(2, false, verbose, false);
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sim.ChildSet("test_reg", "clr", false);
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sim.ChildSet("test_reg", "d_in", true);
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sim.Run(2, false, verbose, print_probe_samples);
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return 0;
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}
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‎demos_src/4_bit_counter_demo.cpp

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#include "c_core.h" // Core simulator functionality
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#include "devices.h" // Four_Bit_Counter Device
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation* sim = new Simulation("test_sim", verbose, {false, 1});
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// Add a 4-bit counter device.
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sim->AddComponent(new Four_Bit_Counter(sim, "test_counter", monitor_on, {{"run", true}}));
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// Add a Clock and connect it to the clk input on the counter.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim->AddClock("clock_0", {false, true}, monitor_on);
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sim->ClockConnect("clock_0", "test_counter", "clk");
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim->Stabilise();
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sim->ChildMakeProbable("test_counter");
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// Add two Probes and connect them to the counter's outputs and clk input.
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sim->AddProbe("clk_input", "test_sim:test_counter", {"clk"}, "clock_0");
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sim->AddProbe("counter_outputs", "test_sim:test_counter", {"q_0", "q_1", "q_2", "q_3"}, "clock_0");
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//~// Run the simulation for 33 ticks.
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//~sim->Run(17, true, verbose, false);
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//~sim->ChildSet("test_counter", "run", false);
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//~sim->Run(2, false, verbose, false);
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//~sim->ChildSet("test_counter", "run", true);
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sim->Run(33, true, verbose, print_probe_samples);
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//~std::cout << static_cast<Device*>(sim->SearchForComponentPointer("test_sim:test_counter"))->GetNestingLevel() << std::endl;
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delete sim;
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return 0;
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}
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‎demos_src/game_of_life_cell_demo.cpp

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#include <vector>
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#include <string>
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#include "c_core.h" // Core simulator functionality
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#include "devices.h"
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#include "game_of_life.h"
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#include "utils.h"
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation* sim = new Simulation("test_sim", verbose);
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sim->AddComponent(new GameOfLife_Cell(sim, "test_cell", monitor_on, {{"not_clear_cycle", true}, {"not_clear_state", true}, {"not_preset_state", true}}));
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim->Stabilise();
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// Add a Clock.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim->AddClock("clock_0", {false, true}, monitor_on);
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sim->ClockConnect("clock_0", "test_cell", "clk");
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// Add Probes.
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sim->AddProbe("counter_outputs", "test_sim:test_cell:counter", {"q_0", "q_1", "q_2", "q_3"}, "clock_0");
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sim->AddProbe("cell_siblings_out", "test_sim:test_cell", {"sibling_0_out", "sibling_0_out", "sibling_1_out", "sibling_2_out", "sibling_3_out", "sibling_4_out", "sibling_5_out", "sibling_6_out", "sibling_7_out"}, "clock_0");
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//~sim->AddProbe("selector_count", "test_sim:test_cell:selector:sibling_counter", {"q_0", "q_1", "q_2", "q_3"}, "clock_0");
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//~sim->AddProbe("selected_sibling", "test_sim:test_cell:selector", {"selected_sibling", "update_flag"}, "clock_0");
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//~sim->AddProbe("counter_run_in", "test_sim:test_cell:counter", {"run"}, "clock_0");
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// Possible sibling states.
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std::vector<std::vector<bool>> sibling_states = {};
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for (int i = 0; i < 9; i ++) {
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std::vector<bool> states = {};
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for (int j = 0; j < i; j ++) {
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states.push_back(true);
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}
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for (int j = i; j < 8; j ++) {
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states.push_back(false);
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}
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sibling_states.push_back(states);
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}
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// We will cycle through all the available sibling states, IE from all dead to all alive, for both cell starting states.
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// We will start with a 'dead' starting state.
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for (int sibling_count_index = 0; sibling_count_index < 9; sibling_count_index ++) {
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for (int k = 0; k < 8; k ++) {
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std::cout << sibling_states[sibling_count_index][k];
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}
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std::cout << std::endl;
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// Make sure Cell is 'dead' and reset.
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sim->ChildSet("test_cell", "not_clear_cycle", false);
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sim->ChildSet("test_cell", "not_clear_cycle", true);
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sim->ChildSet("test_cell", "not_clear_state", false);
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sim->ChildSet("test_cell", "not_clear_state", true);
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// Now set sibling inputs.
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for (int pin_index = 0; pin_index < 8; pin_index ++) {
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std::string sibling_input_name = "sibling_" + std::to_string(pin_index) + "_in";
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sim->ChildSet("test_cell", sibling_input_name, sibling_states[sibling_count_index][pin_index]);
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}
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// Now run for 18 ticks to integrate the sibling inputs and get the new Cell state.
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sim->Run(18, true, verbose, print_probe_samples, false);
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}
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// Now we sweep through all possible sibling states with an initial 'alive' state.
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for (int sibling_count_index = 0; sibling_count_index < 9; sibling_count_index ++) {
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for (int k = 0; k < 8; k ++) {
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std::cout << sibling_states[sibling_count_index][k];
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}
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std::cout << std::endl;
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// Make sure Cell is 'alive' and reset.
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sim->ChildSet("test_cell", "not_clear_cycle", false);
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sim->ChildSet("test_cell", "not_clear_cycle", true);
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sim->ChildSet("test_cell", "not_preset_state", false);
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sim->ChildSet("test_cell", "not_preset_state", true);
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// Now set sibling inputs.
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for (int pin_index = 0; pin_index < 8; pin_index ++) {
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std::string sibling_input_name = "sibling_" + std::to_string(pin_index) + "_in";
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sim->ChildSet("test_cell", sibling_input_name, sibling_states[sibling_count_index][pin_index]);
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}
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// Now run for 18 ticks to integrate the sibling inputs and get the new Cell state.
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sim->Run(18, true, verbose, print_probe_samples, false);
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}
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delete sim;
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return 0;
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}

‎demos_src/gol_cell_descision_demo.cpp

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#include <iostream>
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#include "c_core.h" // Core simulator functionality
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#include "devices.h"
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#include "game_of_life.h"
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#include "utils.h"
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation* sim = new Simulation("test_sim", verbose);
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sim->AddComponent(new GameOfLife_Cell_Decider(sim, "test_decider", monitor_on));
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim->Stabilise();
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// Add a Clock.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim->AddClock("clock_0", {false, true}, monitor_on);
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// Add Probes.
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sim->AddProbe("decider_alive_in", "test_sim:test_decider", {"alive_in"}, "clock_0");
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sim->AddProbe("decider_count_in", "test_sim:test_decider", {"count_in_0", "count_in_1", "count_in_2"}, "clock_0");
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sim->AddProbe("decider_alive_out", "test_sim:test_decider", {"alive_out"}, "clock_0");
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std::vector<bool> prior_state = {false, true};
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for (const auto& this_state : prior_state) {
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sim->ChildSet("test_decider", "alive_in", this_state);
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for (int value = 0; value < 8; value ++) {
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std::vector<bool> counter_outputs = IntToStates(value, 3);
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for (int output_index = 0; output_index < 3; output_index ++) {
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std::string count_pin_name = "count_in_" + std::to_string(output_index);
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sim->ChildSet("test_decider", count_pin_name, counter_outputs[output_index]);
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}
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if ((value == 0) && (!this_state)) {
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sim->Run(1, true, verbose, false);
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} else if ((value == 7) && (this_state)) {
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sim->Run(1, false, verbose, print_probe_samples);
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} else {
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sim->Run(1, false, verbose, false);
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}
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}
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}
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delete sim;
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return 0;
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}

‎demos_src/gol_cell_sibling_selector_demo.cpp

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#include "c_core.h" // Core simulator functionality
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#include "devices.h"
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#include "game_of_life.h"
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#include "utils.h"
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation* sim = new Simulation("test_sim", verbose);
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sim->AddComponent(new GameOfLife_Cell_SiblingSelector(sim, "test_selector", monitor_on, {{"not_clear", true}}));
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim->Stabilise();
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// Add a Clock.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim->AddClock("clock_0", {false, true}, monitor_on);
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sim->ClockConnect("clock_0", "test_selector", "clk");
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// Add Probes.
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sim->AddProbe("siblings_in", "test_sim:test_selector", {"sibling_0", "sibling_1", "sibling_2", "sibling_3", "sibling_4", "sibling_5", "sibling_6", "sibling_7"}, "clock_0");
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sim->AddProbe("selected_sibling", "test_sim:test_selector", {"selected_sibling"}, "clock_0");
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sim->AddProbe("update_flag", "test_sim:test_selector", {"update_flag"}, "clock_0");
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sim->ChildSet("test_selector", "sibling_0", true);
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sim->ChildSet("test_selector", "sibling_1", false);
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sim->ChildSet("test_selector", "sibling_2", true);
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sim->ChildSet("test_selector", "sibling_3", false);
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sim->ChildSet("test_selector", "sibling_4", true);
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sim->ChildSet("test_selector", "sibling_5", false);
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sim->ChildSet("test_selector", "sibling_6", true);
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sim->ChildSet("test_selector", "sibling_7", false);
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sim->ChildSet("test_selector", "not_clear", false);
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sim->ChildSet("test_selector", "not_clear", true);
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sim->Run(20, true, verbose, print_probe_samples);
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delete sim;
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return 0;
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}

‎demos_src/jk_ff_aspc_demo.cpp

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#include "c_core.h" // Core simulator functionality
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#include "devices.h" // JK flip-flop Device
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = false;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation sim("test_sim", verbose);
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// Add a jk flip-flop Device.
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sim.AddComponent(new JK_FF_ASPC(&sim, "test_ff", monitor_on, {{"j", false}, {"k", false}, {"not_p", true}, {"not_c", true}}));
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim.Stabilise();
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// Add a Clock and connect it to the clk input on the jk flip-flop.
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// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim.AddClock("clock_0", {false, true}, monitor_on);
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sim.ClockConnect("clock_0", "test_ff", "clk");
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// Add two Probes and connect them to the jk flip-flop's outputs and clk input.
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sim.AddProbe("flip-flop outputs", "test_sim:test_ff", {"q", "not_q"}, "clock_0");
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sim.AddProbe("flip-flop clk input", "test_sim:test_ff", {"clk"}, "clock_0");
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sim.Run(1, true, verbose, false);
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sim.ChildSet("test_ff", "not_c", false);
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sim.ChildSet("test_ff", "not_c", true);
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sim.Run(1, false, verbose, false);
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sim.ChildSet("test_ff", "not_p", false);
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sim.ChildSet("test_ff", "not_p", true);
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sim.Run(1, false, verbose, false);
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// Run the simulation for ten ticks.
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sim.ChildSet("test_ff", "j", true);
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sim.ChildSet("test_ff", "k", true);
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sim.Run(10, false, verbose, print_probe_samples);
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return 0;
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}

‎demos_src/jk_ff_demo.cpp

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#include "c_core.h" // Core simulator functionality
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#include "devices.h" // JK flip-flop Device
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int main () {
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// Verbosity flags. Set verbose & monitor_on equal to true to display verbose simulation output in the console.
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bool verbose = true;
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bool monitor_on = false;
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bool print_probe_samples = true;
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// Instantiate the top-level Device (the Simulation).
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Simulation sim("test_sim", verbose);
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// Add a jk flip-flop Device.
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sim.AddComponent(new JK_FF(&sim, "test_ff", monitor_on, {{"j", true}, {"k", true}}));
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// We could leave out the default in pin state vector argument, and instead connect 'j' and 'k' in pins
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// to the Simulation's 'true' hidden in pin...
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//~sim.Connect("true", "test_ff", "j");
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//~sim.Connect("true", "test_ff", "k");
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// ...or we could set the pin states manually.
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//~sim.ChildSet("test_ff", "j", true);
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//~sim.ChildSet("test_ff", "k", true);
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// Once we have added all our devices, call the simulation's Stabilise() method to finish setup.
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sim.Stabilise();
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//~// Add a Clock and connect it to the clk input on the jk flip-flop.
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//~// The Clock output will be a repeating pattern of false, true, false, true, etc, starting on false on the first tick.
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sim.AddClock("clock_0", {false, true}, monitor_on);
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sim.ClockConnect("clock_0", "test_ff", "clk");
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//~// Add two Probes and connect them to the jk flip-flop's outputs and clk input.
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//~// Note - we need to use the target Component's 'full name' to connect a Probe.
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sim.AddProbe("flip-flop outputs", "test_sim:test_ff", {"q", "not_q"}, "clock_0");
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sim.AddProbe("flip-flop clk input", "test_sim:test_ff", {"clk"}, "clock_0");
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//~// Run the simulation for ten ticks.
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sim.Run(3, true, verbose, print_probe_samples);
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return 0;
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}

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