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fix returndatacopy and state test #582

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Jun 30, 2023
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12 changes: 7 additions & 5 deletions bus-mapping/src/circuit_input_builder/input_state_ref.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2033,12 +2033,13 @@ impl<'a> CircuitInputStateRef<'a> {
dst_addr: u64, // memory dest starting addr
copy_length: u64, // number of bytes to copy, without padding
memory_updated: Memory,
) -> Result<(CopyEventSteps, CopyEventSteps), Error> {
) -> Result<(CopyEventSteps, CopyEventSteps, Vec<u8>), Error> {
let mut read_steps = Vec::with_capacity(copy_length as usize);
let mut write_steps = Vec::with_capacity(copy_length as usize);
let mut prev_bytes: Vec<u8> = vec![];

if copy_length == 0 {
return Ok((read_steps, write_steps));
return Ok((read_steps, write_steps, prev_bytes));
}

let last_callee_id = self.call()?.last_callee_id;
Expand Down Expand Up @@ -2095,8 +2096,9 @@ impl<'a> CircuitInputStateRef<'a> {
src_chunk_index += 32;

let write_word = Word::from_big_endian(write_chunk);
self.memory_write_word(exec_step, dst_chunk_index.into(), write_word)?;

let mut prev_bytes_write =
self.memory_write_word_prev_bytes(exec_step, dst_chunk_index.into(), write_word)?;
prev_bytes.append(&mut prev_bytes_write);
trace!("write chunk: {current_call_id} {dst_chunk_index} {write_chunk:?}");
dst_chunk_index += 32;

Expand Down Expand Up @@ -2125,7 +2127,7 @@ impl<'a> CircuitInputStateRef<'a> {
write_slot_bytes.len()
);

Ok((read_steps, write_steps))
Ok((read_steps, write_steps, prev_bytes))
}

pub(crate) fn gen_copy_steps_for_log(
Expand Down
4 changes: 2 additions & 2 deletions bus-mapping/src/evm/opcodes/returndatacopy.rs
Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ fn gen_copy_event(
last_callee_return_data_offset + last_callee_return_data_length,
);

let (read_steps, write_steps) = state.gen_copy_steps_for_return_data(
let (read_steps, write_steps, prev_bytes) = state.gen_copy_steps_for_return_data(
exec_step,
src_addr,
src_addr_end,
Expand All @@ -126,7 +126,7 @@ fn gen_copy_event(
dst_addr,
log_id: None,
rw_counter_start,
copy_bytes: CopyBytes::new(read_steps, Some(write_steps), None),
copy_bytes: CopyBytes::new(read_steps, Some(write_steps), Some(prev_bytes)),
})
}

Expand Down
23 changes: 14 additions & 9 deletions zkevm-circuits/src/state_circuit/test.rs
Original file line number Diff line number Diff line change
Expand Up @@ -97,23 +97,23 @@ fn state_circuit_simple_2() {
let memory_op_0 = Operation::new(
RWCounter::from(12),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 0.into()),
);
let memory_op_1 = Operation::new(
RWCounter::from(24),
RW::READ,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 32.into()),
);

let memory_op_2 = Operation::new(
RWCounter::from(17),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(1), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(1), 32.into(), 0.into()),
);
let memory_op_3 = Operation::new(
RWCounter::from(87),
RW::READ,
MemoryWordOp::new(1, MemoryAddress::from(1), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(1), 32.into(), 32.into()),
);

let stack_op_0 = Operation::new(
Expand Down Expand Up @@ -176,12 +176,12 @@ fn state_circuit_simple_6() {
let memory_op_0 = Operation::new(
RWCounter::from(12),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 0.into()),
);
let memory_op_1 = Operation::new(
RWCounter::from(13),
RW::READ,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 32.into()),
);
let storage_op_2 = Operation::new(
RWCounter::from(19),
Expand All @@ -203,7 +203,7 @@ fn lexicographic_ordering_test_1() {
let memory_op = Operation::new(
RWCounter::from(12),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 0.into()),
);
let storage_op = Operation::new(
RWCounter::from(19),
Expand All @@ -225,12 +225,12 @@ fn lexicographic_ordering_test_2() {
let memory_op_0 = Operation::new(
RWCounter::from(12),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 0.into()),
);
let memory_op_1 = Operation::new(
RWCounter::from(13),
RW::WRITE,
MemoryWordOp::new(1, MemoryAddress::from(0), 32.into()),
MemoryWordOp::new_write(1, MemoryAddress::from(0), 32.into(), 32.into()),
);
test_state_circuit_ok(vec![memory_op_0, memory_op_1], vec![], vec![]);
}
Expand Down Expand Up @@ -479,6 +479,7 @@ fn nonlexicographic_order_tag() {
call_id: 1,
memory_address: 10,
value: 12.into(),
value_prev: 0.into(),
};
let second = Rw::CallContext {
rw_counter: 2,
Expand Down Expand Up @@ -678,13 +679,15 @@ fn read_inconsistency() {
call_id: 1,
memory_address: 10,
value: 0.into(),
value_prev: 0.into(),
},
Rw::MemoryWord {
rw_counter: 40,
is_write: false,
call_id: 1,
memory_address: 10,
value: 200.into(),
value_prev: 0.into(),
},
];

Expand Down Expand Up @@ -722,6 +725,7 @@ fn invalid_memory_address() {
call_id: 1,
memory_address: 1u64 << 32,
value: 12.into(),
value_prev: 0.into(),
}];

assert_error_matches(verify(rows), "memory address fits into 2 limbs");
Expand All @@ -735,6 +739,7 @@ fn bad_initial_memory_value() {
call_id: 1,
memory_address: 10,
value: 0.into(),
value_prev: 0.into(),
}];

let v = Fr::from(200);
Expand Down