Fix the bugs in RLP/Tx/PI circuit which are reported by Zellic & KALOS auditors

[kunxian-xia]

Description

This PR aims to fix all the bugs found by Zellic auditors in RLP & Tx & PI circuits.

Issue Link

The bug report can be found here.

Type of change

• Bug fix (non-breaking change which fixes an issue)

Contents

1. finding 3: Fix finding 3 #575
2. finding 4: Fix zellic finding 4 #576
3. finding 5: Fix zellic finding 5 #584
4. finding 6: Fix zellic finding 6 #586
5. finding 7: Fix Zellic & Kalos finding 7 #625
6. finding 10: Fix finding 10 #578
7. finding 11: Fix finding 11 : use length for rlc in rlp table #719
8. finding 13: Fix finding 13 #579
9. finding 14: Fix zellic finding 14 #580
10. finding 17: Fix finding 17 #602
11. tx & pi: Fix the bugs in Tx & PI circuits reported by Zellic & KALOS auditors #612

[icemelon]

Could you keep 1 PR per finding?

[kunxian-xia]

What about 1 commit per finding? Because each fix can be done within about 10 lines of codes.

[icemelon]

No, still better to have one PR per finding. after merged, it'll become 1 commit per fix

[lispc]

ComparatorChip needs a u8 column now in develop. Codes here can be refactored

impl<F: Field, const N_BYTES: usize> ComparatorChip<F, N_BYTES> {
    /// Configure the comparator chip. Returns the config.
    pub fn configure(
        meta: &mut ConstraintSystem<F>,
        q_enable: impl FnOnce(&mut VirtualCells<F>) -> Expression<F> + Clone,
        lhs: impl FnOnce(&mut VirtualCells<F>) -> Expression<F> + Clone,
        rhs: impl FnOnce(&mut VirtualCells<F>) -> Expression<F> + Clone,
        u8_table: TableColumn,
    ) -> ComparatorConfig<F, N_BYTES> {

[lispc]

great. we can mark the asana board to mark them all done

[lispc]

let us merge it after CI passes