diff --git a/chisel-book.tex b/chisel-book.tex
index 4952d2f..e28a7fd 100644
--- a/chisel-book.tex
+++ b/chisel-book.tex
@@ -361,11 +361,12 @@ \section*{Foreword for the Sixth Edition}
 
 \todo{VHDL and SV}
 
-Chisel formal (if finished).
 
 We extended the testing chapter with a description how to access internal signals. \todo{That is too
 little to be mentioned here. More is needed.}
 
+Assertions and Chisel formal (if finished).
+
 We tested the book with following Chisel Versions: 3.5.6, 3.6.0, and 5.1.0.
 \todo{5.1.0 fails on memory loading....}
 Chisel version 6.0.0-RC1 is not supported by the latest ChiselTest version.
diff --git a/slides/07_fsmd.tex b/slides/07_fsmd.tex
index 4c7dd39..bef32b0 100644
--- a/slides/07_fsmd.tex
+++ b/slides/07_fsmd.tex
@@ -17,20 +17,6 @@
 
 
 
-\begin{frame}[fragile]{ChatGPT and Copilot (again)}
-\begin{itemize}
-\item ChatGPT and Copilot are allowed!
-\begin{itemize}
-\item In this course
-\item For coding
-\item And for improving your report writing
-\item In case you want to use it
-\end{itemize}
-\item You are still responsible for the code and text
-\item Write in the preface if you used it
-\item Write a section on reflecting the usage
-\end{itemize}
-\end{frame}
 
 \begin{frame}[fragile]{Overview}
 \begin{itemize}
@@ -43,8 +29,6 @@
 \end{itemize}
 \end{frame}
 
-
-
 \begin{frame}[fragile]{Last Lab}
 \begin{itemize}
 \item A table to describe a 7-segment decoder and drive it
@@ -54,6 +38,17 @@
 \end{itemize}
 \end{frame}
 
+\begin{frame}[fragile]{TinyTapeout}
+\begin{itemize}
+\item Do a \emph{real} chip within DE 2
+\item a multi-project waver (within a multi-project waver)
+\item I can pay a few projects
+\item \href{https://tinytapeout.com/}{TinyTapeout}
+\item \href{https://github.com/schoeberl/tt04-chisel-demo}{Chisel template}
+\end{itemize}
+\end{frame}
+
+
 \begin{frame}[fragile]{Vectors}
 \begin{itemize}
 \item A powerful abstraction
@@ -234,7 +229,7 @@
 \begin{itemize}
 \item 20' break
 \item We are half way through the course
-\item Therefore, a midterm \href{https://docs.google.com/forms/d/e/1FAIpQLSd93nSVDE-sk75GtU3OgMB0TI7HxVB5i3KlDu0YILb39WMdIw/viewform?usp=sf_link}{evaluation}
+\item Therefore, a midterm \href{https://docs.google.com/forms/d/e/1FAIpQLSeG8Xx_CzV8667XW9J90nYniskKuNI6k1FrfsSsEyXkH8O4tg/viewform?usp=sf_link}{evaluation}
 \item Send also on Slack (from the slide sources or the website)
 \end{itemize}
 \end{frame}
@@ -371,6 +366,7 @@
 \item First flip-flop may become metastable
 \item But will resolve within the clock period
 \end{itemize}
+\item Input can arrive at different clock cycles at different places
 \end{itemize}
 \end{frame}
 
@@ -447,7 +443,7 @@
 \item Counters are used to generate timing
 \item An FSM can control a datapath, which is an FSMD
 \item An FSMD is a computing machine
-\item Functions to structure your code
+\item Input needs to be processed (synchronize, maybe debounce)
 \end{itemize}
 \end{frame}
 
diff --git a/slides/08_refactor.tex b/slides/08_refactor.tex
index 4e154e1..f736f12 100644
--- a/slides/08_refactor.tex
+++ b/slides/08_refactor.tex
@@ -15,6 +15,18 @@
 \titlepage
 \end{frame}
 
+\begin{frame}[fragile]{TODO}
+\begin{itemize}
+\item ChipDay
+\item Following TOD must not be in week 8, can be later as well
+\item TODO: more from the mid-term eval, e.g., \emph{Potentially utilizing some more memory (BRAM) or potentially some of the hardware interfaces which the Basys 3 Board provides, such as USB and VGA.} This might be in week 11 with serial port. Or I move more stuff into week 10.
+\item TODO: FIFO as example of the ready valid thing (next week)
+\item TODO: FPGA internals
+\item TODO: A bit more about the physical chip design/architechture. When a chip is shown and referes to, and i have no idea what im looking at, its a bit difficult to follow along.
+
+\end{itemize}
+\end{frame}
+
 \begin{frame}[fragile]{Outline}
 \begin{itemize}
 \item Invited talk by Martine
diff --git a/slides/11_interface.tex b/slides/11_interface.tex
index ab9a15d..1f62b3d 100644
--- a/slides/11_interface.tex
+++ b/slides/11_interface.tex
@@ -18,15 +18,12 @@
 
 \begin{frame}[fragile]{Overview}
 \begin{itemize}
-%\item TODO: more from the mid-term eval, e.g., \emph{Potentially utilizing some more memory (BRAM) or potentially some of the hardware interfaces which the Basys 3 Board provides, such as USB and VGA.} This might be in week 11 with serial port. Or I move more stuff into week 10.
-%\item TODO: FIFO as example of the ready valid thing (next week)
-%\item TODO: FPGA internals
-%\item TODO: A bit more about the physical chip design/architechture. When a chip is shown and referes to, and i have no idea what im looking at, its a bit difficult to follow along.
-%\item Repeat FSMD (for the vending machine)
-%\begin{itemize}
-%\item I have seen some intermix of FSM and datapath
-%\item Works only for small designs
-%\end{itemize}
+\item TODO: Add ad for Luca's course
+\item Repeat FSMD (for the vending machine)
+\begin{itemize}
+\item I have seen some intermix of FSM and datapath
+\item Works only for small designs
+\end{itemize}
 \item Quick reminder on FSMD
 \item Interfaces
 \item Memory (intern and extern)