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lines changed Original file line number Diff line number Diff line change @@ -134,6 +134,22 @@ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
134134 c -> div = div << PWM_CH0_DIV_INT_LSB ;
135135}
136136
137+ /** \brief Set PWM clock divider in a PWM configuration using an 8:4 fractional value
138+ * \ingroup hardware_pwm
139+ *
140+ * \param c PWM configuration struct to modify
141+ * \param integer 8 bit integer part of the clock divider. Must be greater than or equal to 1.
142+ * \param fract 4 bit fractional part of the clock divider
143+ *
144+ * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
145+ * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
146+ * before passing them on to the PWM counter.
147+ */
148+ static inline void pwm_config_set_clkdiv_int_frac (pwm_config * c , uint8_t integer , uint8_t fract ) {
149+ valid_params_if (PWM , fract < 16 );
150+ c -> div = (((uint )integer ) << PWM_CH0_DIV_INT_LSB ) | (((uint )fract ) << PWM_CH0_DIV_FRAC_LSB );
151+ }
152+
137153/** \brief Set PWM counting mode in a PWM configuration
138154 * \ingroup hardware_pwm
139155 *
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