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Piyush Mehtaaxboe
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ata: ahci: ceva: Update the driver to support xilinx GT phy
SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can be used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for the SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Added cevapriv->rst check, for backward compatibility with the older sequence. If the reset controller is not available, then the SATA controller will configure with the older sequences. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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drivers/ata/ahci_ceva.c

Lines changed: 40 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include <linux/module.h>
1313
#include <linux/of_device.h>
1414
#include <linux/platform_device.h>
15+
#include <linux/reset.h>
1516
#include "ahci.h"
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/* Vendor Specific Register Offsets */
@@ -87,6 +88,7 @@ struct ceva_ahci_priv {
8788
u32 axicc;
8889
bool is_cci_enabled;
8990
int flags;
91+
struct reset_control *rst;
9092
};
9193

9294
static unsigned int ceva_ahci_read_id(struct ata_device *dev,
@@ -202,13 +204,48 @@ static int ceva_ahci_probe(struct platform_device *pdev)
202204

203205
cevapriv->ahci_pdev = pdev;
204206

207+
cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
208+
NULL);
209+
if (IS_ERR(cevapriv->rst)) {
210+
if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
211+
dev_err(&pdev->dev, "failed to get reset: %ld\n",
212+
PTR_ERR(cevapriv->rst));
213+
}
214+
205215
hpriv = ahci_platform_get_resources(pdev, 0);
206216
if (IS_ERR(hpriv))
207217
return PTR_ERR(hpriv);
208218

209-
rc = ahci_platform_enable_resources(hpriv);
210-
if (rc)
211-
return rc;
219+
if (!cevapriv->rst) {
220+
rc = ahci_platform_enable_resources(hpriv);
221+
if (rc)
222+
return rc;
223+
} else {
224+
int i;
225+
226+
rc = ahci_platform_enable_clks(hpriv);
227+
if (rc)
228+
return rc;
229+
/* Assert the controller reset */
230+
reset_control_assert(cevapriv->rst);
231+
232+
for (i = 0; i < hpriv->nports; i++) {
233+
rc = phy_init(hpriv->phys[i]);
234+
if (rc)
235+
return rc;
236+
}
237+
238+
/* De-assert the controller reset */
239+
reset_control_deassert(cevapriv->rst);
240+
241+
for (i = 0; i < hpriv->nports; i++) {
242+
rc = phy_power_on(hpriv->phys[i]);
243+
if (rc) {
244+
phy_exit(hpriv->phys[i]);
245+
return rc;
246+
}
247+
}
248+
}
212249

213250
if (of_property_read_bool(np, "ceva,broken-gen2"))
214251
cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;

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