Rename CRG module

Author: sam210723

sim/ltc/crg.v renamed to sim/ltc/reset_gen.v

@@ -2,15 +2,15 @@
  * Generates synchronous RESET signal after 16 clock cycles
  */
 
-module crg(
+module reset_gen(
     input  wire clk,
-    output wire rst_n
+    output wire reset_n
 );
 
     reg [15:0] x = 16'h0000;
     always @(posedge clk)
         x <= {x[14:0], 1'b1};
 
-    assign rst_n = x[15];
+    assign reset_n = x[15];
 
 endmodule;

sim/ltc/top.v

@@ -1,3 +1,7 @@
+/**
+ * SMPTE 12M Linear Timecode (LTC) Generator
+ */
+
 module top(
     input  wire clk,
     output wire ltc
@@ -39,11 +43,11 @@ module top(
     reg [79:0] frame;
     reg        out;
 
-    wire rst_n;
-    crg reset(clk, rst_n);
+    wire reset_n;
+    reset_gen crg(clk, reset_n);
 
     always @(posedge clk) begin
-        if (rst_n) begin
+        if (reset_n) begin
             out <= ~out;
         end
     end