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‎GhidraESP8266_2/.gitignore‎

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bin
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.ant*.xml
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.settings
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.classpath
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.project

‎GhidraESP8266_2/Module.manifest‎

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‎GhidraESP8266_2/build.gradle‎

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// Builds a Ghidra Extension for a given Ghidra installation.
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//
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// An absolute path to the Ghidra installation directory must be supplied either by setting the
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// GHIDRA_INSTALL_DIR environment variable or Gradle project property:
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//
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// > export GHIDRA_INSTALL_DIR=<Absolute path to Ghidra>
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// > gradle
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//
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// or
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//
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// > gradle -PGHIDRA_INSTALL_DIR=<Absolute path to Ghidra>
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//
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// Gradle should be invoked from the directory of the project to build. Please see the
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// application.gradle.version property in <GHIDRA_INSTALL_DIR>/Ghidra/application.properties
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// for the correction version of Gradle to use for the Ghidra installation you specify.
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//----------------------START "DO NOT MODIFY" SECTION------------------------------
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def ghidraInstallDir
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if (System.env.GHIDRA_INSTALL_DIR) {
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ghidraInstallDir = System.env.GHIDRA_INSTALL_DIR
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}
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else if (project.hasProperty("GHIDRA_INSTALL_DIR")) {
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ghidraInstallDir = project.getProperty("GHIDRA_INSTALL_DIR")
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}
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if (ghidraInstallDir) {
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apply from: new File(ghidraInstallDir).getCanonicalPath() + "/support/buildExtension.gradle"
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}
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else {
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throw new GradleException("GHIDRA_INSTALL_DIR is not defined!")
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}
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//----------------------END "DO NOT MODIFY" SECTION-------------------------------

‎GhidraESP8266_2/data/README.txt‎

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The "data" directory is intended to hold data files that will be used by this module and will
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not end up in the .jar file, but will be present in the zip or tar file. Typically, data
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files are placed here rather than in the resources directory if the user may need to edit them.
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An optional data/languages directory can exist for the purpose of containing various Sleigh language
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specification files and importer opinion files.
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The data/build.xml is used for building the contents of the data/languages directory.
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The skel language definition has been commented-out within the skel.ldefs file so that the
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skeleton language does not show-up within Ghidra.
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See the Sleigh language documentation (docs/languages/sleigh.htm or sleigh.pdf) for details
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on Sleigh language specification syntax.
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‎GhidraESP8266_2/data/build.xml‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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+ Compile sleigh languages within this module.
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+ Sleigh compiler options are read from the sleighArgs.txt file.
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+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
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-->
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<project name="privateBuildDeveloper" default="sleighCompile">
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<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
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<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
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<import file="../.antProperties.xml" optional="false" />
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<target name="sleighCompile">
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<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
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<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>
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<path id="sleigh.class.path">
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<fileset dir="${framework.path}/SoftwareModeling/lib">
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<include name="*.jar"/>
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</fileset>
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<fileset dir="${framework.path}/Generic/lib">
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<include name="*.jar"/>
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</fileset>
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<fileset dir="${framework.path}/Utility/lib">
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<include name="*.jar"/>
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</fileset>
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</path>
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<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
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<fail unless="sleigh.compile.exists" />
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<java classname="${sleigh.compile.class}"
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classpathref="sleigh.class.path"
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fork="true"
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failonerror="true">
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<jvmarg value="-Xmx2048M"/>
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<arg value="-i"/>
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<arg value="sleighArgs.txt"/>
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<arg value="-a"/>
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<arg value="./languages"/>
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</java>
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</target>
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</project>

‎GhidraESP8266_2/data/languages/skel.cspec‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->
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<compiler_spec>
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<data_organization>
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<pointer_size value="2" />
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</data_organization>
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<global>
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<range space="ram"/>
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<range space="io"/>
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</global>
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<stackpointer register="SP" space="ram"/>
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<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
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<baseop code="INT_ZEXT"/>
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<baseop code="INT_LEFT" value="12"/>
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<innerop code="INT_ZEXT"/>
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<constresolve>
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<register name="rBBR"/>
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</constresolve>
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</segmentop>
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<default_proto>
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<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
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<input>
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<pentry minsize="1" maxsize="1">
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<register name="A"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="BC"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="HL"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="DE"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IY"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IX"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="2">
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<addr offset="2" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="1">
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<register name="A"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>
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<register name="BC_"/>
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<register name="HL_"/>
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<register name="DE_"/>
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<register name="AF_"/>
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<register name="rBBR"/>
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</unaffected>
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</prototype>
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</default_proto>
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<prototype name="__asmAF" extrapop="2" stackshift="2" strategy="register">
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<input>
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<pentry minsize="1" maxsize="1">
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<register name="A"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="BC"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="HL"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="DE"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IY"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="IX"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="2">
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<addr offset="2" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="2">
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<register name="AF"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>
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<register name="rBBR"/>
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<register name="BC_"/>
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<register name="HL_"/>
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<register name="DE_"/>
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<register name="AF_"/>
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</unaffected>
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</prototype>
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<prototype name="__stdcall" extrapop="2" stackshift="2">
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<input>
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<pentry minsize="1" maxsize="1">
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<register name="A"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="BC"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="HL"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="2">
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<addr offset="2" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="1">
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<register name="AF"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>
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<register name="rBBR"/>
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<register name="BC_"/>
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<register name="HL_"/>
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<register name="DE_"/>
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<register name="AF_"/>
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</unaffected>
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</prototype>
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</compiler_spec>

‎GhidraESP8266_2/data/languages/skel.ldefs‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->
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<language_definitions>
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<!--
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<language processor="ESP8266"
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endian="little"
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size="32"
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variant="default"
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version="1.0"
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slafile="xtensa.sla"
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processorspec="xtensa.pspec"
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id="Xtensa:LE:32:default">
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<description>Skeleton Language Module</description>
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<compiler name="default" spec="xtensa.cspec" id="default"/>
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</language>
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-->
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</language_definitions>

‎GhidraESP8266_2/data/languages/skel.opinion‎

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<opinions>
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<!-- The primary and secondary constraint values must be specified as a decimal string -->
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<constraint loader="ESP8266" compilerSpecID="default">
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<constraint primary="0" processor="Xtensa" size="32" variant="default" />
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</constraint>
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</opinions>

‎GhidraESP8266_2/data/languages/skel.pspec‎

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->
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<processor_spec>
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<programcounter register="PC"/>
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<register_data>
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<register name="AF_" group="Alt"/>
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<register name="BC_" group="Alt"/>
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<register name="DE_" group="Alt"/>
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<register name="HL_" group="Alt"/>
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</register_data>
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<default_symbols>
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<symbol name="RST0" address="ram:0000" entry="true"/>
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<symbol name="RST1" address="ram:0008" entry="false"/>
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<symbol name="RST2" address="ram:0010" entry="false"/>
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<symbol name="RST3" address="ram:0018" entry="false"/>
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<symbol name="RST4" address="ram:0020" entry="false"/>
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<symbol name="RST5" address="ram:0028" entry="false"/>
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<symbol name="RST6" address="ram:0030" entry="false"/>
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<symbol name="RST7" address="ram:0038" entry="false"/>
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</default_symbols>
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</processor_spec>

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