Reimplement some x86 intrinsics without arch-specific LLVM intrinsics #1463
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…e_unaligned` instead of LLVM intrinsics
…r}` instead of LLVM intrinsics
…r}` instead of LLVM intrinsics
…hl` instead of LLVM intrinsics
…hl` instead of LLVM intrinsics
…hr` instead of LLVM intrinsics
…hr` instead of LLVM intrinsics
…hr` instead of LLVM intrinsics
…hr` instead of LLVM intrinsics
…shl` instead of LLVM intrinsics
…shr` instead of LLVM intrinsics
…shr` instead of LLVM intrinsics
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Amanieu
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Aug 29, 2023
crates/core_arch/src/x86/sse2.rs
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| pub unsafe fn _mm_srli_epi64<const IMM8: i32>(a: __m128i) -> __m128i { | ||
| static_assert_uimm_bits!(IMM8, 8); | ||
| transmute(psrliq(a.as_i64x2(), IMM8)) | ||
| if IMM8 >= 32 { |
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…dtwco,bjorn3 Update stdarch submodule and remove special handling in cranelift codegen for some AVX and SSE2 LLVM intrinsics rust-lang/stdarch#1463 reimplemented some x86 intrinsics to avoid using some x86-specific LLVM intrinsics: * Store unaligned (`_mm*_storeu_*`) use `<*mut _>::write_unaligned` instead of `llvm.x86.*.storeu.*`. * Shift by immediate (`_mm*_s{ll,rl,ra}i_epi*`) use `if` (srl, sll) or `min` (sra) to simulate the behaviour when the RHS is out of range. RHS is constant, so the `if`/`min` will be optimized away. This PR updates the stdarch submodule to pull these changes and removes special handling for those LLVM intrinsics from cranelift codegen. I left gcc codegen untouched because there are some autogenerated lists.
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Those were removed from stdarch in rust-lang/stdarch#1463 (`<*mut _>::write_unaligned` is used instead)
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…ediate intrinsics Those were removed from stdarch in rust-lang/stdarch#1463 (`simd_shl` and `simd_shr` are used instead)
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Sep 7, 2023
Update stdarch submodule and remove special handling in cranelift codegen for some AVX and SSE2 LLVM intrinsics rust-lang/stdarch#1463 reimplemented some x86 intrinsics to avoid using some x86-specific LLVM intrinsics: * Store unaligned (`_mm*_storeu_*`) use `<*mut _>::write_unaligned` instead of `llvm.x86.*.storeu.*`. * Shift by immediate (`_mm*_s{ll,rl,ra}i_epi*`) use `if` (srl, sll) or `min` (sra) to simulate the behaviour when the RHS is out of range. RHS is constant, so the `if`/`min` will be optimized away. This PR updates the stdarch submodule to pull these changes and removes special handling for those LLVM intrinsics from cranelift codegen. I left gcc codegen untouched because there are some autogenerated lists.
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Reimplements some x86 without using arch-specific LLVM intrinsics:
_mm*_storeu_*): Use<*mut _>::write_unalignedinstead ofllvm.x86.*.storeu.*._mm*_s{ll,rl,ra}i_epi*): Useif(srl, sll) ormin(sra) to simulate the behaviour when the RHS is out of range. RHS is constant, so theif/minwill be optimized away.The advantages are: