[x86] expose cpuid and xgetbv intrinsics

Author: gnzlbg

src/x86/misc.rs

@@ -0,0 +1,107 @@
+//! Miscelaneous x86 intrinsics available on all hosts.
+//!
+//! TODO: figure out a more discoverable name.
+
+#[cfg(test)]
+use stdsimd_test::assert_instr;
+
+/// Result of the `cpuid` instruction.
+pub struct CpuidResult {
+    /// EAX register.
+    pub eax: u32,
+    /// EBX register.
+    pub ebx: u32,
+    /// ECX register.
+    pub ecx: u32,
+    /// EDX register.
+    pub edx: u32,
+}
+
+/// CUPID instruction.
+///
+/// The `request` parameter is passed in the `eax` register and the `ext`
+/// parameter in the `ecx` register.
+///
+/// The [CPUID Wikipedia page][wiki_cpuid] contains
+/// all the information about which flags to set to query which values, and in
+/// which registers these are reported.
+///
+/// The definitive references are:
+/// - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2:
+///   Instruction Set Reference, A-Z][intel64_ref].
+/// - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and
+///   System Instructions][amd64_ref].
+///
+/// [wiki_cpuid]: https://en.wikipedia.org/wiki/CPUID
+/// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+/// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
+#[inline(always)]
+#[cfg_attr(test, assert_instr(cpuid))]
+pub unsafe fn cpuid(request: u32, ext: u32) -> CpuidResult {
+    let mut r = ::std::mem::uninitialized::<CpuidResult>();
+    asm!("cpuid"
+         : "={eax}"(r.eax), "={ebx}"(r.ebx), "={ecx}"(r.ecx), "={edx}"(r.edx)
+         : "{eax}"(request), "{ecx}"(ext)
+         : :);
+    r
+}
+
+/// Does the CPU has the CPUID instruction?
+#[cfg(target_arch = "x86_64")]
+pub fn has_cpuid() -> bool {
+    // On x86_64 all CPUs have the instruction
+    true
+}
+
+/// Does the CPU has the CPUID instruction?
+#[cfg(target_arch = "x86")]
+pub fn has_cpuid() -> bool {
+    unsafe {
+        // Read EFLAGS:
+        let eflags: u32;
+        asm!("pushf");
+        asm!("popl %eax" : "={eax}"(eflags) : : : );
+        // Invert the ID bit in EFLAGS:
+        let eflags_mod: u32 = eflags | 0x0020_0000;
+
+        // Store the modified EFLAGS (ID bit may or may not be inverted)
+        asm!("pushl %eax" : : "eax"(eflags_mod) : : );
+        asm!("popf");
+
+        // Read EFLAGS again:
+        let eflags_after: u32;
+        asm!("pushf");
+        asm!("popl %eax" : "={eax}"(eflags_after) : : : );
+
+        // Check if the ID bit changed:
+        eflags_after != eflags
+    }
+}
+
+/// Reads the contents of the extended control register `XCR`
+/// specified in `xcr_no`.
+#[inline(always)]
+// FIXME: see
+// https://github.com/rust-lang-nursery/stdsimd/issues/167
+// #[target_feature = "+xsave"]
+#[cfg_attr(test, assert_instr(xgetbv))]
+pub unsafe fn xgetbv(xcr_no: u32) -> u64 {
+    let eax: u32;
+    let edx: u32;
+
+    asm!("xgetbv"
+         : "={eax}"(eax),  "={edx}"(edx)
+         : "{ecx}"(xcr_no)
+         : :);
+
+    ((edx as u64) << 32) | (eax as u64)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    fn test_has_cpuid() {
+        assert!(has_cpuid());
+    }
+}

src/x86/mod.rs

@@ -1,5 +1,7 @@
 //! `x86` and `x86_64` intrinsics.
 
+pub use self::misc::*;
+
 pub use self::sse::*;
 pub use self::sse2::*;
 pub use self::sse3::*;
@@ -28,6 +30,8 @@ mod macros;
 #[macro_use]
 mod runtime;
 
+mod misc;
+
 mod sse;
 mod sse2;
 mod sse3;

src/x86/runtime.rs

@@ -159,31 +159,37 @@ fn test_bit(x: usize, bit: u32) -> bool {
 /// [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 /// [amd64_ref]: http://support.amd.com/TechDocs/24594.pdf
 fn detect_features() -> usize {
-    let extended_features_ebx;
-    let proc_info_ecx;
-    let proc_info_edx;
+    use super::misc::{cpuid, has_cpuid, CpuidResult};
+    let mut value: usize = 0;
 
-    unsafe {
-        /// To obtain all feature flags we need two CPUID queries:
+    // If the x86 CPU does not support the CPUID instruction then it is too
+    // old to support all currently-detectable features.
+    if !has_cpuid() {
+        return value;
+    }
 
-        /// 1. EAX=1, ECX=0: Queries "Processor Info and Feature Bits"
-        /// This gives us most of the CPU features in ECX and EDX (see
-        /// below).
-        asm!("cpuid"
-             : "={ecx}"(proc_info_ecx), "={edx}"(proc_info_edx)
-             : "{eax}"(0x0000_0001_u32), "{ecx}"(0 as u32)
-             : :);
+    // Calling `cpuid` from here on is safe because the CPU has the `cpuid`
+    // instruction.
 
-        /// 2. EAX=7, ECX=0: Queries "Extended Features"
-        /// This gives us information about bmi,bmi2, and avx2 support
-        /// (see below); the result in ECX is not currently needed.
-        asm!("cpuid"
-             : "={ebx}"(extended_features_ebx)
-             : "{eax}"(0x0000_0007_u32), "{ecx}"(0 as u32)
-             : :);
-    }
+    // 1. EAX=1, ECX=0: Queries "Processor Info and Feature Bits";
+    // Contains information about most x86 features.
+    let CpuidResult {
+        ecx: proc_info_ecx,
+        edx: proc_info_edx,
+        ..
+    } = unsafe { cpuid(0x0000_0001_u32, 0) };
 
-    let mut value: usize = 0;
+    // 2. EAX=7, ECX=0: Queries "Extended Features";
+    // Contains information about bmi,bmi2, and avx2 support.
+    let CpuidResult {
+        ebx: extended_features_ebx,
+        ..
+    } = unsafe { cpuid(0x0000_0007_u32, 0) };
+
+    let proc_info_ecx = proc_info_ecx as usize;
+    let proc_info_edx = proc_info_edx as usize;
+
+    let extended_features_ebx = extended_features_ebx as usize;
 
     if test_bit(extended_features_ebx, 3) {
         value = set_bit(value, __Feature::bmi as u32);
@@ -233,18 +239,7 @@ fn detect_features() -> usize {
     // org/mozilla-central/file/64bab5cbb9b6/mozglue/build/SSE.cpp#l190
     //
     if test_bit(proc_info_ecx, 26) && test_bit(proc_info_ecx, 27) {
-        /// XGETBV: reads the contents of the extended control
-        /// register (XCR).
-        unsafe fn xgetbv(xcr_no: u32) -> u64 {
-            let eax: u32;
-            let edx: u32;
-            // xgetbv
-            asm!("xgetbv"
-                 : "={eax}"(eax),  "={edx}"(edx)
-                 : "{ecx}"(xcr_no)
-                 : :);
-            ((edx as u64) << 32) | (eax as u64)
-        }
+        use super::misc::xgetbv;
 
         // This is safe because on x86 `xgetbv` is always available.
         if unsafe { xgetbv(0) } & 6 == 6 {

src/x86/sse2.rs

@@ -1792,7 +1792,9 @@ pub unsafe fn _mm_cvtsd_si64(a: f64x2) -> i64 {
 #[inline(always)]
 #[target_feature = "+sse2"]
 #[cfg_attr(test, assert_instr(cvtsd2si))]
-pub unsafe fn _mm_cvtsd_si64x(a: f64x2) -> i64 { _mm_cvtsd_si64(a) }
+pub unsafe fn _mm_cvtsd_si64x(a: f64x2) -> i64 {
+    _mm_cvtsd_si64(a)
+}
 
 /// Convert the lower double-precision (64-bit) floating-point element in `b`
 /// to a single-precision (32-bit) floating-point element, store the result in
@@ -1857,7 +1859,9 @@ pub unsafe fn _mm_cvttsd_si64(a: f64x2) -> i64 {
 #[inline(always)]
 #[target_feature = "+sse2"]
 #[cfg_attr(test, assert_instr(cvttsd2si))]
-pub unsafe fn _mm_cvttsd_si64x(a: f64x2) -> i64 { _mm_cvttsd_si64(a) }
+pub unsafe fn _mm_cvttsd_si64x(a: f64x2) -> i64 {
+    _mm_cvttsd_si64(a)
+}
 
 /// Convert packed single-precision (32-bit) floating-point elements in `a` to
 /// packed 32-bit integers with truncation.