riscv: use name riscv32 for 32-bit RISC-V architecture

rename internal riscv32 module to riscv_shared

Author: luojia65

crates/core_arch/src/core_arch_docs.md

@@ -185,7 +185,7 @@ others at:
 * [`x86_64`]
 * [`arm`]
 * [`aarch64`]
-* [`riscv`]
+* [`riscv32`]
 * [`riscv64`]
 * [`mips`]
 * [`mips64`]
@@ -198,7 +198,7 @@ others at:
 [`x86_64`]: x86_64/index.html
 [`arm`]: arm/index.html
 [`aarch64`]: aarch64/index.html
-[`riscv`]: riscv/index.html
+[`riscv32`]: riscv32/index.html
 [`riscv64`]: riscv64/index.html
 [`mips`]: mips/index.html
 [`mips64`]: mips64/index.html

crates/core_arch/src/mod.rs

@@ -56,14 +56,14 @@ pub mod arch {
         pub use crate::core_arch::aarch64::*;
     }
 
-    /// Platform-specific intrinsics for the `riscv` platform.
+    /// Platform-specific intrinsics for the `riscv32` platform.
     ///
     /// See the [module documentation](../index.html) for more details.
-    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
-    #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
+    #[cfg(any(target_arch = "riscv32", doc))]
+    #[doc(cfg(any(target_arch = "riscv32")))]
     #[unstable(feature = "stdsimd", issue = "27731")]
-    pub mod riscv {
-        pub use crate::core_arch::riscv::*;
+    pub mod riscv32 {
+        pub use crate::core_arch::riscv_shared::*;
     }
 
     /// Platform-specific intrinsics for the `riscv64` platform.
@@ -73,8 +73,11 @@ pub mod arch {
     #[doc(cfg(any(target_arch = "riscv64")))]
     #[unstable(feature = "stdsimd", issue = "27731")]
     pub mod riscv64 {
-        pub use crate::core_arch::riscv::*;
         pub use crate::core_arch::riscv64::*;
+        // RISC-V RV64 supports all RV32 instructions as well in current specifications (2022-01-05).
+        // Module `riscv_shared` includes instructions available under all RISC-V platforms,
+        // i.e. RISC-V RV32 instructions.
+        pub use crate::core_arch::riscv_shared::*;
     }
 
     /// Platform-specific intrinsics for the `wasm32` platform.
@@ -275,7 +278,7 @@ mod arm;
 
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
 #[doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64")))]
-mod riscv;
+mod riscv_shared;
 
 #[cfg(any(target_arch = "riscv64", doc))]
 #[doc(cfg(any(target_arch = "riscv64")))]

crates/core_arch/src/riscv/mod.rs renamed to crates/core_arch/src/riscv_shared/mod.rs

@@ -1,4 +1,4 @@
-//! RISC-V intrinsics
+//! Shared RISC-V intrinsics
 
 use crate::arch::asm;