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use rustc reductions
1 parent 0632492 commit bdf0d25

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15 files changed

+240
-1345
lines changed

15 files changed

+240
-1345
lines changed

‎coresimd/ppsv/api/arithmetic_reductions.rs

Lines changed: 49 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,61 @@ macro_rules! impl_arithmetic_reductions {
55
($id:ident, $elem_ty:ident) => {
66
impl $id {
77
/// Lane-wise addition of the vector elements.
8+
///
9+
/// FIXME: document guarantees with respect to:
10+
/// * integers: overflow behavior
11+
/// * floats: order and NaNs
12+
#[cfg(not(target_arch = "aarch64"))]
813
#[inline]
914
pub fn sum(self) -> $elem_ty {
10-
super::codegen::sum::ReduceAdd::reduce_add(self)
15+
use ::coresimd::simd_llvm::simd_reduce_add_ordered;
16+
unsafe {
17+
simd_reduce_add_ordered(self, 0 as $elem_ty)
18+
}
1119
}
20+
/// Lane-wise addition of the vector elements.
21+
///
22+
/// FIXME: document guarantees with respect to:
23+
/// * integers: overflow behavior
24+
/// * floats: order and NaNs
25+
#[cfg(target_arch = "aarch64")]
26+
#[inline]
27+
pub fn sum(self) -> $elem_ty {
28+
// FIXME: broken on AArch64
29+
let mut x = self.extract(0) as $elem_ty;
30+
for i in 1..$id::lanes() {
31+
x += self.extract(i) as $elem_ty;
32+
}
33+
x
34+
}
35+
1236
/// Lane-wise multiplication of the vector elements.
37+
///
38+
/// FIXME: document guarantees with respect to:
39+
/// * integers: overflow behavior
40+
/// * floats: order and NaNs
41+
#[cfg(not(target_arch = "aarch64"))]
1342
#[inline]
1443
pub fn product(self) -> $elem_ty {
15-
super::codegen::product::ReduceMul::reduce_mul(self)
44+
use ::coresimd::simd_llvm::simd_reduce_mul_ordered;
45+
unsafe {
46+
simd_reduce_mul_ordered(self, 1 as $elem_ty)
47+
}
48+
}
49+
/// Lane-wise multiplication of the vector elements.
50+
///
51+
/// FIXME: document guarantees with respect to:
52+
/// * integers: overflow behavior
53+
/// * floats: order and NaNs
54+
#[cfg(target_arch = "aarch64")]
55+
#[inline]
56+
pub fn product(self) -> $elem_ty {
57+
// FIXME: broken on AArch64
58+
let mut x = self.extract(0) as $elem_ty;
59+
for i in 1..$id::lanes() {
60+
x *= self.extract(i) as $elem_ty;
61+
}
62+
x
1663
}
1764
}
1865
}

‎coresimd/ppsv/api/bitwise_reductions.rs

Lines changed: 104 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,41 +5,138 @@ macro_rules! impl_bitwise_reductions {
55
($id:ident, $elem_ty:ident) => {
66
impl $id {
77
/// Lane-wise bitwise `and` of the vector elements.
8+
#[cfg(not(target_arch = "aarch64"))]
89
#[inline]
910
pub fn and(self) -> $elem_ty {
10-
super::codegen::and::ReduceAnd::reduce_and(self)
11+
use ::coresimd::simd_llvm::simd_reduce_and;
12+
unsafe {
13+
simd_reduce_and(self)
14+
}
1115
}
16+
/// Lane-wise bitwise `and` of the vector elements.
17+
#[cfg(target_arch = "aarch64")]
18+
#[inline]
19+
pub fn and(self) -> $elem_ty {
20+
// FIXME: broken on aarch64
21+
let mut x = self.extract(0) as $elem_ty;
22+
for i in 1..$id::lanes() {
23+
x &= self.extract(i) as $elem_ty;
24+
}
25+
x
26+
}
27+
1228
/// Lane-wise bitwise `or` of the vector elements.
29+
#[cfg(not(target_arch = "aarch64"))]
1330
#[inline]
1431
pub fn or(self) -> $elem_ty {
15-
super::codegen::or::ReduceOr::reduce_or(self)
32+
use ::coresimd::simd_llvm::simd_reduce_or;
33+
unsafe {
34+
simd_reduce_or(self)
35+
}
1636
}
37+
/// Lane-wise bitwise `or` of the vector elements.
38+
#[cfg(target_arch = "aarch64")]
39+
#[inline]
40+
pub fn or(self) -> $elem_ty {
41+
// FIXME: broken on aarch64
42+
let mut x = self.extract(0) as $elem_ty;
43+
for i in 1..$id::lanes() {
44+
x |= self.extract(i) as $elem_ty;
45+
}
46+
x
47+
}
48+
1749
/// Lane-wise bitwise `xor` of the vector elements.
50+
#[cfg(not(target_arch = "aarch64"))]
1851
#[inline]
1952
pub fn xor(self) -> $elem_ty {
20-
super::codegen::xor::ReduceXor::reduce_xor(self)
53+
use ::coresimd::simd_llvm::simd_reduce_xor;
54+
unsafe {
55+
simd_reduce_xor(self)
56+
}
57+
}
58+
/// Lane-wise bitwise `xor` of the vector elements.
59+
#[cfg(target_arch = "aarch64")]
60+
#[inline]
61+
pub fn xor(self) -> $elem_ty {
62+
// FIXME: broken on aarch64
63+
let mut x = self.extract(0) as $elem_ty;
64+
for i in 1..$id::lanes() {
65+
x ^= self.extract(i) as $elem_ty;
66+
}
67+
x
2168
}
2269
}
2370
}
2471
}
2572

2673
macro_rules! impl_bool_bitwise_reductions {
27-
($id:ident, $elem_ty:ident) => {
74+
($id:ident, $elem_ty:ident, $internal_ty:ident) => {
2875
impl $id {
2976
/// Lane-wise bitwise `and` of the vector elements.
77+
#[cfg(not(target_arch = "aarch64"))]
3078
#[inline]
3179
pub fn and(self) -> $elem_ty {
32-
super::codegen::and::ReduceAnd::reduce_and(self) !=0
80+
use ::coresimd::simd_llvm::simd_reduce_and;
81+
unsafe {
82+
let r: $internal_ty = simd_reduce_and(self);
83+
r != 0
84+
}
85+
}
86+
/// Lane-wise bitwise `and` of the vector elements.
87+
#[cfg(target_arch = "aarch64")]
88+
#[inline]
89+
pub fn and(self) -> $elem_ty {
90+
// FIXME: broken on aarch64
91+
let mut x = self.extract(0) as $elem_ty;
92+
for i in 1..$id::lanes() {
93+
x &= self.extract(i) as $elem_ty;
94+
}
95+
x
96+
}
97+
98+
/// Lane-wise bitwise `or` of the vector elements.
99+
#[cfg(not(target_arch = "aarch64"))]
100+
#[inline]
101+
pub fn or(self) -> $elem_ty {
102+
use ::coresimd::simd_llvm::simd_reduce_or;
103+
unsafe {
104+
let r: $internal_ty = simd_reduce_or(self);
105+
r != 0
106+
}
33107
}
34108
/// Lane-wise bitwise `or` of the vector elements.
109+
#[cfg(target_arch = "aarch64")]
35110
#[inline]
36111
pub fn or(self) -> $elem_ty {
37-
super::codegen::or::ReduceOr::reduce_or(self) != 0
112+
// FIXME: broken on aarch64
113+
let mut x = self.extract(0) as $elem_ty;
114+
for i in 1..$id::lanes() {
115+
x |= self.extract(i) as $elem_ty;
116+
}
117+
x
118+
}
119+
120+
/// Lane-wise bitwise `xor` of the vector elements.
121+
#[cfg(not(target_arch = "aarch64"))]
122+
#[inline]
123+
pub fn xor(self) -> $elem_ty {
124+
use ::coresimd::simd_llvm::simd_reduce_xor;
125+
unsafe {
126+
let r: $internal_ty = simd_reduce_xor(self);
127+
r != 0
128+
}
38129
}
39130
/// Lane-wise bitwise `xor` of the vector elements.
131+
#[cfg(target_arch = "aarch64")]
40132
#[inline]
41133
pub fn xor(self) -> $elem_ty {
42-
super::codegen::xor::ReduceXor::reduce_xor(self) != 0
134+
// FIXME: broken on aarch64
135+
let mut x = self.extract(0) as $elem_ty;
136+
for i in 1..$id::lanes() {
137+
x ^= self.extract(i) as $elem_ty;
138+
}
139+
x
43140
}
44141
}
45142
}

‎coresimd/ppsv/api/boolean_reductions.rs

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,19 +5,43 @@ macro_rules! impl_bool_reductions {
55
($id:ident) => {
66
impl $id {
77
/// Are `all` vector lanes `true`?
8+
#[cfg(not(target_arch = "aarch64"))]
89
#[inline]
910
pub fn all(self) -> bool {
11+
use ::coresimd::simd_llvm::simd_reduce_all;
12+
unsafe {
13+
simd_reduce_all(self)
14+
}
15+
}
16+
/// Are `all` vector lanes `true`?
17+
#[cfg(target_arch = "aarch64")]
18+
#[inline]
19+
pub fn all(self) -> bool {
20+
// FIXME: Broken on AArch64
1021
self.and()
1122
}
23+
24+
/// Is `any` vector lanes `true`?
25+
#[cfg(not(target_arch = "aarch64"))]
26+
#[inline]
27+
pub fn any(self) -> bool {
28+
use ::coresimd::simd_llvm::simd_reduce_any;
29+
unsafe {
30+
simd_reduce_any(self)
31+
}
32+
}
1233
/// Is `any` vector lanes `true`?
34+
#[cfg(target_arch = "aarch64")]
1335
#[inline]
1436
pub fn any(self) -> bool {
37+
// FIXME: Broken on AArch64
1538
self.or()
1639
}
40+
1741
/// Are `all` vector lanes `false`?
1842
#[inline]
1943
pub fn none(self) -> bool {
20-
!self.or()
44+
!self.any()
2145
}
2246
}
2347
}

‎coresimd/ppsv/api/minmax_reductions.rs

Lines changed: 47 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,59 @@ macro_rules! impl_minmax_reductions {
55
($id:ident, $elem_ty:ident) => {
66
impl $id {
77
/// Largest vector value.
8+
///
9+
/// FIXME: document behavior for float vectors with NaNs.
10+
#[cfg(not(target_arch = "aarch64"))]
811
#[inline]
912
pub fn max(self) -> $elem_ty {
10-
super::codegen::max::ReduceMax::reduce_max(self)
13+
use ::coresimd::simd_llvm::simd_reduce_max;
14+
unsafe {
15+
simd_reduce_max(self)
16+
}
17+
}
18+
/// Largest vector value.
19+
///
20+
/// FIXME: document behavior for float vectors with NaNs.
21+
#[cfg(target_arch = "aarch64")]
22+
#[allow(unused_imports)]
23+
#[inline]
24+
pub fn max(self) -> $elem_ty {
25+
// FIXME: broken on AArch64
26+
use ::num::Float;
27+
use ::cmp::Ord;
28+
let mut x = self.extract(0);
29+
for i in 1..$id::lanes() {
30+
x = x.max(self.extract(i));
31+
}
32+
x
33+
}
34+
35+
/// Smallest vector value.
36+
///
37+
/// FIXME: document behavior for float vectors with NaNs.
38+
#[cfg(not(target_arch = "aarch64"))]
39+
#[inline]
40+
pub fn min(self) -> $elem_ty {
41+
use ::coresimd::simd_llvm::simd_reduce_min;
42+
unsafe {
43+
simd_reduce_min(self)
44+
}
1145
}
1246
/// Smallest vector value.
47+
///
48+
/// FIXME: document behavior for float vectors with NaNs.
49+
#[cfg(target_arch = "aarch64")]
50+
#[allow(unused_imports)]
1351
#[inline]
1452
pub fn min(self) -> $elem_ty {
15-
super::codegen::min::ReduceMin::reduce_min(self)
53+
// FIXME: broken on AArch64
54+
use ::num::Float;
55+
use ::cmp::Ord;
56+
let mut x = self.extract(0);
57+
for i in 1..$id::lanes() {
58+
x = x.min(self.extract(i));
59+
}
60+
x
1661
}
1762
}
1863
}

‎coresimd/ppsv/api/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ macro_rules! simd_b_ty {
244244
[define_ty, $id, $($elem_tys),+ | $(#[$doc])*],
245245
[impl_bool_minimal, $id, $elem_ty, $elem_count, $($elem_name),*],
246246
[impl_bitwise_ops, $id, true],
247-
[impl_bool_bitwise_reductions, $id, bool],
247+
[impl_bool_bitwise_reductions, $id, bool, $elem_ty],
248248
[impl_bool_reductions, $id],
249249
[impl_bool_cmp, $id, $id],
250250
[impl_eq, $id],

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