RISC-V: Remove privileged extensions for now

Until in-kernel feature detection is implemented, runtime detection of
privileged extensions is temporally removed along with features themselves
since none of such privileged features are stable.

Co-Authored-By: Taiki Endo <te316e89@gmail.com>

Author: a4lg

crates/std_detect/src/detect/arch/riscv.rs

@@ -115,14 +115,6 @@ features! {
     /// * P: `"p"`
     /// * Zam: `"zam"`
     ///
-    /// Defined by Privileged Specification:
-    ///
-    /// * *Supervisor-Level ISA* (not "S" extension): `"s"`
-    /// * H (hypervisor): `"h"`
-    /// * Svnapot: `"svnapot"`
-    /// * Svpbmt: `"svpbmt"`
-    /// * Svinval: `"svinval"`
-    ///
     /// # Performance Hints
     ///
     /// The two features below define performance hints for unaligned
@@ -331,22 +323,6 @@ features! {
     @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
     /// "Zvkt" Extension for Vector Data-Independent Execution Latency
 
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
-    without cfg check: true;
-    /// "Svnapot" Extension for NAPOT Translation Contiguity
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
-    without cfg check: true;
-    /// "Svpbmt" Extension for Page-Based Memory Types
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
-    without cfg check: true;
-    /// "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
-    without cfg check: true;
-    /// "H" Extension for Hypervisor Support
-
-    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
-    without cfg check: true;
-    /// Supervisor-Level ISA
     @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
     without cfg check: true;
     /// "J" Extension for Dynamically Translated Languages

crates/std_detect/src/detect/os/linux/riscv.rs

@@ -141,7 +141,6 @@ pub(crate) fn detect_features() -> cache::Initializer {
     enable_feature(Feature::c, bit::test(auxv.hwcap, (b'c' - b'a').into()));
     enable_feature(Feature::d, bit::test(auxv.hwcap, (b'd' - b'a').into()));
     enable_feature(Feature::f, bit::test(auxv.hwcap, (b'f' - b'a').into()));
-    enable_feature(Feature::h, bit::test(auxv.hwcap, (b'h' - b'a').into()));
     enable_feature(Feature::m, bit::test(auxv.hwcap, (b'm' - b'a').into()));
     let has_v = bit::test(auxv.hwcap, (b'v' - b'a').into());
     let mut is_v_set = false;

crates/std_detect/src/detect/os/riscv.rs

@@ -107,7 +107,6 @@ pub(crate) fn imply_features(mut value: cache::Initializer) -> cache::Initialize
         imply!(c & f => zcf);
 
         imply!(zicntr | zihpm | zkr | f | zfinx | zve32x => zicsr);
-        imply!(s | h => zicsr);
 
         // Loop until the feature flags converge.
         if prev == value {

crates/std_detect/tests/cpu-detection.rs

@@ -319,11 +319,6 @@ fn riscv_linux() {
     println!("zvksc: {}", is_riscv_feature_detected!("zvksc"));
     println!("zvksg: {}", is_riscv_feature_detected!("zvksg"));
     println!("zvkt: {}", is_riscv_feature_detected!("zvkt"));
-    println!("svnapot: {}", is_riscv_feature_detected!("svnapot"));
-    println!("svpbmt: {}", is_riscv_feature_detected!("svpbmt"));
-    println!("svinval: {}", is_riscv_feature_detected!("svinval"));
-    println!("h: {}", is_riscv_feature_detected!("h"));
-    println!("s: {}", is_riscv_feature_detected!("s"));
     println!("j: {}", is_riscv_feature_detected!("j"));
     println!("p: {}", is_riscv_feature_detected!("p"));
 }