`rustc_scalable_vector(N)` #143924

davidtwco · 2025-07-14T11:13:12Z

Supercedes #118917.

Initial experimental implementation of rust-lang/rfcs#3838. Introduces a rustc_scalable_vector(N) attribute that can be applied to types with a single [$ty] field (for u{16,32,64}, i{16,32,64}, f{32,64}, bool). rustc_scalable_vector types are lowered to scalable vectors in the codegen backend.

As with any unstable feature, there will necessarily be follow-ups as we experiment and find cases that we've not considered or still need some logic to handle, but this aims to be a decent baseline to start from.

See #145052 for request for a lang experiment.

rustbot · 2025-07-14T11:13:17Z

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rustbot · 2025-07-14T11:13:21Z

Some changes occurred in compiler/rustc_attr_parsing

cc @jdonszelmann

Some changes occurred in compiler/rustc_attr_data_structures

cc @jdonszelmann

Some changes occurred in compiler/rustc_passes/src/check_attr.rs

cc @jdonszelmann

Some changes occurred to the intrinsics. Make sure the CTFE / Miri interpreter
gets adapted for the changes, if necessary.

cc @rust-lang/miri, @RalfJung, @oli-obk, @lcnr

Some changes occurred to the CTFE / Miri interpreter

cc @rust-lang/miri

Some changes occurred to the platform-builtins intrinsics. Make sure the
LLVM backend as well as portable-simd gets adapted for the changes.

cc @antoyo, @GuillaumeGomez, @bjorn3, @calebzulawski, @programmerjake

Some changes occurred to MIR optimizations

cc @rust-lang/wg-mir-opt

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cc @WaffleLapkin

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changes to the core type system

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davidtwco · 2025-07-14T11:21:46Z

I've changed this back to a draft and marked it as S-waiting-on-author while I rebase it and get the approval for an experimental implementation to go ahead.

workingjubilee

I do not intend to have repr(simd) survive this year, so I do not think this should be added.

davidtwco · 2025-07-14T16:09:12Z

I do not intend to have repr(simd) survive this year, so I do not think this should be added.

Could you elaborate?

workingjubilee · 2025-07-14T16:10:18Z

I intend to replace it with an approach based on lang items for a variety of reasons, one of them being that to start with, the repr(simd) "attribute" does not compose and should not.

r? @workingjubilee

workingjubilee · 2025-07-14T16:11:51Z

Likewise, scalable vectors do not really have a diversity in their representation. They either go in the scalable vector registers or they don't. They are one type, even if it is parameterized by the element type (and possibly the CPU's Matrix state, idk).

davidtwco · 2025-07-14T16:36:37Z

I intend to replace it with an approach based on lang items for a variety of reasons, one of them being that to start with, the repr(simd) "attribute" does not compose and should not.

I think this discussion is better for the RFC - rust-lang/rfcs#3838 - rather than the implementation.

With that said, I definitely don't think this should to be blocked by your intentions to change repr(simd) - extending our existing, RFC-approved, SIMD infrastructure is a natural way to go about supporting scalable vectors. Unless there's an alternative proposal for changing repr(simd) out there that has been accepted or is on the cusp of being accepted and I've missed it, working from what we have today is all I can do.

Nothing in rust-lang/rfcs#3838 should make your plans impossible as it's just more internal infrastructure that could easily be changed to something else with a well-motivated proposal, no different than repr(simd). It'll be your responsibility to update your plans/proposal if repr(scalable) makes progress first. It goes the other way too, if you make progress changing repr(simd) prior to this making progress then I'll have to update my proposal, that's fine. Unless something I'm proposing completely shuts the door on your plans - which would be worth discussing! - and we decide we'd like to avoid that, then it shouldn't block this.

workingjubilee · 2025-07-14T18:34:57Z

So you want me to race you?

workingjubilee · 2025-07-14T19:41:52Z

My understanding has always been that "an RFC approved it" doesn't mean much when it concerns internal-facing details. We've changed things away from RFC-approved implementation details without redoing the RFC. e.g. #[track_caller] only barely resembles the original implementation described in the RFC.
Specifically, we have removed or heavily modified several parts of RFC1199 already, and each one was a lot of work.
We have had to issue many patches like Ban projecting into SIMD types [MCP838] #143833 for fixing how repr(simd) is compiled. Yes, we have this existing infrastructure, which is how we know how flawed it is.
This is not some random idea I had, it was an issue from some time ago. I am surprised to find out I am the only one who reviews related issues before commencing work on things. Remove repr(simd) attribute and use a lang-item instead #63633
As someone paid to work on this full-time and also empowered as compiler team lead, I fear you have more ability to push through things than me, especially because for various reasons I take a great deal of care before pushing for things. For that reason, while I am willing to concede the changes here might not obstruct a future change, I do expect to be allowed to review this to make that determination, and hoped for a more collaborative approach instead of possibly fighting to rebase over each other.

Extend parsing of `ReprOptions` with `rustc_scalable_vector(N)` which optionally accepts a single literal integral value - the base multiple of lanes that are in a scalable vector. Can only be applied to structs. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

Extend well-formedness checking and HIR analysis to prohibit the use of scalable vectors in structs, enums, unions, tuples and arrays. LLVM does not support scalable vectors being members of other types, so these restrictions are necessary. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

`simd_reinterpret` is a replacement for `transmute`, specifically for use with scalable SIMD types. It is used in the tests for scalable vectors and in stdarch. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

Introduces `BackendRepr::ScalableVector` corresponding to scalable vector types annotated with `repr(scalable)` which lowers to a scalable vector type in LLVM. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

LLVM doesn't handle stores on `<vscale x N x i1>` for `N != 16`, a type used internally in SVE intrinsics. Spilling to the stack to create debuginfo will cause errors during instruction selection. These types that are an internal implementation detail to the intrinsic, so users should never see them types and won't need any debuginfo. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

Scalable vectors cannot be members of ADTs and thus cannot be kept over await points in async functions.

Scalable vector types only work with the relevant target features enabled, so require this for any function with the types in its signature.

davidtwco · 2025-08-12T12:42:35Z

Updated this reflecting changes in rust-lang/rfcs#3838. It doesn't implement everything in it yet, and is definitely incomplete, but it's a starting point.

Trivial changes to rust-analyzer to keep it compiling with changes to `ReprOptions`.

rust-log-analyzer · 2025-08-12T13:57:11Z

The job aarch64-gnu-llvm-19-1 failed! Check out the build log: (web) (plain enhanced) (plain)

Click to see the possible cause of the failure (guessed by this bot)

failures:

---- [codegen] tests/codegen-llvm/scalable-vectors/simple.rs stdout ----

error: verification with 'FileCheck' failed
status: exit status: 1
command: "/usr/lib/llvm-19/bin/FileCheck" "--input-file" "/checkout/obj/build/aarch64-unknown-linux-gnu/test/codegen-llvm/scalable-vectors/simple/simple.ll" "/checkout/tests/codegen-llvm/scalable-vectors/simple.rs" "--check-prefix=CHECK" "--allow-unused-prefixes" "--dump-input-context" "100"
stdout: none
--- stderr -------------------------------
/checkout/tests/codegen-llvm/scalable-vectors/simple.rs:35:11: error: CHECK: expected string not found in input
// CHECK: define <vscale x 4 x i32> @pass_as_ref(ptr noalias noundef readonly align 16 captures(none) dereferenceable(16) %a, <vscale x 4 x i32> %b)
          ^
/checkout/obj/build/aarch64-unknown-linux-gnu/test/codegen-llvm/scalable-vectors/simple/simple.ll:1:1: note: scanning from here
; ModuleID = 'simple.762e3d9a4d4c6830-cgu.0'
^
/checkout/obj/build/aarch64-unknown-linux-gnu/test/codegen-llvm/scalable-vectors/simple/simple.ll:33:6: note: possible intended match here
 %_0 = call <vscale x 4 x i32> @pass_as_ref(ptr noalias noundef nonnull readonly align 16 dereferenceable(16) %a, <vscale x 4 x i32> %b)
     ^

Input file: /checkout/obj/build/aarch64-unknown-linux-gnu/test/codegen-llvm/scalable-vectors/simple/simple.ll
Check file: /checkout/tests/codegen-llvm/scalable-vectors/simple.rs

-dump-input=help explains the following input dump.

Input was:
<<<<<<
            1: ; ModuleID = 'simple.762e3d9a4d4c6830-cgu.0' 
check:35'0     X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
            2: source_filename = "simple.762e3d9a4d4c6830-cgu.0" 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            3: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            4: target triple = "aarch64-unknown-linux-gnu" 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            5:  
check:35'0     ~
            6: ; simple::svdup_n_s32 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~
            7: ; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(none) uwtable 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            8: define <vscale x 4 x i32> @_ZN6simple11svdup_n_s3217ha891f46349370f05E(i32 noundef %op) unnamed_addr #0 { 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            9: start: 
check:35'0     ~~~~~~~
           10:  %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %op, i64 0 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           11:  %_0 = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           12:  ret <vscale x 4 x i32> %_0 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           13: } 
check:35'0     ~~
           14:  
check:35'0     ~
           15: ; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(argmem: read) uwtable 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           16: define <vscale x 4 x i32> @pass_as_ref(ptr noalias nocapture noundef readonly align 16 dereferenceable(16) %a, <vscale x 4 x i32> %b) unnamed_addr #1 { 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           17: start: 
check:35'0     ~~~~~~~
           18:  %_3 = load <vscale x 4 x i32>, ptr %a, align 16 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           19:  %_0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.xar.nxv4i32(<vscale x 4 x i32> %_3, <vscale x 4 x i32> %b, i32 noundef 1) #5 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           20:  ret <vscale x 4 x i32> %_0 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           21: } 
check:35'0     ~~
           22:  
check:35'0     ~
           23: ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           24: define <vscale x 4 x i32> @test() unnamed_addr #2 { 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           25: start: 
check:35'0     ~~~~~~~
           26:  %a = alloca <vscale x 4 x i32>, align 16 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           27:  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %a) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           28: ; call simple::svdup_n_s32 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~
           29:  %0 = tail call <vscale x 4 x i32> @_ZN6simple11svdup_n_s3217ha891f46349370f05E(i32 noundef 1) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           30:  store <vscale x 4 x i32> %0, ptr %a, align 16 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           31: ; call simple::svdup_n_s32 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~
           32:  %b = tail call <vscale x 4 x i32> @_ZN6simple11svdup_n_s3217ha891f46349370f05E(i32 noundef 2) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           33:  %_0 = call <vscale x 4 x i32> @pass_as_ref(ptr noalias noundef nonnull readonly align 16 dereferenceable(16) %a, <vscale x 4 x i32> %b) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:35'1          ?                                                                                                                                    possible intended match
           34:  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %a) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           35:  ret <vscale x 4 x i32> %_0 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           36: } 
check:35'0     ~~
           37:  
check:35'0     ~
           38: ; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           39: declare <vscale x 4 x i32> @llvm.aarch64.sve.xar.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) unnamed_addr #3 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           40:  
check:35'0     ~
           41: ; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           42: declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #4 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           43:  
check:35'0     ~
           44: ; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           45: declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #4 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           46:  
check:35'0     ~
           47: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(none) uwtable "frame-pointer"="non-leaf" "probe-stack"="inline-asm" "target-cpu"="generic" "target-features"="+v8a,+outline-atomics,+neon,+fp-armv8,+sve" } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           48: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(argmem: read) uwtable "frame-pointer"="non-leaf" "probe-stack"="inline-asm" "target-cpu"="generic" "target-features"="+v8a,+outline-atomics,+neon,+fp-armv8,+sve,+neon,+fp-armv8,+sve,+sve2" } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           49: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "frame-pointer"="non-leaf" "probe-stack"="inline-asm" "target-cpu"="generic" "target-features"="+v8a,+outline-atomics,+neon,+fp-armv8,+sve,+neon,+fp-armv8,+sve,+sve2" } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           50: attributes #3 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           51: attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           52: attributes #5 = { nounwind } 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           53:  
check:35'0     ~
           54: !llvm.module.flags = !{!0} 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~
           55: !llvm.ident = !{!1} 
check:35'0     ~~~~~~~~~~~~~~~~~~~~
           56:  
check:35'0     ~
           57: !0 = !{i32 8, !"PIC Level", i32 2} 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           58: !1 = !{!"rustc version 1.91.0-nightly (311dd95da 2025-08-12)"} 
check:35'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>
------------------------------------------

bors · 2025-08-15T00:25:17Z

☔ The latest upstream changes (presumably #145085) made this pull request unmergeable. Please resolve the merge conflicts.

ruanyuxin · 2025-09-02T03:28:24Z

Hello, I'm a student interested in rust. I encountered an error when I was testing with Sims.rs. What should I do：
huawei@DESKTOP-PUT13J1:
~/davidtwco/rust$ ./build/x86_64-unknown-linux-gnu/stage2/bin/rustc
--target=aarch64-unknown-linux-gnu
-C target-feature=+sve,+sve2
--crate-type=lib
--sysroot=./build/x86_64-unknown-linux-gnu/stage2
~/rust-tests/yytest/src/main.rs
error: attributes starting with rustc are reserved for use by the rustc compiler
--> /home/huawei/rust-tests/yytest/src/main.rs:8:3
|
8 | #[rustc_scalable_vector(4)]
^^^^^^^^^^^^^^^^^^^^^

error: cannot find attribute rustc_scalable_vector in this scope
--> /home/huawei/rust-tests/yytest/src/main.rs:8:3
|
8 | #[rustc_scalable_vector(4)]
^^^^^^^^^^^^^^^^^^^^^

error: aborting due to 2 previous errors

rustbot assigned compiler-errors Jul 14, 2025

davidtwco mentioned this pull request Jul 14, 2025

Support for a scalable simd representation #118917

Closed

davidtwco marked this pull request as draft July 14, 2025 11:21

rustbot added S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Jul 14, 2025

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davidtwco mentioned this pull request Jul 29, 2025

SVE and SME on AArch64 rust-lang/rust-project-goals#270

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davidtwco mentioned this pull request Aug 7, 2025

Tracking Issue for Scalable Vectors #145052

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davidtwco and others added 7 commits August 12, 2025 10:05

core: add simd_reinterpret

12342ef

`simd_reinterpret` is a replacement for `transmute`, specifically for use with scalable SIMD types. It is used in the tests for scalable vectors and in stdarch. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

codegen: implement repr(scalable)

dace4f8

Introduces `BackendRepr::ScalableVector` corresponding to scalable vector types annotated with `repr(scalable)` which lowers to a scalable vector type in LLVM. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>

mir_transform: prohibit scalable vectors in async

86e1b7f

Scalable vectors cannot be members of ADTs and thus cannot be kept over await points in async functions.

mono: require target feature for scalable vectors

95e7b35

Scalable vector types only work with the relevant target features enabled, so require this for any function with the types in its signature.

davidtwco force-pushed the sve-infrastructure branch from 4f6b823 to 95e7b35 Compare August 12, 2025 12:40

davidtwco changed the title ~~repr(scalable)~~ rustc_scalable_vector(N) Aug 12, 2025

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rust-analyzer: rustc_scalable_vector

26fb3ae

Trivial changes to rust-analyzer to keep it compiling with changes to `ReprOptions`.

davidtwco force-pushed the sve-infrastructure branch from 6df93d3 to 26fb3ae Compare August 12, 2025 13:13

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rustc_scalable_vector(N) #143924

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`rustc_scalable_vector(N)` #143924

`rustc_scalable_vector(N)` #143924

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