Update LLVM to 19 327ca6c

[DianQK]

Fixes #129887.

r? nikic

[rustbot]

⚠️ Warning ⚠️

• These commits modify submodules.

[DianQK]

@bors try

[bors]

⌛ Trying commit 7c692e1 with merge 9d53093...

[bors]

☀️ Try build successful - checks-actions
Build commit: 9d53093 (9d530932bdfb45b67d1772108e1598eec80b1df7)

[nikic]

@bors r+ rollup=never

[bors]

📌 Commit 7c692e1 has been approved by nikic

It is now in the queue for this repository.

[bors]

⌛ Testing commit 7c692e1 with merge 16beabe...

[bors]

☀️ Test successful - checks-actions
Approved by: nikic
Pushing 16beabe to master...

[rust-timer]

Finished benchmarking commit (16beabe): comparison URL.

Overall result: ❌✅ regressions and improvements - no action needed

@rustbot label: -perf-regression

Instruction count

This is a highly reliable metric that was used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	0.2%	[0.2%, 0.2%]	1
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-1.2%	[-1.2%, -1.2%]	1
All ❌✅ (primary)	-	-	0

Max RSS (memory usage)

Results (secondary 3.3%)

This is a less reliable metric that may be of interest but was not used to determine the overall result at the top of this comment.

	mean	range	count
Regressions ❌ (primary)	-	-	0
Regressions ❌ (secondary)	3.3%	[3.0%, 3.7%]	3
Improvements ✅ (primary)	-	-	0
Improvements ✅ (secondary)	-	-	0
All ❌✅ (primary)	-	-	0

Cycles

This benchmark run did not return any relevant results for this metric.

Binary size

This benchmark run did not return any relevant results for this metric.

Bootstrap: 757.068s -> 756.642s (-0.06%)
Artifact size: 341.32 MiB -> 341.32 MiB (0.00%)

[nikic]

Beta is currently based on a pre-release version of LLVM 19. This updates to a newer (still pre-release) version, which fixes at least one P-high regression from the LLVM 19 upgrade.

[DianQK]

The changes related to us were generated by git --no-pager log --pretty=format:"%s [%h](https://github.com/llvm/llvm-project/commit/%h)" 2b259b3c201f939f2ed8d2fb0a0e9b37dd2d1321...4b8d29c585687084bbcf21471e04f279d1eddc0a --stat -- llvm/lib | sed -e 's/ (#[0-9]*)//g' -e 's/^[[:space:]]*//;s/[[:space:]]*$//'.
Please note that this is only to help us quickly understand what changes in this PR.

Click me

[llvm][CodeGen] Resolve issues when updating live intervals in window scheduler 2651d09ec9c4
llvm/lib/CodeGen/ModuloSchedule.cpp | 3 +++
1 file changed, 3 insertions(+)

[AArch64] Disable SVE paired ld1/st1 for callee-saves. 5e1a55eaa0bb
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 33 ------------------------
1 file changed, 33 deletions(-)

[SLP]Fix PR107036: Check if the type of the user is sizable before requesting its size. 42f18eedc2cf
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 5 +++++
1 file changed, 5 insertions(+)

[RemoveDIs] Fix spliceDebugInfo splice-to-end edge case 11e2a1552f92
llvm/lib/IR/BasicBlock.cpp | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

[AArch64] Remove redundant COPY from loadRegFromStackSlot 52e5a72e9200
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 4 ----
1 file changed, 4 deletions(-)

[AVR] Fix parsing & emitting relative jumps 830b7ebac09e
llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 15 +++++++++++----
llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp | 12 +++++-------
2 files changed, 16 insertions(+), 11 deletions(-)

[DebugInfo][RemoveDIs] Find types hidden in DbgRecords f3da9af3fd26
llvm/lib/IR/DebugProgramInstruction.cpp | 5 +++--
llvm/lib/IR/TypeFinder.cpp | 14 ++++++++++++++
2 files changed, 17 insertions(+), 2 deletions(-)

[IndVars] Check if WideInc available before trying to use it e594b284810c
llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | 28 +++++++++++++++++-----------
1 file changed, 17 insertions(+), 11 deletions(-)

[Instrumentation] Fix EdgeCounts vector size in SetBranchWeights f131edf6fbe8
llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)

[RemoveDIs] Simplify spliceDebugInfo, fixing splice-to-end edge case e1be8cf8723e
llvm/lib/IR/BasicBlock.cpp | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)

[analyzer] Add missing include <unordered_map> to llvm/lib/Support/Z3Solver.cpp 894ec4e3a1d5
llvm/lib/Support/Z3Solver.cpp | 1 +
1 file changed, 1 insertion(+)

[PowerPC] Fix mask for __st[d/w/h/b]cx builtins ed699666de2d
llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 4 ++--
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 12 ++++++------
2 files changed, 8 insertions(+), 8 deletions(-)

[AMDGPU] Remove one case of vmcnt loop header flushing for GFX12 09cca6b1897d
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

[AMDGPU] GFX12 VMEM loads can write VGPR results out of order 441fb41cb487
llvm/lib/Target/AMDGPU/AMDGPU.td | 23 +++++++++++++++++------
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +++
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 7 ++++---
3 files changed, 24 insertions(+), 9 deletions(-)

[PowerPC] Respect endianness when bitcasting to fp128 45b149d25319
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)

[llvm][CodeGen] Address the issue of multiple resource reservations In window scheduling 54579830d81a
llvm/lib/CodeGen/WindowScheduler.cpp | 1 -
1 file changed, 1 deletion(-)

[llvm][CodeGen] Fixed max cycle calculation with zero-cost instructions for window scheduler 5a164a28e37f
llvm/lib/CodeGen/WindowScheduler.cpp | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)

[llvm][CodeGen] Fixed a bug in stall cycle calculation for window scheduler 06d009789f77
llvm/lib/CodeGen/WindowScheduler.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

[llvm][CodeGen] Added a new restriction for II by pragma in window scheduler 7b86034dcb8c
llvm/lib/CodeGen/MachinePipeliner.cpp | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

[llvm][CodeGen] Added missing initialization failure information for window scheduler e81188d58202
llvm/lib/CodeGen/WindowScheduler.cpp | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

[AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a). eba1ef5a1b7a
llvm/lib/Target/AArch64/AArch64Processors.td | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

[DwarfEhPrepare] Assign dummy debug location for more inserted _Unwind_Resume calls 5f744ee5c770
llvm/lib/CodeGen/DwarfEHPrepare.cpp | 7 +++++++
1 file changed, 7 insertions(+)

[MCA][X86] Add missing 512-bit vpscatterqd/vscatterqps schedule data (REAPPLIED) cfe8eb89cbb8
llvm/lib/Target/X86/X86SchedIceLake.td | 2 ++
llvm/lib/Target/X86/X86SchedSkylakeServer.td | 2 ++
2 files changed, 4 insertions(+)

[ConstraintElim] Fix miscompilation caused by PR97974 3ff9d92aae09
llvm/lib/Transforms/Scalar/ConstraintElimination.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

[DAGCombiner] Fix ReplaceAllUsesOfValueWith mutation bug in visitFREEZE b6a562d90fa0
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)

[AMDGPU] Disable inline constants for pseudo scalar transcendentals 43b455b2d2e5
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 6 ++++++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++++
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 8 ++++++++
3 files changed, 18 insertions(+)

[SPARC] Remove assertions in printOperand for inline asm operands 8ea372d8b628
llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 51 -------------------------------
1 file changed, 51 deletions(-)

[apiraino]

Beta backport accepted as per compiler team on Zulip. A backport PR will be authored by the release team at the end of the current development cycle.

@rustbot label +beta-accepted