Add riscv vxworks targets

Author: biabbas

compiler/rustc_target/src/spec/mod.rs

@@ -1842,6 +1842,8 @@ supported_targets! {
     ("powerpc-wrs-vxworks", powerpc_wrs_vxworks),
     ("powerpc-wrs-vxworks-spe", powerpc_wrs_vxworks_spe),
     ("powerpc64-wrs-vxworks", powerpc64_wrs_vxworks),
+    ("riscv32-wrs-vxworks", riscv32_wrs_vxworks),
+    ("riscv64-wrs-vxworks", riscv64_wrs_vxworks),
 
     ("aarch64-kmc-solid_asp3", aarch64_kmc_solid_asp3),
     ("armv7a-kmc-solid_asp3-eabi", armv7a_kmc_solid_asp3_eabi),

compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs

@@ -0,0 +1,21 @@
+use crate::spec::{base, StackProbeType, Target, Cc, LinkerFlavor, Lld};
+pub(crate) fn target() -> Target {
+    let mut base = base::vxworks::opts();
+    base.cpu = "generic-rv32".into();
+    base.max_atomic_width = Some(64);
+    base.add_pre_link_args(LinkerFlavor::Gnu(Cc::Yes, Lld::No), &["-m32"]);
+    base.stack_probes = StackProbeType::Inline;
+    Target {
+        llvm_target: "riscv32".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: Some(3),
+            host_tools: Some(false),
+            std: Some(true),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
+        arch: "risv32".into(),
+        options: base,
+    }
+}

compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs

@@ -0,0 +1,20 @@
+use crate::spec::{base, StackProbeType, Target};
+pub(crate) fn target() -> Target {
+    let mut base = base::vxworks::opts();
+    base.cpu = "generic-rv64".into();
+    base.max_atomic_width = Some(64);
+    base.stack_probes = StackProbeType::Inline;
+    Target {
+        llvm_target: "riscv64".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: Some(3),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 64,
+        data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
+        arch: "risv64".into(),
+        options: base,
+    }
+}

tests/assembly/targets/targets-elf.rs

@@ -615,6 +615,9 @@
 //@ revisions: thumbv8m_main_nuttx_eabihf
 //@ [thumbv8m_main_nuttx_eabihf] compile-flags: --target thumbv8m.main-nuttx-eabihf
 //@ [thumbv8m_main_nuttx_eabihf] needs-llvm-components: arm
+//@ revisions: riscv32_wrs_vxworks
+//@ [riscv32_wrs_vxworks] compile-flags: --target riscv32-wrs-vxworks
+//@ [riscv32_wrs_vxworks] needs-llvm-components: riscv
 //@ revisions: riscv32imc_unknown_nuttx_elf
 //@ [riscv32imc_unknown_nuttx_elf] compile-flags: --target riscv32imc-unknown-nuttx-elf
 //@ [riscv32imc_unknown_nuttx_elf] needs-llvm-components: riscv
@@ -624,6 +627,9 @@
 //@ revisions: riscv32imafc_unknown_nuttx_elf
 //@ [riscv32imafc_unknown_nuttx_elf] compile-flags: --target riscv32imafc-unknown-nuttx-elf
 //@ [riscv32imafc_unknown_nuttx_elf] needs-llvm-components: riscv
+//@ revisions: riscv64_wrs_vxworks
+//@ [riscv64_wrs_vxworks] compile-flags: --target riscv64-wrs-vxworks
+//@ [riscv64_wrs_vxworks] needs-llvm-components: riscv
 //@ revisions: riscv64imac_unknown_nuttx_elf
 //@ [riscv64imac_unknown_nuttx_elf] compile-flags: --target riscv64imac-unknown-nuttx-elf
 //@ [riscv64imac_unknown_nuttx_elf] needs-llvm-components: riscv