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| 1 | +# `armv7a-none-eabi` and `armv7a-none-eabihf` |
| 2 | + |
| 3 | +* **Tier: 2** for `armv7a-none-eabi` |
| 4 | +* **Tier: 3** for `armv7a-none-eabihf` |
| 5 | +* **Library Support:** core and alloc (bare-metal, `#![no_std]`) |
| 6 | + |
| 7 | +Bare-metal target for CPUs in the Armv7-A architecture family, supporting |
| 8 | +dual ARM/Thumb mode, with ARM mode as the default. |
| 9 | + |
| 10 | +Note, this is for processors running in AArch32 mode. For the AArch64 mode |
| 11 | +added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead. |
| 12 | + |
| 13 | +Processors in this family include the [Arm Cortex-A5, 8, 32, etc][cortex-a]. |
| 14 | + |
| 15 | +See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all |
| 16 | +`arm-none-eabi` targets. |
| 17 | + |
| 18 | +[cortex-a]: https://en.wikipedia.org/wiki/ARM_Cortex-A |
| 19 | + |
| 20 | +## Target maintainers |
| 21 | + |
| 22 | +[Rust Embedded Devices Working Group Arm Team] |
| 23 | + |
| 24 | +[Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team |
| 25 | + |
| 26 | +## Requirements |
| 27 | + |
| 28 | +Almost all Armv7-A processors include an FPU (a VFPv3 or a VFPv4). The |
| 29 | +difference between the `-eabi` and `-eabihf` targets is whether the FPU is |
| 30 | +used for passing function arguments. You may prefer the `-eabi` soft-float |
| 31 | +target when the processor does not have a floating point unit or the compiled |
| 32 | +code should not use the floating point unit. |
| 33 | + |
| 34 | +When using the hardfloat targets, the minimum floating-point features assumed |
| 35 | +are those of the VFPv3-D16, which includes single- and double-precision, with |
| 36 | +16 double-precision registers. This floating-point unit appears in Cortex-A8 |
| 37 | +and Cortex-A9 processors. See [VFP in the Cortex-A processors][vfp] for more |
| 38 | +details on the possible FPU variants. |
| 39 | + |
| 40 | +If your processor supports a different set of floating-point features than the |
| 41 | +default expectations of VFPv3-D16, then these should also be enabled or |
| 42 | +disabled as needed with `-C target-feature=(+/-)`. |
| 43 | + |
| 44 | +In general, the following four combinations are possible: |
| 45 | + |
| 46 | +- VFPv3-D16, target feature `+vfp3` and `-d32` |
| 47 | +- VFPv3-D32, target feature `+vfp3` and `+d32` |
| 48 | +- VFPv4-D16, target feature `+vfp4` and `-d32` |
| 49 | +- VFPv4-D32, target feature `+vfp4` and `+d32` |
| 50 | + |
| 51 | +An Armv7-A processor may optionally include a NEON hardware unit which |
| 52 | +provides Single Instruction Multiple Data (SIMD) operations. The |
| 53 | +implementation of this unit implies VFPv3-D32. The target feature `+neon` may |
| 54 | +be added to inform the compiler about the availability of NEON. |
| 55 | + |
| 56 | +You can refer to the [arm-none-eabi](arm-none-eabi.md) documentation for a |
| 57 | +generic guide on target feature and target CPU specification and how to enable |
| 58 | +and disable them via `.cargo/config.toml` file. |
| 59 | + |
| 60 | +[vfp]: https://developer.arm.com/documentation/den0013/0400/Floating-Point/Floating-point-basics-and-the-IEEE-754-standard/ARM-VFP |
| 61 | + |
| 62 | +## Start-up and Low-Level Code |
| 63 | + |
| 64 | +The [Rust Embedded Devices Working Group Arm Team] maintain the [`cortex-ar`] |
| 65 | +and [`cortex-a-rt`] crates, which may be useful for writing bare-metal code |
| 66 | +using this target. The [`cortex-ar` repository](https://github.com/rust-embedded/cortex-ar) |
| 67 | +includes several examples which run in QEMU and build using these targets. |
| 68 | + |
| 69 | +[`cortex-ar`]: https://docs.rs/cortex-ar |
| 70 | +[`cortex-a-rt`]: https://docs.rs/cortex-a-rt |
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