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Auto merge of #147645 - tamird:arch-enum, r=nnethercote
rustc_target: introduce Arch Improve type safety by using an enum rather than strings.
2 parents 8692a99 + e381171 commit 77d99d7

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7 files changed

+60
-20
lines changed

7 files changed

+60
-20
lines changed

‎src/machine.rs‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ use rustc_span::def_id::{CrateNum, DefId};
3131
use rustc_span::{Span, SpanData, Symbol};
3232
use rustc_symbol_mangling::mangle_internal_symbol;
3333
use rustc_target::callconv::FnAbi;
34+
use rustc_target::spec::Arch;
3435

3536
use crate::alloc_addresses::EvalContextExt;
3637
use crate::concurrency::cpu_affinity::{self, CpuAffinityMask};
@@ -716,9 +717,9 @@ impl<'tcx> MiriMachine<'tcx> {
716717
page_size
717718
} else {
718719
let target = &tcx.sess.target;
719-
match target.arch.as_ref() {
720-
"wasm32" | "wasm64" => 64 * 1024, // https://webassembly.github.io/spec/core/exec/runtime.html#memory-instances
721-
"aarch64" => {
720+
match target.arch {
721+
Arch::Wasm32 | Arch::Wasm64 => 64 * 1024, // https://webassembly.github.io/spec/core/exec/runtime.html#memory-instances
722+
Arch::AArch64 => {
722723
if target.options.vendor.as_ref() == "apple" {
723724
// No "definitive" source, but see:
724725
// https://www.wwdcnotes.com/notes/wwdc20/10214/

‎src/shims/alloc.rs‎

Lines changed: 36 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ use rustc_ast::expand::allocator::SpecialAllocatorMethod;
33
use rustc_middle::ty::Ty;
44
use rustc_span::Symbol;
55
use rustc_target::callconv::FnAbi;
6+
use rustc_target::spec::Arch;
67

78
use crate::*;
89

@@ -19,14 +20,41 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
1920
// `library/std/src/sys/alloc/mod.rs` (where this is called `MIN_ALIGN`) and should
2021
// be kept in sync.
2122
let os = this.tcx.sess.target.os.as_ref();
22-
let max_fundamental_align = match this.tcx.sess.target.arch.as_ref() {
23-
"riscv32" if matches!(os, "espidf" | "zkvm") => 4,
24-
"xtensa" if matches!(os, "espidf") => 4,
25-
"x86" | "arm" | "m68k" | "csky" | "loongarch32" | "mips" | "mips32r6" | "powerpc"
26-
| "powerpc64" | "sparc" | "wasm32" | "hexagon" | "riscv32" | "xtensa" => 8,
27-
"x86_64" | "aarch64" | "arm64ec" | "loongarch64" | "mips64" | "mips64r6" | "s390x"
28-
| "sparc64" | "riscv64" | "wasm64" => 16,
29-
arch => bug!("unsupported target architecture for malloc: `{}`", arch),
23+
let max_fundamental_align = match &this.tcx.sess.target.arch {
24+
Arch::RiscV32 if matches!(os, "espidf" | "zkvm") => 4,
25+
Arch::Xtensa if matches!(os, "espidf") => 4,
26+
Arch::X86
27+
| Arch::Arm
28+
| Arch::M68k
29+
| Arch::CSky
30+
| Arch::LoongArch32
31+
| Arch::Mips
32+
| Arch::Mips32r6
33+
| Arch::PowerPC
34+
| Arch::PowerPC64
35+
| Arch::Sparc
36+
| Arch::Wasm32
37+
| Arch::Hexagon
38+
| Arch::RiscV32
39+
| Arch::Xtensa => 8,
40+
Arch::X86_64
41+
| Arch::AArch64
42+
| Arch::Arm64EC
43+
| Arch::LoongArch64
44+
| Arch::Mips64
45+
| Arch::Mips64r6
46+
| Arch::S390x
47+
| Arch::Sparc64
48+
| Arch::RiscV64
49+
| Arch::Wasm64 => 16,
50+
arch @ (Arch::AmdGpu
51+
| Arch::Avr
52+
| Arch::Bpf
53+
| Arch::Msp430
54+
| Arch::Nvptx64
55+
| Arch::PowerPC64LE
56+
| Arch::SpirV
57+
| Arch::Unknown(_)) => bug!("unsupported target architecture for malloc: `{arch}`"),
3058
};
3159
// The C standard only requires sufficient alignment for any *type* with size less than or
3260
// equal to the size requested. Types one can define in standard C seem to never have an alignment

‎src/shims/foreign_items.rs‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ use rustc_middle::{mir, ty};
1515
use rustc_session::config::OomStrategy;
1616
use rustc_span::Symbol;
1717
use rustc_target::callconv::FnAbi;
18+
use rustc_target::spec::Arch;
1819

1920
use super::alloc::EvalContextExt as _;
2021
use super::backtrace::EvalContextExt as _;
@@ -800,20 +801,24 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
800801

801802
// Target-specific shims
802803
name if name.starts_with("llvm.x86.")
803-
&& (this.tcx.sess.target.arch == "x86"
804-
|| this.tcx.sess.target.arch == "x86_64") =>
804+
&& matches!(
805+
this.tcx.sess.target.arch,
806+
Arch::X86 | Arch::X86_64
807+
) =>
805808
{
806809
return shims::x86::EvalContextExt::emulate_x86_intrinsic(
807810
this, link_name, abi, args, dest,
808811
);
809812
}
810-
name if name.starts_with("llvm.aarch64.") && this.tcx.sess.target.arch == "aarch64" => {
813+
name if name.starts_with("llvm.aarch64.")
814+
&& this.tcx.sess.target.arch == Arch::AArch64 =>
815+
{
811816
return shims::aarch64::EvalContextExt::emulate_aarch64_intrinsic(
812817
this, link_name, abi, args, dest,
813818
);
814819
}
815820
// FIXME: Move this to an `arm` submodule.
816-
"llvm.arm.hint" if this.tcx.sess.target.arch == "arm" => {
821+
"llvm.arm.hint" if this.tcx.sess.target.arch == Arch::Arm => {
817822
let [arg] = this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;
818823
let arg = this.read_scalar(arg)?.to_i32()?;
819824
// Note that different arguments might have different target feature requirements.

‎src/shims/windows/foreign_items.rs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ use rustc_abi::{Align, CanonAbi, Size, X86Call};
66
use rustc_middle::ty::Ty;
77
use rustc_span::Symbol;
88
use rustc_target::callconv::FnAbi;
9+
use rustc_target::spec::Arch;
910

1011
use self::shims::windows::handle::{Handle, PseudoHandle};
1112
use crate::shims::os_str::bytes_to_os_str;
@@ -140,7 +141,7 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
140141
// https://github.com/rust-lang/rust/blob/fb00adbdb69266f10df95a4527b767b0ad35ea48/compiler/rustc_target/src/spec/mod.rs#L2766-L2768,
141142
// x86-32 Windows uses a different calling convention than other Windows targets
142143
// for the "system" ABI.
143-
let sys_conv = if this.tcx.sess.target.arch == "x86" {
144+
let sys_conv = if this.tcx.sess.target.arch == Arch::X86 {
144145
CanonAbi::X86(X86Call::Stdcall)
145146
} else {
146147
CanonAbi::C

‎src/shims/x86/bmi.rs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ use rustc_abi::CanonAbi;
22
use rustc_middle::ty::Ty;
33
use rustc_span::Symbol;
44
use rustc_target::callconv::FnAbi;
5+
use rustc_target::spec::Arch;
56

67
use crate::*;
78

@@ -31,7 +32,7 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
3132
let target_feature = if unprefixed_name == "bextr" { "bmi1" } else { "bmi2" };
3233
this.expect_target_feature_for_intrinsic(link_name, target_feature)?;
3334

34-
if is_64_bit && this.tcx.sess.target.arch != "x86_64" {
35+
if is_64_bit && this.tcx.sess.target.arch != Arch::X86_64 {
3536
return interp_ok(EmulateItemResult::NotSupported);
3637
}
3738

‎src/shims/x86/mod.rs‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ use rustc_middle::ty::Ty;
55
use rustc_middle::{mir, ty};
66
use rustc_span::Symbol;
77
use rustc_target::callconv::FnAbi;
8+
use rustc_target::spec::Arch;
89

910
use self::helpers::bool_to_simd_element;
1011
use crate::*;
@@ -41,7 +42,9 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
4142
// https://www.intel.com/content/www/us/en/docs/cpp-compiler/developer-guide-reference/2021-8/addcarry-u32-addcarry-u64.html
4243
// https://www.intel.com/content/www/us/en/docs/cpp-compiler/developer-guide-reference/2021-8/subborrow-u32-subborrow-u64.html
4344
"addcarry.32" | "addcarry.64" | "subborrow.32" | "subborrow.64" => {
44-
if unprefixed_name.ends_with("64") && this.tcx.sess.target.arch != "x86_64" {
45+
if unprefixed_name.ends_with("64")
46+
&& this.tcx.sess.target.arch != Arch::X86_64
47+
{
4548
return interp_ok(EmulateItemResult::NotSupported);
4649
}
4750

@@ -65,7 +68,7 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
6568
this.expect_target_feature_for_intrinsic(link_name, "adx")?;
6669

6770
let is_u64 = unprefixed_name.ends_with("64");
68-
if is_u64 && this.tcx.sess.target.arch != "x86_64" {
71+
if is_u64 && this.tcx.sess.target.arch != Arch::X86_64 {
6972
return interp_ok(EmulateItemResult::NotSupported);
7073
}
7174
let [c_in, a, b, out] =

‎src/shims/x86/sse42.rs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ use rustc_middle::mir;
33
use rustc_middle::ty::Ty;
44
use rustc_span::Symbol;
55
use rustc_target::callconv::FnAbi;
6+
use rustc_target::spec::Arch;
67

78
use crate::*;
89

@@ -431,7 +432,7 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
431432
_ => unreachable!(),
432433
};
433434

434-
if bit_size == 64 && this.tcx.sess.target.arch != "x86_64" {
435+
if bit_size == 64 && this.tcx.sess.target.arch != Arch::X86_64 {
435436
return interp_ok(EmulateItemResult::NotSupported);
436437
}
437438

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