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Convert more EVT's to MVT's in the lowering methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172995 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -8296,9 +8296,9 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) co
82968296

82978297
static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
82988298
const X86Subtarget *Subtarget) {
8299-
EVT VT = Op->getValueType(0);
8299+
MVT VT = Op->getValueType(0).getSimpleVT();
83008300
SDValue In = Op->getOperand(0);
8301-
EVT InVT = In.getValueType();
8301+
MVT InVT = In.getValueType().getSimpleVT();
83028302
DebugLoc dl = Op->getDebugLoc();
83038303

83048304
// Optimize vectors in AVX mode:
@@ -8327,7 +8327,7 @@ static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
83278327
SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
83288328
SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
83298329

8330-
EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8330+
MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
83318331
VT.getVectorNumElements()/2);
83328332

83338333
OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
@@ -8349,9 +8349,9 @@ SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
83498349
SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
83508350
SelectionDAG &DAG) const {
83518351
DebugLoc DL = Op.getDebugLoc();
8352-
EVT VT = Op.getValueType();
8352+
MVT VT = Op.getValueType().getSimpleVT();
83538353
SDValue In = Op.getOperand(0);
8354-
EVT SVT = In.getValueType();
8354+
MVT SVT = In.getValueType().getSimpleVT();
83558355

83568356
if (Subtarget->hasFp256()) {
83578357
SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
@@ -8381,9 +8381,9 @@ SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
83818381

83828382
SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
83838383
DebugLoc DL = Op.getDebugLoc();
8384-
EVT VT = Op.getValueType();
8384+
MVT VT = Op.getValueType().getSimpleVT();
83858385
SDValue In = Op.getOperand(0);
8386-
EVT SVT = In.getValueType();
8386+
MVT SVT = In.getValueType().getSimpleVT();
83878387

83888388
if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
83898389
// On AVX2, v4i64 -> v4i32 becomes VPERMD.
@@ -8498,9 +8498,10 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
84988498

84998499
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
85008500
SelectionDAG &DAG) const {
8501-
if (Op.getValueType().isVector()) {
8502-
if (Op.getValueType() == MVT::v8i16)
8503-
return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(),
8501+
MVT VT = Op.getValueType().getSimpleVT();
8502+
if (VT.isVector()) {
8503+
if (VT == MVT::v8i16)
8504+
return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
85048505
DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
85058506
MVT::v8i32, Op.getOperand(0)));
85068507
return SDValue();
@@ -8542,9 +8543,9 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
85428543
SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
85438544
SelectionDAG &DAG) const {
85448545
DebugLoc DL = Op.getDebugLoc();
8545-
EVT VT = Op.getValueType();
8546+
MVT VT = Op.getValueType().getSimpleVT();
85468547
SDValue In = Op.getOperand(0);
8547-
EVT SVT = In.getValueType();
8548+
MVT SVT = In.getValueType().getSimpleVT();
85488549

85498550
assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
85508551

@@ -8556,8 +8557,8 @@ SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
85568557
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
85578558
LLVMContext *Context = DAG.getContext();
85588559
DebugLoc dl = Op.getDebugLoc();
8559-
EVT VT = Op.getValueType();
8560-
EVT EltVT = VT;
8560+
MVT VT = Op.getValueType().getSimpleVT();
8561+
MVT EltVT = VT;
85618562
unsigned NumElts = VT == MVT::f64 ? 2 : 4;
85628563
if (VT.isVector()) {
85638564
EltVT = VT.getVectorElementType();
@@ -8588,8 +8589,8 @@ SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
85888589
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
85898590
LLVMContext *Context = DAG.getContext();
85908591
DebugLoc dl = Op.getDebugLoc();
8591-
EVT VT = Op.getValueType();
8592-
EVT EltVT = VT;
8592+
MVT VT = Op.getValueType().getSimpleVT();
8593+
MVT EltVT = VT;
85938594
unsigned NumElts = VT == MVT::f64 ? 2 : 4;
85948595
if (VT.isVector()) {
85958596
EltVT = VT.getVectorElementType();
@@ -8623,8 +8624,8 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
86238624
SDValue Op0 = Op.getOperand(0);
86248625
SDValue Op1 = Op.getOperand(1);
86258626
DebugLoc dl = Op.getDebugLoc();
8626-
EVT VT = Op.getValueType();
8627-
EVT SrcVT = Op1.getValueType();
8627+
MVT VT = Op.getValueType().getSimpleVT();
8628+
MVT SrcVT = Op1.getValueType().getSimpleVT();
86288629

86298630
// If second operand is smaller, extend it first.
86308631
if (SrcVT.bitsLT(VT)) {
@@ -8694,7 +8695,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
86948695
static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
86958696
SDValue N0 = Op.getOperand(0);
86968697
DebugLoc dl = Op.getDebugLoc();
8697-
EVT VT = Op.getValueType();
8698+
MVT VT = Op.getValueType().getSimpleVT();
86988699

86998700
// Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
87008701
SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
@@ -9499,7 +9500,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
94999500

95009501
SDValue Cmp = Cond.getOperand(1);
95019502
unsigned Opc = Cmp.getOpcode();
9502-
EVT VT = Op.getValueType();
9503+
MVT VT = Op.getValueType().getSimpleVT();
95039504

95049505
bool IllegalFPCMov = false;
95059506
if (VT.isFloatingPoint() && !VT.isVector() &&
@@ -9610,9 +9611,9 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
96109611

96119612
SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
96129613
SelectionDAG &DAG) const {
9613-
EVT VT = Op->getValueType(0);
9614+
MVT VT = Op->getValueType(0).getSimpleVT();
96149615
SDValue In = Op->getOperand(0);
9615-
EVT InVT = In.getValueType();
9616+
MVT InVT = In.getValueType().getSimpleVT();
96169617
DebugLoc dl = Op->getDebugLoc();
96179618

96189619
if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
@@ -9646,7 +9647,7 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
96469647

96479648
SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
96489649

9649-
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
9650+
MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
96509651
VT.getVectorNumElements()/2);
96519652

96529653
OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);

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