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Commit 53abc28

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Merging r276980:
------------------------------------------------------------------------ r276980 | tstellar | 2016-07-28 07:30:43 -0700 (Thu, 28 Jul 2016) | 12 lines AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling Summary: We were using reserved VGPRs for SGPR spilling and this was causing some programs with a workgroup size of 1024 to use more than 64 registers, which is illegal. Reviewers: arsenm, mareko, nhaehnle Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22032 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277084 91177308-0d34-0410-b5e6-96231b3b80d8
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-6
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lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -738,7 +738,8 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(
738738
MachineBasicBlock::iterator Insert = Entry.front();
739739
DebugLoc DL = Insert->getDebugLoc();
740740

741-
TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
741+
TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
742+
*MF);
742743
if (TIDReg == AMDGPU::NoRegister)
743744
return TIDReg;
744745

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg (
203203
Spill.Lane = Lane;
204204

205205
if (!LaneVGPRs.count(LaneVGPRIdx)) {
206-
unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
206+
unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
207+
*MF);
207208

208209
if (LaneVGPR == AMDGPU::NoRegister)
209210
// We have no VGPRs left for spilling SGPRs.

lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -957,10 +957,13 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
957957
/// \brief Returns a register that is not used at any point in the function.
958958
/// If all registers are used, then this function will return
959959
// AMDGPU::NoRegister.
960-
unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
961-
const TargetRegisterClass *RC) const {
960+
unsigned
961+
SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
962+
const TargetRegisterClass *RC,
963+
const MachineFunction &MF) const {
964+
962965
for (unsigned Reg : *RC)
963-
if (!MRI.isPhysRegUsed(Reg))
966+
if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
964967
return Reg;
965968
return AMDGPU::NoRegister;
966969
}

lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -185,7 +185,8 @@ struct SIRegisterInfo final : public AMDGPURegisterInfo {
185185
unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
186186

187187
unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
188-
const TargetRegisterClass *RC) const;
188+
const TargetRegisterClass *RC,
189+
const MachineFunction &MF) const;
189190

190191
unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
191192
unsigned getVGPR32PressureSet() const { return VGPR32SetID; };

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