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Commit 4bef961

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topperctopperc
committed
Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 4d0cdca commit 4bef961

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2 files changed

+62
-229
lines changed

2 files changed

+62
-229
lines changed

‎lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines changed: 55 additions & 229 deletions
Original file line numberDiff line numberDiff line change
@@ -1739,242 +1739,68 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
17391739
return false;
17401740
}
17411741

1742-
bool X86AsmParser::
1743-
processInstruction(MCInst &Inst,
1744-
const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1745-
switch (Inst.getOpcode()) {
1746-
default: return false;
1747-
case X86::AND16i16: {
1748-
if (!Inst.getOperand(0).isImm() ||
1749-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1750-
return false;
1751-
1752-
MCInst TmpInst;
1753-
TmpInst.setOpcode(X86::AND16ri8);
1754-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1755-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1756-
TmpInst.addOperand(Inst.getOperand(0));
1757-
Inst = TmpInst;
1758-
return true;
1759-
}
1760-
case X86::AND32i32: {
1761-
if (!Inst.getOperand(0).isImm() ||
1762-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1763-
return false;
1764-
1765-
MCInst TmpInst;
1766-
TmpInst.setOpcode(X86::AND32ri8);
1767-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1768-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1769-
TmpInst.addOperand(Inst.getOperand(0));
1770-
Inst = TmpInst;
1771-
return true;
1772-
}
1773-
case X86::AND64i32: {
1774-
if (!Inst.getOperand(0).isImm() ||
1775-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1776-
return false;
1777-
1778-
MCInst TmpInst;
1779-
TmpInst.setOpcode(X86::AND64ri8);
1780-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1781-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1782-
TmpInst.addOperand(Inst.getOperand(0));
1783-
Inst = TmpInst;
1784-
return true;
1785-
}
1786-
case X86::XOR16i16: {
1787-
if (!Inst.getOperand(0).isImm() ||
1788-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1789-
return false;
1790-
1791-
MCInst TmpInst;
1792-
TmpInst.setOpcode(X86::XOR16ri8);
1793-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1794-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1795-
TmpInst.addOperand(Inst.getOperand(0));
1796-
Inst = TmpInst;
1797-
return true;
1798-
}
1799-
case X86::XOR32i32: {
1800-
if (!Inst.getOperand(0).isImm() ||
1801-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1802-
return false;
1803-
1804-
MCInst TmpInst;
1805-
TmpInst.setOpcode(X86::XOR32ri8);
1806-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1807-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1808-
TmpInst.addOperand(Inst.getOperand(0));
1809-
Inst = TmpInst;
1810-
return true;
1811-
}
1812-
case X86::XOR64i32: {
1813-
if (!Inst.getOperand(0).isImm() ||
1814-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1815-
return false;
1816-
1817-
MCInst TmpInst;
1818-
TmpInst.setOpcode(X86::XOR64ri8);
1819-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1820-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1821-
TmpInst.addOperand(Inst.getOperand(0));
1822-
Inst = TmpInst;
1823-
return true;
1824-
}
1825-
case X86::OR16i16: {
1826-
if (!Inst.getOperand(0).isImm() ||
1827-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1828-
return false;
1829-
1830-
MCInst TmpInst;
1831-
TmpInst.setOpcode(X86::OR16ri8);
1832-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1833-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1834-
TmpInst.addOperand(Inst.getOperand(0));
1835-
Inst = TmpInst;
1836-
return true;
1837-
}
1838-
case X86::OR32i32: {
1839-
if (!Inst.getOperand(0).isImm() ||
1840-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1841-
return false;
1842-
1843-
MCInst TmpInst;
1844-
TmpInst.setOpcode(X86::OR32ri8);
1845-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1846-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1847-
TmpInst.addOperand(Inst.getOperand(0));
1848-
Inst = TmpInst;
1849-
return true;
1850-
}
1851-
case X86::OR64i32: {
1852-
if (!Inst.getOperand(0).isImm() ||
1853-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1854-
return false;
1855-
1856-
MCInst TmpInst;
1857-
TmpInst.setOpcode(X86::OR64ri8);
1858-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1859-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1860-
TmpInst.addOperand(Inst.getOperand(0));
1861-
Inst = TmpInst;
1862-
return true;
1863-
}
1864-
case X86::CMP16i16: {
1865-
if (!Inst.getOperand(0).isImm() ||
1866-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1867-
return false;
1868-
1869-
MCInst TmpInst;
1870-
TmpInst.setOpcode(X86::CMP16ri8);
1871-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1872-
TmpInst.addOperand(Inst.getOperand(0));
1873-
Inst = TmpInst;
1874-
return true;
1875-
}
1876-
case X86::CMP32i32: {
1877-
if (!Inst.getOperand(0).isImm() ||
1878-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1879-
return false;
1880-
1881-
MCInst TmpInst;
1882-
TmpInst.setOpcode(X86::CMP32ri8);
1883-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1884-
TmpInst.addOperand(Inst.getOperand(0));
1885-
Inst = TmpInst;
1886-
return true;
1887-
}
1888-
case X86::CMP64i32: {
1889-
if (!Inst.getOperand(0).isImm() ||
1890-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1891-
return false;
1742+
static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
1743+
bool isCmp) {
1744+
MCInst TmpInst;
1745+
TmpInst.setOpcode(Opcode);
1746+
if (!isCmp)
1747+
TmpInst.addOperand(MCOperand::CreateReg(Reg));
1748+
TmpInst.addOperand(MCOperand::CreateReg(Reg));
1749+
TmpInst.addOperand(Inst.getOperand(0));
1750+
Inst = TmpInst;
1751+
return true;
1752+
}
18921753

1893-
MCInst TmpInst;
1894-
TmpInst.setOpcode(X86::CMP64ri8);
1895-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1896-
TmpInst.addOperand(Inst.getOperand(0));
1897-
Inst = TmpInst;
1898-
return true;
1899-
}
1900-
case X86::ADD16i16: {
1901-
if (!Inst.getOperand(0).isImm() ||
1902-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1903-
return false;
1754+
static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
1755+
bool isCmp = false) {
1756+
if (!Inst.getOperand(0).isImm() ||
1757+
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1758+
return false;
19041759

1905-
MCInst TmpInst;
1906-
TmpInst.setOpcode(X86::ADD16ri8);
1907-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1908-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1909-
TmpInst.addOperand(Inst.getOperand(0));
1910-
Inst = TmpInst;
1911-
return true;
1912-
}
1913-
case X86::ADD32i32: {
1914-
if (!Inst.getOperand(0).isImm() ||
1915-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1916-
return false;
1760+
return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
1761+
}
19171762

1918-
MCInst TmpInst;
1919-
TmpInst.setOpcode(X86::ADD32ri8);
1920-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1921-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1922-
TmpInst.addOperand(Inst.getOperand(0));
1923-
Inst = TmpInst;
1924-
return true;
1925-
}
1926-
case X86::ADD64i32: {
1927-
if (!Inst.getOperand(0).isImm() ||
1928-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1929-
return false;
1763+
static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
1764+
bool isCmp = false) {
1765+
if (!Inst.getOperand(0).isImm() ||
1766+
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1767+
return false;
19301768

1931-
MCInst TmpInst;
1932-
TmpInst.setOpcode(X86::ADD64ri8);
1933-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1934-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1935-
TmpInst.addOperand(Inst.getOperand(0));
1936-
Inst = TmpInst;
1937-
return true;
1938-
}
1939-
case X86::SUB16i16: {
1940-
if (!Inst.getOperand(0).isImm() ||
1941-
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1942-
return false;
1769+
return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
1770+
}
19431771

1944-
MCInst TmpInst;
1945-
TmpInst.setOpcode(X86::SUB16ri8);
1946-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1947-
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1948-
TmpInst.addOperand(Inst.getOperand(0));
1949-
Inst = TmpInst;
1950-
return true;
1951-
}
1952-
case X86::SUB32i32: {
1953-
if (!Inst.getOperand(0).isImm() ||
1954-
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1955-
return false;
1772+
static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
1773+
bool isCmp = false) {
1774+
if (!Inst.getOperand(0).isImm() ||
1775+
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1776+
return false;
19561777

1957-
MCInst TmpInst;
1958-
TmpInst.setOpcode(X86::SUB32ri8);
1959-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1960-
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1961-
TmpInst.addOperand(Inst.getOperand(0));
1962-
Inst = TmpInst;
1963-
return true;
1964-
}
1965-
case X86::SUB64i32: {
1966-
if (!Inst.getOperand(0).isImm() ||
1967-
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1968-
return false;
1778+
return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
1779+
}
19691780

1970-
MCInst TmpInst;
1971-
TmpInst.setOpcode(X86::SUB64ri8);
1972-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1973-
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1974-
TmpInst.addOperand(Inst.getOperand(0));
1975-
Inst = TmpInst;
1976-
return true;
1977-
}
1781+
bool X86AsmParser::
1782+
processInstruction(MCInst &Inst,
1783+
const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1784+
switch (Inst.getOpcode()) {
1785+
default: return false;
1786+
case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
1787+
case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
1788+
case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
1789+
case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
1790+
case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
1791+
case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
1792+
case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
1793+
case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
1794+
case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
1795+
case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
1796+
case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
1797+
case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
1798+
case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
1799+
case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
1800+
case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
1801+
case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
1802+
case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
1803+
case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
19781804
}
19791805
}
19801806

‎test/MC/X86/intel-syntax-encoding.s

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,13 @@
3131
// CHECK: encoding: [0x48,0x83,0xc0,0xf4]
3232
add rax, -12
3333

34+
// CHECK: encoding: [0x66,0x83,0xf8,0xf4]
35+
cmp ax, -12
36+
// CHECK: encoding: [0x83,0xf8,0xf4]
37+
cmp eax, -12
38+
// CHECK: encoding: [0x48,0x83,0xf8,0xf4]
39+
cmp rax, -12
40+
3441
LBB0_3:
3542
// CHECK: encoding: [0xeb,A]
3643
jmp LBB0_3

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