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Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 64437ea commit 4aee1bb

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7 files changed

+35
-34
lines changed

7 files changed

+35
-34
lines changed

‎lib/Target/X86/InstPrinter/X86InstComments.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -77,19 +77,19 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
7777
case X86::VPALIGNR128rm:
7878
Src2Name = getRegName(MI->getOperand(1).getReg());
7979
DestName = getRegName(MI->getOperand(0).getReg());
80-
DecodePALIGNMask(MVT::v16i8,
81-
MI->getOperand(MI->getNumOperands()-1).getImm(),
82-
ShuffleMask);
80+
DecodePALIGNRMask(MVT::v16i8,
81+
MI->getOperand(MI->getNumOperands()-1).getImm(),
82+
ShuffleMask);
8383
break;
8484
case X86::VPALIGNR256rr:
8585
Src1Name = getRegName(MI->getOperand(2).getReg());
8686
// FALL THROUGH.
8787
case X86::VPALIGNR256rm:
8888
Src2Name = getRegName(MI->getOperand(1).getReg());
8989
DestName = getRegName(MI->getOperand(0).getReg());
90-
DecodePALIGNMask(MVT::v32i8,
91-
MI->getOperand(MI->getNumOperands()-1).getImm(),
92-
ShuffleMask);
90+
DecodePALIGNRMask(MVT::v32i8,
91+
MI->getOperand(MI->getNumOperands()-1).getImm(),
92+
ShuffleMask);
9393

9494
case X86::PSHUFDri:
9595
case X86::VPSHUFDri:

‎lib/Target/X86/Utils/X86ShuffleDecode.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,8 @@ void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
6161
ShuffleMask.push_back(NElts+i);
6262
}
6363

64-
void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
64+
void DecodePALIGNRMask(MVT VT, unsigned Imm,
65+
SmallVectorImpl<int> &ShuffleMask) {
6566
unsigned NumElts = VT.getVectorNumElements();
6667
unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
6768

‎lib/Target/X86/Utils/X86ShuffleDecode.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
3535
// <0,2> or <0,1,4,5>
3636
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
3737

38-
void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
38+
void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
3939

4040
void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
4141

‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3004,7 +3004,7 @@ static bool isTargetShuffle(unsigned Opcode) {
30043004
case X86ISD::PSHUFHW:
30053005
case X86ISD::PSHUFLW:
30063006
case X86ISD::SHUFP:
3007-
case X86ISD::PALIGN:
3007+
case X86ISD::PALIGNR:
30083008
case X86ISD::MOVLHPS:
30093009
case X86ISD::MOVLHPD:
30103010
case X86ISD::MOVHLPS:
@@ -3054,7 +3054,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
30543054
SelectionDAG &DAG) {
30553055
switch(Opc) {
30563056
default: llvm_unreachable("Unknown x86 shuffle node");
3057-
case X86ISD::PALIGN:
3057+
case X86ISD::PALIGNR:
30583058
case X86ISD::SHUFP:
30593059
case X86ISD::VPERM2X128:
30603060
return DAG.getNode(Opc, dl, VT, V1, V2,
@@ -4592,9 +4592,9 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT,
45924592
case X86ISD::MOVLHPS:
45934593
DecodeMOVLHPSMask(NumElems, Mask);
45944594
break;
4595-
case X86ISD::PALIGN:
4595+
case X86ISD::PALIGNR:
45964596
ImmN = N->getOperand(N->getNumOperands()-1);
4597-
DecodePALIGNMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4597+
DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
45984598
break;
45994599
case X86ISD::PSHUFD:
46004600
case X86ISD::VPERMILP:
@@ -6932,7 +6932,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
69326932
// nodes, and remove one by one until they don't return Op anymore.
69336933

69346934
if (isPALIGNRMask(M, VT, Subtarget))
6935-
return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6935+
return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
69366936
getShufflePALIGNRImmediate(SVOp),
69376937
DAG);
69386938

@@ -12435,7 +12435,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1243512435
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
1243612436
case X86ISD::PTEST: return "X86ISD::PTEST";
1243712437
case X86ISD::TESTP: return "X86ISD::TESTP";
12438-
case X86ISD::PALIGN: return "X86ISD::PALIGN";
12438+
case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
1243912439
case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
1244012440
case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
1244112441
case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
@@ -17416,7 +17416,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
1741617416
case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
1741717417
case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
1741817418
case X86ISD::SHUFP: // Handle all target specific shuffles
17419-
case X86ISD::PALIGN:
17419+
case X86ISD::PALIGNR:
1742017420
case X86ISD::UNPCKH:
1742117421
case X86ISD::UNPCKL:
1742217422
case X86ISD::MOVHLPS:

‎lib/Target/X86/X86ISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,7 @@ namespace llvm {
294294
TESTP,
295295

296296
// Several flavors of instructions with vector shuffle behaviors.
297-
PALIGN,
297+
PALIGNR,
298298
PSHUFD,
299299
PSHUFHW,
300300
PSHUFLW,

‎lib/Target/X86/X86InstrFragmentsSIMD.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
160160
def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
161161
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
162162

163-
def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
163+
def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
164164

165165
def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
166166
def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;

‎lib/Target/X86/X86InstrSSE.td

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -5167,7 +5167,7 @@ defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
51675167
// SSSE3 - Packed Align Instruction Patterns
51685168
//===---------------------------------------------------------------------===//
51695169

5170-
multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5170+
multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
51715171
let neverHasSideEffects = 1 in {
51725172
def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
51735173
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
@@ -5187,7 +5187,7 @@ multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
51875187
}
51885188
}
51895189

5190-
multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5190+
multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
51915191
let neverHasSideEffects = 1 in {
51925192
def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
51935193
(ins VR256:$src1, VR256:$src2, i8imm:$src3),
@@ -5204,42 +5204,42 @@ multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
52045204
}
52055205

52065206
let Predicates = [HasAVX] in
5207-
defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5207+
defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
52085208
let Predicates = [HasAVX2] in
5209-
defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5209+
defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
52105210
let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5211-
defm PALIGN : ssse3_palign<"palignr">;
5211+
defm PALIGN : ssse3_palignr<"palignr">;
52125212

52135213
let Predicates = [HasAVX2] in {
5214-
def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5214+
def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52155215
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5216-
def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5216+
def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52175217
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5218-
def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5218+
def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52195219
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5220-
def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5220+
def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
52215221
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
52225222
}
52235223

52245224
let Predicates = [HasAVX] in {
5225-
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5225+
def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52265226
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5227-
def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5227+
def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52285228
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5229-
def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5229+
def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52305230
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5231-
def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5231+
def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52325232
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
52335233
}
52345234

52355235
let Predicates = [UseSSSE3] in {
5236-
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5236+
def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52375237
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5238-
def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5238+
def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52395239
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5240-
def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5240+
def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52415241
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5242-
def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5242+
def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
52435243
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
52445244
}
52455245

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