Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit 26827f3

Browse files
topperctopperc
committed
Make LowerVSETCC a static function and use MVT instead of EVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172969 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 0c8607b commit 26827f3

File tree

2 files changed

+65
-63
lines changed

2 files changed

+65
-63
lines changed

‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 65 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -9136,65 +9136,10 @@ SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
91369136
return SDValue();
91379137
}
91389138

9139-
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9140-
9141-
if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
9142-
9143-
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
9144-
SDValue Op0 = Op.getOperand(0);
9145-
SDValue Op1 = Op.getOperand(1);
9146-
DebugLoc dl = Op.getDebugLoc();
9147-
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9148-
9149-
// Optimize to BT if possible.
9150-
// Lower (X & (1 << N)) == 0 to BT(X, N).
9151-
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
9152-
// Lower ((X >>s N) & 1) != 0 to BT(X, N).
9153-
if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9154-
Op1.getOpcode() == ISD::Constant &&
9155-
cast<ConstantSDNode>(Op1)->isNullValue() &&
9156-
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
9157-
SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9158-
if (NewSetCC.getNode())
9159-
return NewSetCC;
9160-
}
9161-
9162-
// Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9163-
// these.
9164-
if (Op1.getOpcode() == ISD::Constant &&
9165-
(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9166-
cast<ConstantSDNode>(Op1)->isNullValue()) &&
9167-
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
9168-
9169-
// If the input is a setcc, then reuse the input setcc or use a new one with
9170-
// the inverted condition.
9171-
if (Op0.getOpcode() == X86ISD::SETCC) {
9172-
X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9173-
bool Invert = (CC == ISD::SETNE) ^
9174-
cast<ConstantSDNode>(Op1)->isNullValue();
9175-
if (!Invert) return Op0;
9176-
9177-
CCode = X86::GetOppositeBranchCondition(CCode);
9178-
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9179-
DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9180-
}
9181-
}
9182-
9183-
bool isFP = Op1.getValueType().isFloatingPoint();
9184-
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9185-
if (X86CC == X86::COND_INVALID)
9186-
return SDValue();
9187-
9188-
SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9189-
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9190-
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9191-
DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9192-
}
9193-
91949139
// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
91959140
// ones, and then concatenate the result back.
91969141
static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9197-
EVT VT = Op.getValueType();
9142+
MVT VT = Op.getValueType().getSimpleVT();
91989143

91999144
assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
92009145
"Unsupported value type for operation");
@@ -9214,26 +9159,27 @@ static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
92149159
SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
92159160

92169161
// Issue the operation on the smaller types and concatenate the result back
9217-
MVT EltVT = VT.getVectorElementType().getSimpleVT();
9218-
EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9162+
MVT EltVT = VT.getVectorElementType();
9163+
MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
92199164
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
92209165
DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
92219166
DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
92229167
}
92239168

9224-
SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
9169+
static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9170+
SelectionDAG &DAG) {
92259171
SDValue Cond;
92269172
SDValue Op0 = Op.getOperand(0);
92279173
SDValue Op1 = Op.getOperand(1);
92289174
SDValue CC = Op.getOperand(2);
9229-
EVT VT = Op.getValueType();
9175+
MVT VT = Op.getValueType().getSimpleVT();
92309176
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9231-
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
9177+
bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
92329178
DebugLoc dl = Op.getDebugLoc();
92339179

92349180
if (isFP) {
92359181
#ifndef NDEBUG
9236-
EVT EltVT = Op0.getValueType().getVectorElementType();
9182+
MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
92379183
assert(EltVT == MVT::f32 || EltVT == MVT::f64);
92389184
#endif
92399185

@@ -9374,6 +9320,63 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
93749320
return Result;
93759321
}
93769322

9323+
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9324+
9325+
MVT VT = Op.getValueType().getSimpleVT();
9326+
9327+
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9328+
9329+
assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9330+
SDValue Op0 = Op.getOperand(0);
9331+
SDValue Op1 = Op.getOperand(1);
9332+
DebugLoc dl = Op.getDebugLoc();
9333+
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9334+
9335+
// Optimize to BT if possible.
9336+
// Lower (X & (1 << N)) == 0 to BT(X, N).
9337+
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
9338+
// Lower ((X >>s N) & 1) != 0 to BT(X, N).
9339+
if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9340+
Op1.getOpcode() == ISD::Constant &&
9341+
cast<ConstantSDNode>(Op1)->isNullValue() &&
9342+
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
9343+
SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9344+
if (NewSetCC.getNode())
9345+
return NewSetCC;
9346+
}
9347+
9348+
// Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9349+
// these.
9350+
if (Op1.getOpcode() == ISD::Constant &&
9351+
(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9352+
cast<ConstantSDNode>(Op1)->isNullValue()) &&
9353+
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
9354+
9355+
// If the input is a setcc, then reuse the input setcc or use a new one with
9356+
// the inverted condition.
9357+
if (Op0.getOpcode() == X86ISD::SETCC) {
9358+
X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9359+
bool Invert = (CC == ISD::SETNE) ^
9360+
cast<ConstantSDNode>(Op1)->isNullValue();
9361+
if (!Invert) return Op0;
9362+
9363+
CCode = X86::GetOppositeBranchCondition(CCode);
9364+
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9365+
DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9366+
}
9367+
}
9368+
9369+
bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9370+
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9371+
if (X86CC == X86::COND_INVALID)
9372+
return SDValue();
9373+
9374+
SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9375+
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9376+
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9377+
DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9378+
}
9379+
93779380
// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
93789381
static bool isX86LogicalCmp(SDValue Op) {
93799382
unsigned Opc = Op.getNode()->getOpcode();

‎lib/Target/X86/X86ISelLowering.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -822,7 +822,6 @@ namespace llvm {
822822
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
823823
DebugLoc dl, SelectionDAG &DAG) const;
824824
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
825-
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
826825
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
827826
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
828827
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;

0 commit comments

Comments
 (0)