Skip to content

Commit bbfa246

Browse files
committed
[AArch64][Falkor] Fix bug in falkor prefetcher fix pass.
Summary: In rare cases, loads that don't get prefetched that were marked as strided loads could cause a crash if they occurred in a loop with other colliding loads. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38261 llvm-svn: 314252
1 parent a4b2f5d commit bbfa246

File tree

2 files changed

+33
-3
lines changed

2 files changed

+33
-3
lines changed

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -710,9 +710,14 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
710710
if (!TII->isStridedAccess(MI))
711711
continue;
712712

713-
LoadInfo LdI = *getLoadInfo(MI);
714-
unsigned OldTag = *getTag(TRI, MI, LdI);
715-
auto &OldCollisions = TagMap[OldTag];
713+
Optional<LoadInfo> OptLdI = getLoadInfo(MI);
714+
if (!OptLdI)
715+
continue;
716+
LoadInfo LdI = *OptLdI;
717+
Optional<unsigned> OptOldTag = getTag(TRI, MI, LdI);
718+
if (!OptOldTag)
719+
continue;
720+
auto &OldCollisions = TagMap[*OptOldTag];
716721
if (OldCollisions.size() <= 1)
717722
continue;
718723

llvm/test/CodeGen/AArch64/falkor-hwpf-fix.mir

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -305,3 +305,28 @@ body: |
305305
bb.1:
306306
RET_ReallyLR
307307
...
308+
---
309+
# Check that we handle case of strided load with no HW prefetcher tag correctly.
310+
311+
# CHECK-LABEL: name: hwpf_notagbug
312+
# CHECK-NOT: ORRXrs %xzr
313+
# CHECK: LDARW %x1
314+
# CHECK-NOT: ORRXrs %xzr
315+
# CHECK: LDRWui %x1
316+
name: hwpf_notagbug
317+
tracksRegLiveness: true
318+
body: |
319+
bb.0:
320+
liveins: %w0, %x1, %x17
321+
322+
%w1 = LDARW %x1 :: ("aarch64-strided-access" load 4)
323+
%w1 = LDRWui %x1, 0 :: ("aarch64-strided-access" load 4)
324+
%w17 = LDRWui %x17, 0 :: ("aarch64-strided-access" load 4)
325+
326+
%w0 = SUBWri %w0, 1, 0
327+
%wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
328+
Bcc 9, %bb.0, implicit %nzcv
329+
330+
bb.1:
331+
RET_ReallyLR
332+
...

0 commit comments

Comments
 (0)