Skip to content

Commit 92af831

Browse files
borsbors
committed
Auto merge of rust-lang#126518 - matthiaskrgr:rollup-wb70rzq, r=matthiaskrgr
Rollup of 9 pull requests Successful merges: - rust-lang#125829 (rustc_span: Add conveniences for working with span formats) - rust-lang#126361 (Unify intrinsics body handling in StableMIR) - rust-lang#126417 (Add `f16` and `f128` inline ASM support for `x86` and `x86-64`) - rust-lang#126424 ( Also sort `crt-static` in `--print target-features` output) - rust-lang#126428 (Polish `std::path::absolute` documentation.) - rust-lang#126429 (Add `f16` and `f128` const eval for binary and unary operationations) - rust-lang#126448 (End support for Python 3.8 in tidy) - rust-lang#126488 (Use `std::path::absolute` in bootstrap) - rust-lang#126511 (.mailmap: Associate both my work and my private email with me) r? `@ghost` `@rustbot` modify labels: rollup
2 parents 687a68d + 128e2b4 commit 92af831

File tree

30 files changed

+719
-512
lines changed

30 files changed

+719
-512
lines changed

‎.mailmap

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -379,6 +379,7 @@ Markus Westerlind <marwes91@gmail.com> Markus <marwes91@gmail.com>
379379
Martin Carton <cartonmartin+git@gmail.com>
380380
Martin Habovštiak <martin.habovstiak@gmail.com>
381381
Martin Hafskjold Thoresen <martinhath@gmail.com>
382+
Martin Nordholts <martin.nordholts@codetale.se> <enselic@gmail.com>
382383
Matej Lach <matej.lach@gmail.com> Matej Ľach <matej.lach@gmail.com>
383384
Mateusz Mikuła <mati865@gmail.com>
384385
Mateusz Mikuła <mati865@gmail.com> <mati865@users.noreply.github.com>

‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -959,6 +959,43 @@ fn llvm_fixup_input<'ll, 'tcx>(
959959
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
960960
Abi::Vector { .. },
961961
) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
962+
(
963+
InlineAsmRegClass::X86(
964+
X86InlineAsmRegClass::xmm_reg
965+
| X86InlineAsmRegClass::ymm_reg
966+
| X86InlineAsmRegClass::zmm_reg,
967+
),
968+
Abi::Scalar(s),
969+
) if bx.sess().asm_arch == Some(InlineAsmArch::X86)
970+
&& s.primitive() == Primitive::Float(Float::F128) =>
971+
{
972+
bx.bitcast(value, bx.type_vector(bx.type_i32(), 4))
973+
}
974+
(
975+
InlineAsmRegClass::X86(
976+
X86InlineAsmRegClass::xmm_reg
977+
| X86InlineAsmRegClass::ymm_reg
978+
| X86InlineAsmRegClass::zmm_reg,
979+
),
980+
Abi::Scalar(s),
981+
) if s.primitive() == Primitive::Float(Float::F16) => {
982+
let value = bx.insert_element(
983+
bx.const_undef(bx.type_vector(bx.type_f16(), 8)),
984+
value,
985+
bx.const_usize(0),
986+
);
987+
bx.bitcast(value, bx.type_vector(bx.type_i16(), 8))
988+
}
989+
(
990+
InlineAsmRegClass::X86(
991+
X86InlineAsmRegClass::xmm_reg
992+
| X86InlineAsmRegClass::ymm_reg
993+
| X86InlineAsmRegClass::zmm_reg,
994+
),
995+
Abi::Vector { element, count: count @ (8 | 16) },
996+
) if element.primitive() == Primitive::Float(Float::F16) => {
997+
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
998+
}
962999
(
9631000
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
9641001
Abi::Scalar(s),
@@ -1036,6 +1073,39 @@ fn llvm_fixup_output<'ll, 'tcx>(
10361073
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
10371074
Abi::Vector { .. },
10381075
) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
1076+
(
1077+
InlineAsmRegClass::X86(
1078+
X86InlineAsmRegClass::xmm_reg
1079+
| X86InlineAsmRegClass::ymm_reg
1080+
| X86InlineAsmRegClass::zmm_reg,
1081+
),
1082+
Abi::Scalar(s),
1083+
) if bx.sess().asm_arch == Some(InlineAsmArch::X86)
1084+
&& s.primitive() == Primitive::Float(Float::F128) =>
1085+
{
1086+
bx.bitcast(value, bx.type_f128())
1087+
}
1088+
(
1089+
InlineAsmRegClass::X86(
1090+
X86InlineAsmRegClass::xmm_reg
1091+
| X86InlineAsmRegClass::ymm_reg
1092+
| X86InlineAsmRegClass::zmm_reg,
1093+
),
1094+
Abi::Scalar(s),
1095+
) if s.primitive() == Primitive::Float(Float::F16) => {
1096+
let value = bx.bitcast(value, bx.type_vector(bx.type_f16(), 8));
1097+
bx.extract_element(value, bx.const_usize(0))
1098+
}
1099+
(
1100+
InlineAsmRegClass::X86(
1101+
X86InlineAsmRegClass::xmm_reg
1102+
| X86InlineAsmRegClass::ymm_reg
1103+
| X86InlineAsmRegClass::zmm_reg,
1104+
),
1105+
Abi::Vector { element, count: count @ (8 | 16) },
1106+
) if element.primitive() == Primitive::Float(Float::F16) => {
1107+
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
1108+
}
10391109
(
10401110
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
10411111
Abi::Scalar(s),
@@ -1109,6 +1179,36 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
11091179
InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
11101180
Abi::Vector { .. },
11111181
) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
1182+
(
1183+
InlineAsmRegClass::X86(
1184+
X86InlineAsmRegClass::xmm_reg
1185+
| X86InlineAsmRegClass::ymm_reg
1186+
| X86InlineAsmRegClass::zmm_reg,
1187+
),
1188+
Abi::Scalar(s),
1189+
) if cx.sess().asm_arch == Some(InlineAsmArch::X86)
1190+
&& s.primitive() == Primitive::Float(Float::F128) =>
1191+
{
1192+
cx.type_vector(cx.type_i32(), 4)
1193+
}
1194+
(
1195+
InlineAsmRegClass::X86(
1196+
X86InlineAsmRegClass::xmm_reg
1197+
| X86InlineAsmRegClass::ymm_reg
1198+
| X86InlineAsmRegClass::zmm_reg,
1199+
),
1200+
Abi::Scalar(s),
1201+
) if s.primitive() == Primitive::Float(Float::F16) => cx.type_vector(cx.type_i16(), 8),
1202+
(
1203+
InlineAsmRegClass::X86(
1204+
X86InlineAsmRegClass::xmm_reg
1205+
| X86InlineAsmRegClass::ymm_reg
1206+
| X86InlineAsmRegClass::zmm_reg,
1207+
),
1208+
Abi::Vector { element, count: count @ (8 | 16) },
1209+
) if element.primitive() == Primitive::Float(Float::F16) => {
1210+
cx.type_vector(cx.type_i16(), count)
1211+
}
11121212
(
11131213
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
11141214
Abi::Scalar(s),

‎compiler/rustc_codegen_llvm/src/llvm_util.rs

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -394,10 +394,15 @@ fn print_target_features(out: &mut dyn PrintBackendInfo, sess: &Session, tm: &ll
394394
(*feature, desc)
395395
})
396396
.collect::<Vec<_>>();
397+
398+
// Since we add this at the end ...
397399
rustc_target_features.extend_from_slice(&[(
398400
"crt-static",
399401
"Enables C Run-time Libraries to be statically linked",
400402
)]);
403+
// ... we need to sort the list again.
404+
rustc_target_features.sort();
405+
401406
llvm_target_features.retain(|(f, _d)| !known_llvm_target_features.contains(f));
402407

403408
let max_feature_len = llvm_target_features

‎compiler/rustc_const_eval/src/interpret/operator.rs

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -357,14 +357,18 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
357357
let left = left.to_scalar();
358358
let right = right.to_scalar();
359359
Ok(match fty {
360-
FloatTy::F16 => unimplemented!("f16_f128"),
360+
FloatTy::F16 => {
361+
self.binary_float_op(bin_op, layout, left.to_f16()?, right.to_f16()?)
362+
}
361363
FloatTy::F32 => {
362364
self.binary_float_op(bin_op, layout, left.to_f32()?, right.to_f32()?)
363365
}
364366
FloatTy::F64 => {
365367
self.binary_float_op(bin_op, layout, left.to_f64()?, right.to_f64()?)
366368
}
367-
FloatTy::F128 => unimplemented!("f16_f128"),
369+
FloatTy::F128 => {
370+
self.binary_float_op(bin_op, layout, left.to_f128()?, right.to_f128()?)
371+
}
368372
})
369373
}
370374
_ if left.layout.ty.is_integral() => {
@@ -424,11 +428,16 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
424428
}
425429
ty::Float(fty) => {
426430
let val = val.to_scalar();
431+
if un_op != Neg {
432+
span_bug!(self.cur_span(), "Invalid float op {:?}", un_op);
433+
}
434+
427435
// No NaN adjustment here, `-` is a bitwise operation!
428-
let res = match (un_op, fty) {
429-
(Neg, FloatTy::F32) => Scalar::from_f32(-val.to_f32()?),
430-
(Neg, FloatTy::F64) => Scalar::from_f64(-val.to_f64()?),
431-
_ => span_bug!(self.cur_span(), "Invalid float op {:?}", un_op),
436+
let res = match fty {
437+
FloatTy::F16 => Scalar::from_f16(-val.to_f16()?),
438+
FloatTy::F32 => Scalar::from_f32(-val.to_f32()?),
439+
FloatTy::F64 => Scalar::from_f64(-val.to_f64()?),
440+
FloatTy::F128 => Scalar::from_f128(-val.to_f128()?),
432441
};
433442
Ok(ImmTy::from_scalar(res, layout))
434443
}

‎compiler/rustc_expand/src/mbe/transcribe.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ impl MutVisitor for Marker {
3131
// it's some advanced case with macro-generated macros. So if we cache the marked version
3232
// of that context once, we'll typically have a 100% cache hit rate after that.
3333
let Marker(expn_id, transparency, ref mut cache) = *self;
34-
span.update_ctxt(|ctxt| {
34+
*span = span.map_ctxt(|ctxt| {
3535
*cache
3636
.entry(ctxt)
3737
.or_insert_with(|| ctxt.apply_mark(expn_id.to_expn_id(), transparency))

‎compiler/rustc_hir_analysis/src/check/intrinsicck.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,10 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
6262
ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Some(InlineAsmType::I64),
6363
ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => Some(InlineAsmType::I128),
6464
ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => Some(asm_ty_isize),
65+
ty::Float(FloatTy::F16) => Some(InlineAsmType::F16),
6566
ty::Float(FloatTy::F32) => Some(InlineAsmType::F32),
6667
ty::Float(FloatTy::F64) => Some(InlineAsmType::F64),
68+
ty::Float(FloatTy::F128) => Some(InlineAsmType::F128),
6769
ty::FnPtr(_) => Some(asm_ty_isize),
6870
ty::RawPtr(ty, _) if self.is_thin_ptr_ty(ty) => Some(asm_ty_isize),
6971
ty::Adt(adt, args) if adt.repr().simd() => {
@@ -105,8 +107,10 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
105107
width => bug!("unsupported pointer width: {width}"),
106108
})
107109
}
110+
ty::Float(FloatTy::F16) => Some(InlineAsmType::VecF16(size)),
108111
ty::Float(FloatTy::F32) => Some(InlineAsmType::VecF32(size)),
109112
ty::Float(FloatTy::F64) => Some(InlineAsmType::VecF64(size)),
113+
ty::Float(FloatTy::F128) => Some(InlineAsmType::VecF128(size)),
110114
_ => None,
111115
}
112116
}

‎compiler/rustc_middle/src/mir/interpret/value.rs

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,13 @@ impl<Prov: Provenance> fmt::LowerHex for Scalar<Prov> {
6969
}
7070
}
7171

72+
impl<Prov> From<Half> for Scalar<Prov> {
73+
#[inline(always)]
74+
fn from(f: Half) -> Self {
75+
Scalar::from_f16(f)
76+
}
77+
}
78+
7279
impl<Prov> From<Single> for Scalar<Prov> {
7380
#[inline(always)]
7481
fn from(f: Single) -> Self {
@@ -83,6 +90,13 @@ impl<Prov> From<Double> for Scalar<Prov> {
8390
}
8491
}
8592

93+
impl<Prov> From<Quad> for Scalar<Prov> {
94+
#[inline(always)]
95+
fn from(f: Quad) -> Self {
96+
Scalar::from_f128(f)
97+
}
98+
}
99+
86100
impl<Prov> From<ScalarInt> for Scalar<Prov> {
87101
#[inline(always)]
88102
fn from(ptr: ScalarInt) -> Self {

‎compiler/rustc_smir/src/rustc_smir/context.rs

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -64,9 +64,10 @@ impl<'tcx> Context for TablesWrapper<'tcx> {
6464
}
6565

6666
fn has_body(&self, def: DefId) -> bool {
67-
let tables = self.0.borrow();
68-
let def_id = tables[def];
69-
tables.tcx.is_mir_available(def_id)
67+
let mut tables = self.0.borrow_mut();
68+
let tcx = tables.tcx;
69+
let def_id = def.internal(&mut *tables, tcx);
70+
tables.item_has_body(def_id)
7071
}
7172

7273
fn foreign_modules(&self, crate_num: CrateNum) -> Vec<stable_mir::ty::ForeignModuleDef> {
@@ -323,13 +324,6 @@ impl<'tcx> Context for TablesWrapper<'tcx> {
323324
tcx.intrinsic(def_id).unwrap().name.to_string()
324325
}
325326

326-
fn intrinsic_must_be_overridden(&self, def: IntrinsicDef) -> bool {
327-
let mut tables = self.0.borrow_mut();
328-
let tcx = tables.tcx;
329-
let def_id = def.0.internal(&mut *tables, tcx);
330-
tcx.intrinsic_raw(def_id).unwrap().must_be_overridden
331-
}
332-
333327
fn closure_sig(&self, args: &GenericArgs) -> PolyFnSig {
334328
let mut tables = self.0.borrow_mut();
335329
let tcx = tables.tcx;
@@ -516,7 +510,7 @@ impl<'tcx> Context for TablesWrapper<'tcx> {
516510
let mut tables = self.0.borrow_mut();
517511
let instance = tables.instances[def];
518512
tables
519-
.has_body(instance)
513+
.instance_has_body(instance)
520514
.then(|| BodyBuilder::new(tables.tcx, instance).build(&mut *tables))
521515
}
522516

‎compiler/rustc_smir/src/rustc_smir/mod.rs

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,16 +51,33 @@ impl<'tcx> Tables<'tcx> {
5151
self.mir_consts.create_or_fetch(constant)
5252
}
5353

54-
pub(crate) fn has_body(&self, instance: Instance<'tcx>) -> bool {
54+
/// Return whether the instance as a body available.
55+
///
56+
/// Items and intrinsics may have a body available from its definition.
57+
/// Shims body may be generated depending on their type.
58+
pub(crate) fn instance_has_body(&self, instance: Instance<'tcx>) -> bool {
5559
let def_id = instance.def_id();
56-
self.tcx.is_mir_available(def_id)
60+
self.item_has_body(def_id)
5761
|| !matches!(
5862
instance.def,
5963
ty::InstanceDef::Virtual(..)
6064
| ty::InstanceDef::Intrinsic(..)
6165
| ty::InstanceDef::Item(..)
6266
)
6367
}
68+
69+
/// Return whether the item has a body defined by the user.
70+
///
71+
/// Note that intrinsics may have a placeholder body that shouldn't be used in practice.
72+
/// In StableMIR, we handle this case as if the body is not available.
73+
pub(crate) fn item_has_body(&self, def_id: DefId) -> bool {
74+
let must_override = if let Some(intrinsic) = self.tcx.intrinsic(def_id) {
75+
intrinsic.must_be_overridden
76+
} else {
77+
false
78+
};
79+
!must_override && self.tcx.is_mir_available(def_id)
80+
}
6481
}
6582

6683
/// Build a stable mir crate from a given crate number.

‎compiler/rustc_span/src/lib.rs

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -520,6 +520,7 @@ impl SpanData {
520520
pub fn with_hi(&self, hi: BytePos) -> Span {
521521
Span::new(self.lo, hi, self.ctxt, self.parent)
522522
}
523+
/// Avoid if possible, `Span::map_ctxt` should be preferred.
523524
#[inline]
524525
fn with_ctxt(&self, ctxt: SyntaxContext) -> Span {
525526
Span::new(self.lo, self.hi, ctxt, self.parent)
@@ -576,9 +577,8 @@ impl Span {
576577
self.data().with_hi(hi)
577578
}
578579
#[inline]
579-
pub fn with_ctxt(mut self, ctxt: SyntaxContext) -> Span {
580-
self.update_ctxt(|_| ctxt);
581-
self
580+
pub fn with_ctxt(self, ctxt: SyntaxContext) -> Span {
581+
self.map_ctxt(|_| ctxt)
582582
}
583583
#[inline]
584584
pub fn parent(self) -> Option<LocalDefId> {
@@ -1059,9 +1059,8 @@ impl Span {
10591059
}
10601060

10611061
#[inline]
1062-
pub fn apply_mark(mut self, expn_id: ExpnId, transparency: Transparency) -> Span {
1063-
self.update_ctxt(|ctxt| ctxt.apply_mark(expn_id, transparency));
1064-
self
1062+
pub fn apply_mark(self, expn_id: ExpnId, transparency: Transparency) -> Span {
1063+
self.map_ctxt(|ctxt| ctxt.apply_mark(expn_id, transparency))
10651064
}
10661065

10671066
#[inline]
@@ -1109,15 +1108,13 @@ impl Span {
11091108
}
11101109

11111110
#[inline]
1112-
pub fn normalize_to_macros_2_0(mut self) -> Span {
1113-
self.update_ctxt(|ctxt| ctxt.normalize_to_macros_2_0());
1114-
self
1111+
pub fn normalize_to_macros_2_0(self) -> Span {
1112+
self.map_ctxt(|ctxt| ctxt.normalize_to_macros_2_0())
11151113
}
11161114

11171115
#[inline]
1118-
pub fn normalize_to_macro_rules(mut self) -> Span {
1119-
self.update_ctxt(|ctxt| ctxt.normalize_to_macro_rules());
1120-
self
1116+
pub fn normalize_to_macro_rules(self) -> Span {
1117+
self.map_ctxt(|ctxt| ctxt.normalize_to_macro_rules())
11211118
}
11221119
}
11231120

0 commit comments

Comments
 (0)