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1 | 1 | # `{arm,thumb}*-none-eabi(hf)?` |
2 | 2 |
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3 | | -## Tier 2 Target List |
| 3 | +## Common Target Details |
| 4 | + |
| 5 | +This documentation covers details that apply to a range of bare-metal targets |
| 6 | +for 32-bit Arm CPUs. The `arm-none-eabi` flavor of the GNU compiler toolchain is |
| 7 | +often used to assist compilation to these targets. |
| 8 | + |
| 9 | +Details that apply only to only a specific target in this group are covered in |
| 10 | +their own document. |
| 11 | + |
| 12 | +### Tier 2 Target List |
4 | 13 |
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5 | 14 | - Arm A-Profile Architectures |
6 | 15 | - `armv7a-none-eabi` |
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16 | 25 | - *Legacy* Arm Architectures |
17 | 26 | - None |
18 | 27 |
|
19 | | -## Tier 3 Target List |
| 28 | +### Tier 3 Target List |
20 | 29 |
|
21 | 30 | - Arm A-Profile Architectures |
22 | 31 | - `armv7a-none-eabihf` |
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28 | 37 | - [`armv4t-none-eabi` and `thumbv4t-none-eabi`](armv4t-none-eabi.md) |
29 | 38 | - [`armv5te-none-eabi` and `thumbv5te-none-eabi`](armv5te-none-eabi.md) |
30 | 39 |
|
31 | | -## Common Target Details |
32 | | - |
33 | | -This documentation covers details that apply to a range of bare-metal targets |
34 | | -for 32-bit Arm CPUs. In addition, target specific details may be covered in |
35 | | -their own document. |
| 40 | +## Instruction Sets |
36 | 41 |
|
37 | 42 | There are two 32-bit instruction set architectures (ISAs) defined by Arm: |
38 | 43 |
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39 | 44 | - The [*A32 ISA*][a32-isa], with fixed-width 32-bit instructions. Previously |
40 | | - known as the *Arm* ISA, this originated with the original ARM1 of 1985 and has |
| 45 | + known as the *Arm* ISA, this originated with the original Arm1 of 1985 and has |
41 | 46 | been updated by various revisions to the architecture specifications ever |
42 | 47 | since. |
43 | 48 | - The [*T32 ISA*][t32-isa], with a mix of 16-bit and 32-bit width instructions. |
44 | 49 | Note that this term includes both the original 16-bit width *Thumb* ISA |
45 | 50 | introduced with the Armv4T architecture in 1994, and the later 16/32-bit sized |
46 | | - *Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. Again, these |
47 | | - ISAs have been revised by subsequent revisions to the relevant Arm |
48 | | - architecture specifications. |
| 51 | + *Thumb-2* ISA introduced with the Armv6T2 architecture in 2003. |
| 52 | + |
| 53 | +Again, these ISAs have been revised by subsequent revisions to the relevant Arm |
| 54 | +architecture specifications. |
49 | 55 |
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50 | 56 | There is also a 64-bit ISA with fixed-width 32-bit instructions called the *A64 |
51 | 57 | ISA*, but targets which implement that instruction set generally start with |
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