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RalfJungRalfJung
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Rollup merge of rust-lang#72439 - westernmagic:master, r=Amanieu
NVPTX support for new asm! This PR implements the new `asm!` syntax for the `nvptx64-nvidia-cuda` target. r? @Amanieu
2 parents b965196 + e18054d commit 3789455

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‎src/doc/unstable-book/src/library-features/asm.md‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -468,12 +468,17 @@ Here is the list of currently supported register classes:
468468
| ARM | `qreg` | `q[0-15]` | `w` |
469469
| ARM | `qreg_low8` | `q[0-7]` | `t` |
470470
| ARM | `qreg_low4` | `q[0-3]` | `x` |
471+
| NVPTX | `reg16` | None\* | `h` |
472+
| NVPTX | `reg32` | None\* | `r` |
473+
| NVPTX | `reg64` | None\* | `l` |
471474
| RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
472475
| RISC-V | `freg` | `f[0-31]` | `f` |
473476

474477
> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
475478
>
476479
> Note #2: On x86-64 the high byte registers (e.g. `ah`) are only available when used as an explicit register. Specifying the `reg_byte` register class for an operand will always allocate a low byte register.
480+
>
481+
> Note #3: NVPTX doesn't have a fixed register set, so named registers are not supported.
477482
478483
Additional register classes may be added in the future based on demand (e.g. MMX, x87, etc).
479484

@@ -495,6 +500,9 @@ Each register class has constraints on which value types they can be used with.
495500
| ARM | `sreg` | `vfp2` | `i32`, `f32` |
496501
| ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
497502
| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
503+
| NVPTX | `reg16` | None | `i8`, `i16` |
504+
| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
505+
| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
498506
| RISC-V32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
499507
| RISC-V64 | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
500508
| RISC-V | `freg` | `f` | `f32` |
@@ -610,6 +618,9 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
610618
| ARM | `dreg` | None | `d0` | `P` |
611619
| ARM | `qreg` | None | `q0` | `q` |
612620
| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
621+
| NVPTX | `reg16` | None | `rs0` | None |
622+
| NVPTX | `reg32` | None | `r0` | None |
623+
| NVPTX | `reg64` | None | `rd0` | None |
613624
| RISC-V | `reg` | None | `x1` | None |
614625
| RISC-V | `freg` | None | `f0` | None |
615626

‎src/librustc_codegen_llvm/asm.rs‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -254,6 +254,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
254254
]);
255255
}
256256
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
257+
InlineAsmArch::Nvptx64 => {}
257258
}
258259
}
259260
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -410,6 +411,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
410411
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
411412
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
412413
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
414+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
415+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
416+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
413417
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
414418
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => "f",
415419
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg) => "r",
@@ -452,6 +456,7 @@ fn modifier_to_llvm(
452456
modifier
453457
}
454458
}
459+
InlineAsmRegClass::Nvptx(_) => None,
455460
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
456461
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
457462
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)
@@ -502,6 +507,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
502507
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
503508
cx.type_vector(cx.type_i64(), 2)
504509
}
510+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
511+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
512+
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
505513
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
506514
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => cx.type_f32(),
507515
InlineAsmRegClass::X86(X86InlineAsmRegClass::reg)

‎src/librustc_target/asm/mod.rs‎

Lines changed: 26 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ macro_rules! def_regs {
6060
#error = [$($bad_reg:literal),+] => $error:literal,
6161
)*
6262
}) => {
63+
#[allow(unreachable_code)]
6364
#[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]
6465
#[allow(non_camel_case_types)]
6566
pub enum $arch_reg {
@@ -102,19 +103,20 @@ macro_rules! def_regs {
102103
pub(super) fn fill_reg_map(
103104
_arch: super::InlineAsmArch,
104105
mut _has_feature: impl FnMut(&str) -> bool,
105-
map: &mut rustc_data_structures::fx::FxHashMap<
106+
_map: &mut rustc_data_structures::fx::FxHashMap<
106107
super::InlineAsmRegClass,
107108
rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
108109
>,
109110
) {
111+
#[allow(unused_imports)]
110112
use super::{InlineAsmReg, InlineAsmRegClass};
111113
$(
112114
if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {
113-
if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
115+
if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
114116
set.insert(InlineAsmReg::$arch($arch_reg::$reg));
115117
}
116118
$(
117-
if let Some(set) = map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
119+
if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
118120
set.insert(InlineAsmReg::$arch($arch_reg::$reg));
119121
}
120122
)*
@@ -146,11 +148,13 @@ macro_rules! types {
146148

147149
mod aarch64;
148150
mod arm;
151+
mod nvptx;
149152
mod riscv;
150153
mod x86;
151154

152155
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
153156
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
157+
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
154158
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
155159
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
156160

@@ -162,6 +166,7 @@ pub enum InlineAsmArch {
162166
AArch64,
163167
RiscV32,
164168
RiscV64,
169+
Nvptx64,
165170
}
166171

167172
impl FromStr for InlineAsmArch {
@@ -175,6 +180,7 @@ impl FromStr for InlineAsmArch {
175180
"aarch64" => Ok(Self::AArch64),
176181
"riscv32" => Ok(Self::RiscV32),
177182
"riscv64" => Ok(Self::RiscV64),
183+
"nvptx64" => Ok(Self::Nvptx64),
178184
_ => Err(()),
179185
}
180186
}
@@ -196,6 +202,7 @@ pub enum InlineAsmReg {
196202
Arm(ArmInlineAsmReg),
197203
AArch64(AArch64InlineAsmReg),
198204
RiscV(RiscVInlineAsmReg),
205+
Nvptx(NvptxInlineAsmReg),
199206
}
200207

201208
impl InlineAsmReg {
@@ -236,6 +243,9 @@ impl InlineAsmReg {
236243
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
237244
Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)
238245
}
246+
InlineAsmArch::Nvptx64 => {
247+
Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
248+
}
239249
})
240250
}
241251

@@ -281,6 +291,7 @@ pub enum InlineAsmRegClass {
281291
Arm(ArmInlineAsmRegClass),
282292
AArch64(AArch64InlineAsmRegClass),
283293
RiscV(RiscVInlineAsmRegClass),
294+
Nvptx(NvptxInlineAsmRegClass),
284295
}
285296

286297
impl InlineAsmRegClass {
@@ -290,6 +301,7 @@ impl InlineAsmRegClass {
290301
Self::Arm(r) => r.name(),
291302
Self::AArch64(r) => r.name(),
292303
Self::RiscV(r) => r.name(),
304+
Self::Nvptx(r) => r.name(),
293305
}
294306
}
295307

@@ -302,6 +314,7 @@ impl InlineAsmRegClass {
302314
Self::Arm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Arm),
303315
Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
304316
Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
317+
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
305318
}
306319
}
307320

@@ -321,6 +334,7 @@ impl InlineAsmRegClass {
321334
Self::Arm(r) => r.suggest_modifier(arch, ty),
322335
Self::AArch64(r) => r.suggest_modifier(arch, ty),
323336
Self::RiscV(r) => r.suggest_modifier(arch, ty),
337+
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
324338
}
325339
}
326340

@@ -336,6 +350,7 @@ impl InlineAsmRegClass {
336350
Self::Arm(r) => r.default_modifier(arch),
337351
Self::AArch64(r) => r.default_modifier(arch),
338352
Self::RiscV(r) => r.default_modifier(arch),
353+
Self::Nvptx(r) => r.default_modifier(arch),
339354
}
340355
}
341356

@@ -350,6 +365,7 @@ impl InlineAsmRegClass {
350365
Self::Arm(r) => r.supported_types(arch),
351366
Self::AArch64(r) => r.supported_types(arch),
352367
Self::RiscV(r) => r.supported_types(arch),
368+
Self::Nvptx(r) => r.supported_types(arch),
353369
}
354370
}
355371

@@ -367,6 +383,7 @@ impl InlineAsmRegClass {
367383
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
368384
Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
369385
}
386+
InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
370387
})
371388
})
372389
}
@@ -379,6 +396,7 @@ impl InlineAsmRegClass {
379396
Self::Arm(r) => r.valid_modifiers(arch),
380397
Self::AArch64(r) => r.valid_modifiers(arch),
381398
Self::RiscV(r) => r.valid_modifiers(arch),
399+
Self::Nvptx(r) => r.valid_modifiers(arch),
382400
}
383401
}
384402
}
@@ -518,5 +536,10 @@ pub fn allocatable_registers(
518536
riscv::fill_reg_map(arch, has_feature, &mut map);
519537
map
520538
}
539+
InlineAsmArch::Nvptx64 => {
540+
let mut map = nvptx::regclass_map();
541+
nvptx::fill_reg_map(arch, has_feature, &mut map);
542+
map
543+
}
521544
}
522545
}

‎src/librustc_target/asm/nvptx.rs‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
4+
def_reg_class! {
5+
Nvptx NvptxInlineAsmRegClass {
6+
reg16,
7+
reg32,
8+
reg64,
9+
}
10+
}
11+
12+
impl NvptxInlineAsmRegClass {
13+
pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
14+
&[]
15+
}
16+
17+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
18+
None
19+
}
20+
21+
pub fn suggest_modifier(
22+
self,
23+
_arch: InlineAsmArch,
24+
_ty: InlineAsmType,
25+
) -> Option<(char, &'static str)> {
26+
None
27+
}
28+
29+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
30+
None
31+
}
32+
33+
pub fn supported_types(
34+
self,
35+
_arch: InlineAsmArch,
36+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
match self {
38+
Self::reg16 => types! { _: I8, I16; },
39+
Self::reg32 => types! { _: I8, I16, I32, F32; },
40+
Self::reg64 => types! { _: I8, I16, I32, F32, I64, F64; },
41+
}
42+
}
43+
}
44+
45+
def_regs! {
46+
// Registers in PTX are declared in the assembly.
47+
// There are no predefined registers that one can use.
48+
Nvptx NvptxInlineAsmReg NvptxInlineAsmRegClass {}
49+
}

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