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build-riscv :
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strategy :
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matrix :
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- # All generated code should be running on stable now, MRSV is 1.61 .0
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- toolchain : [ stable, nightly, 1.61 .0 ]
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+ # All generated code should be running on stable now, MRSV is 1.67 .0
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+ toolchain : [ stable, nightly, 1.67 .0 ]
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target :
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- riscv32i-unknown-none-elf
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- riscv32imc-unknown-none-elf
Original file line number Diff line number Diff line change @@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Add ` senvcfg ` CSR
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- Add ` scontext ` CSR
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- Add ` mconfigptr ` CSR
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+ - Bump MSRV to 1.67.0 for ` log ` to ` ilog ` name change
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### Changed
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name = " riscv"
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version = " 0.13.0"
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edition = " 2021"
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- rust-version = " 1.61 "
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+ rust-version = " 1.67 "
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repository = " https://github.com/rust-embedded/riscv"
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authors = [" The RISC-V Team <risc-v@teams.rust-embedded.org>" ]
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categories = [" embedded" , " hardware-support" , " no-std" ]
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