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Auto merge of #53 - japaric:gh46, r=japaric
don't expose registers clidr, ctr, ccsidr, csselr to ARMv6-M targets as these are only available on ARMv7-M devices
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src/peripheral/mod.rs

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@@ -104,12 +104,16 @@ pub struct CPUID {
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pub isar: [RO<u32>; 5],
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reserved1: u32,
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/// Cache Level ID
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#[cfg(any(armv7m, test))]
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pub clidr: RO<u32>,
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/// Cache Type
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#[cfg(any(armv7m, test))]
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pub ctr: RO<u32>,
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/// Cache Size ID
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#[cfg(any(armv7m, test))]
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pub ccsidr: RO<u32>,
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/// Cache Size Selection
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#[cfg(any(armv7m, test))]
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pub csselr: RW<u32>,
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}
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