Skip to content

Commit ab0c405

Browse files
Merge pull request #57 from thejpster/test-v7a-eabihf
Run tests on armv7a-none-eabihf.
2 parents 13b3f8f + f6b9ce2 commit ab0c405

11 files changed

+114
-4
lines changed

.github/workflows/build.yml

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -101,20 +101,20 @@ jobs:
101101
cargo build
102102
103103
# Build the workspace for the target architecture but using nightly to compile libcore
104-
# Technically it doens't need 'setup' but it makes the graph look nicer
104+
# Technically it doesn't need 'setup' but it makes the graph look nicer
105105
build-tier3:
106106
runs-on: ubuntu-24.04
107107
needs: setup
108108
strategy:
109109
matrix:
110110
target:
111-
- armebv7r-none-eabi
112-
- armebv7r-none-eabihf
113-
- armv7r-none-eabi
114111
- armv7a-none-eabi
115112
- armv7a-none-eabihf
113+
- armv7r-none-eabi
116114
- armv7r-none-eabihf
117115
- armv8r-none-eabihf
116+
- armebv7r-none-eabi
117+
- armebv7r-none-eabihf
118118
steps:
119119
- name: Checkout
120120
uses: actions/checkout@v4
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!
Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
Hello, this is semihosting! x = 1.000, y = 2.000
2+
PANIC: PanicInfo {
3+
message: I am an example panic,
4+
location: Location {
5+
file: "src/bin/hello.rs",
6+
line: 19,
7+
column: 5,
8+
},
9+
can_unwind: true,
10+
force_no_backtrace: false,
11+
}
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is a prefetch abort exception example
2+
prefetch abort occurred
3+
IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
4+
IFSR Status: Ok(DebugEvent)
5+
IFAR (Faulting Address Register): Ifar(0)
6+
caught bkpt_from_a32
7+
Doing it again
8+
prefetch abort occurred
9+
IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
10+
IFSR Status: Ok(DebugEvent)
11+
IFAR (Faulting Address Register): Ifar(0)
12+
caught bkpt_from_a32
13+
Skipping instruction
14+
Recovered from fault OK!
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is a prefetch abort exception example
2+
prefetch abort occurred
3+
IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
4+
IFSR Status: Ok(DebugEvent)
5+
IFAR (Faulting Address Register): Ifar(0)
6+
caught bkpt_from_t32
7+
Doing it again
8+
prefetch abort occurred
9+
IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
10+
IFSR Status: Ok(DebugEvent)
11+
IFAR (Faulting Address Register): Ifar(0)
12+
caught bkpt_from_t32
13+
Skipping instruction
14+
Recovered from fault OK!
Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xc08 rev=0x0 }
2+
CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
3+
Mpidr(0)
4+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
5+
SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
x = 1, y = 2, z = 3.000
2+
In svc_handler, with arg=0xabcdef
3+
In svc_handler, with arg=0x456789
4+
x = 1, y = 2, z = 3.000
5+
PANIC: PanicInfo {
6+
message: I am an example panic,
7+
location: Location {
8+
file: "src/bin/svc.rs",
9+
line: 22,
10+
column: 5,
11+
},
12+
can_unwind: true,
13+
force_no_backtrace: false,
14+
}
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
Hello, this is a undef exception example
2+
undefined abort occurred
3+
caught udf_from_a32
4+
Doing it again
5+
undefined abort occurred
6+
caught udf_from_a32
7+
Skipping instruction
8+
Recovered from fault OK!
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
Hello, this is a undef exception example
2+
undefined abort occurred
3+
caught udf_from_t32
4+
Doing it again
5+
undefined abort occurred
6+
caught udf_from_t32
7+
Skipping instruction
8+
Recovered from fault OK!

0 commit comments

Comments
 (0)